Very high aspect ratio through-silicon vias (TSVs) fabricated using automated magnetic

assembly of nickel wires

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J. Micromech. Microeng. 22 (2012) 105001 (9pp) doi:10.1088/0960-1317/22/10/105001

Very high aspect ratio through-silicon vias(TSVs) fabricated using automatedmagnetic assembly of nickel wiresA C Fischer, S J Bleiker, T Haraldsson, N Roxhed, G Stemmeand F Niklaus

Microsystem Technology Laboratory, School of Electrical Engineering, KTH Royal Institute ofTechnology, Osquldas vag 10, SE-100 44 Stockholm, Sweden

E-mail: andreas.fischer@ee.kth.se

Received 11 May 2012, in final form 28 June 2012Published 17 August 2012Online at stacks.iop.org/JMM/22/105001

AbstractThrough-silicon via (TSV) technology enables 3D-integrated devices with higher performanceand lower cost as compared to 2D-integrated systems. This is mainly due to smallerdimensions of the package and shorter internal signal lengths with lower capacitive, resistiveand inductive parasitics. This paper presents a novel low-cost fabrication technique formetal-filled TSVs with very high aspect ratios (>20). Nickel wires are placed in via holes of asilicon wafer by an automated magnetic assembly process and are used as a conductive path ofthe TSV. This metal filling technique enables the reliable fabrication of through-wafer viaswith very high aspect ratios and potentially eliminates characteristic cost drivers in the TSVproduction such as advanced metallization processes, wafer thinning and general issuesassociated with thin-wafer handling.

(Some figures may appear in colour only in the online journal)

1. Introduction

3D-integrated system in package (3D-SiP) solutions, whichare based on vertical chip stacking, are a general trend inelectronics and MEMS packaging. Not only do 3D-SiPsdecrease device cost by reducing the volume and weight ofthe package, but they also improve the system performancethrough enhanced signal transmission speed and lower powerconsumption, which is important for various demandingapplications [1, 2]. Different technologies for the electricalinterconnection of stacked dies exist, such as wire bonding,flip-chip bonding and through-silicon vias (TSVs). Inparticular, TSVs enable shorter signal path lengths withsuperior electrical characteristics in terms of lower capacitive,resistive and inductive parasitic components [3]. Therefore,large development efforts for the realization of reliableand cost-efficient TSVs are currently ongoing and firstcommercially available devices such as MEMS inertialsensors and microphones, CMOS imagers and power LEDssuccessfully incorporate TSV technology [4–6].

The structure and hence the fabrication of TSVs can beroughly divided into three major elements: a vertical holethrough the substrate, a conductive core and a dielectric layeracting as an insulator between the conductor and the substrate.The most common fabrication techniques of these elementsare briefly discussed in the following subsections.

Via holes. Various methods for the formation of via holesexist and can be categorized into dry etching [1, 7–13], wetetching [8] and drilling processes [4, 14]. Via holes can haveeither straight [9, 10, 12, 13, 15] or tapered sidewall profiles[7, 11] as well as combinations of both [8, 1]. Typical diametersof via holes vary between a few microns [2, 9] and severalhundreds of microns [12, 15]. The majority of TSVs havean aspect ratio between 1 and 10. Deep reactive ion etching(DRIE) is by far the most commonly used technology to formTSV holes. DRIE offers an excellent process controllabilityand is capable of creating high aspect ratio vias with specificsidewall profiles and topographies. The etch rate of DRIEis aspect ratio dependent and may cause several topographicimperfections on the sidewalls of the via holes such asscalloping, caused by alternating etch and passivation steps,

0960-1317/12/105001+09$33.00 1 © 2012 IOP Publishing Ltd Printed in the UK & the USA

J. Micromech. Microeng. 22 (2012) 105001 A C Fischer et al

Table 1. Relative permittivity εr and mechanical properties(Young’s modulus E and coefficient of thermal expansion (CTE)) ofcommonly used TSV insulation materials, including silicon nitrideand silicon oxide as well as emerging low-k insulators. Siliconserves as reference in the first row.

CTEMaterial εr E (GPa) (ppm/K)

Si [23] – 190 2.33SiO2 (PECVD TEOS) [24] 3.9 64 2.61Si3N4 (LPCVD) [25] 7 261 1.7–2.3BCB 3000 Series (Dow) [26] 2.65a 2.7–3 42.3Parylene N [27] 2.65b 2.4 69SU-8 2000 (MicroChem) [28] 3.2c 2 52InterVia 8023 (Dow) [29] 3.2d 4 62

a1–20 GHz.b60 Hz–1 MHz.cAt 10 MHz.dAt 1 GHz.

which results in corrugated sidewalls. By using state-of-the-art DRIE equipment, these effects can be minimized [7] andadopted to the demands of subsequent insulation, barrier andseed-layer deposition steps.

Via insulator. Chemical vapor deposition (CVD) is awell-established CMOS-compatible process with moderatetemperature requirements [1, 2, 11, 9] and is therefore themost commonly used method for a direct deposition of silicondioxide or silicon nitride on via sidewalls. Organic dielectrics[16, 17] including benzocyclobutene (BCB) [13, 15, 18, 19],epoxy-based polymers [13, 12], silicone [13] or Parylene [11]are used as well. Polymers, especially low-k types with alower relative permittivity compared to silicon dioxide, arevery attractive for the realization of TSVs with improvedelectrical characteristics in terms of lower capacitive parasitics[20, 12, 15]. The relative permittivity of selected via insulationmaterials are listed in table 1. Furthermore, polymers can actas a buffer for thermo-mechanical stress that is caused bycoefficient of thermal expansion (CTE) mismatches betweenthe via metallization and the silicon bulk material [17, 21,20, 22]. As shown in table 1, the Young modulus of thesepolymers is typically two orders of magnitude lower ascompared to silicon dioxide and silicon nitride.

Via conductor. The formation of a low-resistivity viaconductor is the most critical and often most costly part ofthe via fabrication. The two basic via designs are either basedon solid or lined metallizations for the vertical conductor.Established processes are electrodeposition of copper[8, 9, 11–13, 22], CVD of tungsten [2, 30], CVD of polysilicon[2, 31] and the use of low-resistivity bulk silicon [10]. Inparticular, electrodeposition of copper, being a very wellestablished semiconductor process, is used by many researchgroups and implemented in most commercialized devicescontaining TSVs. Electrodeposition of copper benefits fromwidely available tool vendor support and process maturityas well as being amenable to deposition at near to roomtemperature, but suffers due to its complexity in termsof process controllability, reliability and throughput [4]. Inparticular, it is challenging to implement high aspect ratioTSVs with void-free conductive metal cores [4, 9, 32].Alternative approaches to plating processes have therefore

(a) (b)

Ni

SiO2

BCBiS

(c) (d)

Figure 1. Via formation concept. (a) The via hole is formed byDRIE, stopping on a silicon dioxide layer. (b) A conductive,ferromagnetic nickel core is placed in the via hole by magneticassembly. (c) The remaining hollow space in the via cavity is filledwith the thermosetting polymer BCB. (d) A grinding and polishingstep removes excess polymer and nickel from the frontside.

Table 2. Electrical resistivity ρ and mechanical properties (Young’smodulus E and coefficient of thermal expansion (CTE)) of commonTSV metallizations and ferromagnetic elements. Silicon serves asreference in the first row.

CTEMaterial ρ (�m) E (GPa) (ppm K−1)

Si [23] – 190 2.33Cu [39] 1.7 × 10−8 110 16.4Tu [39] 5.65 × 10−8 400 4.4Au [39] 2.2 × 10−8 77.2 14.4Ni [39] 6.4 × 10−8 207 13.1Co [39] 6.24 × 10−8 211 12.5Fe [39] 8.9 × 10−8 200 12.2

been investigated, such as the via filling with conductive metalpastes [1, 33, 34], solder [35, 36] as well as the use of wire-bonded metal cores [37, 38, 15].

As shown in table 2, the electrical resistivity offerromagnetic nickel is similar to tungsten, but approximatelythree to four times higher as compared to gold and copper.The CTE of nickel is approximately 20% lower as comparedto copper. Volume-manufactured nickel wires with diametersdown to 10 μm are commercially available and are typicallyused for chemically resistant woven filter cloth, screen printingmasks and recently also for wire bonded interconnections inhigh-temperature packaging of SiC electronics [40].

In this work, we present the automated magnetic assemblyof solid conductive via cores into TSV holes with very highaspect ratios. Magnetism as a non-contact force enables acontrolled manipulation of ferromagnetic features over longdistances and is insensitive to the surrounding medium andindependent of details of the surface chemistry. Magneticfields can have high-energy densities and can influencefeature sizes from macro- to nano-scale. These advantageouscharacteristics are very attractive and have been reported invarious assembly approaches [41]. The presented concept forthe TSV metallization and insulation process enables highaspect ratio vias with an inherently void-free metal core.

As depicted in figure 1, the filling of the via with aconductive material is not realized by a deposition of a

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J. Micromech. Microeng. 22 (2012) 105001 A C Fischer et al

metal but by an instant filling technique that magneticallyassembles pre-formed conductive via cores into the via holes.The via insulator is a polymer that acts both as low-kelectrical insulator and buffer against thermo-mechanicallyinduced stresses. As shown in figures 1(b) and (c), theorder of the metallization and insulation process step isreversed as compared to most conventional TSV fabricationscenarios where the metallization is gradually grown onbarrier, insulation and seed layers. The proposed approachtherefore does not require any additional high aspect ratiolithography and patterning of the insulation polymer. Moreimportantly, this insulation technique is insensitive to thetopography of the via sidewall (i.e. scallops). The proposedfabrication method enables a cost-effective fabrication of highaspect ratio TSVs especially for low- to medium-I/O densityapplications such as interposers and MEMS. A proof ofconcept of the fabrication of TSVs with an aspect ratio of 8by manual magnetic assembly has been shown by the authorsearlier [18, 19]. This method has also been adopted for theassembly of SMD capacitors into through-silicon holes [42].

2. TSV fabrication by automated magnetic assembly

2.1. Robotic assembly setup

An automated assembly process that utilizes the ferromagneticproperties of nickel has been developed for the placement ofnickel cores into via holes. In this process, an excess amountof nickel wires are randomly placed on the frontside of a waferand assembled into etched via holes. By applying a magneticfield, induced by a permanent magnet from the backside ofthe wafer, the nickel wires align themselves along the fieldlines and erect themselves perpendicular to the wafer surface,as shown in figure 2. Because of the magnetic force the wiresalways will remain above the magnet. This effect allows thenickel wires to be steered around on the wafer surface bysimply moving the permanent magnet laterally underneaththe wafer. The assembly of the nickel cores is achieved bymagnetically moving the wires over the via holes. The upright

B = 0 T B = 1.1 T(a) (b)

Figure 2. Behaviour of nickel wires in a magnetic field. (a) About300 straight nickel wires (35 μm diameter, 350 μm length) withoutan applied field. (b) A magnetic field of 1.1 T is generated by acylindrical permanent magnet. It aligns the nickel wires along thefield lines perpendicular to the ground plane.

position of the wires allows them to be pulled into the holesby the magnet.

For this magnetic assembly process a robotic setup hasbeen devised. It is based on a handler robot (IWH-series) for200 mm wafers from Isel Germany AG. Figure 3 shows aschematic depiction of the robot arm that has been modified inorder to mount a cubic permanent magnet with an edge lengthof 5 mm. This tool enables a programmable movement of themagnet with three degrees of freedom at a precision of 30 μm.That way different movement patterns were implemented andadopted to varying layouts of via holes. Also depicted infigure 3 is a camera that is mounted directly above the magnetand faces the frontside of the substrate. It is used to opticallyinspect the substrate surface before and after the assemblyand to monitor the assembly process. Furthermore, the toolstill retains its capability to handle wafers with the wafergripper that is a part of the robot arm. This robot arm hasa movement range of ±240◦ around its axis, ±366 mm inthe radial direction and 323 mm in the vertical direction.The maximum speeds are 360◦s−1, 1000 mm s−1 radial and450 mm s−1 vertical. By using a wafer handler robot for themagnetic assembly, an automated cassette-to-cassette processcan be implemented, i.e. picking a wafer from a input/outputcassette, placing it on a dedicated assembly stage, performingthe magnetic assembly and placing the wafer back into thecassette.

Assembly ArmWafer Scanner

Wafer Gripper

Wafer Cassette

AssemblyStage

(a) (b)

PermanentMagnet

Wires

Robot Arm

Camera

Wafer

Figure 3. (a) Assembly setup with the wafer gripper and assembly part on the robot arm in the centre of the table, the wafer cassette stationand the assembly stage to its right. The assembly process consists of four steps: (1) scanning the cassette for wafers, (2) picking the chosenwafer and placing it on the assembly stage, (3) positioning the assembly arm, placing the magnetic via cores manually on the substrate andcarrying out the automated magnetic assembly, (4) putting the wafer back into the cassette. (b) Schematic drawing showing the custom-builtassembly arm that consists of a permanent magnet mounted on an aluminium sheet and a camera above the magnet.

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J. Micromech. Microeng. 22 (2012) 105001 A C Fischer et al

Blue Tape

Ni WireAZ 4562Photoresist

Application of Ni Wire Polymer Embedding

Dice Test with Custom Adhesion Promoter

Dicing of Ni Wire

Dice Test with HMDS Adhesion Promoter

38 µmDicing Groove

Photoresist peels off during dicing!

Photoresist withstands dicing process!

38 µmDicing Groove

Wafer

Photo-resist

NiWire

DicingGroove

(a)

(d ) (e)

(b) (c) Dicing Blade

Figure 4. Nickel wire preparation. (a) The nickel wires are manually placed on a dummy wafer and fixated at the outer perimeter of thecarrier with the help of blue tape. (b) The wires are then embedded in a matrix of photoresist and subsequently diced. (c) The microscopicimage of a diced nickel wire with a diameter of 35 μm. (d) The microscopic image of a dicing test with a pitch of 150 μm with photoresistand standard HMDS adhesion promoter. The photoresist peels off during dicing. The adhesion showed to be insufficient for dicing pitchesbelow 500 μm. (e) The microscopic image of a dicing test with a pitch of 150 μm with photoresist and custom adhesion promoter. Theresist fully adheres to the substrate.

2.2. Nickel wire preparation

In order to cut a nickel wire into rods of a defined length, acutting process was developed. For the experiments, Ni-270wire with a purity of 99.97% with two different diameterswas used, 15 and 35 μm. As depicted in figure 4(a), severalwires are placed in parallel on a silicon carrier wafer andsubsequently embedded in a polymer matrix (figure 4(b)) inorder to safely fixate the wires on the carrier wafer and tominimize the deformation and burr creation during the cuttingprocess. The wires are then cut with the help of a wafer dicingtool (figure 4(c)) and finally released by dissolving the polymerin a solvent.

A good adhesion of the photoresist to the silicon substrateis essential in order to ensure a proper fixation of the wirerods during the dicing process. Figure 4(d) depicts that thephotoresist tends to peel off with decreasing dicing pitch (i.e.nickel rod length) on substrates that are treated with standardhexamethyldisilazane (HMDS) as an adhesion promoter. Inorder to increase the yield of the wire cutting process, thebond strength between the carrier substrate and the novolac-based photoresist was increased by a custom-made adhesionpromoter. The silicon carrier substrate was immersed ina solution of 5% 3-(triethoxysilyl)propylsuccinicanhydrideand 95% Toluene for 10 min. The wafer was then rinsedwith Toluene, blow-dried and finally baked in a oven at atemperature of 105 ◦C for 10 min. The applied silane reactswith the wafer surface via a silanization reaction, forming avery thin, covalently bonded organic layer. Upon completion ofthe silanization step, a very dense concentration of anhydridegroups is exposed on the surface. Anhydride groups readilyreact with the hydroxyl groups present in the uncured novolac

photoresist, that is applied later on. After the aforementionedtreatment, the wires were manually placed on a dummy waferand fixated with blue tape at the outer perimeter of a carrier,as shown in figure 4(a). A layer of AZ R©4562 photoresist wasthen spin-coated on the carrier wafer at 1000 rpm for 30 s. Thephotoresist was soft baked on a hotplate at a temperature of50 ◦C for 3 min. A low soft-baking temperature was chosen inorder to retain sufficient elastic properties of the polymer. Asdepicted in figure 4(c), the nickel wires were fully embeddedin the photoresist matrix. A DAD 320 (DISCO Corporation,Japan) wafer dicing tool that was equipped with a 38 μmwide dicing blade was used to cut the wires. The dicingfeed speed was 10 mm s−1. The accurate alignment of thedicing tool allowed for perfectly perpendicular cuts and thelength of the rods could be precisely controlled by the dicingtool. Figure 4(e) shows that the resist fully adheres to thesilicon surface and does not peel off for dicing pitches of150 μm. That way a yield of 100% for the cutting processcould be achieved. Subsequently, the nickel rods could easilybe released by dissolving the resist layer with acetone. Thisprocess allows a very precise cutting of many wires in paralleland can produce several thousands of nickel rods per run.Laser cutting or automated wire cutting tools may serve as analternative method especially for a high-volume production ofnickel rods.

2.3. TSV fabrication

The fabrication process for the TSVs is illustrated in figure 5and is based on double-side polished 100 mm Si wafers witha 2 μm thick silicon dioxide layer on both sides, which wascreated by thermal wet oxidization at 1100 ◦C. The oxide acts

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J. Micromech. Microeng. 22 (2012) 105001 A C Fischer et al

Silicon Silicon Oxide

Nickel

BCB

Gold

Via

F

orm

atio

nV

ia F

illin

g by

Mag

netic

Ass

embl

yV

iaC

onta

cts

NS

NS

NS Magnet

(a) (b) (c) (d )

(e) (f ) (g) (h)

(i ) ( j ) (k)

Figure 5. The TSV fabrication scheme can be divided into three main steps. First is the formation of the via hole by DRIE etching, second isthe magnetic assembly of the conductive TSV core and third is the filling with the dielectric.

MagnetArray Chip

Array Chip

Magnet

(a)

(b)

5 mm

d

d

MovementPattern A

MovementPattern B

Figure 6. Movement patterns of the assembly robot. (a) Smalladvancing rectangles with an edge length of d = 0.76 mm. (b) Longlinear sweep with a length of approximately d = 1.5 cm. Thesweeping is based on a radial movement of the robotic arm. In bothillustrations the sweeps are approximated to straight linearmovements due to the large radius of the radial movement(approximately 0.75 m) and the comparable short sweep length d.

both as a hard mask for the DRIE step and as an electricalinsulator for the metal lines, which will finally connect thevia on the frontside and backside of the substrate. A standardlithography on the frontside of the substrate defines the circularopenings for the vias. The silicon dioxide is dry-etched byRIE, as illustrated in figure 5(b). As depicted in figure 5(c), aBosch DRIE process creates via holes with straight side walls.The DRIE stops at the silicon dioxide on the bottom of thecavity. A subsequent high temperature treatment at 1100 ◦Cin a furnace is used to remove polymer residuals from the

DRIE passivation cycles by pyrolization. In the same furnace,a thermal oxidation at 1100 ◦C creates a 0.5 μm thick silicondioxide layer, as shown in figure 5(d). The silicon dioxidelayer ensures an electrical insulation of the via sidewalls andcreates a hydrophilic surface on the via sidewall, which is ofimportance for the insulation step that is carried out later on.

The pre-fabricated nickel cores are then distributed on thefrontside of the target wafer. By utilizing the robotic assemblytool, the permanent magnet on the assembly arm can be movedinto close proximity of the backside of the wafer, as indicatedin figure 5( f ). The nickel wires that are manually placed onthe wafer surface are drawn to the location of the magnetand erect themselves perpendicular to the substrate surface.With programmed patterns for the magnet movement, all viaholes can be filled in an automated process. The results ofthe performed assembly experiments, including the movementpatterns and the yield of the filling process, are presented insection 4.

The via cavities are subsequently filled with thethermosetting polymer BCB CYCLOTENE R© 3022-46(figure 5(g)), which is known to be suited for a void-freefilling of high aspect ratio features [43]. In order to reducethe viscosity of the polymer, the substrate is placed on ahotplate with a temperature of 60 ◦C before the polymer ismanually applied to the wafer surface using a syringe. Asthe polymer is not spin-coated, the resulting polymer layerhas a non-uniform thickness on the order of 100−150 μm.The subsequent hard-curing of the BCB is performed on ahotplate in a vacuum chamber using the temperature profileaccording to the manufacturer’s standard process procedures[26]. The entire curing procedure was performed in a vacuumenvironment at 0.02 mbar in order to prevent any void for-mation in the polymer. A subsequent grinding and polishingstep removes excess nickel and BCB from the surface of thesubstrate, as shown in figure 5(i). A lithography and RIE ofthe silicon dioxide and BCB residues opens the contact areaof the via on the backside of the wafer, as illustrated in

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J. Micromech. Microeng. 22 (2012) 105001 A C Fischer et al

figure 5( j). Two consecutive TiW/Au depositions(50/1000 nm) on both sides of the wafer interconnectsthe nickel cores of the vias. A lithography, wet Au etch anddry TiW etch (figure 5(k)) are made to define the Kelvin teststructures.

3. Experimental results

The performance of the robotic assembly setup in terms ofassembly speed was evaluated and an optical inspection andan electrical characterization of the fabricated TSVs wereperformed.

3.1. Automated magnetic assembly

A series of assembly experiments with different movementparameters was conducted. As shown in figure 6, the magneticassembly process was performed on array structures ofvia holes with an excessive amount of nickel wires ofapproximately 2500–3000. The wires in these experiments hada diameter of 35 μm and a length of 360 μm. The via holeshad a diameter of 42 μm and were fabricated in arrays of 10 ×10 vias with a pitch of 350 μm on a substrate with a thicknessof 350 μm. With respect to the array size of 3.5 mm and thesize of the cubic permanent magnet with an edge length of5 mm, two different movement patterns were programmed,as schematically illustrated in figure 6. The pattern infigure 6(a) has a very short sweep length d of 0.76 mm,whereas the pattern in figure 6(b) sweeps over the array with asweep length d of 1.5 cm. Furthermore, the experiments havebeen conducted at two assembly motion speeds, a fast motionat 120 ◦s−1 and a slow motion at 4 ◦s−1. The vertical distanceof the magnet to the backside of the wafer was approximately125 μm in all experiments.

As figure 7 shows, the filling rate, i.e. the number of filledvia holes per second, is dependent on the speed and the sweeplength d of the assembly motion. Larger sweep lengths resultin a faster filling process. The lateral force on the wires only

0

10

20

30

40

50

60

70

80

90

100

0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 160 170 180 190 200 210

Time [s]

Yie

ld -

Fill

ed H

ole

s [%

]

Fast pattern A (fig. 6 a)Fast pattern B (fig. 6 b)Slow pattern B (fig. 6 b)Slow pattern B (fig. 6 b)

Figure 7. Filling rates for the assembly of via arrays (10 × 10holes). Two different movement patterns and two different speedswere tested. The slow patterns exhibited a yield of 100% and thehighest filling rate.

occurs due to a gradient in the magnetic field, which is moreprominent near the edge of the cubic magnet. For small sweeplengths, this implies that the wires located above the centreof the magnet move very little or not at all, which explainsthe poor filling rate from the movement pattern shown infigure 6(a). Also shown in figure 7, the assembly processimproves with decreasing speed of the assembly motion.A fast assembly motion causes the wires to tilt from theirperpendicular position while being dragged along the substratesurface which makes it more difficult to pull them into the viaholes. Slower motion speeds reduce the wire tilt and thereforeincrease the filling rate. As shown in figure 7, a filling yield of100% within 66 to 81 s could be demonstrated by using themovement pattern indicated in figure 6(b) and a slow motionspeed of 4 ◦s−1.

As shown in figure 8, assembled wires that are protrudingthe substrate surface act both as a mechanical and magneticobstruction for the excess wires during the assembly process.

Figure 8. SEM image of a 30 × 30 array with a pitch of 120 μm of nickel wires placed in the via hole prior to the filling of BCB. Theminimum via hole diameter for a 35 μm wire was determined to be 40 μm.

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J. Micromech. Microeng. 22 (2012) 105001 A C Fischer et al

100 µm

AAluminum

Nickel

BCB

Silicon

Aluminum

Nickel

BCB

Silicon

(a) (b)

Figure 9. (a) SEM image of a polished cut through a TSV with an aspect ratio of 8. Note: as indicated in the drawing, the sample was tiltedduring the grinding process of the cross section, which leads to the apparent view of a non-constant via diameter, from [18]. (b) Opticalmicroscope image of a polished cut through a TSV with an aspect ratio of 31 for the metal core and an overall aspect ratio of 24.

DMM

Dual In-Line Package (DIP)

Au Wire Bonds(b)

(a)

Figure 10. (a) Test chip with a 10 × 10 TSV array that has beenmounted in the cavity of a 24-pin dual in-line package (DIP).(b) Illustration of the contacting scheme for the four-wire resistancemeasurement of a chain of two TSVs.

These two effects have a negative impact on the filling rate. Inorder to overcome the mechanical obstruction, the wires canbe cut to a length that is the same or shorter as the depth ofthe via holes. Due to the magnetization of the nickel duringthe assembly process, the excess wires can stick to the endsof assembled wires and cluster even if the assembly-magnetmoves on. It is possible to demagnetize and thereby eliminatethe clustering of the ferromagnetic nickel rods by reversingthe magnetic field by either flipping the permanent magnetor using an alternating magnetic field that is induced by aelectromagnet. By flipping the permanent magnet it was evenpossible to fill a via array with a very dense pitch of 120 μmwith wires that were considerably protruding the surface byapproximately 150 μm, as shown in figure 8.

Potentially, the assembly process can be improved andfurther accelerated by the implementation of a direct optical

inspection feedback. The camera, depicted in figure 3, thatis mounted on the assembly robot has only been used formonitoring the assembly process in our experiments. By usingan automated pattern recognition, the software can be extendedto be able to identify filled and empty holes. This informationcan then be used to implement a feedback loop for the assemblymovement. Thus, an adaptive optimization of the assemblymovement during operation can be obtained. Moreover, thisaddition would provide the assembly process with an inherentquality control functionality that detects unfilled via holes.

3.2. Cross-section inspection of filled TSVs

In order to evaluate the filling with dielectric and nickel,several polished cuts through magnetically assembled TSVshave been prepared and inspected by optical microscopy andscanning electron microscopy (SEM). As shown in figures 9(a)and (b), the filling with BCB was successfully conductedwithout any visible air-voids or defects after the completehard curing procedure. Also, due to the use of wire as a basematerial, the nickel core is inherently void-free. There are noindications for delamination of the BCB at the via side wallsor the via core, which might cause mechanical or electricalfailures of the vias. Figure 9(a) shows the cross-section of amagnetically assembled TSV with an aspect ratio of 8 thatconsists of a nickel core with diameter of 35 μm, a length of325 μm and a via hole diameter of 40 μm. As depicted infigure 9(b), a similar inspection was performed with amagnetically assembled TSV with an aspect ratio ofapproximately 24. This TSV consists of a nickel core withdiameter of 15 μm and a length of 470 μm that was assembledin a via hole with a diameter of 20 μm.

3.3. Electrical characterization

The electrical resistance of magnetically assembled nickelTSVs with a diameter of 35 μm and a length of 250 μmhas been evaluated. A chip with a 10 × 10 array of TSVswith a pitch of 350 μm was mounted in a ceramic dual in-line package with an open cavity (figure 10(a)). As illustratedin figure 10(b), each via was contacted on the frontside withtwo wire bonds that have been placed with an automatic wirebonder model ESEC 3100+. On the backside, the vias are

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J. Micromech. Microeng. 22 (2012) 105001 A C Fischer et al

electrically connected by a blank metallization. A four-wiremeasurement was performed on 25 pairs of TSVs (i.e. 50TSVs) using a HP 34401A digital multimeter. The measuredtotal resistance is in average 83 m� for two TSVs, includingtheir contact metallization on the frontside and backside ofthe chip. This is in good agreement with the theoreticalresistance of one pair of Ni TSVs of the given dimensions,which is approximately 40 m�, excluding any contactmetallization.

4. Conclusions

The fabrication of TSVs with aspect ratios of up to 24based on an automated magnetic assembly process has beendemonstrated. Smaller TSV diameters and higher aspectratios are feasible but limited by the smallest commerciallyavailable diameter of ferromagnetic wires, which is to ourknowledge currently 10 μm for nickel. The novel automatedmagnetic assembly process enables a high-speed filling of TSVholes with high aspect ratio via cores for low- to medium-I/O density applications such as interposers and MEMS.The presented concept addresses main fabrication objectivesrelevant for state-of-the-art, low-resistance metal TSVs suchas reliable fabrication of high aspect ratio vias, void-freesolid metallizations, sufficient thermo-mechanical stabilityand reduction of fabrication costs.

Acknowledgments

This work has been funded in part by the European ResearchCouncil (ERC) through the Starting grant (no 277879).The authors also would like to thank Nora Heinig for hercollaboration and technical support.

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