Versatile Gate

8/8/2019 Versatile Gate

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VERSATILE GATE FOR ARTIFICIAL NEURAL NETWORK CIRCUIT

Abul hasanat Muhammad jahanur rahman email: [email protected]

Texas A&M University and College of North Atlantic [email protected]

Member of IEEE and AIChE Mobile: +974-5408676

ABSTRACT

This paper provides descriptive design analysis of an innovative device called Versatile gate by

analyzing its electronic structure. The prime purpose of this device is to introduce hardware baseflexible neural network system which can change internal electronic structure by changing the

gates arrangement. Currently electronics circuit chips are made based on basic logic gates like

AND, OR, NOR etc. Once they are embedded, the chip structure is permanent. This Versatile gate removes this hindrance through its multipurpose function of converting into any one of the

basic six logic gates based upon input control signals. In short, any circuit architecture can be

made only using this gate and using external software they can be turned into series or parallel

connection of AND or NOR or XOR gates. It’s like hardware base artificial neural network chip,whose internal logic gates arrangement can be changed through software control. Because this

gate can act like any other logic gates one at a time. This can introduce flexible AI (artificial

intelligent) Microchip in its basic level.

It is a multipurpose device, which can be transformed into any types of gates, amplifier,

differentiator, and integrator. It has control inputs which guides transformation of this device.This implies that any chip made of this device can change hardware structure just by using

software program. This enables hardware upgrading without buying new chips. This reduces

electronic wasteland, which proves that it is very ergonomic and environmental friendly.

RESEARCH PURPOSE

• This versatile logic gate can perform various gate functions by selecting control inputs

• Demonstrate its capability to function as amplifier, differentiator, integrator, XOR, AND,

OR, NOT and its inverse gates

• Experiment is continuing to make it as close as possible to ideal op-amp functionality, for

example infinite open-loop gain, infinite bandwidth, infinite input impedances resulting

in zero input currents, infinite slew rate, zero output impedance and zero noise.

• Reduce inverse relationship between bandwidth and gain and also noise interference.

• It is made of high impedance CMOS transistor for higher input resistance and wide

bandwidth with low impedance BJT transistor at the output for lower impedance.

• Introduction of internal harmonic resonance power regulator circuit and ring bus

feedback system in this gate for further advancement.

mailto:[email protected]









CIRCUIT DESIGN

It has two main parts known as master and slave. First one is called “Logic network” and later

one is “Balancing network” which is a upgraded structure of op-amp. The main part is the master

or “Logic network”, which provides transformation functionality of changing from one logic

gate to another. It has twelve control inputs and three outputs. Input 1 and 8 are main control

system or power inputs. Channel inputs have complementary sides with each other either one

have to be logic 1(positive power source) and other 0 (negative source). It consists of two

enhanced MOSFET connected with four JFET complementary differential circuits. These JFETs

have internal dynamic memory functionality for the main channel input. This JFET has control

gate (CG) and floating gate (FG) that is insulated all around by an oxide layer. The FG is between the CG and the substrate and acts like a capacitor to store the binary information on it as

a static memory. When electrons are on the FG, they modify (partially cancel out) the electric

field coming from the CG along with the threshold voltage of the cell. Depending on this

tunneling voltage on the CG, electrical current will either flow or not flow.



This is controlled by the number of electrons present on the FG. The presence or absence of this

charge level (incoming signal from input 2 and 5) is sensed and translated into 1s and 0s. These

four JFETS of this logical circuit are programmed by starting up electrons flowing from the

source to the drain through two master inputs through hot-electron injection process. The bit can

be erased by a large voltage differential between the CG and source. Input 3, 4, 6 and 7 are

control inputs connected through micro thyristor switch which induces different functionality

based on the logical input arrangement. Input 2 and 5 are for digital or analog data input. In the

following logic table, different configuration of this gate is given based upon eigth control inputs

(four SCR inputs and four AUX inputs). Rests are for data inputs and outputs. Any one or all

three outputs can be used. Usually these three outputs are directly connected “balance network”

which is slave part, not necessary for the main function of this versatile gate. In the table ‘X’

indicates either 1 or 0 bit. ‘-’ means no signal needed or open circuit connection.

G

AUX INPUTSCR INPUTCHANNEL INPUT

Input 2&5MASTER

INPUT

Input

12

Input

11

Input

10

Input

932B

Input733B

Input634B

Input435B

Input336B

P-JFET

(2)37B

P-JFET

(1)38B

n-JFET

(2)39B

n-JFET

(1)40B

Input841B

Input1

43B

X44B

X45B

X46B

X47B

048B

049B

150B

151B

X52B

X53B

X54B

X55B

X56B

1

57B

N58B

X59B

X60B

X61B

X62B

163B

164B

065B

066B

X67B

X68B

X69B

X70B

171B

X

72B

A73B

X74B

X75B

176B

X77B

078B

079B

180B

081B

X82B

X83B

X84B

X85B

-86B

-

87B

A88B

X89B

X90B

X91B

192B

093B

094B

095B

196B

X97B

X98B

X99B

X100B

-101B

-

102B

N103B

X104B

1105B

X106B

X107B

0108B

1109B

0110B

0111B

X112B

X113B

X114B

X115B

-116B

-

117B

N118B

1119B

X120B

X121B

X122B

1123B

0124B

0125B

0126B

X127B

X128B

X129B

X130B

-131B

-

132B

X133B

X134B

1135B

X136B

1137B

0138B

1139B

0140B

1141B

X142B

X143B

X144B

X145B

-146B

-

147B

X148B

1149B

X150B

1151B

X152B

1153B

0154B

1155B

0156B

X157B

X158B

X159B

X160B

-161B

-

162B

X163B

X164B

X165B

X166B

X167B

1168B

1169B

1170B

1171B

X172B

X173B

X174B

X175B

1176B

1



Output 1 and 2 are complementary of each other. Based upon eight control inputs, 8 bits signal is

required to change the internal function of this versatile gate. In the following demonstration,

data inputs 5 and 2 are feed with logic high or 1 for one time functioning as OR gate and another

time as AND gate by changing the eight control inputs according to above table.



From the voltage meter, value is zero and current has value above zero which indicates output is

logic high or one. Likewise other truth table of different logic gates can be carried out by this

versatile gate (The program used here is MultiSim7). For the slave or “balancing network” of

this gate, it is just a modified op-amp for stabilizing the gate’s signal process. It has push-pull

complementary amplifiers, level translator and current sensing bridge, current limiter, offset

remover and signal stabilizing through emitter follower feedback transistor connects back to the

source reducing saturation distortion and increases bandwidth. It has internal filter that smooth

out the voltage signal level by removing (spike or noise) sideband harmonic distortion or ripples.

The circuit within the black box in the above figure has two open base inputs for two cascade

amplifier where outputs 1 and 2 goes in. One single output comes out from circuit at the end

within the green box, which has NOT gate configuration that can be turn on or off. This whole

design with master and slave connected together can act as clock or counter since master can

produce two complementary output signals. The clock speed depends on internal capacitance



called transient response (τ = RC). Its Miller capacitance can decrease bandwidth and increase

noise. In order to reduce this effect, capacitive schottky transistors (it has low forward voltage

drop and a very fast switching action) must be used for high processing speed and bandwidth.

External crystal or RLC filter circuit can also be added to the slave section of this gate. In the

blue box of the above figure, this circuit provides a constant voltage drop between its collector

and emitter regardless of the current passing through it. If the base current to the transistor is zero

then voltage between base and emitter becomes equal to threshold voltage, which makes the

current flowing through the two bridge resistors with same value. This serves to bias the two

output transistors slightly into conduction reducing crossover distortion. Current limiting circuit

(yellow box) increases source impedance along with high differential gain.

CONCLUSION

• It enables hardware base artificial neural network (ANN) circuit design like human brain(neurons) instead of software base ANN circuit using fuzzy logic.

• 3B

It can be used to build upgradeable microprocessors and microcontroller, whose hardware

structure can be changed.

• 184BIt can be used to build Random access decoder (RAD) whose address code can be

changed using external signal or software.

• 185BIt can operate as Digital to Analog converter and vice versa, oscillator, comparator,

modulator and demodulator for amplitude, frequency and phase modulation based upon

the configuration of the slave circuit .

• 186B

It can miniaturize the circuit. Since same amount of gates can be used to make different

circuit structure for different functions within the same chip. For example, a microchip

made with this gate can be turned into any Intel or AMD chip through programming .This

enables hardware upgrading without buying new chips. This lower electronic wasteland.

Versatile Gate

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