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Transcript of verilog - University of Malta · PDF fileVerilog and Concurrency • In the behavioural...
Verilog
• Like VHDL, Verilog HDL is like a programming language but:
– Statements can execute simultaneously unlike programming
– e.g. nand (y1,a1,b1);
nand (y2,a2,b2);
or (out,y1,y2);
– all statements await changes on their inputs and the first to see such a change will ‘execute’ to update its output
1
2
3
1
2
3
1
2
3
a1
b1
a2
b2
y1
y2
out
Verilog and Concurrency
• In the behavioural realm, there are 2 types of assignment
– Continuous assignment
• assign <identifier> = <expression>
• assign y1 = a1 & b1;
• assign y2 = a2 & b2;
• assign out = y1 & y2;
– Statement is executed when the terms in the expression change value independent of the ordering of the statements
Verilog and Concurrency
• In the behavioural realm, there are 2 types of
assignment
– Procedural assignment
• More like traditional computer programs
• Statement executes when encountered in source code
sequence
• Left hand side is retain until overridden and not
necessarily re- evaluated when the right hand side
terms changes in value
• y1 = a1 & b1;
Anatomy of a Verilog HDL model
module <module_name>;
<declarations>
<instantiations>
<assignments>
<task and function definitions>
endmodule
Verilog Syntax
• Verilog is case-sensitive by default
• Lexical tokens are separated by white space (spaces, tabs, newlines)
– e.g. a = 0;
OR
a
=
0
;
– Statements are terminated by semicolon except endmodule, begin, end, fork, join, endtask,endfunction
Identifiers and Keywords
• Identifiers used for names of modules, netsmstorage registers and instances
• Must begin with letter
• Can contain letters, digits and underscore
• Keywords are reserved and define the language constructs of Verilog (e.g. module, if, begin)
• Certain built-in system functions and tasks start with $ (e.g. $stop or $display)
Verilog Declarations
• Datatypes:– Nets
• For signals driven in structural instances or continuous assignments
• Different types for resolving contention in different ways
• e.g. wire, tri, supply0/1
– Register- type• Driven by procedural assignment
• Retain driven value till overridden
• reg: - for storing the state of electrical signals in behavioural models
• integer, real: - for storing numerical data in behavioural models
• time: - for storing values of the simulation time in behavioural models
Verilog Declarations - Examples
module My_test1;
wire data, q, qbar;
reg clk, reset, preset;
<assignments>
<instantiations>
<task and function definitions>
endmodule
Net and Register Objects
• Verilog integer is a 32-bit object
• Verilog real is a 64-bit object
• Nets and registers represent, by default, 1-bit
signals
e.g. wire w, x, y; // 3 one-bit nets
reg r, s, t; // 3 one-bit registers
• Verilog bit can have 4 values – 0, 1, x
(unknown) or z (undriven)
Vector Nets and Registers
• Can declare vector nets and registers
wire [3:0] a,b ; //Two 4-bit nets
reg [15:8] g, h; //Two 8-bit registers
• Can declare memories
reg [7:0] mem1[0:255]; //One 8x256
• Can only set or retrieve a whole word at a
time (e.g. 8-bits from above example) from
memory
Verilog Assignments
• In its simplest form, a Verilog assignment sets
the whole or part of a net or register (l.h.s.) to
the result of an expression (r.h.s.)
• Expressions
– Constants
– Expressions involving operators and one or more
operands
– Results of functions
Verilog Constants
• Verilog constants have a size
• Their size may be the same or different from the size of the object to which they are being assigned
• Numerical constants (except reals) have 3 part specification– Size in bits of the constant
– Base -> h (hex) d (decimal) o (octal) b (binary)
– Value• e.g. 16’h1a3f – 16-bit hex number, 5’b10101, 239 (default
decimal)
Verilog Constants
• String constants must be enclosed in double
quotes – 8-bits required per character –
– “Bus busy” (requires 64-bits)
• Real constants
– Scientific or decimal notation
– Decimal values must have digit before decimal
point
Expressions using Operators
• Binary operators take 2 operands
– Arithmetic operators: +,-,*,/,%
– Comparison operators: <,>,<=,>=,==,!=,===,!==
– Logical operators: && (and),|| (or)
– Bit-wise: &, |, ^ (xor), ^~ (xnor)
• For logical operations
– Zero is FALSE, Non-zero is TRUE
Expressions using Operators
• Unary operators take 1 operand
– Arithmetic operators: +,-
– Logical Not: !
• Bit Shift operations: >>,<<
• Conditional: a?b:c
• Concatenation: {a,b}
• Multiple Concatenation: {n{a,b}}
Procedural Assignment 1
• Procedural assignment is the only way to set
up stimuli to drive a system
• Values are assigned to registers
• Values are retained until reassigned
• They can be introduced by the initial construct
• They can be introduced through the always
construct
initial construct
• All initial constructs begin executing concurrently at simulation_time = 0
• Syntax is initial <statment>;
• begin/end construct can be used to initiate a sequence of assignments starting at time = 0
initial
begin
<statements>
end
always construct
• Any always constructs begin executing concurrently at simulation_time = 0
• As each always construct completes execution, the whole construct begin executing again from the beginning
• begin/end can be used with always to execute a group of statementalways
begin
<statements>
end
delay control
• delay controls are used to control the simulation time at which statements are executed– Two forms:
• Explicit form: # <delay_value>
• Event form: @<event_occurrence>
e.g.
initial
begin
a=0;
#20 a=1; //a becomes 1 at simulation time 20
#50 a=0; //a becomes 0 at simulation time 70
end
delay control
e.g.
always
@(posedge reset) q=0;
//q is reset when the reset signal rises
– Can equally use @(negedge) or @(<signal>) to be
sensitive to changes
Gate Level Modelling
• Verilog contains some built-in gate primitives
• Normal gates: - and, nand, or, nor, xor, xnor, buf, not
• Tristate gates: - bufif0, bufif1, notif0, notif1
• Unidirectional MOS switches: - nmos, pmos, cmos, rnmos, rpmos, rcmos
• Bidirectional pass devices: - tran, tranif0, tranif1, rtran, rtranif0, rtranif1
• Constant load primitives: - pullup, pulldown
Gate Connections
• Gates and, nand, or, nor, xor, xnor have one output which appears first in the port list and an arbitrary number of input after
• Gates buf and not have an arbitrary number of outputs, which appear first in the port list and a single input after that
• Devices bufif, notif, nmos, pmos, tranif has one output (first), one data input and one control input
Gate Connections
• cmos devices contains one output, one data
input and two control inputs
• tran devices – two bidirectional ports
• Gate instances –
– and (weak0, strong1)#(1:2:3, 2:3:4) g(out,in1,in2)
-- driver strengths
-- delay for signal goes to 1:0:Z
Module Instances
lower g1 (i, o, clock, out,in) //module instance
.....
.....
module lower (in1, out1, clk, out2, in2);
wait construct
• Comparing:
@(posedge clk) statement; with
wait (clk) statement;
• With the first construct, statement will not be executed until another rising edge occurs on clk, even if clk is already high
• With the latter construct, if clk is already high, statement will execute immediately – wait is a level sensitive construct
begin/end
• begin/end are used to group statements
• Statements within begin/end block execute
sequentially in the order they appear
fork/join
• Similar to begin/end but statements will
execute in parallel
fork
#20 a=10;
#50 b=b+1;
#15 q=d;
join
if
• Conditional constructs
– if (expression) statement;
– else if (expression) statement;
– else if (expression) statement;
– else statement
case
case (control_expression)
value_1: stat_1;
value_2: stat_2;
....
default: stat_last;
endcase
• casez treats ‘z’ as dont cares
• casex treats ‘x’ and ‘z’ as dont cares
Looping constructs
• for loop
– for (initial_expression; condition; iterated_expression)
– e.g. for (i=0; i<20; i=i+1) a[i]=0;
• Loop indefinitely
– forever statement;
• Loop a specified number of times
– e.g. repeat (count) statement;
• Loop as long as a condition is true
– while (condition) statement;
Tasks
• Tasks
– Method of grouping together logically connected statements so that they can be activated from several different places
– Optional arguments must be declared input, output or inout
– Can contain statements with timing controls
– Exits when its statement (begin/end) is complete
– Do not return a value, exit through output/inoutarguments
Task
task my_task;
<declarations including arguments>
..
<statements>
endtask
task invocation: my_task; OR my_task(a,b,x,y);
• Argument order must match order of argument declarations in task definition
• Arguments passed by value; input upon entry and outputs on exit
Functions
• Functions
– Return a single value
– Cannot include statements with timing controls
– Must have one or more arguments
– Cannot be called from tasks or vice-versa
– Optional function type if function does not return
a scalar