VERILOG QUESTIONS

1. What is the race condition in verilog.....? Ans :The situation when two expressions are allowed to execute at same instance of time without mentioning the order of execution.2. List the levels of abstraction in verilog.....? Ans : 1. Behavioral level 2. Register-Transfer level 3. Gate level 4. Switch levels3. Which are the two types of design methodologies? Ans : Top down and Bottom up4. Num = 'bX; What will be the value of Num? Ans : 8'bxxxx_xxxx5. What are the differences between wire and register? Ans : Wire just transfer input to output, Register stores the value as a variable until or unless another value replaces it.6. What are the differences between logical AND and reduction AND? Ans : Reduction and takes one operand and perform a bit by next bit operation.7. What is the difference between swapping the contents of two registers with temp register and without temp register? Ans : We use temp register in case of blocking statements to swap the registers contents. We wont use temp register for non blocking statements.8. How logical shift differs from arithmetic shift? Ans : In logical shift the MSB will be accumulated by zero's In arithmetic shift MSB will be accumulated by sign bit.9. What is the conditional operator and how it is used? Ans : Operator which assigns any one variable out of two by evaluating the expression mentioned in that operator. Syntax : cond_expr? true_expr:false_expr10. What is the difference between == and ===? Ans : == it is logical equality.=== it is case equality. 11. What exactly expression reg[8*13:1] string_val; signifies? Ans : Reg can hold up to 13 characters.12. When output port is generated by a submodule what will be the type of output a. register b. wire Ans : b13. List the built in primitives? Ans : gates, transmission gates and switches.14. Name the two possible ways by which we can instantiate the modules? Ans : Port order connection and Port name connection.15. Which assignment statement we usually use in dataflow modeling? Ans : A continuous assignment statement.16. What are rise delay and turn off delays? Ans :The rise delay is associated with a gate output transition to 1 from another value(0,x z) turnofff delay is associated with a gate output transition to z from another value(0,1,x)17. What is inter delay? explain with an example Ans : Delay where command waits for particular time steps before executing that command.ex: #10 a=b+c;18. What is intra delay? explain with an example Ans : Here the evaluated expression waits for specified time to assign value to LHS.ex : a = #10 b+c;19. What are the difference between inter and intra delays? Ans : Inter delay simply wait for appropriate no of time steps before executing the command.ex : #10 q = x + y;Intra delay wait for appropriate no of time steps before assignment of RHS to LHS.ex : q = #10 x + y; 20. Which is the stable one in the following a. #10 q=x+y; b. q= #10 x+y; Ans : b21. What are the differences between continuous and procedural assignments? Ans : Difference between continuous and procedural assignments. Continuous assignments procedural assignments 1 Assigns primarily to net Assigns primarily to reg 2 Values continuously drive to out put Values will be stored into variables 3 Occurs in assignments to wire,port and net Occurs in constructs like always,initial,task,function.22. What are the differences between assignment in initial and always blocks? Ans : Assignment in initial Assignment in always 1. Execute from time 0 in simulation and proceed in the specified sequence. This also begin from time 0, and repeat forever as a function of the changes on sensitivity list. 2. Execution stops when the end of the block is reached. Execution continuously repeats according to the change in values of sensitivity list. 3. Non-synthasizable Synthasizable23. What are the differences between blocking and non blocking statements? Ans : Blocking Non blocking 1. The evaluation of the expression of the RHS is updated to LHS autonomously based on delay. But here RHS will not be updated to LHS immediately 2. In case of multiple blocking assignments the trailing assignments are blocked. Multiple blocking assignments can be scheduled to occurconcurrently on next evaluation cycle. 3. There is a possibility of race condition in this. Race condition can be avoided. 4 Represented by = operator sign between LHS and RHS. Represented by < =operator sign between LHS and RHS.24. What are the differences between Task and Functions? Ans : Task Function1. Can contain time control statements like @(posedge). Executes in zero simulation time.2. Can call any number of function or tasks. Can call any number of functions but not tasks 3. Cannot return any value when called instead the task can have output arguments. It can return any value when called.25. How re-entrant task,function differs from static task,functions ? Ans : Re-entrant task,functions have a key word automatic between task and name of the task which replicates and allocates the variables. But it is not possible in static.26. How we can convert static task and function to re-entrant task and function? Ans : By adding key word automatic between task and name of the task.27. What is an effect of keyword automatic for re-entrant task? Ans : It replicates the variables and allocates the variables in task.28. What is an fork--join exactly mean? Ans : fork--join groups two or more statements together in parallel, so that all statements are evaluated concurrently.29. Which assignment statement will be used in Behavioral modeling? Ans : Procedural assignment statements.30. Always and initial blocks are called ______ blocks. Ans : Procedural31. What is sensitivity list? Ans : It is an event timing control that controls when all statements in the procedural block will start to be evaluated.32. What are procedural assignment statements? Ans : The statements within a procedure which executes sequentially.33. How we can avoid race condition? Ans : By using non blocking statements.34. How we can represent a blocking and non blocking assignments? Ans : Blocking can be represented by wire.Non blocking can be represented by latch.35. List process synchronization supported by verilog? Ans : event, fork and join, disable. 36. What actually event does? Ans : It suspends the process until specified event to occur.37. What wait does actually? Ans : It suspends the process until expression become true.38. What forever loop does? Ans : this loop executes continuously and never completes until you break it intentionally.39. When generate statements are used? Ans : Generate statements are used when the same operation or module instance is repeated for multiple bits of vector.40. List out the different methods to create generate statement? Ans : Generate loop, Generate conditional, Generate case.41. Which are the two types of UDP's in verilog? Ans : 1. Combinational UDP2. Sequential UDP42. Why RTL synthesis is important? Ans : It is important to improve designers productivity to meet today's design complexity.43. What is the difference between always with @ and always without @? Ans : The only difference is always with @ can be synthesized but not other one.The always without @ will be used only in test benches. 44. What is the difference between $display and $monitor? Ans : $display display its parameter whenever that is executed. $monitor display its parameter whenever the value of parameter changes.45. Write a code for 2:1 Mux? Ans : assign mux_out = (sel)? din_1 : din_0;46. Write a Verilog code which divides the clock by 2? Ans : always @ (posedge clk_in)if (reset)clk_out