Verilog misc rev a.ppt - Worcester Polytechnic Instituteusers.wpi.edu/~rjduck/Verilog misc rev...
Transcript of Verilog misc rev a.ppt - Worcester Polytechnic Instituteusers.wpi.edu/~rjduck/Verilog misc rev...
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Jim Duckworth, WPI Verilog (Misc) Module 1
Verilog
Misc
(blocking, time constraints, clocks, customizing
modules)
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Blocking Example (incorrect result)
Synthesizing Unit <blocking>.
WARNING:Xst:646 - Signal <c> is assigned but never used. This unconnected signal
will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <b> is assigned but never used. This unconnected signal
will be trimmed during the optimization process.
Found 1-bit register for signal <d>.
Summary:
inferred 1 D-type flip-flop(s).
Unit <blocking> synthesized.
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Non-Blocking (expected result)
Synthesizing Unit <non_blocking>.
Related source file is "non_blocking.v".
Found 1-bit register for signal <d>.
Found 1-bit register for signal <b>.
Found 1-bit register for signal <c>.
Summary:
inferred 3 D-type flip-flop(s).
Unit <non_blocking> synthesized.
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Jim Duckworth, WPI Verilog (Misc) Module 4
Timing Constraints
• Used to guide the synthesis tools
• Example 32-bit counter - no constraints (speed grades -4 and -5)======================================================
Advanced HDL Synthesis Report
Macro Statistics
# Counters : 1
32-bit up counter : 1
======================================================
Timing Summary:
---------------
Speed Grade: -4
Minimum period: 6.680ns (Maximum Frequency: 149.703MHz)
Minimum input arrival time before clock: No path found
Maximum output required time after clock: 8.094ns
Maximum combinational path delay: No path found
===============================================
Speed Grade: -5
Minimum period: 5.767ns (Maximum Frequency: 173.400MHz)
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Jim Duckworth, WPI Verilog (Misc) Module 5
Adding timing constraint
• Add to UCF file:– NET "clk" PERIOD = 6ns HIGH 50%;
WARNING:Par:62 - Your design did not meet timing.
-------------------------------------------------------------------------------------------
Constraint | Check | Worst Case | Best Case | Timing |Timing | Slack | Achievable |
Errors | Score
-------------------------------------------------------------------------------------------
* NET "clk_BUFGP/IBUFG" PERIOD = 6 ns HIGH | SETUP| -0.456ns | 6.456ns | 9| 1430
50% | HOLD | 2.432ns | | 0| 0
-------------------------------------------------------------------------------------------
1 constraint not met.
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Jim Duckworth, WPI Verilog (Misc) Module 6
Try relaxing constraint
• NET "clk" PERIOD = 6.5ns HIGH 50%;
----------------------------------------------------------------------------------
Constraint | Check| Worst Case | Best Case | Timing | Timing | Slack| Achievable |
Errors | Score
----------------------------------------------------------------------------------
NET "clk_BUFGP/IBUFG" PERIOD = 6.5 ns HIG | SETUP| 0.203ns| 6.297ns| 0| 0
H 50% | HOLD | 2.280ns| | 0| 0
----------------------------------------------------------------------------------
All constraints were met.
• Also see Timing Constraint User Guide
• Examples:
NET ‘abc’ OFFSET = OUT xx ns AFTER ‘clk’;
NET ‘def’ OFFSET = IN xx ns BEFORE ‘clk’;
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Jim Duckworth, WPI Verilog (Misc) Module 7
Clock Skew
• The difference between the time a clock signal arrives at
the source flip-flop in a path and the time it arrives at the
destination flip-flop.
– Misalignment of clock edges
– Degrades (reduces) time for flip-flop to flip-flop timing
• Can be caused by different things but wire interconnect
delays are the main cause inside FPGAs
– There are fast dedicated clock circuits and slower data paths
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Jim Duckworth, WPI Verilog (Misc) Module 8
Old method of deriving slower clocks
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Jim Duckworth, WPI Verilog (Misc) Module 9
WARNING:Route:455 - CLK Net:clk_1Hz may have excessive
skew because 0 CLK pins and 1 NON_CLK pins failed to
route using a CLK template.
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Jim Duckworth, WPI Verilog (Misc) Module 10
Synthesis uses two clock signals
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Jim Duckworth, WPI Verilog (Misc) Module 11
Two clock signals – not good!
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Jim Duckworth, WPI Verilog (Misc) Module 12
Modify to only use one clock signal
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Jim Duckworth, WPI Verilog (Misc) Module 13
Clock signals use dedicated lines
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Jim Duckworth, WPI Verilog (Misc) Module 14
Clock drives all flip-flops
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Jim Duckworth, WPI Verilog (Misc) Module 15
Verilog Lower Level Module with Parameters
Jim Duckworth, WPI
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Jim Duckworth, WPIVerilog (Misc) Module
16Jim Duckworth, WPI
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Jim Duckworth, WPI Verilog (Misc) Module 17
Three copies of XYZ module
Jim Duckworth, WPI
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Jim Duckworth, WPI Verilog (Misc) Module 18
RTL Schematic showing 3 modules
Jim Duckworth, WPI
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Shift Register – Fixed Size
Jim Duckworth, WPI Verilog (Misc) Module 19
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Jim Duckworth, WPI Verilog (Misc) Module 20
Modifying Component Size
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Jim Duckworth, WPI Verilog (Misc) Module 21
Making two copies – different size
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Jim Duckworth, WPI Verilog (Misc) Module 22
Schematic of two shift registers
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Jim Duckworth, WPI Verilog (Misc) Module 23
(Misc) Using UCF to specify pin options
Jim Duckworth, WPI
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Jim Duckworth, WPI Verilog (Misc) Module 24Jim Duckworth, WPI
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Jim Duckworth, WPI Verilog (Misc) Module 25Jim Duckworth, WPI