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Transcript of verilog hdl chapter 4
7/24/2019 verilog hdl chapter 4
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E&C-ENG 5535Verilog HDL
Lecture 04Chapter 03
Language Elements
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Chapter Outline
! Language Elements
! Comments
! Identifiers
! Keywords! Bidirectional Gates
! Charge Storage Strength
! ……….
! Value Set
!
Compiler Directives
Chaudhry-Lecture 04, Ch. 03 29/2/15
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Chaudhry-Lecture 04, Ch. 03 3
Comments
! Two types:!
Single line comment
//This is a single-line comment on a dedicated line
! Multiple lines comment
/* This is a multiple-line comment.More comments go here.
More comments. */
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Chaudhry-Lecture 04, Ch. 03 4
Identifiers
! An identifier is a name given to an object or variable so that it can be referencedelsewhere in the design.! An identifier should be:
! Unique
! The first character must be a letter or underscore ( _ )! It is case sensitive.! Can contain up to 1024 characters
Input a, b, cin; //a, b, and cin are identifiers
output sum, cout; //sum and cout are identifiersreg z1;
! Escaped identifiers begin with a backslash ( \ ) and end with a white space (space,
tab, or new line) and provide means to include any printable ASCII character in an
identifier. For example; \assign is different than the keyword assign
\2005
\~$~\*************
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Category Keywords
Bidirectional gates rtrantran
rtranif0tranif0
rtranif1tranif1
Charge Storage Strengths large medium small
CMOS Gates cmos rcmos
Combinational Logic Gates andnorxnor
bufnotxor
nandor
Continuous Assignment assign
Data Types integerregtri
triandvectored
wor
realscalaredtri0
triorwand
realtimetimetri1
triregwire
Module Declaration module endmodule
MOS Gates nmosrpmos
pmos rnmos
Multiway Branching casedefault
casexendcase
casez
Named Event event
Parameters defparam parameter specparam
Port Declaration inout input output
Procedural Constructs always initial
Procedural Continuous Assignment assignrelease
deassign force
Keywords:Verilog has alist of specialpredefined,
non-escapedidentifierscalledkeywords.
5Chaudhry-Lecture 04, Ch. 039/2/15
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Category Keywords
Signal Strengths highz0pull1supply0weak1
highz1strong0supply1
pull0strong1weak0
Specify Block specify endspecify
Tasks & Functions function
task
endfunction
endtask
Three-State Gates bufif0notif1
bufif1 notif0
Timing Control edge negedge posedge
User-defined Primitives primitivetable
endprimitiveendtable
Procedural Flow control beginendforkrepeat
disableforifwait
elseforever
joinwhile
Pull Gates pulldown pullup
Keywords (Cont…)
6Chaudhry-Lecture 04, Ch. 039/2/15
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Chaudhry-Lecture 04, Ch. 03 7
Keywords: Bidirectional Primitive Gates
! The signals on either side of the gates can bespecified as inputs or inout.
! tran (transmission) gate (switch): act as a buffer
between two signals! tran, tranif0, tranif1, rtran, rtranif0, rtranif1
are bidirectional primitive gates
Example: tran inst1(inout1, inout2);
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Chaudhry-Lecture 04, Ch. 03 8
Keywords: Bidirectional Primitive Gates
! tranif0 and tranif1 have two bidirectional terminals
plus a control input.tranif0 inst1(inout1, inout2, control);
As, tranif0 gate connects the two signals only if thecontrol input is a logical 0, otherwise the output of the
gate is a high impendence.
! rtran, rtranif0, rtranif1 are called resistive gates. Theyoperate the same way as previous gates but have highersource-to-drain impedance.
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Chaudhry-Lecture 04, Ch. 03 9
Keywords: CMOS Gates
! A cmos gate can be modeled with nmos and pmos
device to implement cmos transmission gate.
! The rmos gate is high resistive version of the cmos
gate.
cmos inst1 (output, data_input, n_enable, p_enable);
nmos inst2 (output, input, control);
pmos inst3 (output, input, control);
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Chaudhry-Lecture 04, Ch. 03 10
Keywords: Value Set
! Sometimes {0,1} binary set is not enough torepresent the state of a switch.
! See the following case:
a
b
0
1
cIf a = b = 0, c = ?
If a = b = 1, c = ?
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Chaudhry-Lecture 04, Ch. 03 11
Keywords: Value Set ….
! a = b = 0, c = Z
! a = b = 1, c = X
! Initially, every line is X
! X is used in simulation.
!
In real circuit, the value is determined by thecircuit
a
b
0
1
c
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Chaudhry-Lecture 04, Ch. 03 12
Keywords: Value Set…
! 0: Logical 0; // false condition
!
1: Logical 1; // true condition
! X: Unknown logic value
!
Z: High impedance; // floating state
and 0 1 Z X
0 0 0 0 0
1 0 1 X X
Z 0 X X X
X 0 X X X
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Chaudhry-Lecture 04, Ch. 03 13
Keywords: Value Set…
! b = X-bar
!
But in Verilog, there is no such thing as “X-bar ”!
If b = X, and therefore a = X, which should be 0
X a = ? b
X and X-bar Problem
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Chaudhry-Lecture 04, Ch. 03 14
Keywords:Combinational LogicGates
and, nand, or, nor,xor, xnor, buf, not are all called
combinational logicgates
gate_type inst1(output,
input_1, input_2, …);
and
Truth table for ANDGate Built-In-
Primitive
Inputsx1 x2
Outputz
0 0 0
0 1 0
1 0 0
1 1 1
0 x 0
0 z 0
1 x x
1 z x
Inputsx1 x2
Outputz
x 0 0
x 1 x
x x x
x z x
z 0 0z 1 x
z x x
z z x
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Chaudhry-Lecture 04, Ch. 03 15
Keywords:Combinationa
l LogicGates…
or
Truth table for ORGate Built-In-
Primitive
Inputsx1 x2
Outputz
0 0 0
0 1 1
1 0 11 1 1
0 x x
0 z x
1 x 1
1 z 1
Truth table for ORGate Built-In-
Primitive
Inputsx1 x2
Outputz
x 0 xx 1 1
x x x
x z x
z 0 xz 1 1
z x x
z z x
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Chaudhry-Lecture 04, Ch. 03 16
Keywords: Combinational LogicGates…
Truth table for bufGate
Input Output
0 0
1 1
x x
z x
buf a non-inverting primitive with
one scalar input and one or
more scalar outputs.
buf inst1(output, input); //one output
buf inst2(output_1, output_2, …, output_n, input);//multiple outputs
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Chaudhry-Lecture 04, Ch. 03 17
Keywords:
CombinationalLogic Gates …
nand
Truth table for NANDGate for the AND
function
Inputsx1 x2
Outputz
0 0 1
0 1 1
1 0 1
1 1 0
0 x 1
0 z 1
1 x x
1 z x
Truth table for NANDGate for the OR
function
Inputsx1 x2
Outputz
x 0 1x 1 x
x x x
x z x
z 0 1z 1 x
z x x
z z x
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Chaudhry-Lecture 04, Ch. 03 18
Keywords
(Cont…)CombinationalLogic Gates…
nor
Truth table for NORGate for the OR
function
Inputsx1 x2
Outputz
x 0 x
x 1 0
x x x
x z x
z 0 xz 1 0
z x x
z z x
Truth table for NORGate for the AND
function
Inputsx1 x2
Outputz
0 0 1
0 1 0
1 0 0
1 1 0
0 x x
0 z x
1 x 0
1 z 0
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Chaudhry-Lecture 04, Ch. 03 19
Keywords: Combinational LogicGates…
notTruth table for the
logical NOT built-In-Primitive
Input Output
0 1
1 0
x xz x
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Chaudhry-Lecture 04, Ch. 03 20
Keywords: Combinational LogicGates…
xorTruth table for LogicalExclusive-OR Built-In-
Primitive
Inputsx1 x2
Outputz1
x 0 x
x 1 x
x x x
x z x
z 0 xz 1 x
z x x
z z x
Truth table for LogicalExclusive-OR Built-In-
Primitive
Inputsx1 x2
Outputz1
0 0 0
0 1 1
1 0 1
1 1 0
0 x x
0 z x
1 x x1 z x
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Chaudhry-Lecture 04, Ch. 03 21
Keywords: Combinational LogicGates…
xnor
Truth table for LogicalExclusive-NOR Built-
In-Primitive
Inputsx1 x2
Outputz1
0 0 1
0 1 0
1 0 01 1 1
0 x x
0 z x
1 x x
1 z x
Truth table for LogicalExclusive-NOR Built-
In-Primitive
Inputsx1 x2
Outputz1
x 0 x
x 1 x
x x x
x z x
z 0 xz 1 x
z x x
z z x
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Chaudhry-Lecture 04, Ch. 03 22
Keywords :Three-State
Gates…
Truth table for buff0
Input Control Output0 0 0
0 1 z
0 x 0/z
0 z 0/z
1 0 11 1 z
1 x 1/z
1 z 1/z
x 0 x
x 1 z
x x x
x z x
z 0 x
z 1 z
z x x
z z x
Truth table for buff1
Input Control Output0 0 z
0 1 0
0 x 0/z
0 z 0/z
1 0 z
1 1 1
1 x 1/z
1 z 1/z
x 0 z
x 1 x
x x x
x z x
z 0 z
z 1 x
z x x
z z x9/2/15
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Chaudhry-Lecture 04, Ch. 03 23
Keywords:
Three-StateGates…
Truth table for notif0
Input Control Output0 0 1
0 1 z
0 x 1/z
0 z 1/z
1 0 01 1 z
1 x 0/z
1 z 0/z
x 0 x
x 1 z
x x x
x z x
z 0 x
z 1 z
z x x
z z x
Truth table for notif1
Input Control Output0 0 z
0 1 1
0 x 1/z
0 z 1/z
1 0 z
1 1 0
1 x 0/z
1 z 0/z
x 0 z
x 1 x
x x x
x z x
z 0 z
z 1 x
z x x
z z x9/2/15
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Summary
! Language Elements
! Comments
!
Identifiers!
Keywords: Bidirectional Gates
Chaudhry-Lecture 04, Ch. 03 249/2/15