Verilog Basics 3 Assingments
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Transcript of Verilog Basics 3 Assingments
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Digital System Design
Verilog:Assignments
Dr. Bassam Jamil
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Topics
Blocks (Named, always, initial )
Continuous Assignment
Procedural Assignment
Blocking
Non-blocking
Event blocking (wait, @, #)
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Block Types
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Assignment Types: Overview
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Modeling
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Modeling Examples
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Continuous Assignment Statement
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Concurrent (Continuous) Assign Statement
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2-1 Mux Using Continuous Assignment
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4-1 Mux Using Continuous Assignment
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3-1 Mux Using Continuous Assignment
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8-bit MULT Using Continuous Assignment
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Procedural Blocking Assignment
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Event Control
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Event Control
# delay
delay execution for specific amount of time
@ ( signal )
Delay the execution until a logic transition on the signal
@ ( posedge signal) or @ (negedge signal)
Delay the execution until the specified transition on the signal
wait ( expression)
Delay execution until the expression evaluates True
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Blocking Assignment Example
wait for a to change: 0 to 1
posedge a
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Another Blocking Assignment Example
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Non-Blocking Assignment
Non-blocking assignment evaluates at the end of the time step.
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Blocking vs. Non-blocking (1)
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Blocking vs. Non-blocking (2)
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Blocking vs. Non-blocking (3)
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Delays and (Blocking vs. Non-blocking)
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Chain of 3 Registers Using Non-Blocking
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Same Chain Using Structural
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Implicit Event Expression List
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Implicit Event Expression List
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Implicit Event Expression List