Verilog: A simple UpDown Counter Implemntation
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A simple Up Down Counter implementation in verilog. If the state is Count Up the device will count up else count down.
Transcript of Verilog: A simple UpDown Counter Implemntation
UpDown Counter
Count to 15 then back to 0 and vice versa. `timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: // // Create Date: 11:19:04 12/19/2012 // Design Name: // Module Name: UpDownCounter // Project Name: // Target Devices: // Tool versions: // Description: // // Dependencies: // // Revision: // Revision 0.01 - File Created // Additional Comments: // ////////////////////////////////////////////////////////////////////////////////// module UpDownCounter( input reset, input enable, input clk, output count ); wire clk; wire reset; wire enable; reg [4:0]count; reg count_state; // 1 => Up; 0 => Down always @(posedge clk) begin if (enable && !reset) begin if (count_state) begin count = count + 1; if (count == 15) begin count_state = 0; end
end else begin count = count - 1; if (count == 0) begin count_state = 1; end end end else begin count = 0; count_state = 1; end end endmodule `timescale 1ns / 1ps //////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: // // Create Date: 11:31:31 12/19/2012 // Design Name: UpDownCounter // Module Name: D:/ACADS/ECE 195/UpDownCounter/UpDownCounter_tb.v // Project Name: UpDownCounter // Target Device: // Tool versions: // Description: // // Verilog Test Fixture created by ISE for module: UpDownCounter // // Dependencies: // // Revision: // Revision 0.01 - File Created // Additional Comments: // //////////////////////////////////////////////////////////////////////////////// module UpDownCounter_tb; // Inputs reg reset; reg enable; reg clk; // Outputs wire [4:0]count;
// Instantiate the Unit Under Test (UUT) UpDownCounter uut ( .reset(reset), .enable(enable), .clk(clk), .count(count) ); initial begin // Initialize Inputs reset = 0; enable = 0; clk = 0; // Initialize Inputs clk = 0; reset = 0; enable = 0; // Wait 100 ns for global reset to finish #10; reset = 1; enable = 0; #10; reset = 0; enable = 1;
#50 reset = 1; #10 enable = 0; #30 enable = 1; #50 reset = 0; #1000; $finish; end // Provide clock always begin #10 clk = !clk; end endmodule
