Verification Methodology of Gigabit Switch System 1999/9/9 Yi Ju Hwan.
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Verification Methodology of Gigabit Verification Methodology of Gigabit Switch System Switch System 1999/9/9 Yi Ju Hwan
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Transcript of Verification Methodology of Gigabit Switch System 1999/9/9 Yi Ju Hwan.
Verification Methodology of Verification Methodology of Gigabit Switch SystemGigabit Switch System
1999/9/9Yi Ju Hwan
AgendaAgenda
Design flow & Verification Example
Algorithm-level design & verification RT-level design & verification Gate-level verification
Introduction to Gigabit project Verification methodology of gigabit
switch system Summary
Design FlowDesign Flow
Create Project Spec. Decision
Spec.
Design FlowDesign Flow
Spec.
Design
Design & CodingSimulation
Verification
Tape-out
Design FlowDesign Flow
Fabrication
CHIP!!!
Testing
Design & Verification ExampleDesign & Verification Example
Motion picture
MPEG encodingMPEG bit stream
Broadcast system
Algorithm-level Design & Algorithm-level Design & VerificationVerification
MPEG encodingAlgorithm levelModel
Motion picture file
MPEG file
MPEG player
RT-level Design & VerificationRT-level Design & Verification
Motion picture file
MPEG file
MPEG player
Broadcast system interface modelMPEG encoder modelCamera interface
Model
Gate-level Verification Gate-level Verification (Hardware Emulation)(Hardware Emulation)
Motion picture
MPEG bit stream
Broadcast system
Emulator
Gigabit Ethernet Switch Gigabit Ethernet Switch ProjectProject
8x8 Switch Fabric 16 Gbps bandwidth
Gigabit Port Controller Individual lookup engine Full gigabit line-rate support
SF SF
PC PC
PC PC
PC PC
PC PC
PC PC
PCPC
PCPC
PCPC
NP NP
GMIIGMII
GMIIGMII
GMIIGMII
GMIIGMIIGMIIGMII
GMIIGMII
GMIIGMII
GMIIGMII
ExpansionExpansion
32x32 Switch with 12 SF, 32 PC
SF SF P
C P
C P
C P
C P
C P
C P
C P
C
SF SF
PC
PC
PC
PC
PC
PC
PC
PC
SF SF
NP
NP
SF SF
SF SF SF SF
PC
PC
PC
PC
PC
PC
PC
PC
PC
PC
PC
PC
PC
PC
PC
PC
NP
NP
SF SF
PC
PC
PC
PC
PC
PC
PC
PC
SF SF
PC
PC
PC
PC
PC
PC
PC
PC
SF SF
NP
NP
SF SF
SF SF SF SF
PC
PC
PC
PC
PC
PC
PC
PC
PC
PC
PC
PC
PC
PC
PC
PC
NP
NP
Verification StrategyVerification Strategy
Architecture-level verification High-level description in C-language Decision making about expansion scheme, architecture
Simulation with network environment model RT-level description in Verilog HDL Actual design & debugging with Virtual Network
Software emulation PC with Verilog simulator Verification with real network environment
Hardware emulation Hardware prototype board with FPGA Verification with other chipset (network processor, MAC
interface)
Building Environment ModelBuilding Environment Model(Virtual Network)(Virtual Network)
Captured packets Real application program Controlled traffic
• Use traffic generation routine of network simulator Various packets
• TCP, UDP, ARP, IPX...
RealRealNetworkNetwork
EnvironmentEnvironment
PacketPacketcapturecapture
Analysis &Analysis &FilteringFiltering
VirtualVirtualNetworkNetwork
EnvironmentEnvironment
GESIM(Architecture-level GESIM(Architecture-level Verification)Verification)
VnetVnet
VnetVnetI/FI/FTxTx
VnetVnetI/FI/FRxRx
ModelModel
PCPC
PCPCSFSF
SimulatorSimulator
EventEventHandlerHandlerSchedulerScheduler
ReceivedReceivedpacketspackets
ExecutorExecutorEventEventQueueQueue
ParametersParameters
PacketsPacketsto be sentto be sent
DebuggerDebuggerUnitUnit
C routineC routine
Virtual Network with PLI(RT-Virtual Network with PLI(RT-level Design & Verification)level Design & Verification)
VnetVnet
VnetVnetI/FI/FTxTx
VnetVnetI/FI/FRxRx
Verilog SimulatorVerilog Simulator
PCPC
PCPC
SFSF
ReceivedReceivedpacketspackets
ParametersParameters
PacketsPacketsto be sentto be sent
MACMACinterfaceinterface
(PLI)(PLI)
MACMACinterfaceinterface
(PLI)(PLI)
Software EmulationSoftware Emulation
RealRealNetworkNetwork
EnvironmentEnvironment
MACMAC(NIC)(NIC)
MACMAC(NIC)(NIC)
PCPC
PCPC
SFSF
MACMACinterfaceinterface
(PLI)(PLI)
MACMACinterfaceinterface
(PLI)(PLI)
NetworkNetworkProcessor(PLI)Processor(PLI)
SSRAMSSRAM SDRAMSDRAM
SSRAMSSRAM SDRAMSDRAM
PCPC VerilogVerilog
SimulatorSimulator
Advantage & Disadvantage of Advantage & Disadvantage of Software EmulationSoftware Emulation
No design change Easy to debug Easy to build system
No hardware design overhead
Functionality check with real network system
No hardware interface verification Slow emulation speed
300k gate RTL simulation: 100 cycle/sec @ 143MHz Ultra Sparc with VCS
Hardware EmulationHardware Emulation
RealRealNetworkNetwork
EnvironmentEnvironment
PHYPHY PCPC(FPGA)(FPGA)
SFSF(FPGA)(FPGA)
NetworkNetworkProcessorProcessor
SSRAMSSRAM SDRAMSDRAM
MACMAC(LUC3M08)(LUC3M08)
PHYPHY PCPC(FPGA)(FPGA)
SSRAMSSRAM SDRAMSDRAM
MACMAC(LUC3M08)(LUC3M08)
Prototype boardPrototype board
SummarySummary
Spec. decision Architecture level-simulation & verification
Design System modeling RT-level simulation & verification
Emulation Prototype board, Emulator, FPGA
