Velocity Toolkit Release Notes Developed by Jeffrey Platt Alliance ATE Consulting, Inc The Alliance Velocity Toolkit is designed to allow test engineers an easy and effective method for transferring data from design formats into test language formats. In addition, ports are provided for transferring data from one test platform to another. The following formats are handled

• Encounter, TetraMax and FastScan WGL • VCD and EVCD • Verilog VCT • Credence D10 STIL • Teradyne J750 • Teradyne J973 • Teradyne UltraFlex • Agilent 93K • Credence ASL3sK • First Silicon JTAG interface from TCL scripts • SMBus register dump representation • I2C register dump representation • General Purpose JTAG register write • Credence Sapphire • Catalyst TP (export only) • KVD DigMod (export only)

Release: September 15, 2005: ShellConstructor_V0.1 • Base functionality is available for both Windows and Linux platforms. This includes all of the above functions. • Source is included instead of formal documentation Release: September 21, 2005: ShellConstructor_V0.2 • Replaced windows installation with new utility for converting Windows based files to Unix based files. The program is called Unix2Win and is a 3rd party program that was purchased for re-release. • Fixed the pattern/repeat functionality. This functionality was not working for block repeats prior to this. • Added Linux package for extracting AVC files directly out of the 93K offline software. • Bug fix to add handling of Compare to Drive transitions in the same tiling period of a VCD file. Prior to fix, NOP’s were issued when a switch from Compare to Drive was seen within a single tile. I/O pins need the capability of going input to output and vice versa. • Updated ASL3K translation process to handle 93K bursts. This involves a fix to the BINtoAVC program that extracts bursts into standalone AVC files that use subroutine calls. The resulting ASL patterns will not be subroutines but each subroutine will be automatically converted into its own standalone binary pattern. The calling of each pattern within the burst must still be handled manually by the calling ASL test program. • Added a simple snap-to algorithm to the VCD loading process to prevent input and output edge requirements to get out of control. Inputs will be snapped forward to the nearest 1/8 of a period. Outputs will be snapped backward to the nearest 1/6 of a period. This will only work if the period will create and X2 or X4 input data stream. And also creates an X3 or smaller output stream. Release: October 3, 2005 : ShellConstructor_V0.4 • Added a command line version of the AVC to ASL translator • Added a feature to AVC to ASL to prompt user for definition of wave table for patterns that are not directly defined by the test plan file (*.tpl) • Added group definitions to the configuration definition. These groups will automatically have their timing information defined together and the AVC’s will be printed as just the groups. Vectors will still be printed one at a time but DVC’s will be defined as just groups • Added command line versions of WGLtoAVC, VCDtoAVC, and AVCtoASL to the Windows release. The command line versions had been used in Linux only before. Scripting and other factors made this addition logical. • Added multiport capability to the WGL translation process. Setup of domains will work exactly as the setup for VCD/EVCD files • Separated the pin configuration code from the VCD into its own DLL so that the code can be more easily transported to other objects.

Release: October 11, 2005 : ShellConstructor_V0.5 • Rearchitected the multi-port feature of the WGL translation process to increase throughput. Prior to change, each domain was processed independently which resulted in many redundant actions. After changes, the domains are processed in parallel to reduce redundancy • Reformatted the output of DVC file to put grouped pins on same line rather than 8 pins at a time. • Removed a number of string manipulation actions that were only in place for source debug. • Added functions and typedefs in string library to handle the process of filtering strings based on predefined column numbers. intVector and stringVector types are introduced to store lists of active columns and lists of strings respectively. • Updated the pattern recognition algorithm in the AVC output engine to fix a bug caused by recognition of blocks that are smaller than the minimum repeat size. • Modified all parsers to define keywords with namepaces to make keywords consistent from library to library. This ensures a convention that all keywords will be self contained in each library rather the inheriting from other libraries. • Moved all configuration file actions in to PinConfig library. This eliminates custom functions that resided in VCD, WGL, etc…. Release: October 13, 2005 : ShellConstructor_V0.6 • Fixed a bug in the AVC output that caused repeated blocks of less then the minimum requested limit to be expanded improperly. This bug was partially addressed in the October 11 release. The analysis portion was corrected but the output portion was not fixed until this release. Release: October 31, 2005 : ShellConstructor_V0.7 • Updated the S9K translation process to fix a bug n the interpretation of Muxxed timing. Originally muxxes were interpreted as pins that were attached to more than on DUT channel. This is backwards. The correct function will handle multiple S9K resources connected to a single pin. • Cleaned the process of Exporting AVC files to account for the consolidation of the configuration process. • Created an RPM to simplify the install process onto Linux. At the moment, the user must be root to install it. But, this should change in the future. • Fixed a bug that prevented the last scan instance in WGL files from translating properly if it is not followed by a regular parallel vector.

Release: December 9, 2005 : ShellConstructor_V0.8 • Modified the AVC import of S9K patterns to retain the 3 character Hex representation of data so that large waveform sets can be accurately represented without running out of single character indexes • Updated the loading of S9K programs to handle optional file name structures. • Updated the S9K loader to use a modified Configuration file to allow user defined input of pattern lists when the C9K file does not explicitly use a vectorFiles directive. Release: Jabuary 15, 2006 : ShellConstructor_V0.9 • Improved the functionality of the S9K to AVC converter to allow large files to be translated without error • Improved the link between the Windows environment and the Linux environment Release: March 17, 2006 : ShellConstructor_V1.0 • Added a STIL loader to the toolkit. This allows STIL to be chosen as the desired output format Release: April 6, 2006: ShellConstructor_V1.1 • Updated the Configuration setup to encapsulate the pin setups inside a PINLIST/END PIN LIST keyword. This is done so that pin names that match other keywords can be masked from incorrect usage. • Modified the configuration to add “DEVICE jeyword to WGL and VCD translation so that a common timing setup can be defined that will be named based upon this key • Added Pattern manipulation functionality for Diamond program generation • Added WGLtoD10 to array of translation flows • Modified compilation and installation to allow only binaries to be used in packages. • Added D10Shell document. This document describes the configuration file in detail. This file applies to all program formats Release: April 11, 2006: ShellConstructor_V1.2 •Added Pattern manipulation features to the D10 Shell Constructor • Added the use of variables in configuration files to allow generic patterns to be applied to any configuration • Modified the arguments of the WGLtoAVC and VCDtoAVC programs to allow more control over optimization. Block repeats can be turned on and off independently of the use of optimization

Release: April 24, 2006: ShellConstructor_V1.3 •Added Customizable Timing and levels blocks to the configuration file that can be used with the D10Shell program as well as the WGLtoD10 program • Updated the generic functions for the D10 to allow DClevels from the STIL file to be used instead of standard API programming for levels Release: April 26, 2006: ShellConstructor_V1.4 •Added a J750 Reader that converts J750 timing into STIL. This is not yet completely functional as of this release but the tool can be used as a string point for hand manipulation of STIL file. • Fixed a bug that caused incorrect timeplates to be used when translating scan cycles that use a different timeplate then the parallel vector that follows them. • Corrected an error that would allow multiple instances of categories with the same name when exporting D10 STIL files. Each category name must be unique. A check is implemented to make sure this is auto-corrected. Release: May 1, 2006: ShellConstructor_V1.5 • Updated the J750 Spec Loader to allow formulas to be used in spec statements. Release: May 17, 2006: ShellConstructor_V1.7.1 • Added Levels block interpretation to the J750 Loader • Modified the VCD/EVCD transition builder to properly map changes • Modified Windows and Linux command line versions to print proper usage directives • Added gzip file format manipulation to WGL and EVCD translation programs • Fixed a bug that prevented multiple files from translating properly • Add command line directives to modify the extent of the output of J750 programs. Program, source and tester files can be blocked to prevent recompilation of files that need no modification • Added optimization to J750 translator so that timing blocks that are not used can be omitted to facilitate faster compilation and loading in D10 environment • Added STIL macro output to D10 program developer programs

Release: June 1, 2006: ShellConstructor_V1.7.4 • Updated Levels and Timing Block output of D10 to allow for use of both custom and predefined timing from source files • Fixed a few bugs that prevented WGL files from being interpreted as D10 STIL properly. • Updated Pin configuration option to allow aliases for pin names to be defined so that multiple input formats with unmatched pin names can be merged with a single congifuration file • Updated the WGL to AVC to allow for multiple files as the VCD format was done before. Release: June 12, 2006: ShellConstructor_V1.8 • Added a Beta version of the J973 to D10 translator. This added 1 library and 1 executable. Release: July 7, 2006: ShellConstructor_V1.8.2 •A different set of logic was inserted to recognize the beginning and ending of comments. This was causing the load portion to hang as the end of a comment was sometimes never seen. • Updated J750 Loader to properly use edges for compares. Drive edgfes wer being used for both drive and receive. • Changed the default behavior so that optimized code output is created by default. • Loader changes were made to the J750 to make it more robust. This shouldn’t affect the output, other than to make it less likely to be incorrect. • Updated the logic that defines when and where Tri-State compares can be used. This prevents illegal combinations of edges. • Basic J973 translator is added. This is pre-Beta and likely not workable yet. • Reconciled differences between Windows and Linux versions. • Cleaned and added comments to code. Doesn't affect run time at all • Added install README

Release: July 20, 2006: ShellConstructor_V1.9 • Added compilation of D10 program after translation. This is meant to simplify process so that only one action needs to be taken to create or recreate a test program • Added run time options to allow for overrides of spec sheets and spec categories fort J750 translation. Both will default to the production settings as defined in JOB sheets if not specified but options now allow overrides • Updated the WGL to D10 export to use the proper scale factor so that the correct period is used. Errors were seen when period was not defined in nanoseconds. Now all outputs will be normalized properly to ns period units • Fixed a bug in the BintoHex function that was interpreting some hex codes improperly. • Updated STIL export engine so that PatternExecs use proper versions of timing and levels. Custom timings and levels were not properly integrated with production usage of these parameters. • Updated patternList export of STIL so that pattern Lists are used properly. • Updated PinConfig loader to properly handle self-defined groups and to ignore sections of pinLists after “#” is received. The trailing comments were being interpreted as groups instead. • Added the fail trigger as default behavior in all d10 program exports • Added the Clamp voltage as a used parameter in the D10 continuity tests. • Updated the Usage statements for all command line programs • Added CFG creation utility to the windows release of this. This will be added to command line Linux at a later date • Updated equation parser to match the needs of the newer releases of D10 software • Added new transition types to VCD/EVCD loader. • Added more graceful exits to all command lines that are not used properly. • Removed memory leaks that slowed down large file performance of WGL and VCD/EVCD loader.

Release: August 4, 2006: ShellConstructor_V1.9.1 • Updated Generic.cpp to ensure that valid clamps are requested. Only ranges from -1

to 8 are allowed. • Updated the WGL import function of the STIL converter to allow each timeplate to

retain its proper period as defined in the WGL file. • Updated STILLoader so ensure that patternNames do not have unsupportable

characters like “.”. • Added singular translation of M9K files which have no associated timing information • Added trigger pins to export of STIL files. Triggers can be added on any available

channel. • Added logic to handle J750 programs that also have mixed signal functionality. This

causes extra columns to appear that are ignored by pure digital translations • Updated WGL Loader to allow for indexes on pin names that are outside the quotes.

Most of the time indexes will remain inside quotes, but sometimes timeplate definitions will put these indexes outside the quotes.

• Updated WGL loader to enhance the use of busses in the signal map and timeplate sections.

• Updated the WGLtoD10 to allow patterns will any file extension to be loaded. Prior to this only *.wgl would result in valid outputs.

• Updated STIL output engine to ensure that ALL patterns can be executed individually through a Test function. This will work even if no flow is defined by the configuration

• Add trigger pins to all of the D10 export programs. This feature is used by adding pins of type “TRIG” into the pinList section of the configuration. This will result in additional columns that will appear at the end of each vector that can be modified later to insert triggers at any point and on any channel.

Release: August 11, 2006: ShellConstructor_V2.0 • Updated Generic.cpp to ensure that valid clamps are requested. Only ranges from -1

to 7 are allowed. Previous release had bugs on the clamp setup line. • Updated the IDDQ function calls to use the PatternExec for pattern execution. Prior

releases did not add the “Exec” to the end of the pattern name to define the name fully, which caused a run time error

• Added automatic generation of “allins” and “allouts” groups. This allows the IDDQ function above to properly connect resources

• Modified how pattern names are extracted from WGL files so that names used for PatternBurst and PatternExec blocks are consistent. Without consistency, process of creating calling functions in TestFunctions.cpp will be unpredictable. This was causing invalid PatternExec names and uncontrolled test numbers to be created.

• Corrected a bug that prevented TRIG pins from being properly entered into the resource files.

• Removed automatic correction features that were inserted into the J750 spec parser. These automatic corrections were intended to patch problems in the equation parser for earlier releases of ITE. This has since been fixed and is no longer necessary.

• Usage statement attached to WGLtoD10 program • Added a Beta version of GUI front end to the ShellConstructor library. No

documentation for this has been added yet but the functionality of the GUI matches the behavior with the simplest options of masking STIL file, Source file and/or Tester File creation. In addition a utility is provided that helps in the creation of new configuration files.

• Modifications were made to the underlying libraries to keep track of system directory locations so that GUI operation will match command line operation.

• Corrected a number of instances where directory structure differences between Linux and Windows prevented proper functionality in Linux.

Release: September 27, 2006: ShellConstructor_V2.1 • Updated J750 to properly handle SBC, SBH, and SBL timing formats. Inputs retain

all edges. I/O pins are converted as R0 and R1 to preserve the control over the edge placement of the compare

• Updated J750 loader to block import of test instances that are not defined as functional tests. This was done in order to prevent multiple formats from being defined

• Updated the WGL loader to allow for incremental timing setups. STIL output will reflect the last loaded state for each pin defined.

• Modified WGL loader to properly scale timing to nanoseconds • Updated STIL export engine to block specs that are used math functions that are not

recognized by the D10 loader. Specifically, this is to remove errors caused by “10^0”.

• Added use of shared libraries to house functionality for a number of powerful script objects provided by Credence

• Moved source for user commands and generic functions out of local program and into externally loaded and compiled libraries.

• Adjusted configuration to allow J750 and J973 tests to be defined in the same fashion using CFG Test blocks to override or explicitly define usage in STIL.

• Updated ShellConstructor documentation to reflect additional formats that are supported additionally since the initial authoring.

• Added VCD/EVCD translation. Automatically cyclizes and converts timestamped data to STIL..

• Removed the need for the usage of GENERIC and USER functions variables in constructor

• Updated STIL vector output to create a special pin group that is used only for vector definitions. This allows allpins to remove pins that do not need to be tested in DC tests such as continuity.

• Spec Definitions will now be defined with quotes so that possible usage of STIL keywords as spec names such as Period will not result in errors.

• Added support for Encounter WGL files. These are formatted slightly differently than TetraMax and FastScan.

• Cleaned up the import of J750 specs to properly adjust units and to remove spaces in names of sets.

• Adjusted the STIL pattern export engine to ensure that each TestFunction calls the correct PatternExec block.

• Added minimal support for MCG pins. Full support will require MUX functionality to achieve rates greater than 2X of tester period.

• Tuned normalization process to force edges that are placed output of range to remain in range. In certain instances, timing tables contain wave tables that are intended to be used only with specific spec sets. When compiled with incompatible spec sets, even unused waveform tables will cause ITE compile errors unless the edges are forced to remain in range.

• Fixed a bug that prevented both J750 and J973 translator to properly create PatternExec and TestFunctions for instances of custom patterns defined by the Shell configuration.

• Added utility to view Original source files from within the ShellConstructor GUI. This will make it easier to access source files to determine what is being handled improperly and to verify the things that are being handled properly.

Release: October 17, 2006: ShellConstructor_V2.2 • Updated J750 and K973 loader to adjust how the default levels and default timing are

defined. ACSpec and DCSpec will now apply define the default but will not override the settings of tests defined by the source program

• Modified the Generic Functions library to use “format” instead of “allpins” for connect and disconnect statements in digital tests. This will allow trigger pins to be connected as needed.

• Updated the J750 loader to block Levels blocks that are not used to reduce the size of levels file and to remove errors caused by incomplete levels blocks.

• Centrallized some functionality to reduce the differences between GUI and command line operation. Some differences are inevitable because of integration of WxWidgets vs stdout message handling.

• Corrected an error in STIL export that was preventing custom levels from defining itself properly. Only the “default” group was being interpreted. Other group definitions were not being written to the resulting output STIL file.

• Updated how aliases are defined in J750 loader to prevent circular references that caused incomplete spec setups

• Corrected patternExec definition logic to prevent invalid DC and AC Specsets from being requested. “DC” and “AC” must be added to prevent the problem of duplicate category names for levels and timing.

• Pin Count for groups in Signal definitions corrected to reflect correct number of pins in the group. The number was always defined with one more than was actually present.

• Updated Configuration loader to ensure that custom groups are inserted to the proper domains. Without this, groups would be removed from the domains and therefore not present in output STIL files.

• Corrected inconsistency in the VCD/EVCD loader that was causing format group to be incorrectly defined so that resulting patterns would not be compiled properly.

• Corrected STIL loader to prevent custom levels and custom timing from being defined twice.

• Corrected STIL loader to prevent trigger pins from being defined twice. • Added a provision to remove units from spec named “scale”. This will prevent some

errors that are caused by the fact that the D10 compiler calculates “1ns*5ns” to be “5e-9nS” instead of “5ns”. This is not a universally correctable issue but this will address many such instances so that the resulting program compiles as expected.

Release: October 26, 2006: ShellConstructor_V2.3 • Add serial scan export capability to the WGL translation process. When enabled,

macros will be used to represent scan instances. When disabled (as default) scan instances will be exported as regular parallel vectors.

• Added ROFF pin type capability to J750 test translations. • Upgraded the usage of relative paths to allow the GUI and command line versions of

all programs to export to the same location. Relative paths will always be interpreted relative to the location of the CFG file.

• Cleaned command line and GUI code to make sure that they work as equivalently as can be.

• Updated the normalization process to handle units intelligently. Some edges were being calculated improperrly because units were not consistently used from pin to pin.

• Add infinite Loop and STOP capability to the export process. • Added upgraded version of the command line library functions. • Fixed a bug that prevented multiple custom levels blocks from being properly

integrated. Release: November 13, 2006: ShellConstructor_V2.4 • Updated the J973 loader to better handle testcases that did not follow the J973 reverse

compiler process. • Corrected the STIL loader to properly load and process level information. This was

previously not implemented because the tool was originally developed for platforms that did not have any levels information.

• Updated J750 loader to properly handle masking and unmasking of vectors that use binary data.

• Added usage warnings alert the user to possible errors with configuration such as misspelled file names or missing pins.

• Added utility to more accurately handle load processes that involved “include” references to other files.

• Updated the user_commands library to properly connect the “format” group so that trigger pins are automatically active. This was changed from the “allpins” group

• Added up to date script commands library

Release: November 27, 2006: ShellConstructor_V2.4.2 • Fixed a bug in previous release that prevented GUI from loading unless a full build of

wxGTK is installed. This package should require only a handful of shared libraries fro GTK, which are included with the release.

• Made adjustments to the output of specs to make sure that units are valid. uA_per_V was still making it through when it should have been filtered.

• Added a feature to automatically offset all edges to prevent negative edge placement • Fixed a bug in the J973 loader which was causing timing formats to be defined

improperly. RL, RH, timings were being translated as NRZ. • Made a few adjustments to make sure that the STIL loader properly handles the

output from the J973, J750, WGL, and 93K translators • Updated the WGL loader to allow multiple patterns to be translated from within a

single WGL file. Pattern names taken from block name if multiple patterns are found. If only one pattern is there then the pattern name will match the filename.

• The 93K loader has been activated but this is not yet complete, so don’t plan on using it for this release.

• Updated the D10 Generic Functions to allow either VIS or DPS cards to be used interchangeable in test programs. Both will be treated as generic power supplies so that high level usage is identical.

Release: December 1, 2006: ShellConstructor_V2.4.3 • Updated J973 Waveadr loader to allow unitless specs to be processed as untiless

instead of applying a “ns” as default timing • Modified the J750 loader to allow for extended and normal timing. This affects the

way drivers are turned off for compare cycles • Fine tuned the WGL loader to handle inversions within scan states when the dummy

cycles are added explicitly by the simulation. Previously these dummy cycles were added by the ShellConstructor. When already present inside the WGL scan states, the processing of inversions was out of sync

• Corrected the process by which negative edges are normalized to move edges to the positive. Offsets added only if negative edges occur, otherwise, these offsets are left out to simplify the equations.

• Changed the timing and levels specs output to use a common XXX_Specs.stil file instead of including timing specs in timing file and level specs in spec file. Since the D10 does not differentiate between timing specs and level specs anyway, the STIL files will now reflect this.

• Corrected bug in Spec calculation engine that was applying units incorrectly, resulting in miscalculated edges.

• Beta version of 93K Loader is now available • Added provision to WGL loader that will allow timeplate masking to occur.

Timeplates may define only “X”, even though the pattern uses L and H. This modification will map L and H to X if the timeplate only defines X. Prior to the change only X would be mapped.

Release: December 15, 2006: ShellConstructor_V2.4.5 • Added a new feature to both the GUI and command line translators to allow append

mode. If using Append mode, existing programs will be used as a starting point and new patterns, timing, etc will be added to existing programs without overwriting and/or removing existing information.

• Updated the EVCD loader to load each pattern into its own timing block. This is because different pattern will use different waveforms and possibly use different sampling rates.

• All platforms will now use the pattern name for the pin list instead of “format” This is to allow pattern that use different pins to be simultaneously loaded. The user_commands library is updated to allow programs created under previous revisions to be successfully executed despite using “format” as the digital pin group.

• Updated the STIL loader to fix a bug that prevented procedures from being properly loaded and referenced if these are present in the source program.

• Cleaned up the trigger insertion process so that triggers are not added twice to programs that already have triggers added.

• Modified the defaultTiming variable so that each pattern will have its own default timing. This is done so that multiple patterns with different wavetable formats to be loaded without corrupting the program by associating all patterns with a single default timing block. There can now be as many default Timing blocks as there are patterns loaded. Each pattern can have its own default..

• Corrected bug that prevents the STIL loader from overriding timing and specs. PatternExecs were not updating properly. This will now allow existing programs to be updated through the ShellConstructor.

• Added the normalization feature to the STIL loader. Previously this flag would be ignored so that existing programs that have not been normalized could not be normalized through the STIL loader. This will now work so that multiple patterns can be translated without normalization and this can feature can be added separately to an existing program.

• Fixed a bug that was preventing trigger pins from being written when loaded from an existing program. These pins were being masked out of these blocks. This will now add triggers properly.

• Updated STIL import functions from all platforms to add a Z action to turn off the driver for compare actions on all IO type pins. Leaving the driver on will prevent proper loading and invalidate some read actions.

• Updated the 93K loader to allow simple X1 patterns to be translated. Negative timings may require the normalization flag to be set to prevent D10 compile errors.

• Corrected a bug that caused incorrect DCSpecs to be defined when J750 test programs use a namespace style to determine DCSpecs. “Namespace::specName” as defined in the spec sheets, is then used as just ::specName in the test Instance sheet. Therefore, a default namespace is chosen from the spec sheet. This had been hardwired to “Ambient, which caused problems

• Updated the Hex to Binary functionality on the J750loader to properly handle hex displays. Bug was causing vector length to not match the pin group length.

Release: January 26, 2007: Velocity_V3.0 • Added licensing features to allow for secure distribution of toolkit • Verilog VCT format has been added. By default RCONFIG files are required to

obtain timing information • ASL3K CPTD format translation added. Timing will default to NRZ for all pins.

Timing can be generated using the CFG file • Added automatic generation of TDR routine for D10 programs. This is requested

with the FIXTURE_CAL variable in the CFG. • Additional error messages inserted to the VCD Loader to inform the user of cync

issues. By default, no snapping is used so that errors in sample rate can be dealt with prior to the long process of loading the whole file.

• A number of error checks are put in place to allow more flexibility in the CFG. For example, tests and patterns that are not valid will provide error messages so that these problems can more easily be fixed. Flow entries will be masked if they are not properly available.

• Added loop, jump, and conditional jump capabilities to the D10 user library • Updated the power up and power down sequences to account for the use of multiple

board types on the D10. VIS and DPS can now be simultaneously used. • Custom pattern and custom test features expanded • X2+ modes can now be handled in the AVCtoD10 function. • CFG will now allow aliases that match pin name to be used so that the alias column if

used can define all pins explicitly. This will make the CFG more easily readable when more than 2 pin name scheme are in place.

• A Debug button has been added so that large patterns can be handled in smaller pieces to verify their validity before they are completely translated.

Release: February 2, 2007: Velocity_V3.1 • Update release materials to add a configuration script that will ensure that all files and

directories have the proper privileges. • Added a log file to store error and status information in a file that will be located in

directory from which configuration file is loaded from. If no write priveleges are available the log file will be skipped.

Release: February 7, 2007: Velocity_V3.1.1 • Updated trigger definition in STIL to include an explicit definition for the Z action • Updated the log file to include a reference to the active configuration that is loaded • Modified the character formatting in the New Configuration function to make

columns more readable • Corrected aliasing for EVCD, WGL, and VERILOG loaders so that the proper pin

name is used instead of the alias that might be used in the SIM file • Pulled the user procedures out and placed these into a separately defined library

called DiamondUserProc. This is installed at the same level as Velocity and is referenced through a link.

• Corrected a bug in CPTD loader so that multiple files can be properly handled Release: February 15, 2007: Velocity_V3.2 • Added functionality to configuration to allow pin by pin and cycle by cycle masking

schemes to be introduced to mask outputs at cycles and in ranges. This has been applied only the VCD loader and AVC export engine. For STIL output, only VCD will process masking. Future release will add remaining formats to this feature.

• Added verification during load time that will exit gracefully, if no PERIOD is defined for an EVCD load process. If not sample rate is defined, the output will be garbage

• Corrected bug in pin configuration definition that prevented CLK pins from being processed properly by EVCD and VCD patterns

• Updated Velocity documentation to add MASK properties to custom pattern definitions.

• Added feature to update snap resolution marker in GUI to reflect RZ.R1 timing requests for VCD/EVCD load operations. STIL loader will automatically use the snap resolution to interpret raw waveforms to distill them in to properly loadable STIL waveforms.

Release: February 23, 2007: Velocity_V3.2.1 • Corrected bug in J750 loader that added masked pins into groups in which portions of

the group are active and portions should be masked. This caused a problem when pin groups did not match the format of vector content. This fix will allow multiple packages to be translated from the same source.

• Added a feature into the configuration file loader to check for duplicate aliases which cause import problems on all formats. Aliases can only be used once. This will now print an error message instructing the user where a fix should be made.

• Fixed a bug in the WGL export that prevented D10 JUMP labels from containing proper data if the configuration uses pins that are not all DPIN96. Other resource types were being used as the domain which ended up with empty vector strings.

• Added evaluation and use of spec slectors to te J750 loader and export engine. This will aprovide a mechanism to adjust the selction of spec levels between MIN, MAX , and TYP.

• Adjusted the (3K loader to properly handle Window compares for the AVC to D10 translation port. Prior to this change, some waveforms using a Window compare did not properly turn of the driver. Resulting waveform dropped the compare and left only the driver turning off.

• Added automatic creation of and offline_cfg.txt file for the D10 so that any offline machine can properly load a program without having to edit the global offline_cfg file. This will allow easier testing of systems wwith differeing hardware configurations

• Adjusted the STIL equation evaluation engine to evaluate units of elements in line to ensure that proper results occur independent of unit usage.

Release: March 1, 2007: Velocity_V3.3 • Optimized the VCT loader to enhance the speed. There were many instances were

actions were repeated on a line by line basis that needed to be tweaked so that they no longer needed to be defined every line. This should over a 6X-7X improvement in throughput

• Removed the Enable Macro feature because this feature is not properly supported by Credence

• Updated the J750 loader to properly handle pins that do not have timing parameters defined even though they might be defined inn a vector. This is a masking technique that was not supported on previous releases. These will now be mapped to don’t care actions

• Added scan template support to the 93K to D10 translator. These are directly mapped first to STIL macros and then expanded to normal STL vectors due to the aforementioned removal of macros due to Credence limitation in diamond loader.

Release: March 9, 2007: Velocity_V3.3.1 • Added Multiport support to he VCT to 93K translator. • Corrected a bug introduced by the 3.3 release that scrambled the order of the data in

the vector statements • Corrected a bug in the normalization process that sometimes prevented all periods

from having periods defined in each category • Added a predefined masking waveform so that pins defined in vectors that are not

defined in timing will translate properly for 93K to D10 translation flow.

• Added code to search for and insert repeats to the STIL optimization engine. This is activated when the optimization flag is asserted.

• Updated the J750 loader to handle IF statements in Spec blocks. Since this does not map to anything in STIL syntax, the statement is replaced wit the evaluated entry from the J750 spreadsheet

• Updated the J750 level import to expand groups so that duplicate definitions for pins is prevented. If 2 groups are used in J750 that both reference a common pin, this will result in a compile error on the D10.

• Modified the D10 TDR function export to prevent MASKED pins from being included in the program. Inclusion of MASKED pins was causing errors caused by the fact that the top level program removes these from the SIG file.

• Updated some of the compiler options to increase the speed of all translation tools • Fixed a bug in the append mode so the VCD, VCT and WGL can properly be added

to existing D10 programs. The bug was causing level spec categories were not being deinfed properly.

• Updated the AIC output to make sure that one and only one instance of each pattern is inserted. Also ensured that a valid DVC file is exported. DVC file data was being ignored

• Changed the VCT timing import to handle RZ and R1 formats. • Updated the STIL Loader to ensure that spec selectors are maintained properly • Updated Export of STIL selector blocks to put quotes around spec names in case spec

names are equal to keywords, such as Period. • Added some logic to keep track of which spec sets are for DC and which are for AC. • Added “all” pin group to imported 93K patterns exported to D10. • Updated the J973 loader to separate subroutines into separate files. Separating makes

the output compatible with the STIL Loader. • Fixed a bug that caused CJUMP labels to be printed for timings that were not

appropriate. Now only waveform tables in the same time set will be used in the CJUMP section.

Release: March 23, 2007: Velocity_V3.4 • Corrected the method used to extract DVC into waveform tables. The new method

will more properly determine which edges are needed when DVC files are greater than X1 mode. Old method had holes that would add or remove necessary actions from listing

• Added functionality to allow masking to handle more complicated character translations. Each mask definition can move individual characters to any arbitrary defined state character.

• Modified how WGL is imported and exported to STIL to allow for conditional and cycle to cycle pin masking and data modifications.

• Added a new replace substring function to speed up some of the processing. Pointers are used to reduce the amount of data transfer needed.

• Modified the J973 missing pins warning to only warn for pins that are referenced by LVMADR and missing from the CFG. Previous method, which compared the pinadr to the CFG resulted in more warnings than were needed. If pins are not called by the LVMADR then the fact they are missing from the CFG is irrelevant.

• Added a warning message at the end of the LVMADR loader to warn user of possibly missing timesettable file. Missing this file when it is needed with result in an empty vector file as well as no timing present

• Adjusted the J973 to STIL import process to remove warnings for edge adjustments for waveform tables that are not exported. Often times, many wavetables are imported even though only a handful are actually used. If optimization is used, the unused waveform tables are masked from the export. This will now also mask the warnings about edge adjustments.

• Updated the Append features so that existing data is more exactly maintained. • Corrected bug in J750 loader that was choosing incorrect columns for patterns

translated in which pin masking removes portions of grouped items rather than all of a grouped item.

• Redefined the licensing approach to allow more granularity for more customized installations.

Release: April 3, 2007: Velocity_V3.5 • Updated STIL , Job File, and Make files so that individual patterns can be compiled

into their own .PAT file. This will enable incremental compiles and decouples the pattern translation process from the D10 Shell features. Faster compile times on appended patterns will be one of the positive results. New patterns can be inserted into any other program htat has been created using a compatible configuration.

• Corrected Bug in AVC to D10 timing translation to account for edgesa that appear out of order in DVC. Explicit data results will be transferred to D10 data.

• Updated the append mode to read JOB file instead of pattern files. This eliminates the need for recompile as the old pattern is left untouched

• Added check in AVC loader to prevent data bit strings greater than 8 to be created. RZ and R1 X4 mode is the maximum allowable when transferring directly to D10. Some DVC have waveforms that are unused and are not possible on the D10, This check will prevent crashes that occur when these types of timing are encountered.

• Updated the J973 loader to allow pin groups that begin with “GROUP” to be included properly. These were blocked because of a keyword complication.

• Added interpretation of the Ignore statement in the J973 LVMADR files. • Updated the WGL equation set parser to prevent invalid data from being transferred

to STIL. This was causing invalid and uncompilable SPEC sets. • Corrected the intperpetation of WGL specs sp that periods are properly defined. This

corrects an error that caused Normalized results to have divide by Zero data in waveform tables

• Improved the data masking and data manipulation functionality to allow for aynchronous data to be included.

• Updated the multi time domain export feature to block empty timing and patterns • Modified the Configuration file to allow for imbedded groups. Group entries must be

defined either as pins or as groups before they are used in other groups • Re-activated the grouping of pins for VCD timing accumulation. Configuration

groups will result in grouped timing. This is only useful if snapping is instituted. Otherwise the accumulated timings will break the STIL’s waveform table listing. Too many edges will be required. All pins in the group will require every edge for every pin. If snapping is used, these will be forced together.

Release: April 5, 2007: Velocity_V3.5.1 • Modified the STIL loader to account for the reorganized STIL file structure.

Individual patterns are now organized into their own directories. • Updated the 93K Loader to remove waveforms that are invalid. Such as waveforms

that have multiple data points all at the same edge placement. • Corrected the EVCD loader to properly end the outputs during export of the last page.

The last page was continuing beyond the proper end of the pattern to continue exporting the remaining data in the page buffer.

Release: April 6, 2007: Velocity_V3.5.2 • Corrected a bug in the Masking feature that was causing truncation of cycles. NULL

characters were inserted instead of the proper masking character. • Corrected a Bug in the SVMADR load process that was not handling repeat properly.

Expanded Loops contained one too few iterations. • Added warnings for missing pins that occur within groups. Prior to this no warnings

would occur if any other pin in the group is present. Release: April 9, 2007: Velocity_V3.5.3 • Adjusted the masking scheme to allow the map and conditions to change for pins

from cycle to cycle. Now multiple PINS statements will be allowed for each pin. Release: April 13, 2007: Velocity_V3.5.5 • Corrected a bug in the AVC Loader that caused looping and cycle count to get out of

sync when optimization was enabled. • Optimized some of the process for applying masking and filtering. Duplicate mask

searches have been removed. • Added a couple of missing transition types to the EVCD translation process. This

affected analog simulations. • Added default data for Masked pins to properly define default state • Added the ability to put comments at the end of lines within the PINLIST section of

the CFG file • Modified the WGL to STIL import feature to prevent double clock timeplates from

automatically defining a ZX waveform. This prevents resource overload that can cause compile errors.

• Added feature that will automatically allow scan instances to export data into a dedicated scan domain to allow compression on non scan pins

• Updated the “append” mode to properly handle cases where asynchronous patterns have been previously defined.

Release: April 13, 2007: Velocity_V3.5.6 • Corrected bug in masking scheme that caused a crash when snap enabled EVCD files

were translated. Snapping converted from Wave Index to state map, but masking was still using wave indexes. Illegal characters were requested.

• Added checks to the WGL loader to account for multiple data values on IO pins. • Corrected Bug in 93K loader that was causing crashes due to missing timing data.

Release: April 27, 2007: Velocity_V4.0 • Consolidated the Sim to Test features of velocity into a common library that is called

from both the GUI and the command line versions. This change will make future changes easier to maintain.

• Fixed a bug in the WGL export that was causing memory to crash on larger files. • Replaced all of the command line programs with options that are added to velocity as

command line arguments. (i.e. VCDtoD10 is now velocity –vcdtod10) • Added Quick Start Guide to the documentation listing and addeda linkage to open it

from GUI • Added viewer for license file from the GUI Release: April 28, 2007: Velocity_V4.0.1 • Corrected a bug in the WGL translator that was preventing STIL vector patterns from

closing properly when they are being exported. This error was introduced as part of the code consolidation efforts of V4.0

• Corrected a bug in WGL loader that was omitting timplate entries that were entered as groups instead of direct pin entries

Release: May 2, 2007: Velocity_V4.0.2 • Finished the replacement of all command line versions with a non interactive path

through the common velocity executable • Corrected bug in 93K to STIL translator to allow “PERIOD” to be used as spec

properly • Optimized the WGL pattern block loader to reduce the translation time. Each vector

line was being tokenized completely even though only the first 3-5 characters are needed as tokens.

• Incremental improvements to the error reporting schemes for License retrieval and configuration loading.

• Corrected a WGL loader bug that caused problems when two files loaded together contain different timeplates lists.

Release: May 9, 2007: Velocity_V4.0.3 • Modified license read function to allow both eth0 and eth1 connections to be valid • Modified the configuration loader to make the use of relative paths more flexible.

PATH can lead with “.” Or “..”. PROGRAM and DEVICE must be hard strings. • Corrected BUG that caused DRIVE spec to be used for Z action in custom timing

usage even if the DRIVE spec was left undefined. • Corrected some case sensitivity issues that were blocking parts of time and level

sheets in J750 loader. • Modified Node Locking check to allow either eth0 or eth1 to be used. • Corrected the cycle remapping used when processing AVC files to allow unsnapped

edges to retain proper waveform. • Added check to STIL export to prevent procedure calls on the first cycle. • Corrected case sensitivity issues in custom PATTERN block statements • Corrected bug which prevented multiple WGL files from choosing the proper default

timings • Corrected bug which prevented WGL equation sets from being properly read if min

and max optional parameters are defined • Corrected bug in LVMADR loader that caused pattern to reset if comments were

inserted during the pattern data section. • Added corrective measures to remove empty directories after processing is completed • Added functionality to extend the utility of the xmode option for AVC processing. • Added compile only option into the Build menu • Optimized the relative path usage in the CFG. PATH can be relative. DEVICE and

PROGRAM must be explicitly defined. Full path will be built properly from these locations.

• Added Check to configuration loader to provide warnings if channels are duplicated Release: May 14, 2007: Velocity_V4.0.4 • Corrected Error in the CFG creation function that [reveted WGL from being properly

used as source file. No pins were properly extracted. • Modified the WGL loader to allow scan chains to be formatted with or without quotes

around chain elements • Adjusted the STIL export tool to clean the insertion of labels and comments. Release: May 16, 2007: Velocity_V4.0.5 • Corrected error in WGL loader where scan chains with empty lines were being

inserted as nodes. This casused a crash when the head or tail of a chain was not a member of the pinList

• Corrected error in AIC file to properly account for multi port patterns • Added warning for pattern names that exceed the 40 character maximum. AIT does

not handle these pattern names properly.

Release: June 7, 2007: Velocity_V4.0.6 • Corrected a set up bugs in the 93K loader that was preventing carious formats from

appearing in the resulting wave tables • Modified the test number auto generation process to prevent duplicates. • Optimized the STIL loader retain comments properly • J973 loader will properly provide error messages for missing files • Added error messages to configuration loader to alert user of possible errors Release: June 18, 2007: Velocity_V4.1 • Added beta-test (proof of concept) export to VCD for STIL and WGL loaders • Corrected interpretation error for the usage of sub routines in the J973 translations.

Calls occurred before calling vector instead of after as they should be • Corrected error in WGL loader that blocked evaluation of inversions • Added warning for LEVEL and TIMING block names that being with a digit. • Corrected Bug in ShellConstructor that blocked STIL production when no patterns

were needed. This bug prevented DC only tests from having a signals.stil file • Corrected Bug in WGL Loader that prevented scan instance markers from appearing

in the proper location • Added a feature to expand groups used in J973 timing blocks so that each pin is

defined explicitly. This was causing errors because the J973 can redefine pins. Loading only one instance with each pin will prevent this error

• Corrected a bug that prevented J750 test instances from loading all patterns when spaces appeared in the program file.

• Modified how NoOps are translated from 93K files Release: June 25, 2007: Velocity_V4.1.1 • Corrected bug that blocked the EVCD output when D10 features are also enabled • Added definition of undefined pins to DVC files to remove undefined timing

warnings • Blocked mask data from appearing in incorrect domains. Masked pins were showing

up in all domains by mistake. • Made page size larger for VCD loader so that larger repeat blocks can be obtained. • Removed EVCD export of “NoAction” to reduce size of file.

Release: June 28, 2007: Velocity_V4.1.3 • Corrected the import of repeat and loop blocks in J750 programs • Changed the J973 spec load process to prevent parenthesis from being removed when

they should not be. • Updated the CFG creation process for the 93K sources. This was crashing before

export • Corrected bug that prevented undefined pins from being removed from the 93K

loader. Extra pins caused crash during export process • Added use of the debug option in the 93K loader. If selected, pattern loader will exit

early to provide way of checking validity of file without having to run the entire pattern

• Corrected bug that prevented scan ports from loading completely in the 93K loader • Corrected bug in “View” that defaulted the types to inappropriate settings. • Changed the way specs are redefined by custom tests. ACSPEC and TIMING will be

used to choose the category and block for timing specs. DCSPEC and LEVELS will be used to choose the category and block for levels specs. This replaces the override scheme from before.

• Corrected bug that prevented normalization from properly formatting the timing for the 93k loader

• Corrected a bug in the STIL loader that moved subroutine calls to the wrong location and blocked the vector after.

• Updated the STIL export to allow specs and timing to be changed through the CFG. • Updated the STIL loader to block loading of empty comment lines. Release: July 3, 2007: Velocity_V4.2 • Corrected EVCD export drive strengths and data mappings • Optimized the EVCD export to reduce time for each pattern • Corrected bug in STIL to AVC that was putting everything into a single file rather

than breaking each pattern into its own files • Added multiport to STIL to AVC path • Corrected bugs in Append mode to allow existing programs to be properly loaded

without overwriting new information that is need from new files. Release: July 6, 2007: Velocity_V4.2.1 • Adjusted the page size algorithm for the VCD loader to account for timescale

variations. • Corrected bug that crashed when Gzipped files were loaded for EVCD translations • Modified the progress messages to make it consistent • Added “quiet” mode to non-interactive usage so that all gui properties can be

bypassed for batch mode operation.

Release: July 9, 2007: Velocity_V4.2.2 • Corrected a bug in the STIL to EVCD path that caused busses to end up with identical

data that not longer matched the parallel vector. • Adjusted how J973 SVMADR loops and repeats are expanded. • Corrected an error in the page size adjustment that was improperly handling

timescales for the EVCD loader. • Corrected a major memory leak that was leaving cycled EVCD information

uncleaned after each page was purged. Release: July 11, 2007: Velocity_V4.3 • Added support the zlib compression library to allow inline loading and exporting og

gzip files. This will allow larger file support and prevents the need for system calls for gzip and gunzip. AVC and EVCD files will be automatically exported into gzip files. Any file can be loaded from gz file. The source files will remain zipped throughout.

• Corrected a bug in the cycled EVCD creation process that was not resetting properly between pages.

Release: July 13, 2007: Velocity_V4.3.1 • Reimplementation of the AVC export from STIL to allow large file support. AVC

will now be exported in pages to prevent memory usage from getting out of control. • Added a few warnings to account for STIL errors that will prevent proper translation

of files. • Added –help to the command line to provide some easy usage help from the

command line. • Corrected a bug caused by the differences between STL operation in Windows vs.

Linux. Indexing in maps was getting out of sync and causing exported vectors to vary from the timing.

• Optimized the page adjustment further to optimize memory usage. • Fixed a bug in the AIC loader that was repeatedly adding ports to multi port bursts

definitions instead of only once. • Corrected an error in the J750 loader that was converting hex data to binary and

leaving to many bits in place for some single pin groups. Or groups that are not included in the active configuration.

Release: July 24, 2007: Velocity_V4.4 • Updated the EVCD export to maintain the port mappings for resimulation. • Updated the J750 pattern loader to properly handle masking of C code and comments

that occur after the last valid vector in ATP files. • Added warning to let user know of configuration mismatches that cause device cycle

data to be dropped for missing pins when aliases are missing. Release: July 26, 2007: Velocity_V4.4.1 • Added support for mach4 mode in J973 patterns. Init • Corrected bug introduced by 4.4 that prevented J750 patter set sheets from being read

properly • Corrected bug in CFG that potentially caused problems when “default” timing and

levels are requested in TEST blocks with no custom timing or custom levels blocks defined.

• Added configuration creation from the command line • Added help comments to proceed after invalid usage is used. • Corrected a bug that caused a crash when multiple EVCD files are chosen and

snapping has been enabled. • Modified the AIC output engine so that multiport bursts are ignored if there are not

valid vector defs for multiple ports. Empty ports will be ignored. • Modified the parser engine to properly inform when the end of file is reached for the

progress meter • Added auto correction to keep normalized edges inside the 4 cycle boundary. Release: August 8, 2007: Velocity_V4.5.2 • Window comparisons will be converted to edge strobes • This was caused by an error in logic for how the "default" levels and timing where

chosen. This was getting complicated by the fact that the two patterns have different but overlapping test instances which call them. The default was getting set to early in the process so the second pattern was using defaults instead of the values defined in the file. I hope this one is fixed now.

• I had not properly made adjustments to SBC IO pins as I had done on the J973. I was using "0" instead of driveOn also. So, the error was confusing. The edge should not have been included at all, let alone arbitrarily assigned to 0. I was also using the return for receive data instead of he "open" variable.

• I am not able to repeat this one using 4.5.2. It is possible that ongoing UltraFlex modifications may have temporarily screwed this section of the loader up. I have been cleaning this as I progress and may have accidentally fixed this one.

• Just an old fashioned error in logic. Should be OK now. • I need to verify that using the "p" works, but this has been changed. I can just repeat

the drive data because the 0 or 1 may be a pulse. repeating the data would possible

insert pulses where there should not be one. "p" is the correct value, but I am not sure about its usage yet.

• "\r" was being removed, but a typo in the function was removing the "r" characters, even those that were part of equations

• J750 loader will now check to see if normal mode or extended mode is used. Loops will be properly handled.

• scan instance processing is updated to allow for missing pins from the FORMAT line to be automatically added in.

• The configuration loader will now automatically increment the test number to account for multiple records in a test

• Updated the way SBC waveforms are imported so that waveforms are not dropped. Conflicts with possible xmode waveforms were causing premature exit from the waveform formatting routine.

• Updated the 93K pin export to use DFGP and DFGE as needed • Optimized EVCD export that will override the timing in sim to save time. • Corrected error in STIL export that was causing cycle count to get out of sync when

loops are back to back. • Corrected STIL export to move Wave table definition outside of loops. Release: August 17, 2007: Velocity_V4.5.4 • Corrected bug in double to string function that was applying units improperly in some

instances • Updated the auto test numbering logic so that DC tests are properly handled. More

test numbers were needed for these tests. • Fixed bug in custom timing and levels usage. Now all custom tests will use the

timing and levels if they are defined. • Fixed a bug in the 93K loader that was preventing scan instance L’s and H’s from

being used. O’s and 1’s were not being converted for output scan chains. • Corrected pin configuration Export to prevent groups from getting printed twice and

to ensure that imbedded groups are printed prior to their use. • Corrected Error in STIL loader that was causing comments in vectors to get out of

sync Release: August 23, 2007: Velocity_V4.5.6 • Modified the AVC import function from STIL to allow duplicate waveforms from

different indexes. This allows clocks to be hardwired as toggling all the time and/or masked all the time independent of he data in vector files.

• Added group definitions to the custom timing in DVC files. • Added the Z to custom timing compare cycles. • Adjusted the EVCD loader to allow Return-to timings to be used with the custom

timing.

Release: Sept 14, 2007: Velocity_V4.6 • Added Subroutine import from AVC to STIL. • Added more complete support for DVC import to properly handle drive terminations

for compare cycles and mid-state comparisons • Added X mode support for J973 and J750 to STIL translations • Corrected error in cycled EVCD export to make sure timesets are not improperly

reset between pages. • Adjusted the 93K import to correct missing specs • Enhanced the STIL equation evaluation engine to allow conditional specs to be

evaluated properly. • Added block of CTIM from AVC loader. • Corrected error in DVC loader to prevent masked pins on a given line from causing

all the pins on that PINS statement line from being blocked from inclusion in STIL timing.

• Corrected the addition of “all” group to J750 translations • Enhanced the EVCD import to properly allow for timeset switching. Initial periods

for regions that are not defined with a consistent period will use the period from the first valid section.

Release: Sept 28, 2007: Velocity_V4.6.1 • Updated the documentation to split User Guide from Configuration Guide • Corrected bug in Equation parser that was hanging on some imbedded equations. • Corrected bug in the STIL timing export to prevent certain equations from aliasing

into waveform format setups. Prevented some data from showing up properly in 93K translator

• Added conditional spec referencing capability in J750 translator • Corrected bug in pattern list loader for J750 which was preventing some Pattern

Execs from being properly created. • Updated the SpecAdr loader to optimize for speed • Corrected J750 loader bug that caused improper interpretation of Normal vs.

Extended Mode. • Updated the STIL export to allow surround by waveforms to be used with custom

timing • Corrected bug in 93K loader which was blocking the inclusion of some required

waveforms. Caused timing to vector mismatch.

Release: October 3, 2007: Velocity_V4.6.3 • Corrected a bug in the J973 waveadr loader that was preventing certain formatting

schemes to block edgesets from inclusion. This caused svmadr and lvmadr files to load improperly in subsequent steps

• Corrected 93K loader error that was preventing data X data from translating properly. • Adjusted J973 spec loader to optimize for more speed and prevent loss of data. Release: November 26, 2007: Velocity_V4.7.3 • Modified the Spec export to allow different spec sets to be defined in each STIL

pattern directory • Reactivated the Macro usage option for WGL scan to STIL scan representation • Reactivated the J973 config file usage so that specsets can be automatically obtained

without having to use the CFG Test block. • Made some adjustments to the 93K DVC loader to correct some errors that were

removing waveforms that were improperly evaluated to be unused. • Modified the WGL pattern loader to correct an error that was causing pin counts to

get off on some cycles • Adjusted the way that loops are loaded to remove the automatic flattening that was

occurring. By flattening, the load time was increasing too much. Loops in source will no longer be automatically flattened

• Added some new error and warning messages to make user problems easier to fix. Release: November 30, 2007: Velocity_V4.7.4 • Corrected a bug that caused a crash when WGLtoD10 option is chosen in quiet mode

from the command line • Adjusted the configuration loader to allow “PIN” and “PINS” keyword to be used

interchangeably inside TEST definitions • Adjusted the J973 import process to automatically set the defaultTiming category if

J973 CONFIG file is used. • Adjusted the parameter defs in the TEST blocks to allow lower case values to be used

to express Volts, Amps, and Seconds. • Adjusted the export function for custom timing to account for multiple cycle

waveforms. Surround by waveforms were being exported with duplicated edges which caused compile errors. These extra edges will now be auto calculated instead.

• Added ASL3K export functions. These will only be active if the ASL3K license in installed.

• Adjusted the usage of custom levels to properly interpret specs inherited from other blocks.

Release: December 15, 2007: Velocity_V4.8 • Modified the Main Panel so that “Build D10” is replaced with “Build STIL”. This

was done so that the tool is applied more generally to all the platforms that would use STIL. No functionality changes are associated with this.

• Adjusted the STIL export so that specs that evaluate to invalid edge placements are blocked from usage. This was done because of compiler changes in 1.5.3 of ITE.

• Adjusted the custom timing output to properly handle multi-edge waveforms even when the spec list is incomplete. CLK and PULSE no longer are required. The trailing edge will be auto-calculated just as it is when normalization is used.

• Made some adjustments to enhance merging of multiple source platforms Release: February 20, 2008: Velocity_V5.1 • Made corrections to J750 loader to allow more test instances to be interpreted and

allows the patterns sets to be included more robustly. • Adjusted the comment fields to be more descriptive. • Updated configuration loader to allow source’s with no predefined pin order to use

the order from the CFG to defined the vector file format order. • Added more error checks to the pin configuration loader • Added a new licensing methods • Incremental improvements to the J973, J750, and 93K program translators • Adjustments to use new compilation features of newer ITE releases • Corrected errors in custom patterns creation • Added ability to stop pattern loads with a cancel button on the progress meter. When

cancelled, the portion of the file that has been loaded will be processed as normal.

Release: February 29, 2008: Velocity_V5.1.2 • Corrected error in the configuration loader that caused the “allPins” group to be

improperly defined. Reorder feature from previous release caused the trigger pin’s to be included when they should not have been.

• Adjusted the J750 loader to make sure that the beginning and ending of each sheet is properly maintained. An inconsistency could have caused sheets to be misinterpreted.

• Adjusted the J750 vector loader to allow for inline subroutines to be defined. This was causing entire vectors to be masked because the regular vector would be improperly cleared when the inline subroutine was entered in the load process.

• Added SOURCE_PORT and TARGET_PORT variables to the configuration to allow the beta GUI to predefine the port’s that are to be used for a given device. This makes translation a single button click instead of three.

• Made corrections to the 93K loader to properly order edges for the cases where cycle expansion is done. Xmode reductions were causing data to get scrambled when equations were used instead of raw times.

• Added MASK and STROBE command interpretation to the VCD loader. These commands can be imbedded as encoded test_instr register entries. STROBE and will turn on compare values. MASK will turn them off.

• Adjusted J750 pattern loader to allow subroutines with immediate returns. Prior to change immediate returns were seen as empty subroutine and the resulting export ignored the pattern.

• Added a few more tests to the J750 loader to allow for more test instances to be passed through to STIL PatternExecs

Release: March 14, 2008: Velocity_V5.1.4 • Added masking functionality to the EVCD loader for CPTD translation. • Adjusted J750 loader to set each spec set as unused until referenced by a calling test

instance so that duplicate category names are not introduced. • Made some adjustments to J750 loader to allow more cell references to be interpreted

as equations instead of using the XLS file’s evaluated result. For example, some cells reference cells that occur later in the file. Some accounting needed to be added so that forward references are allowable.

• Adjusted the J750 import engine to more accurately locate the proper specsets. Errors were happening that caused DC and AC specs to swapped.

• Corrected error in STIL export that was sometimes causing the level specs to be left out of the custom level usage schemes

• Corrected error in STIL export optimization that was not properly accounting for wave table changes in vectors. Error caused empty vectors to be inserted.

• Corrected error in J750 pattern loader that was causing commands and comments to get out of sync with the associated vector data. This error was introduced by an incomplete fix added by V5.1

• Applied updated Masking to the STIL export from VCD

• Updated the VCD loader to allow for old style VCD files to be passed without crashing

• Corrected a bug that was causing pattern execs imported from J750 test instances to use subroutine names instead of pattern names.

• Added some more usage error messages to the AVC/DVC translator Release: May 20, 2008: Velocity_V5.2.2 • Introduced the new version of the GUI as a beta. • Adjusted the optimization scheme to create more ways of optimizing. There is now

an added ability to leave original looping in pattern without introducing new compression. Compression will now also search for multi-line blocks for compression schemes

• Relay pins will be exported to STIL as Pseudo pins • Added Verilog feedback to Tester to Tester ports. • Added parallel scan support to STIL output • Added feature to allow users to adjust how libraries are included. These can now be

included as externally linked or copied internally to make the resulting programs portable.

• Corrected some bugs in the J973 translator to properly handle DDR cases • Added scan support to UltraFlex and J750 pattern translation • Added help documentation to Windows release • Added GTKWave support to Windows release • Added timing diagram to beta GUI file manager • Created more warnings and errors for configuration loader to provide more guidance. • Incremental improvements to all tester to tester ports • Modifed the make file options to use different compile options for DDR patterns so

that resources are not used up. • Adjusted Diamond JOB file to properly include libraries and properly create the

appropriate make files. Release: May 30, 2008: Velocity_V5.2.3 • Added messages to the log that will express options that are different from the

default. This will allow the complete conditions for the test to be passed to support. • Corrected an error in the pattern recognition feature that blocked the Jump/CJump

vectors from being properly inserted • Corrected error in J750 loader that attempted to use evaluate undefined timing sets. If

these are used, ITE complication errors will occur but this will be considered normal operation as the J750 program should not compile either.

• Corrected a bug that was preventing global variables from being properly imported to J750/UtralFlex

Release: June 10, 2008: Velocity_V5.3 • Corrected bug introduced at 5.2 that caused the normal vs. extended mode to be

incorrectly determined in J750 and UltraFlex patterns • Added buttons to the GUI for opening source and opening tester software • Added some more flexibility for evaluating conditional specs in J750 and UltraFlex

timing and levels. • Adjusted the location that is searched for v93000 CAE tools. • Corrected error in J750 loader that was adding duplicate entries into some groups and

causing vector length to be out of sync with the actual pin group size. • Corrected error in WGL spec evaluation that was causing values to be evaluated to

zero when they were not supposed to be. WGL files can use two equation sets simultaneously. These will now be imported into a single spec set in STIL.

• Corrected a bug in the AVC loader that was improperly treating xmode=1 waveforms with surround by data as if they were xMode 3. This forced incorrect data to be inserted into the resulting VEC file

• Corrected a similar bug to AVC xmode 1 surround by waveforms that were also preventing waveforms with inconsistent edges to be properly translated. Return waveforms for drive 0 with a third edge used for the subsequent drive 1 were being translated as X3. The timing was being translated correctly but the data was missing proper mapping.

• Adjusted the cycle count comment to match the cycle count seen in ITE patternTool and datalogger. Increments from 1 instead of 0.

• Corrected bug in DVC to STIL importer that was incorrectly placing edges from XModes greater than 1 into STIL waveform tables.

• Corrected a bug in the AVC import to STIL that was improperly warning of possible waveform changes from usages of multiple timing blocks. Custom timing should not have created this warning because they are known to be inherently different already.

• Corrected the bypass of import optimization that is now performed during export instead. The bypass was not properly circumventing all of the import functions, resulting in missing data in the resulting output.

• Added button to open browser for documentation and added training class slides to documentation list

• Added some functionality to automatically correct STIL errors caused by procedure calls that use differing pin lists from the calling pattern. Initial states must be defined for all pins that are used by a pattern.

• Adjusted the WGL export to STIL to break very large patterns into multi-file pattern bursts. This is to eliminate possible Kernel errors caused by file size limitations. WGL files can result in very large STIL representations.

• Adjusted J750 pin levels loader to expand pin groups so that reassignment will get taken care of for level sheets in which pins are multiply defined.

• Corrected and error in the VCD waveform loader to AVC that was improperly handling the scale Factor.

• Automatic groups will be created for busses during the VCD loader process. This will simplify the timing by merging busses together.

• Corrected a bug in the VCD loader that caused glitches to potentially appear as real data when enabling snapping. The two edges would snap to the same edge.

• Added a provision to the DVC export engine to allow return and solid waveforms to coexist in the same table even when snapping is enabled and multiple edges are requested.

• Corrected a bug that was clearing the format list on patterns that use multi port representation.

• Corrected the symbols that are assigned to the feedback Verilog files for busses. • Modified the multi line loop to allow XModes greater than 1 to be properly handled.

The length of loops must be a modulus of the xMode and the location of each loop must start at a spot that is compatible with both the length and the xMode.

Release: July 9, 2008: Velocity_V5.3.2 • Adjusted the J750 translator progress meter to properly reflect the target port • Added the Full Verilog Test Bench to the Verilog feedback. EVCD file and

Testbench file will both be exported in a Verilog directory. • Corrected error that did not properly clear information when going from one device to

another for J750 pattern translations. • Added a button to automatically archive the target program • Corrected an error in the WGL loader that prevented specs from being properly

loaded if used • Added simple HX support to the v93K export features. At this point 2 channels if 2

or 4 bit muxxing can be used. • Corrected a bug in the J973 loader that prevented some groups from being loaded in

the timing properly • Adjusted the order of pins assigned by the “initial state” group so that the order

matches the remaining cycles as closely as possible. Initial state group is only used for cycle zero procedure calls

• Adjusted the loading of complicated DVC files so that data is properly interpreted in the associated vector files.

• Added more support for differential channels when translating J750/UltraFlex to STIL.

Release: September 26, 2008: Velocity_V5.4.1 • Added RelayOpen, RelayClose, and a GoNoGo continuity test to the list of available

test functions that can be autognerated for the Diamond platform. • Added loader and tabular export engine for Sapphire XML programs • Updated normalization to make standard throughout all source and target platforms • Added general purpose 93K TestMethod generation. • Modified the J973 loader to properly interpret the specadr file’s order of tokens. • Updated the J750 and UltraFlex loaders to account for possible empty lines that

would have been read in as empty level and timing sets. Empty lines will be ignored. • Updated the AVC/DVC loader to properly handle groups. Groups must first be added

to the CFG. • Added group import capability for the CFG generation based on 93K pin

configuration file contents • Added HX support to AVC/DVC export engine • Updated the CFG loader to properly handle the situation where a TEST block uses the

$default pattern setup • Added warnings and auto-correction for CFG TEST blocks that use invalid timing,

level or spec settings. • Modified the order of loading blocks so that very large WGL files can be processed

without running out of memory. The scan states will now be loaded, interpreted, and purged as they are needed.

• Corrected an error in the incorporation of CFG groups and source platform groups that caused some items to be omitted and other repeated in error.

• Scan instances will be paged in 100 instance increments for ASL3000 output to avoid error capture errors.

• General bug fixes and optimization to all loaders and export engines • Added additional CFG loader warnings and auto-corrections to account for TEST,

PATTERN, and FLOW blocks • Updated the AVC import process to properly set the Noop edges to match the proper

value so that resources are not exhausted. • Updated DIBU usage to force an automatic inclusion of 5V and 12V static supply

channels for Diamond configurations which use relay connections. P5V and P12V will be protected pin names that will automatically be used to accommodate proper API’s.

• Updated configuration usage documentation to define the newly introduced RELAY commands to the CFG.

Release: October 16, 2008: Velocity_V5.4.3 • Modified the J750 and UltraFlex loaders to more reliably choose timing and specs for

patterns that are not already used by the source program. • Added Model to the list of CFG parameters. Only valid for 93K export. • Adjusted the pattern recognition to properly handle data rates greater than one when

paged export is occurring. This will prevent loops from beginning on invalid cycles that are not proper multiples of the data rate. This is only a factor for 93K export

• Adjusted UltraFlex Dual mode timing interpretation. • Adjusted the automated CFG creation process so that capital letters are used for pin

lists by default. • Adjusted the initial state group definition so that multiple insertions of pins does not

occur when sub groups are used • Added additional opcode interpretation to the J750 and UltraFlex pattern loader • Added proper usage of newer user libraries for Diamond • Modified the default no action waveform that is created for VCD translations • Corrected bug in VCD to DVC translator that was leaving out some actions • Added some usage warnings to alert the user to possible compilation issues that will

be asserted by using multiple data per cycle. • Updated VCD snapping to enable pulses that are faster than the snap resolution • Made a number of updates to the STIL export engine to comply more strictly with the

STIL standard. • Adjustments made to account for minimum pulse width declarations. Automatic

adjustments will be made with notifications to the log window • Corrected a bug in the optimization functions that left out the vector data in pre-

existing loops for STIL export functions.

Release: October 30, 2008: Velocity_V5.4.4 • Updated the J973 loader to create default values for specs that are not assigned values

after being defined in the spec form. • Updated the J973 loader to handle more features of the MCG operations of waveadrs • Adjusted how subroutines are loaded and called in the J973 loader • Fixed a bug in the J973 loader that prevented certain formats from properly finding

the start of patterns • Corrected a bug that incorrectly overwrote label names with opcodes • Added an error message for improper keywords in CFG Test definitions that will

cause errors upon compilation for Diamond programs • Added proper unit setups for timing and levels STIL blocks so that these are STIL

compliant. • Adjusted group definitions so that aliases that differ only by case are eliminated. This

is a STIL compliance issue • Corrected calls to the VDD continuity test in Diamond programs to properly account

for the optional delay value • Adjusted J973 import to allow for Noop action to be inserted. This is needed if pins

are not all defined and/or a subroutine is called at cycle zero. • Added a default setup to the CFG TEST definition so that a pattern is automatically

inserted to functional tests if no explicit pattern is requested. • Optimized the J973 spec loader to reduce redundant operations that slowed the

process down. • Corrected a bug in the interpretation of DDR J973 pattern data op codes. Loops were

not getting properly terminated or they were being expanded improperly. • Added warning to the STIL export engine to alert the user if alternate timing is

available that does not need auto-correction. Otherwise, timing will auto correct using spec sets that are requested. If nothing was explicitly requested and adjustment is needed, the adjustments will be made with no warnings.

• Corrected bug in the loop expansion of double data rate vector patterns. • Adjusted the VCD/EVCD loader to account for registers and wires simultaneously. • Corrected J973 mach4 mode to import to STIL as a double data rate vector. • Updated the J750 loader to allow the cancel button to exit before the program is

finished loading. Prior to this change, the cancel only applied to the pattern section. • Corrected bug in J750/UltraFlex loader that was causing the pin loader to get out of

sync with which pin or group was active. Pin groups would occasionally be entered as regular pins, which would cause duplicate entries to be issued.

• Changed the default interpretation of the MCG operation of J973 to be a RL format. • Corrected bug in VCD scaling that was remapping edges together improperly • Adjusted J973 loader to account for conditional compilation flags in ADR files • Corrected bug where units were being applied in error to scalar values.

Release: October 31, 2008: Velocity_V5.4.5 • Corrected bug in VCD loader that caused the page size to become too large for the

memory to handle • Added ability to convert STIL patterns using multiple pin groups into AVC format

with a single pin group. • Corrected timing to use only valid characters. Lower case L, H, and T were

potentially being used. • Added feature to the CFG loader to warn user of possible use of long pin names. Release: November 7, 2008: Velocity_V5.4.6 • Added KVD and Catalyst pattern export engines • Adjusted comments to use proper c-style • Corrected bug in J750 loader that was blocking some cell references from being

interpreted correctly • Additional adjustments to STIL export were made to make things more IEEE

compliant. • Adjusted STIL loader to optimize for speed. Interpretation of masked pins will noe

only be done on the first line. Subsequent lines will mask the same columns as the first line.

Release: November 10, 2008: Velocity_V5.4.7 • Corrected bug in STIL equation evaluation engine that prevented equations that do

not use specs from being evaluated. • Updated progress meter to provide warnings associated with large files. Files larger

that 2G will potentially get out of sync with the progress meter. This is a warning but does not cause errors. The progress meter will appear to hang, but it is not really hung. Be patient, and the program will eventually come out.

• Modified the J973 waveadr loader to make it more robust. Slight changes in the formatting were causing some wave tables to be dropped.

Release: November 12, 2008: Velocity_V5.4.8 • Reduced the volume of information that is sent to the progress meter for STIL loader

to improve throughput. This only affects the non-STIL output ports.

Release: November 17, 2008: Velocity_V5.5 • New licensing scheme implemented. Old scheme will still be readable, but new

licenses will use new encoding method. • Removed unneeded features from AVC loader to enhance speed. • Corrected bug in CFG generator that prevented EVCD from properly creating

PinLists • Adjustments to the STILtoAVC and AVCtoSTIL ports so that naming conventions

are the same. Timing blocks will now retain the names rather than reverting to the names of the patterns. This will reduce duplication of timing from pattern to pattern.

• Corrected bugs in the new config code for AVC and J750. J750 was optimized to work a little bit faster when only needing pins for CFG.

• Corrected bug in cycleCount comments in STIL export engine. Loops were incrementing the cycle count by one extra cycle.

• Modified the STIL export to combine 2 cycle loops if both cycles are the same. This will be done regardless of the optimization level.

• Corrected a bug in the VCD file processing that caused a crash in normal VCD file loading when an empty timestamp marker is encountered. The fix will let the user know the previous timestamp so that the missing time can be found. The line itself will be ignored.

• Adjusted parser engine to allow large file to be more accurately monitored for progress.

• Simplified the code that handles VCD direction control. Usage is not different but the code that interprets this usage is simplified.

• Added pin column label comments to AVC output port. • Modified the way that VCD/EVCD symbol duplication is handled. If both pins that

are defined with the same symbol are IO channels, then the first one will be masked in favor of the second. Warnings will be inserted to alert the user of condition.

• Corrected BUG in the STIL pattern compression algorithm that was not properly accounting for comments that should interrupt otherwise compressible sections of vectors.

Release: November 20, 2008: Velocity_V5.5.1 • Optimized the J973 loader to more efficiently handling the process of masking pins.

This will reduce the load time immensely as fewer loops will be needed to perform the masking actions.

• Adjusted the STIL export engine to properly block masked pins from the pattern pin column label.

• Added UltraFlex feature to allow timesheet and waveset references to be handled in direct fashion instead of only through indirect cell references.

• Decoupled the AVC loader port from some of the other Tester to Tester ports so that AVC to STIL could be enabled for 93K users.

• Corrected bug in the interpretation of J750 and Flex SBL and SBH waveforms. • Corrected test numbering bug that caused test number duplication with Diamond port

Release: November 26, 2008: Velocity_V5.5.2 • Corrected bug that prevented VCD bus definitions from consistently being defined.

Indexes that did not start at 0 were being dropped from pin group definitions. • Corrected VCD timing import to unneeded Z actions that occur in some drive

waveforms. This waveform is a byproduct of the startup conditions and should be dropped.

• Corrected a bug in the AVC loader that was improperly assuming that a space would appear before the semicolon on each line of the AVC files. This potentially would cause empty STIL files to be exported using the AVC to STIL port.

Release: December 2, 2008: Velocity_V5.5.3 • Enabled more of the tools for command line usage. AVCtoSTIL and STILtoCAT are

now activated. • Adjusted how DVC files are converted to properly allow pulses to be translated into

STIL notation. • Adjusted 93K pin configuration export to allow input only and output only channels

to be exported.

Release: January 6, 2009: Velocity_V5.5.4 • Modified 93K pin configuration creation to allow input only and output only setups to

be configured. Prior to this all digital pins were defined as IO so that the scope could be enabled for all pins. This is now left to the discretion of the user

• Added columns to the 93K AIC file to easily allow modifications to be made to pattern names to account for 40 character limitation of pattern names.

• Adjusted the WGL timeplate loader to prevent for multiple definitions of pins from overlapping improperly. After the adjustment, only the first definition for with input or output state will be active.

• Enabled the Flex and J750 translator for the 93K AVC/DVC output port. Automatic compilation will not yet work, but the pattern and timing files will be available for hand compilation using AIC and AIT.

• Added feature to properly mask POWER pins from AVC loader if included as regular IO pins in source file.

• Improved the stability of the waveadr loader for the J973 port. After fix, the program will keep in sync more accurately.

• Added provision to Diamond source file exports to correct function names that match C++ keywords like “short”.

• Adjusted how masking is optimized in the J973 pattern loader to account for column changes from line to line.

• Optimized the J973 pinadr loader to speed up the processing of the groups section • Changed the J973 subroutine loader to change how labels are defined. A disconnect

was occurring between the label names in the SVMADR and the way the LVMADR was calling it.

• Optimized the J973 SVMADR and LVMADR loaders to reduce the time required for calculating tokens.

• Removed the “default” from the pattern names used for the default port. Multi Port bursts will now have “_burst” appended to the name

• Updated the J750/UltraFlex translator to allow AVC/DVC export. This export process is not optimized in terms of timings but it will export everything so that hand removal of unneeded timings can be done.

Release: February 12, 2009: Velocity_V5.6.2 • Updated the licensing scheme to allow binary content • Added interpretation of the tristate comparison to the VCD/EVCD translator for all

target ports • Corrected some of the warning messages so that they are not printed when theyt are

not really needed. • Updated the way that the automatic spec groups are defined so that the append mode

would read in the same thing that is created. • Corrected a bug in the VCD loader that was preventing the X state character from

being loaded • Updated the way that edges per data and snapping are used so that fewer period

calculation errors are seen. The algorithm will be more reliable now. • Activated the WGL to Catalyst port. • Corrected STIL equation evaluation to properly handle scientific notation in

expressions. • Updated to properly handle the M character in J750/UltraFlex • Corrected bug in WGL equation loader that was causing some expressions to be split

between value, min ,and max instead of applying to all • Adjusted the way dual mode timings are loaded and imported to STIL to properly

account for setups that ignore certain edges. i.e. dual mode timing with drive data but no return will ignore the second edge.

• Adjusted the DVC output to allow a way to manage the Z actions that are used when multiple edges are defined per VCD cycle. Input only pins will only apply Z action to the first edge encountered. Compare actions will have X’s replaced with Z’s in the cases where an L or H is also requested. This will ensure that the drive is turned off for compare cycles.

• Changed the interpretation of UltraFlex Dual mode so that these are translated as single data rate by default instead of double data rate using 2 edges per cycle instead of 1.

• Corrected bug that was erasing commands in scan WGL files after first page. • Adjusted the autocorrection for usage of the static supplies that accompany the usage

of relay channels on the Diamond platform. Static names will automatically assigned to channels 128, 130, and 131 of the DIBU boards.

• Added automatic merging for J750 mux channels • Adjusted the input and output snapping resolution calculation so that only rational

numbers are used for snapping. Irrational numbers were causing drift issues for the resulting waveforms.

Release: February 19, 2009: Velocity_V5.6.3 • Added the ability to redefine the polarity of DIR pins so that they can be negative true

output enables. This will be done by adding the “NEG” character to the end of the control pin definition in the CFG pinlist section.

• Updated the documentation to add explanation of the mask MAP object in the configuration guide.

• Enabled the custom pattern section for 93K output. This can be used to provide customizable copies of patterns and modified masking schemes.

• Added the feature to mask the cycles that occur before time zero in EVCD/VCD files. This feature is enabled by default, but can be disabled by turning off all optimizations from hr GUI or from the command line.

• Corrected a bug that was improperly reassigning timings during J750 and UltraFlex translation.

• Corrected a bug in the WGL loader that was preventing scan states, scan chains, and scan cells from properly handling entries with square brackets in the name. Names were being truncated so that no data was found. This caused a hang situation.

• Corrected a bug in the WGL loader that was blocking the inclusion of timeplates when specs are used.

• Adjusted the snapping resolution equations so that the proper number of edges will be received.

• Added a feature to the AVC/DVC export that will use the tester model to determine the minimum period. Auto corrections can now be focused to the desired target platform.

• Added details to the DVC export engine that will help the user define manual periods when the calculated period does not provide legal results. The error messages will also provide some guidance on how the Velocity options should be set.

• Updated the way that UltraFlex dual timing mode is interpreted. Prior to the change, dual mode would be treated as an X2 pattern. This is now changed so that the dual mode patterns will be treated as regular X1 patterns. X2 will be left as an option that can be requested by the user.

• Updated the 93K loader to allow more than one AVC DVC combination to be used. Prior to the change DVC specs would get overwritten or ignored. These will not allow you to properly define the timing in one run. Alternatively, the append mode can now also be used to merge the two timing setups.

• Modified how J750 and UltraFlex global variables are included with specs. Global variables that are used in timing equations will be removed from the global space and inserted into each category of the spec sets so that they are properly represented and to prevent duplication inside DC spec sets.

Release: February 26, 2009: Velocity_V5.6.4 • Corrected bug in WGL loader to prevent hanging caused by particular arrangement of

include statements. Prior to change scanstate and scanchain blocks needed to be in the same file. Now these can be split by different includes.

• Corrected bug that could cause pattern name to improperly change when include files are used. Pattern will not be properly named based on the top level master file.

• Further updates to the AVC loader so that multiple AVC/DVC pairs can be translted in single run without losing timing information. All DVC’s will be loaded separately now and associations will be assumed based on the base names of each file.

• Adjusted some case sensitivity issues in the CFG loader Release: April 8, 2009: Velocity_V5.6.6 • Added a “-“ pin type that will allow IEEE stil export of unused pins in the target

signals list as PSEUDO pins. This will provide inherent documentation of unused pins

• Modified the padding of unused scan chains so that 0’s are used for input chains that are not used

• Added support for TetraMax WGL files. • Corrected bug in AVC to STIL transfer that caused multiple AVC/DVC files to be

associated improperly if more than once was chosen. • Corrected bug in WGL scan interpretation that caused errors with chains that were

either purely input or purely output. • Adjusted the STIL scan macro output to include inversions in the scan block

representation. • Adjusted a dedicated Inovys STIL export port • Added references to the Verigy STIL reader so that the STIL port can be used for the

93K as well.

Release: June 28, 2009: Velocity_V5.8.6 • Updated the AVC export to allow XModes greater than 2 to have automatically

generated CMB files. • Modified the VCD loader to insert strobes when oversampling is used • Corrected bug in AVC loader that was preventing certain instances of subroutines to

be translated properly • Changed usage of subroutines in STIL export to remove the initialState vector. This

was used to account for situations where the subroutine pinlist is different than the calling pattern. The current usage makes this unnecessary now.

• Corrected bugs in the creation of the AIC file so that proper usage is maintained when append mode is used.

• Changed the way groups are used in the DVC export. The DVC will not longer modify the data to allow more groupings to be made. This will be left to the compiler.

• Corrected paging errors in the masking scheme. Masking statements that look forward will now automatically allow paging adjustments

• Incremental performance and speed enhancements to the VCD loader Release: August 4, 2009: Velocity_V5.8.7 • Performance and speed enhancements to the AVC masking usage. • Added a GLOBAL mask scheme that will allow for faster implementation of masks

that are setup for tester specific reasons. i.e. I/O turn around time adjustments. • Corrected bug in the general purpose Diamond Shell Contructor. • Added additional flag to the GUI to allow J750/UltraFlex DC tests to be

enabled/disabled with a switch • Adjusted the 93K archive feature to zip up the entire device directory instead of just

the ascii file target directory Release: August 25, 2009: Velocity_V5.8.7d • Corrected bug in usage of custom levels that was improperly setting the spec

category • Fixed bug in paging scheme for VCD loader that was blocking masks at the end of

pages in certain instances • Re-activated masking in the STIL export engine

Release: September 18, 2009: Velocity_V5.8.8b • Modified outputs so the equation sets are named appropriately for each pattern. • Added the ability to import loops in WGL files. • Corrected bug in optimizer that caused loops to occur at invalid locations and with

incorrectly defined lengths. • Reactivated gzipped export of AVC and Verilog files. This is done so that files larger

than 2G can be exported without forcing kernel restrictions • Added custom loops to the AVC export process • Updated the STILreader setup file. • Modified the Verilog testbench export so that only change states are exported. File

size is reduced by this greatly. • Adjusted the order of Environment and Group blocks in STIL export • Added conditional adjustment of pattern groups so that group names do not exceed 16

characters for certain ports. • Updated CMB file creation so that multi port considerations are made. • Added proper accounting for edge usage for the WGL to STIL import process • Corrected some bugs in the J750/UltraFlex spec loader. • Optimized the J750/UltraFlex loaded to ignore spec categories that are never used. Release: October 7, 2009: Velocity_V5.8.9a • Updated the usage of multiple edges to properly account for the insertion if

intermediate comparisons. • Added MUX2 and MUX4 pin types to allow muxxing of signals to allow higher

speed operation. • Updated Verigy compilation to allow more flexibility in usage. • Reordered the usage of mask blocks so that default and custom masks can be used

without conflict • Added more error reporting to ease problem solving. • Updated Verilog testbench export. • Updated Verilog Cycled EVCD export.

Release: October 23, 2009: Velocity_V5.9b • Corrected bug in AVC loader that was improperly setting up wave indexes when

multiple DVC’s are referenced • Optimized the Verilog feedback to allow AVC to STIL translations to also include

Verilog feedback option • Updated WGL loader to allow single cycle loops • Added I2C loader option. This is similar in scope to the previously created SMBus

and FS2 options. This port is enabled automatically with the APG port license. • Corrected bug in WGL export that improperly defined the pattern pin group when

large scan files are split into multiple STIL pattern files • Added feature to the STIL export process that will allow surround-by waveforms to

be blocked with a CFG file directive. If asserted, the first edge of the surround-by will be removed.

Release: November 25, 2009: Velocity_V5.9.1 • Added JTAG port that separates FS2 from general purpose JTAG. • Added feature to toggle the usage of FAST mode timing when exporting to Verigy

93K port. • Optimized the setup files that are created for the Verigy port to properly handle

various usages of Xmodes, Fast mode, normalization and custom timings. Certain usage combinations were resulting in compilation errors.

• Upgraded the creation of combination files to allow for xmodes above 4. This is a requirement for handling higher speed devices

• Corrected a bug in the usage of compression that was improperly placing the beginning, end and size of loops relative to the data bit rate.

• Added feature to create static default states for pins when they are not used. This is important in the JTAG, I2C, and FS2 ports.

Release: January 20, 2010: Velocity_V5.9.1c • Updated JTAG port to support multiple patterns with HEX inputs • Updated WGL loader to support ultra-large functional WGL patterns • Updated J750/UltraFlex loader to properly handle expansion of loops in procedures

when they are concurrent. • Updated J750/UltraFlex loader to properly handle DC specs • Updated the Catalyst output port • Updated combination file creation to properly handle multi port • Updated STILreader and AIT/AIV setup files • Updated progress meter dialog to handle Ultra Large files. • Updated the Masking Utility so that global masks can be applied to specific pins. • Incremental improvements to the error reporting process for configuration file • Updated AVC compilation structure so that Xmode adjustments can be made without

having to completely retranslate

• Upgraded Xmode and Compression algorithms so they can be used together. • Adjusted the CTIM padding to allow Xmodes with period switching • Corrected bug in J973 loader that incorrectly handled busses and triggers • Corrected STIL loader so that modular file structures can be completely loaded • Corrected BUG in UltraFlex opcode usage, so that loops, masks, and procedure calls

occur at proper locations Release: January 29, 2010: Velocity_V5.9.1d • Upgraded J750/UltraFlex loader to handle forward referencing and direct referencing

so that timings can be defined properly when they are referenced to other pin’s edges. • Corrected Bug in the AVC loader to handle Xmode to STIL single mode transitions. • Added multiport support to the STIL export for those STIL targets that accept

multiple clock timings • Corrected a bug in the AVC export that allowed for loops that exceed the target

limits. • Incremental improvements made to the compilation setup files for all ports • Corrected UltraFlex pattern loader to properly use counter loops. Release: February 3, 2010: Velocity_V5.9.1e • Added support for memory test instance loading to the J750/UltraFlex loader • Corrected STIL export so that procedure calls do not happen inside loops. • Corrected normalization bug so that each spec set has waveform tables separately

calculated for the STIL export engine. • Corrected some minor issues with regard to the setup file used by Verigy STILreader. • Cleaned up some of the methods for choosing STIL comments. • Updated Diamond Compile process so that procedure calls remain present in the

output file tree view after process is finished. • Corrected ATP file loader so that files with both procedure and main patterns can be

fully loaded. • Updated Verigy STIL output so that Selector blocks are masked. This is not yet

supported. • Updated the STIL export engine to make sure that trigger pins are not multiply added

to timing and levels blocks. • Corrected the usage of the initial state so that only patterns that call a procedure that

has a different pinlist will use the initial state vector. Otherwise the line will be skipped.

• Updated the J750/UltraFlex loader to allow Memory Test, PMU, and PowerSupply tests to be included. If no custom flow is defined, a default flow extracted from the source program will be used instead.

• Updated Verigy STIL output to properly mark units in timing and specs

Release: February 10, 2010: Velocity_V5.9.2 • Added timeset switching capability to the Catalyst output port • Adding multi-line loop support to the Catalyst output port • Added Level equation export to the Verigy output port • Added xMode support to the IEEE STIL compilation process. • Corrected bugs in the IEEE port that prevented multiple patterns from properly

defining their own pin lists when using Multiple time domains. • Added TSET mapping block to configuration to allow for controlled timeset number

setups. TSET numbering will occur in alphabetical order of device cycle names otherwise.

• Added Compression support to the Catalyst export engine. • Modified AVC to STIL export so that pseudo timeset switching properly shows R0

and R1 waveforms as they are used. • Added additional test type support to the UltraFlex loader

Release: March 24, 2010: Velocity_V5.9.3 • Corrected comment structures for the Catalyst port • Enhanced the 93K import to allow for multiple ways to handle surround by

waveforms. Some STIL ports imply edge usage restrictions that mean surround by and compare waveforms need to be formatted certain ways. This can now be handled automatically or adjusted certain ways

• Corrected bugs in the J750 loader that were introduced during the 5.9.1 release’s UltraFlex fixes

• Updated the log file so that each execution creates a uniquely named log file with a timestamp.

• Updated the way that flows and subflows are imported for the J750/UltraFlex loader. Empty flows will be blocked.

• Corrected how the min and max are used for the 9K to STIL port. Min and max will be imported but since these are often only used for start and stop points for spec searches, these are not going to be referenced through selector blocks. They are present only for reference.

• Corrected the correction logic for comparisons outside of range. Corrections were made for delays that were greater than the limit. These are now corrected if they greater than or equal to the limit.

• Corrected bug in usage of CFG Test blocks that was leaving out test blocks in the resulting program.

• Corrected bugs in J973 MCG interpretation. • Warnings that were sent only to stderr are now sent to report window as well. • Added error message to indicate that incompatible setup files were called together

resulting in empty timing. This will instruct the use on corrective actions. • Remd the feature rthat attempted to xho a default flow when none was setup by the

CFG. • Corrected a bug in the AVC loader that was adding garbage to end of lines that

contained masking and used groups in the AVC

Release: April 25, 2010: Velocity_V5.9.3b • Corrected bug in STIL loader that was not recognizing Vector statements that were

after a comment line and inside a loop. • Updated STIL loader to provide warnings for missing CFG pins • Updated the AVC loader to automatically remap 0 and 1 to L and H for output only

channels. • Correction STIL to 93K translation port to properly account for the minimum loop

length and locations for sequencer commands when using Xmodes. • Updated J750 and UltraFlex loader to properly account for default units • Added additional functionality to determine the correct columns to use for defining

the patternSets in J750 and UF test instances. • Added functionality to properly remove internal nodes from WGL signal lists • Added Additional HX support to the AVC export process. Release: June 2, 2010: Velocity_V5.9.4 • Adjusted the limitations on AVC comment lengths. Long comments will now be

allowed. These will be truncated by the target compiler, but the comments will be left intact in the ascii files

• Added additional V101 STIL support. • Added more Test types to the supported list for J750 and UltraFlex conversions to

STIL. • Incremental improvements to the interactions with the V93000 ascii interface. • Updated the error messages associated with misused configuration blocks. Release: July 8, 2010: Velocity_V5.9.4c • Corrected bug in STIL loader that crashed when Z was used for the tristate

comparison. • Cleaned and removed some warnings that were not relavant. • Modifications to the wave orders that are used in the CMB files. This is done to

make the compiled tiing files easier to read. • Corrected bug that had wrong ownerships on a couple of GUI resources. • Updatedto make compatible with RH5.