Vector FPGA Acceleration of 1 -D DWT Computations … FPGA Acceleration of 1 -D DWT Computations...

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Vector FPGA Acceleration of 1-D DWT Computations using Sparse Matrix Skeletons Sidharth Maheshwari, Gourav Modi, Siddhartha, Nachiket Kapre School of Computer Science and Engineering Nanyang Technological University

Transcript of Vector FPGA Acceleration of 1 -D DWT Computations … FPGA Acceleration of 1 -D DWT Computations...

Page 1: Vector FPGA Acceleration of 1 -D DWT Computations … FPGA Acceleration of 1 -D DWT Computations using Sparse Matrix Skeletons Sidharth Maheshwari, Gourav Modi, Siddhartha, Nachiket

VectorFPGAAccelerationof1-DDWTComputationsusingSparseMatrix

Skeletons

SidharthMaheshwari,GouravModi,Siddhartha,NachiketKapreSchoolofComputerScienceandEngineering

NanyangTechnologicalUniversity

Page 2: Vector FPGA Acceleration of 1 -D DWT Computations … FPGA Acceleration of 1 -D DWT Computations using Sparse Matrix Skeletons Sidharth Maheshwari, Gourav Modi, Siddhartha, Nachiket
Page 3: Vector FPGA Acceleration of 1 -D DWT Computations … FPGA Acceleration of 1 -D DWT Computations using Sparse Matrix Skeletons Sidharth Maheshwari, Gourav Modi, Siddhartha, Nachiket

Matrix-Form1-DDWT

• Formulation:𝐶 = 𝑇𝑀 % 𝑋, where 𝑇𝑀 = ∏ 𝑇()

*)

• TMmatrixishighlysparseØLargenumberofmultiply-by-zerooperations

ØLargememoryfootprintconsistingofzeroes

• Goals:Ø SIMD-friendlyoperationsonnon-zerovaluesonly

Ø CustomizedDMAroutinesforefficientbandwidthutilization

Page 4: Vector FPGA Acceleration of 1 -D DWT Computations … FPGA Acceleration of 1 -D DWT Computations using Sparse Matrix Skeletons Sidharth Maheshwari, Gourav Modi, Siddhartha, Nachiket

Matrix-Form1-DDWT

• Formulation:𝐶 = 𝑇𝑀 % 𝑋, where 𝑇𝑀 = ∏ 𝑇()

*)

• TMmatrixishighlysparseØLargenumberofmultiply-by-zerooperations

ØLargememoryfootprintconsistingofzeroes

• Goals:Ø SIMD-friendlyoperationsonnon-zerovaluesonly

Ø CustomizedDMAroutinesforefficientbandwidthutilization

Page 5: Vector FPGA Acceleration of 1 -D DWT Computations … FPGA Acceleration of 1 -D DWT Computations using Sparse Matrix Skeletons Sidharth Maheshwari, Gourav Modi, Siddhartha, Nachiket

Matrix-Form1-DDWT

• Formulation:𝐶 = 𝑇𝑀 % 𝑋, where 𝑇𝑀 = ∏ 𝑇()

*)

• TMmatrixishighlysparseØLargenumberofmultiply-by-zerooperations

ØLargememoryfootprintconsistingofzeroes

• Goals:Ø SIMD-friendlyoperationsonnon-zerovaluesonly

Ø CustomizedDMAroutinesforefficientbandwidthutilization

Page 6: Vector FPGA Acceleration of 1 -D DWT Computations … FPGA Acceleration of 1 -D DWT Computations using Sparse Matrix Skeletons Sidharth Maheshwari, Gourav Modi, Siddhartha, Nachiket

SparseMatrixSkeleton

• Removemultiply-by-zerooperations• ReductioninmemoryfootprintofTM.

36

8

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ModifiedMatrix-Form1-DDWTN=65536

Page 8: Vector FPGA Acceleration of 1 -D DWT Computations … FPGA Acceleration of 1 -D DWT Computations using Sparse Matrix Skeletons Sidharth Maheshwari, Gourav Modi, Siddhartha, Nachiket

VectorBloxMXP

• Lanes: 16-32• Scratchpad: 64-128 KB• DMA bandwidth: 4-32 B/cycle

Page 9: Vector FPGA Acceleration of 1 -D DWT Computations … FPGA Acceleration of 1 -D DWT Computations using Sparse Matrix Skeletons Sidharth Maheshwari, Gourav Modi, Siddhartha, Nachiket

𝑁 = 2-., 𝐿 = 6𝑎𝑛𝑑𝑘 = 3

Results- Speedup

05

1015202530354045505560

MXP−DE2 MXP−DE4 MXP−ZedBoard

Speedup Baseline CPU

Raspberry PiZedboardBeagleBone Black

Page 10: Vector FPGA Acceleration of 1 -D DWT Computations … FPGA Acceleration of 1 -D DWT Computations using Sparse Matrix Skeletons Sidharth Maheshwari, Gourav Modi, Siddhartha, Nachiket

𝑁 = 2-., 𝐿 = 6𝑎𝑛𝑑𝑘 = 3

Results- Speedup

05

1015202530354045505560

MXP−DE2 MXP−DE4 MXP−ZedBoard

Speedup Baseline CPU

Raspberry PiZedboardBeagleBone Black

Page 11: Vector FPGA Acceleration of 1 -D DWT Computations … FPGA Acceleration of 1 -D DWT Computations using Sparse Matrix Skeletons Sidharth Maheshwari, Gourav Modi, Siddhartha, Nachiket

𝑁 = 2-., 𝐿 = 6𝑎𝑛𝑑𝑘 = 3

Results- Speedup

05

1015202530354045505560

MXP−DE2 MXP−DE4 MXP−ZedBoard

Speedup Baseline CPU

Raspberry PiZedboardBeagleBone Black

Page 12: Vector FPGA Acceleration of 1 -D DWT Computations … FPGA Acceleration of 1 -D DWT Computations using Sparse Matrix Skeletons Sidharth Maheshwari, Gourav Modi, Siddhartha, Nachiket

Summary

• We propose a Modified Matrix-Form scheme to unlock inherentparallelism in 1-D DWT

• We exploit the sparsity pattern in TM to reduce complexity fromO(𝑛8) to O(𝑛) using :

Ø Skeletons to avoid wastefulmultiply-by-zero operationsØ Rearrangement of input samples

• Speedups of 12-103x over state-of-the-art in-built signal libraryin Octave (dwt function)

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ExperimentalSetupMatrix-form1-DDWT

SparseMatrixSkeletons

CPU- OptimizedOpenBLASroutinesinOctaveandC(compiledwith–O3)- PerformancemeasuredusingPAPIv5.4.3- 32bARMv7onBeagleboneBlack,Zedboard,andARMv6onRaspberryPi

CPU+MXP- CustomizedDMAroutinesfordatatransferbetweenhostandMXP- 16-32vectorlanes- 64-128KBscratchpadmemory- PerformancemeasuredusingMXPTimingAPI- AlteraDE2/DE4andZedboard

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Results- Throughput

𝑁 = 2-., 𝐿 = 6𝑎𝑛𝑑𝑘 = 3

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20

40

60

80

0.1 1.0Throughput (GOps/S)

Ener

gy (m

J)●

●●

ARM (Beagl.)

ARM (Rasp.)

ARM (Zedb.)

MXP−DE2

MXP−DE4

MXP−Zed

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CHALLENGES:• Largevolumeofdata• Strictreal-timeprocessingconstraints• Highaccuracydemands• Energyconstraints,especiallyinembedded systems

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ModifiedMatrix-Form1-DDWTRearrangement


166,300 DWT

166,300 DWT

DWT TURKEY 2013

DWT TURKEY 2013

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FireFox 2 - DWT GmbH

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Amenability of Multigrid Computations to FPGA-Based Acceleration*

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1 © Copyright DWT GROUP 1 DWT reserve the right to make modifications without prior notice.

1 © Copyright DWT GROUP 1 DWT reserve the right to make modifications without prior notice.

FPGA Implementation of Image Fusion Technique Using DWT for … · 2016-09-09 · the proposed fusion algorithm based on DWT. Key Words: Unmanned Autonomous Vehicles, Micro Air Vehicle,

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COMPE472 Parallel Computing Embarrassingly Parallel Computations Partitioning and Divide-and-Conquer Strategies Pipelined Computations Synchronous Computations.

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Author's personal copy · Author's personal copy Explicit design of FPGA-based coprocessors for short-range force computations in molecular dynamics simulationsq ,qq Yongfeng Gu1,

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kaushal patel-DWT

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DWT Curves

DWT Curves

FPGA based Acceleration of Linear Algebra Computations.

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FPGA Implementation of 2D-DWT and SPIHT Architecture for ... · The HDL code is developed in Verilog for the modified filter architecture in 1D and 2D DWT processor is implemented

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Inform Your Instinct - DWT

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Performance analysis of DWT based OFDM over FFT based OFDM and implementing on FPGA

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Privacy Preserving Computations accelerated using FPGA ... · FPGA Overlay architecture and leverage hardware acceleration to tackle the scalability and efficiency challenges inherent

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w HUMBER PROGRESS 595 DWT PRODUCT TANKER · 2017-03-13 · HUMBER PROGRESS 595 DWT PRODUCT TANKER TANK ARRANGEMENT GENERAL INFORMATION Description: 595 DWT Single Hull EstuaryTanker

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An FPGA -based Run -time Reconfigurable 2 -D Discrete ... · 3.4 Variable -Width Adder ... One -level decomposition using the two -dimensional DWT, ... using an XCV1000 device with

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