201O 2nd International Conference on Mechanical and Electronics Engineering (ICMEE 2010)

Design and Implement of FFT Processor for OFDMA System Using FPGA

WANG Xiu-fang School of Electric Information Engineering;

Northeast Petroleum University Daqing City Heilongjiang Province, China

wxfdqpi@163.com

Abstract-In the downlink module of Orthogonal Frequency Division Multiple Access (OFDMA) system, there is needed an alterable points FFT processor. Therefore, it is meaningful to design a FFT processor for the FFT processor which input data points could be alterable. In this paper the variable input FFT processor is designed to meet the requirements of OFDMA system. For this, in this paper we select the 2D Fourier transform algorithm as the kernel algorithm, use VHDL language to present in detail a design of two-stage pipeline structure, use QuartusII and ModelSim SE for the simulation, and verify on the EP3C25Q240CSN chip FPGA. Simulation results show that the way of implementation and design is right and meet the IEEES02.16e standard, at the same time the data precision is 16 bits, limit the clock frequency of 100MHz, the overall timing design stability , and it could reach the scope of real-time processing.

Keywords - OFDMA; FFT; FPGA

I. INTRODUCTION

In modem communication systems Orthogonal Frequency Division Multiple (OFDM) plays a crucial role, and it will be replaced by Orthogonal Frequency Division Multiple Access (OFDMA) in the next generation wireless communication systems such as WiMAX and 3G-LTE standard [1], [2]. The OFDMA PRY is based on OFDMA modulation [3], which comprises of OFDM modulation as well as subcarrier allocation. Therefore, it is significant to focus more attention on wireless communication technology. IEEE Std 802.16 family [4] is a wireless metropolitan area network standard which is detailed in fixed service in 2004 edition and the 2005 edition for mobile access technology.

Many research staffs have put themselves in this project. Reference [5] presented a cascade structure of FFT processor which could implement input data length alterable based on radix-16 and radix-2/4/8 mix radix algorithm. Because the architectures needed more storage resources, the design need improve. At the same time it need increase precision using floating-point instead of fixed-point. Reference [6] presented a structure of FFT processor which used in DAB system base on radix-2 and radix-4 mix radix algorithm. It also needs improve the precision like paper in [5]. Therefore, after analyzed and compared the various FFT algorithms, Radix-2 Decimation-In-Time FFT and 2D FFT algorithms have been chosen. In order to ensure precision, the floating-point system used in the design. The paper presents a variable point FFT processor of a pipeline structure which occupied small area. The article is structured as follows. Fourier

HOU Zhen-long School of Electric Information Engineering;

Northeast Petroleum University Daqing City Heilongjiang Province, China

houzhenlong1314@163.com

Transforms which is chosen in this design are illustrated in Section II. In Section III, we propose the novel variable point FFT processor. In Section IV, the implementation and simulation will be detailed. At last, the concise conclusions remark this paper.

II. FOURIER TRANSFORM

Discrete Fourier Transform (DFT) is widely used in communications, radar, antenna arrays, GPS navigation, voice processing, image processing, and sonar systems. In different areas of signal processing also has an important position.

The Discrete Fourier transform (DFT) of the N-point

input X ( k ) is defined as follows:

N-I X(k) = LxCn)W;k

n=O k = 0,1, ... N -1 ( 1)

• • C

I h Wnk -j2trIN. EquatIOn (1): N IS the tranSlorm engt , N = e IS

twiddle factor. The Fast Fourier Transform (FFT) which presented by

Cooley and Tukey in their paper: "An algorithm for the machine calculation of complex Fourier Series" in 1965 is an optimized fast algorithm and increase the computational efficiency of the DFT. The algorithm is divided into time-based (DIT) and based on the frequency (DIF) fast Fourier transform. Both the DIF and the DIT FFT reorder the data from normal to bit reversed order (or the converse). The basic idea of these algorithms are that the N point FFT is divided into smaller and smaller parts until only two points FFT(Radix-2).

Long FFTs are quite often used for frequency analysis and communications applications[61• These long word lengths affect the memory architecture because long word lengths require more memory bandwidth for the matrix transpositions. The architecture is implemented using two shorter length FFTs (lengths NJ and N2) to calculate an FFT ofiengthN = NI xN2•

The two-dimensional (2D) FFT of N = NI X N2 is

defined as follows: N1-l 2;rn)k2 Nz-l _j2trn2kz _j2Jtnzk1

X[A;N2+k2]=�)e-J�(Ix[n2Nl+�]e N')]e N,

......... (2)

978-1-4244-7481-3/$26.00 © 2010 IEEE V2-297 Volume 2

2010 2nd International Conference on Mechanical and Electronics Engineering (ICMEE 2010)

� 64-point FFT

---+ Twiddle

---+ Data Storage

---. Variable point FFT

Module Factor Module Module Module (include -v

2-point,8-point,16-poin t t t

I I t and 32-point FFT

Select and control module Module)

Output

c:::::)

Fig.I.Block diagram of the overall design of the FFT processor

['S.;iirth:Jrt .... ··· · · · .. · · · .. ··· .. . ... ................................... .

Fig.2. The architecture of the overall design

III. ARCHITECTURE DESIGN

For the variable point FFT processing, if cascade method and pipeline structure was used "ping-pong" memory architecture adopted in the design, each level need a lot of memory, so the system becomes too large. Therefore, this paper used 2D FFT algorithm to design the FFT processor, not only improved the system level of the parallelism, but also reduced the demand for memory systems.

A. The overall design of the FFT processor

The FFT module is the core part in the OFDMA system, IEEE Std 802.16-2005 defined clearly: the core module of OFDMA physical layer is the FFT module, which can be used in the FFT points are: 2048 points (back compatible with IEEE Std 802.16-2004), 1024 points, 512 points and 128 points. The design about variable point FFT processor is just based on FFT module in OFDMA system application.

According to the idea of two-dimensional Fourier algorithm, i.e. N = 128, NJ = 2, N2 = 64. From 128 = 2 * 64 We find that when achieve 128-point FFT, Firstly the data is arranged in 64 lines and 2 rows, Secondly the input data will transform the 64 points FFT, then the result multiplies twiddle factor, Thirdly, let the result do 2 points FFT. Similarly, Calculation of the 512-point FFT firstly do the 64 points FFT, then transform further 8 points FFT; The same way to calculate the 1024 and 2048 points FFT. Block diagram of the overall design of the FFT processor as shown in Fig.l. In Fig.2 we see that the architecture of the overall design described by VHDL language.

B. 64-point FFT module

This module is the most frequently used in the design. Four kinds of input data length all must first pass through the 64 points FFT module. Block diagram of this part is shown in Figure 3.

Input 8-point FFT

module

Twiddle

Factor

Wnk N

8-point FFT

module

utput

c::>

Fig.3 Pipeline structure of the 64-point FFT processor

TABLE I. RESULTS OF 8-POINT FFT PROCESSOR

Results ofS-point FFT module Results of Matlab

Rea/parts 111Ulginary parts

I 0 1.0000

5.01045 3.38915 5.0104 + 3.389li

2.50005 4.50005 2.5000 + 4.5000i

-7.01045 4.38915 -7.0104 + 4.389li

6 0 6.0000

-7.01045 -4.38915 -7.0104 - 4.3891i

2.50005 -4.50005 2.5000 - 4.5000i

5.01045 -3.38915 5.0104 - 13891i

The same idea in the module based on 2D Fourier transform algorithm is composed of two 8-point FFT modules. So 8-point FFT module is the kernel in this part, its performance affects the whole design. The 8-point FFT processor architecture consists of a single radix-2 butterfly (which is referred as the butterfly processing element), a dual-port FIFO RAM, a coefficient ROM, a controller and

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2010 2nd International Conference on Mechanical and Electronics Engineering (ICMEE 2010)

an address generation unit. The Input data is [1 -1 0.5 -3 2 -2.5 0 4] and the result of 8-point FFT module and the result of MATLAB are shown in Table 1. It is inferred that: the results of the 8-point FFT module match that from Matlab. And the result error is within the allowable range. Therefore, it's acceptable to adopt the 8-point FFT processor as the kernel module of the 64-point FFT module.

C. Select and control module

This part is the kernel to complete the alterable data length in the design. It is based on the input data points to select the results stored in the middle data memory, and then choose the way to next flow. A two bits signal 'mode' is chosen as the mode signal. When mode = 00, means to choose 2 points FFT module, to complete the 128-point FFT; when mode = 01, means to choose 8 FFT module, to complete the 512-point FFT; Equally: When the mode = 10, means to completed 1024 point FFT; when mode = 11, means to complete the 2048 point FFT.

IV. SIMULATION AND IMPLEMENTATION

The input data length of our proposed FFT processor is a parameter which can be decided by itself at the range of 128, 512, 1024 and 2048 points. Take 1024 points FFT as an example. At first, the 1024 points FFT is coded by MATLAB language. After the chosen FFT algorithm is valid, the architecture of the processor was modeled in VHDL language and functionally verified using QuartusII software and timing simulation using ModelSim SE software. When verifY the timing simulation, a testbench file included the TEXTIO package was written to read input data and write FFT result, Parts of the procedure as follows:

file vector yle text open read mode is "F: \test J_FFninput. txt" ;

file vector yle text open write mode is "F: \test J_FFnresult. txt" ;

Figure 4 is the FFT waveform which the input points changing to 1024-point mode, it shows that after a latency of 21.175 us the FFT results start to output. The results of the simulation were seen to match the theoretical calculation of Matlab, result error within the allowable range, therefore, the design and implementation is right and meet the standard IEEE802.16e FFT requirements.

V. CONCLUSIONS

In this paper, a variable point FFT processor was designed using FPGA and was applicable to OFDMA system successfully. The processor use VHDL language to describe the circuit, use QuartusII 7.2 software to build the model, and use ModelSim SE 6.2b software to verifY the timing function. The results showed that: the successful completion of the design altered input points FFT computation, design precision 16-bit, and limited to 100MHz clock frequency, the overall timing design stability, FFT processing result was correct. Therefore, this design can be applied to real-time signal processing system, completes the main computing modules in the OFDMA system.

REFERENCES

[I] WiMAX Forum, Krishna Ramadas and Raj Jain, "WiMAX System Evaluation Methodology" version 2.1 July 2008

[2] 3GPP TR 25.814 v.I.S, Physical Layer Aspects for Evolved UTRA(release 7),May 2006.

[3] www.ofdma-manfred.com

[4] IEEE Std 802.16e™-200S and IEEE Std 802.16™-2004/Corl-200S

[5] Zhang Zhu-jun, " Optimum Design of FFT Processor with Cascade Structure Based on FPGA," J. Nanjing University of Science and Technology. 2009. in press.

[6] Xie Yan-Iin. "Design and Implementation of a Scalable Pipeline FFT Processor Based on FPGA" D. Xi Dian University.2007, in press.

Fig.4 Waveform of the 1024-point FFT

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