VCU110 EVALUATION PLATFORM HW-U1-VCU110 D XCVU190 … · 2015. 9. 21. · 3 1 2 bas40-04 40v c357 2...

92
THE DOCUMENTATION IS DISCLOSED TO YOU “AS-IS” WITH NO WARRANTY OF ANY DOCUMENTATION. INCLUDING ANY LOSS OF DATA OR LOST PROFITS, ARISING FROM YOUR USE OF CONSEQUENTIAL, INDIRECT, EXEMPLARY, SPECIAL, OR INCIDENTAL DAMAGES, OF THIRD-PARTY RIGHTS. IN NO EVENT WILL XILINX BE LIABLE FOR ANY MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NONINFRINGEMENT STATUTORY, REGARDING THE DOCUMENTATION, INCLUDING ANY WARRANTIES OF KIND. XILINX MAKES NO OTHER WARRANTIES, WHETHER EXPRESS, IMPLIED, OR XILINX IS DISCLOSING THIS USER GUIDE, MANUAL, RELEASE NOTE, SCHEMATIC, AND/OR SPECIFICATION (THE “DOCUMENTATION”) TO YOU SOLELY FOR USE IN THE DEVELOPMENT OF DESIGNS TO OPERATE WITH XILINX HARDWARE DEVICES. YOU MAY NOT REPRODUCE, DISTRIBUTE, REPUBLISH, DOWNLOAD, DISPLAY, POST, OR TRANSMIT THE DOCUMENTATION IN ANY FORM OR BY ANY MEANS INCLUDING, BUT NOT LIMITED TO, ELECTRONIC, MECHANICAL, PHOTOCOPYING, RECORDING, OR OTHERWISE, WITHOUT THE PRIOR WRITTEN CONSENT OF XILINX. XILINX EXPRESSLY DISCLAIMS ANY LIABILITY ARISING OUT OF YOUR USE OF THE DOCUMENTATION. XILINX RESERVES THE RIGHT, AT ITS SOLE DISCRETION, TO CHANGE THE DOCUMENTATION WITHOUT NOTICE AT ANY TIME. XILINX ASSUMES NO OBLIGATION TO CORRECT ANY ERRORS CONTAINED IN THE DOCUMENTATION, OR TO ADVISE YOU OF ANY CORRECTIONS OR UPDATES. XILINX EXPRESSLY DISCLAIMS ANY LIABILITY IN CONNECTION WITH TECHNICAL SUPPORT OR ASSISTANCE THAT MAY BE PROVIDED TO YOU IN CONNECTION WITH THE THE DOCUMENTATION. THE XILINX HARDWARE, FPGA AND CPLD DEVICES REFERRED TO HEREIN ("PRODUCTS") ARE SUBJECT TO THE TERMS AND CONDITIONS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED AT http://www.xilinx.com/warranty.htm. THIS LIMITED WARRANTY DOES NOT EXTEND TO ANY USE OF PRODUCTS IN AN APPLICATION OR ENVIRONMENT THAT IS NOT WITHIN THE SPECIFICATIONS STATED ON THE XILINX DATA SHEET. ALL SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE. PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE, OR FOR USE IN ANY APPLICATION REQUIRING FAIL-SAFE PERFORMANCE, SUCH AS LIFE-SUPPORT OR SAFETY DEVICES OR SYSTEMS, OR ANY OTHER APPLICATION THAT INVOKES THE POTENTIAL RISKS OF DEATH, PERSONAL INJURY OR PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). USE OF PRODUCTS IN CRITICAL APPLICATIONS IS AT THE SOLE RISK OF CUSTOMER, SUBJECT TO APPLICABLE LAWS AND REGULATIONS. ALL SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE. DISCLAIMER: VCU110 EVALUATION PLATFORM HW-U1-VCU110 XCVU190-FLGC2104 A B C D 1 2 3 4 D C B A 4 3 2 1 SHEET SIZE: B SHEET OF VER: REV: DRAWN BY: TITLE: DATE: 1.0 01 BF 09/21/2015:13:57 PCB P/N: 1280790 TEST P/N: TSS0174 SCH P/N: 0381622 ASSY P/N: 0431880 92 1 Title Page SCHEM, ROHS COMPLIANT HW-U1-VCU110_REV1_0

Transcript of VCU110 EVALUATION PLATFORM HW-U1-VCU110 D XCVU190 … · 2015. 9. 21. · 3 1 2 bas40-04 40v c357 2...

  • THE DOCUMENTATION IS DISCLOSED TO YOU “AS-IS” WITH NO WARRANTY OF ANYDOCUMENTATION.

    INCLUDING ANY LOSS OF DATA OR LOST PROFITS, ARISING FROM YOUR USE OFCONSEQUENTIAL, INDIRECT, EXEMPLARY, SPECIAL, OR INCIDENTAL DAMAGES,OF THIRD-PARTY RIGHTS. IN NO EVENT WILL XILINX BE LIABLE FOR ANYMERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NONINFRINGEMENTSTATUTORY, REGARDING THE DOCUMENTATION, INCLUDING ANY WARRANTIES OFKIND. XILINX MAKES NO OTHER WARRANTIES, WHETHER EXPRESS, IMPLIED, OR

    XILINX IS DISCLOSING THIS USER GUIDE, MANUAL, RELEASE NOTE, SCHEMATIC,AND/OR SPECIFICATION (THE “DOCUMENTATION”) TO YOU SOLELY FOR USE INTHE DEVELOPMENT OF DESIGNS TO OPERATE WITH XILINX HARDWARE DEVICES.YOU MAY NOT REPRODUCE, DISTRIBUTE, REPUBLISH, DOWNLOAD, DISPLAY, POST,OR TRANSMIT THE DOCUMENTATION IN ANY FORM OR BY ANY MEANS INCLUDING,BUT NOT LIMITED TO, ELECTRONIC, MECHANICAL, PHOTOCOPYING, RECORDING,OR OTHERWISE, WITHOUT THE PRIOR WRITTEN CONSENT OF XILINX.XILINX EXPRESSLY DISCLAIMS ANY LIABILITY ARISING OUT OF YOUR USE OFTHE DOCUMENTATION. XILINX RESERVES THE RIGHT, AT ITS SOLE DISCRETION,TO CHANGE THE DOCUMENTATION WITHOUT NOTICE AT ANY TIME. XILINX ASSUMESNO OBLIGATION TO CORRECT ANY ERRORS CONTAINED IN THE DOCUMENTATION, ORTO ADVISE YOU OF ANY CORRECTIONS OR UPDATES. XILINX EXPRESSLYDISCLAIMS ANY LIABILITY IN CONNECTION WITH TECHNICAL SUPPORT ORASSISTANCE THAT MAY BE PROVIDED TO YOU IN CONNECTION WITH THE

    THE DOCUMENTATION.

    THE XILINX HARDWARE, FPGA AND CPLD DEVICES REFERRED TO HEREIN ("PRODUCTS")ARE SUBJECT TO THE TERMS AND CONDITIONS OF THE XILINX LIMITED WARRANTY WHICHCAN BE VIEWED AT http://www.xilinx.com/warranty.htm. THIS LIMITED WARRANTYDOES NOT EXTEND TO ANY USE OF PRODUCTS IN AN APPLICATION OR ENVIRONMENT THATIS NOT WITHIN THE SPECIFICATIONS STATED ON THE XILINX DATA SHEET.

    ALL SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE.

    PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE, OR FOR USE IN ANYAPPLICATION REQUIRING FAIL-SAFE PERFORMANCE, SUCH AS LIFE-SUPPORT OR SAFETYDEVICES OR SYSTEMS, OR ANY OTHER APPLICATION THAT INVOKES THE POTENTIALRISKS OF DEATH, PERSONAL INJURY OR PROPERTY OR ENVIRONMENTAL DAMAGE

    ("CRITICAL APPLICATIONS"). USE OF PRODUCTS IN CRITICAL APPLICATIONS IS ATTHE SOLE RISK OF CUSTOMER, SUBJECT TO APPLICABLE LAWS AND REGULATIONS. ALLSPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE.

    DISCLAIMER:

    VCU110 EVALUATION PLATFORM HW-U1-VCU110

    XCVU190-FLGC2104

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    PCB P/N: 1280790

    TEST P/N: TSS0174SCH P/N: 0381622

    ASSY P/N: 0431880

    921

    Title PageSCHEM, ROHS COMPLIANTHW-U1-VCU110_REV1_0

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    TEST P/N: TSS0174SCH P/N: 0381622

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    922

    Block DiagramSCHEM, ROHS COMPLIANTHW-U1-VCU110_REV1_0

    BANK# PAGE#

    BANK 0

    BANK#14-pin JTAG CONN.

    Page 26

    PAGE#

    BANK 67

    BANK 70BANK 71

    MECHANICALS

    BANK 84

    BANK 66 PWR/GND BANKS4

    55

    3

    BANK 72

    BANK 65 BANK 94

    DECOUP. CAPS

    77

    9

    8

    9

    11

    Page 91

    18-2324-25

    & Buffers

    User SMA Clock

    SYSMON OP AMPs

    Pages 69-70

    System Controller

    Page 50-53,58

    IIC, JTAG, SD J83

    Page 75VCCINT Regulator @ 80A

    Page 77VADJ_1V8 Regulator @ 10A

    Page 78VCC1V2 Regulator @ 10A

    Page 81MGTAVCC Regulator @ 45A

    Page 82MGTAVTT Regulator @ 45A

    Page 83MGTVCCAUX Regulator @ 1A

    SYS_5V0 Regulator @ 1A

    Page 88SYS_1V0 Regulator @ 2A

    Page 88SYS_2V5 Regulator @ 2A

    12VDC

    Page 27-28

    QDR2+ 36-bit

    Page 39

    FMC HPC0 DP[0:7]

    HR

    HR

    HPHPHP

    0

    HP

    66 65

    U1

    GTH224

    GTH230

    GTH229

    GTH228

    GTH227

    GTH226

    GTH225

    XCVU190FLGC2104

    67

    HP

    727170

    84

    94HP

    GTH233 GTH231

    GTH220 GTH221

    GTH222

    GTY124

    GTY130

    GTY129

    GTY128

    GTY127

    GTY126

    GTY125

    GTY131

    GTY121

    GTY122

    GTY133

    GTY120

    VCCBRAM

    VCCAUX, VCCAUX_IO

    VCCINT, VCCINT_IO

    VCCINT

    MGTY120-122 10MGTY124-127MGTY128-131MGTY132-133

    1213

    17

    MGTH220-222MGTH224-227

    MGTH228-231MGTH232-233

    1415

    16

    PAGE#DIGILENT USB JTAG

    CY7C2663KV18-550BZXC(18-bit SIO)

    Page 29-31

    RLD3 36-bit

    MT44K16M36RB-093E(36-bit CIO)

    Page 29,30

    RLD3 18-bit

    MT44K32M18RB-093E(18-bit CIO)

    HYBRID MEM. CUBE

    Page 32-37

    SI5328C andSI53340

    Page 38

    Page 43

    FMC HPC1 DP[0:7]

    Page 63

    BULLSEYE3 J111 PCIe

    HPC0 LA

    Page 39,67

    HPC1 LA

    Page 43,67

    FMCFMC

    Page 60

    INTERLAKEN J121

    Page 63

    BULLSEYE1 J87 GTY

    Page 54-55

    CFP4 MODULES 0-3

    Page 63

    BULLSEYE2 J122 GTY

    J107-J110

    Page 59

    EXAMAX J116

    Clock Buffer

    SI5328B andSI53301, SI53340

    Page 57, 62

    Clock Buffers

    SYSCLK_300

    CLK_125MHZ USER_SI570

    DUAL QSPI Pg. 65ETHERNET PHY Pg. 64DUAL USB UART Pg.66IIC MAIN Pg. 72

    PMOD HDR.Page 71

    GPIO LEDsPage 67

    GPIO DIP

    Page 67

    SW. 4-POLEPBSW W,NPBSW E,S

    PBSW CPB CPU_RESET

    SYSMON MUXINTERFACE TOBANK 67

    Page 71

    Page 79VCC1V5 Regulator @ 6A

    Page 80HMC1V2 Regulator @ 20A

    Page 84UTIL_0V9 Regulator @ 15A

    Page 85UTIL_1V35 Regulator @ 10A

    Page 86UTIL_3V3 Regulator @ 20A

    Page 87

    Page 88SYS_1V8 Regulator @ 1A

    also VCCINT_IO and VCCBRAM

    Page 76VCC_1V8 Regulator @ 10A also VCCAUX and VCCAUX_IO

    GTH232GTY132

    68

    HP

    BANK 68 6

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    TEST P/N: TSS0174SCH P/N: 0381622

    ASSY P/N: 0431880

    923

    FPGA Bank 0SCHEM, ROHS COMPLIANTHW-U1-VCU110_REV1_0

    GNDGND

    GND GND

    GRN

    RED

    1%

    261

    R472

    1 2

    R473261

    1%

    1 2

    R1154.70K

    1%

    1

    2

    DS2

    LED-GRN-RED

    21

    4 3FPGA_INIT_B

    FPGA_VBATT

    Bank 0 HR

    GND

    R339DNP

    DNP

    1

    2

    SYSMON_AGND

    FPGA_TDO_FMC_TDIJTAG_TMSJTAG_TCK

    FPGA_CCLK

    FPGA_M2

    FPGA_PROG_B

    FPGA_DONE

    FPGA_VBATT

    FPGA_INIT_B

    FPGA_SYSMON_VCCGND

    D153

    1

    2

    BAS40-0440V

    C357

    2

    1DNPDNP

    VCC1V8 VCC1V8

    FPGA_DONE

    VCC1V8

    UTIL_3V3

    25V0.1UF

    1

    2

    C2

    U53

    3

    2

    1

    4

    6

    5 DIR

    VCCB

    B

    VCCA

    GND

    A

    SC70_6

    SN74AVC1T45

    2

    1

    1%

    4.70KR116

    GND

    2 1LED-GRN-SMTDS34

    1

    DNP

    DNPR547

    2SYSMON_VP_R_I2C

    GND

    SYSMON I2C Address jumpers

    COMBINED_PGOOD

    J78

    4321

    HDR_1X4

    GND

    R5531

    2

    200

    1%1%

    200

    2

    1R554

    C5400.1UF

    25V 2

    1

    DIR

    VCCB

    B

    VCCA

    GND

    A

    U84SC70_6

    SN74AVC1T45

    3

    2

    1

    4

    6

    5

    GNDGND

    1

    2 25V0.1UFC541C542

    0.1UF25V 2

    1

    PCIe Test Header

    C633

    25V

    1

    20.1UF

    1 2 3

    HDR_1X3

    J5

    VCCINT_FPGA

    GND

    LAYOUT: Place CCLK termination padsafter last QSPI device

    GND

    SYSMON_VN_R_I2C

    POR_OVERRIDE selectDefault: 2-3 GND

    J80

    HDR_1X22 1 SYSMON_VP

    SYSMON_VN12HDR_1X2

    J81

    NC

    GND

    GND GND

    VCC1V8

    DIR

    VCCB

    B

    VCCA

    GND

    A

    U90 SC70_6

    SN74AVC1T45

    3

    2

    1

    4

    6

    5

    C6420.1UF

    25V 2

    1 C643

    25V0.1UF

    2

    1

    1 2

    1%

    261

    R598

    R548 1

    2

    20.5K

    1%

    1%

    20.5K

    2

    1R560

    FPGA Bank 0

    JTAG_TDI

    COMBINED_PGOOD_LS

    VCC1V8_FPGA

    UTIL_3V3

    UTIL_3V3

    UTIL_3V3

    FPGA_M1FPGA_M0

    FPGA_M2FPGA_M1FPGA_M0

    R10831

    2

    1.21K

    1%

    VCC1V8

    GND

    1%

    1.21K

    2

    1 R1084

    R10851

    2

    1.21K

    1%

    SYS_1V8

    SYS_1V8

    R6

    1%

    4.70K1

    2

    VCC1V8

    B1

    1

    2BAT_TS518_TS621_DUAL

    TS518FE_FL35E

    1 2

    L13

    FERRITE-600

    VCC1V8_FPGA

    GND

    SYSMON_VPSYSMON_VN

    L87

    FERRITE-600

    21

    GND

    QSPI0_IO1

    QSPI0_CS_B

    QSPI0_IO0

    QSPI0_IO3QSPI0_IO2

    C2055

    2

    10.47UF10V

    SW16

    6

    45

    123

    SDA03H1SBD

    1/10W

    1/16W

    1/10W

    1/16W

    DNP

    1/16W

    DNP

    1/10W

    DNP 1/10W

    1/10W

    200MW

    1/10W

    1/10W1/10W

    1/10W

    1/10W

    X5R

    DNPDNP

    DNPR4181

    2

    1/16W1%

    1.00KR16651

    2

    VCC1V8_FPGA

    U1

    K14AB14AF14AE20AE19AB20AB19AC19AD20AC20AD19AN13AB16AD16AB15AD15AF15P14AE14M14AC14AH14AF16AK14AM14T14V14Y14

    AE15AC15 VCCO_0_AC15

    VCCO_0_AE15M0_0_Y14M1_0_V14M2_0_T14

    D00_MOSI_0_AM14D01_DIN_0_AK14

    D02_0_AF16D03_0_AH14

    DONE_0_AC14CFGBVS_0_M14

    PROGRAM_B_0_AE14INIT_B_0_P14

    TDI_0_AF15TDO_0_AD15TMS_0_AB15TCK_0_AD16

    CCLK_0_AB16VBATT_AN13

    VN_AD19VP_AC20

    VREFP_AD20VREFN_AC19

    GNDADC_AB19VCCADC_AB20

    DXN_AE19DXP_AE20

    RDWR_FCS_B_0_AF14POR_OVERRIDE_AB14

    PUDC_B_0_K14

    XCVU190FLGC2104BANK 0

    SOC_FLGC2104_IRON

    SOC_VU190_FLGC2104_IRONWOOD

    1/16W4.70KR236

    1%

    1

    2

    POR_OVERRIDE_PIN

  • A

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    C

    D

    1234

    D

    C

    B

    A

    4 3 2 1

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    PCB P/N: 1280790

    TEST P/N: TSS0174SCH P/N: 0381622

    ASSY P/N: 0431880

    924

    FPGA Banks 65SCHEM, ROHS COMPLIANTHW-U1-VCU110_REV1_0

    Bank 65 HP

    FPGA_EMCCLK

    SYSMON_SDA_LSSYSMON_SCL_LS

    FPGA Banks 65

    VCC1V8_FPGA

    FMC_HPC0_PRSNT_M2C_B_LS

    FMC_HPC1_PRSNT_M2C_B_LS

    QSPI1_IO1

    QSPI1_CS_B

    QSPI1_IO0

    QSPI1_IO3QSPI1_IO2

    PHY_RESET_LS

    PHY_INT_LS

    PHY_MDC_LS

    SGMII_RX_NSGMII_RX_P

    PHY_MDIO_LSFMC_HPC1_PG_M2C_LS

    SGMII_TX_PSGMII_TX_N

    IIC_MAIN_SCL_LS

    USER_SI570_CLOCK_P

    SGMIICLK_NSGMIICLK_P

    SGMIICLK_N

    SGMIICLK_P

    2

    1

    1%

    100R865

    SGMII_RX_N

    SGMII_RX_P

    2

    1 R1178100

    1%

    USER_SI570_CLOCK_P

    USB_UART_TXUSB_UART_RTS

    USB_UART_CTSUSB_UART_RX

    PMBUS_ALERT_FPGASM_FAN_PWM

    SM_FAN_TACH

    SYSCTLR_GPIO_5SYSCTLR_GPIO_7

    CLK_125MHZ_N

    CLK_125MHZ_P

    CLK_125MHZ_NCLK_125MHZ_P

    SYSCTLR_GPIO_6IIC_MUX_RESET_B_LS

    MOD_RSTN_CFP4_LSGLB_ALRMN_CFP4_LS

    1%

    100R1501

    2

    1%

    100R8661

    2

    USER_SI570_CLOCK_N

    USER_SI570_CLOCK_N

    FMC_VADJ_ON_LSVADJ_1V8_PGOOD_LS

    ILKN_FC_TX_SYNC_LS

    ILKN_FC_RX_SYNC_LS

    ILKN_FC_TX_DATA_LS

    ILKN_FC_RX_DATA_LS

    ILKN_FC_TX_CLK_LSILKN_FC_RX_CLK_LS

    SI5328_RST_LSIIC_MAIN_SDA_LS

    1/10W

    1/10W

    1/10W

    1/10W

    FMC_HPC0_PG_M2C_LS

    CFP4_REC_CLOCK_C_NCFP4_REC_CLOCK_C_P

    U1

    BE20BF20BD20BE16BF16BE19BF19BD18BE18BE17BF17BD17BD16BC20BC19BA19BB19BA21BB21BB18BC18AY20BA20BC21AY19AY18AV20AW20AV19AW18AW17AV21AW21AU18AV18AT21AU21AT19AU19AR20AT20AR19AR18AM21AN21AM19AN19AN20AP20AP21AN18AP18AM18

    AM20AR21AT18AW19BB20BF18 VCCO_65_BF18

    VCCO_65_BB20VCCO_65_AW19VCCO_65_AT18VCCO_65_AR21VCCO_65_AM20

    VREF_65_AM18IO_L1N_T0L_N1_DBC_RS1_65_AP18IO_L1P_T0L_N0_DBC_RS0_65_AN18

    IO_T0U_N12_VRP_A28_65_AP21IO_L2N_T0L_N3_FWE_FCS2_B_65_AP20

    IO_L2P_T0L_N2_FOE_B_65_AN20IO_L3N_T0L_N5_AD15N_A27_65_AN19IO_L3P_T0L_N4_AD15P_A26_65_AM19

    IO_L4N_T0U_N7_DBC_AD7N_A25_65_AN21IO_L4P_T0U_N6_DBC_AD7P_A24_65_AM21

    IO_L5N_T0U_N9_AD14N_A23_65_AR18IO_L5P_T0U_N8_AD14P_A22_65_AR19IO_L6N_T0U_N11_AD6N_A21_65_AT20IO_L6P_T0U_N10_AD6P_A20_65_AR20

    IO_L7N_T1L_N1_QBC_AD13N_A19_65_AU19IO_L7P_T1L_N0_QBC_AD13P_A18_65_AT19

    IO_L8N_T1L_N3_AD5N_A17_65_AU21IO_L8P_T1L_N2_AD5P_A16_65_AT21

    IO_L9N_T1L_N5_AD12N_A15_D31_65_AV18IO_L9P_T1L_N4_AD12P_A14_D30_65_AU18

    IO_L10N_T1U_N7_QBC_AD4N_A13_D29_65_AW21IO_L10P_T1U_N6_QBC_AD4P_A12_D28_65_AV21

    IO_L11N_T1U_N9_GC_A11_D27_65_AW17IO_L11P_T1U_N8_GC_A10_D26_65_AW18

    IO_T1U_N12_PERSTN1_65_AV19IO_L12N_T1U_N11_GC_A09_D25_65_AW20IO_L12P_T1U_N10_GC_A08_D24_65_AV20

    IO_L13N_T2L_N1_GC_QBC_A07_D23_65_AY18IO_L13P_T2L_N0_GC_QBC_A06_D22_65_AY19

    IO_T2U_N12_CSI_ADV_B_65_BC21IO_L14N_T2L_N3_GC_A05_D21_65_BA20IO_L14P_T2L_N2_GC_A04_D20_65_AY20

    IO_L15N_T2L_N5_AD11N_A03_D19_65_BC18IO_L15P_T2L_N4_AD11P_A02_D18_65_BB18

    IO_L16N_T2U_N7_QBC_AD3N_A01_D17_65_BB21IO_L16P_T2U_N6_QBC_AD3P_A00_D16_65_BA21

    IO_L17N_T2U_N9_AD10N_D15_65_BB19IO_L17P_T2U_N8_AD10P_D14_65_BA19IO_L18N_T2U_N11_AD2N_D13_65_BC19IO_L18P_T2U_N10_AD2P_D12_65_BC20

    IO_L19N_T3L_N1_DBC_AD9N_D11_65_BD16IO_L19P_T3L_N0_DBC_AD9P_D10_65_BD17

    IO_L20N_T3L_N3_AD1N_D09_65_BF17IO_L20P_T3L_N2_AD1P_D08_65_BE17IO_L21N_T3L_N5_AD8N_D07_65_BE18IO_L21P_T3L_N4_AD8P_D06_65_BD18

    IO_L22N_T3U_N7_DBC_AD0N_D05_65_BF19IO_L22P_T3U_N6_DBC_AD0P_D04_65_BE19

    IO_L23N_T3U_N9_I2C_SDA_65_BF16IO_L23P_T3U_N8_I2C_SCLK_65_BE16

    IO_T3U_N12_PERSTN0_65_BD20IO_L24N_T3U_N11_DOUT_CSO_B_65_BF20

    IO_L24P_T3U_N10_EMCCLK_65_BE20

    XCVU190FLGC2104BANK 65

    SOC_FLGC2104_IRON

    SOC_VU190_FLGC2104_IRONWOOD

    NC

  • A

    B

    C

    D

    1234

    D

    C

    B

    A

    4 3 2 1

    SHEET SIZE: B

    SHEET OF

    VER:

    REV:

    DRAWN BY:

    TITLE:

    DATE: 1.0

    01

    BF

    09/21/2015:13:57

    PCB P/N: 1280790

    TEST P/N: TSS0174SCH P/N: 0381622

    ASSY P/N: 0431880

    925

    FPGA Banks 66 67SCHEM, ROHS COMPLIANTHW-U1-VCU110_REV1_0

    Bank 67 HP

    Bank 66 HP

    GND

    240R382

    1%

    1

    2

    VRP_67

    GND

    240R700

    1%

    1

    2

    VRP_66

    FPGA Banks 66 67

    Layout: Place resistor and capacitor for VREFUnderneath the FPGA via arrayright next to the via

    HMC_L0TXPSHMC_L0RXPSHMC_L1TXPSHMC_L1RXPS

    VCC1V5_FPGA

    VCC1V5_FPGA

    HMC_REFCLK_SELHMC_FERR_B

    HMC_P_RST_B

    GND

    QDR2_18B_D0

    QDR2_18B_D7

    VREF_66

    VRP_66

    QDR2_18B_DOFF_B

    QDR2_18B_K_PQDR2_18B_K_N

    SYSMON_AD2_R_PSYSMON_AD2_R_N

    SYSMON_AD0_R_PSYSMON_AD0_R_NSYSMON_AD8_R_PSYSMON_AD8_R_N

    USER_SMA_CLOCK_PUSER_SMA_CLOCK_N

    36-bit QDR2+: 1x18-bit SIOD,Q[17:0]/ADDR/CTRL

    QDR2+ MEM_IF

    GND

    VREF_67

    VRP_67

    QDR2_18B_CQ_B

    QDR2_18B_CQ

    HMC_REFCLK_BOOT_1HMC_REFCLK_BOOT_0

    GPIO_DIP_SW0

    GPIO_DIP_SW2GPIO_DIP_SW3

    GPIO_DIP_SW1

    USER_SMA_CLOCK_N

    USER_SMA_CLOCK_P

    1%

    100R14481

    2

    TX_DIS_MOD3_CFP4_LSTX_DIS_MOD2_CFP4_LSTX_DIS_MOD1_CFP4_LSTX_DIS_MOD0_CFP4_LS

    MOD_LOPWR_MOD3_CFP4_LSMOD_LOPWR_MOD2_CFP4_LS

    MOD_LOPWR_MOD1_CFP4_LS

    MOD_LOPWR_MOD0_CFP4_LS

    MOD_ABS_MOD3_CFP4_LSMOD_ABS_MOD2_CFP4_LS

    MOD_ABS_MOD1_CFP4_LS

    MOD_ABS_MOD0_CFP4_LS

    1/10W1/10W

    1/10W

    U1

    BE24BF24BD21BD23BE23BF21BF22BB24BC24BD22BE22BB23BC23AY25BA25BA22BB22AY24BA24AY22AY23AW22AW23AW25AV23AV24AT24AT25AV25AU23AU24AT26AU26AT22AU22AR24AR25AR22AR23AP26AP27AM24AN24AN25AP25AP22AP23AM26AN26AM27AM23AN23AM22

    AN27AP24AU25AV22BA23BD24BE21 VCCO_66_BE21

    VCCO_66_BD24VCCO_66_BA23VCCO_66_AV22VCCO_66_AU25VCCO_66_AP24VCCO_66_AN27

    VREF_66_AM22IO_L1N_T0L_N1_DBC_66_AN23IO_L1P_T0L_N0_DBC_66_AM23

    IO_T0U_N12_VRP_66_AM27IO_L2N_T0L_N3_66_AN26IO_L2P_T0L_N2_66_AM26

    IO_L3N_T0L_N5_AD15N_66_AP23IO_L3P_T0L_N4_AD15P_66_AP22

    IO_L4N_T0U_N7_DBC_AD7N_66_AP25IO_L4P_T0U_N6_DBC_AD7P_66_AN25

    IO_L5N_T0U_N9_AD14N_66_AN24IO_L5P_T0U_N8_AD14P_66_AM24IO_L6N_T0U_N11_AD6N_66_AP27IO_L6P_T0U_N10_AD6P_66_AP26

    IO_L7N_T1L_N1_QBC_AD13N_66_AR23IO_L7P_T1L_N0_QBC_AD13P_66_AR22

    IO_L8N_T1L_N3_AD5N_66_AR25IO_L8P_T1L_N2_AD5P_66_AR24IO_L9N_T1L_N5_AD12N_66_AU22IO_L9P_T1L_N4_AD12P_66_AT22

    IO_L10N_T1U_N7_QBC_AD4N_66_AU26IO_L10P_T1U_N6_QBC_AD4P_66_AT26

    IO_L11N_T1U_N9_GC_66_AU24IO_L11P_T1U_N8_GC_66_AU23

    IO_T1U_N12_66_AV25IO_L12N_T1U_N11_GC_66_AT25IO_L12P_T1U_N10_GC_66_AT24

    IO_L13N_T2L_N1_GC_QBC_66_AV24IO_L13P_T2L_N0_GC_QBC_66_AV23

    IO_T2U_N12_66_AW25IO_L14N_T2L_N3_GC_66_AW23IO_L14P_T2L_N2_GC_66_AW22

    IO_L15N_T2L_N5_AD11N_66_AY23IO_L15P_T2L_N4_AD11P_66_AY22

    IO_L16N_T2U_N7_QBC_AD3N_66_BA24IO_L16P_T2U_N6_QBC_AD3P_66_AY24

    IO_L17N_T2U_N9_AD10N_66_BB22IO_L17P_T2U_N8_AD10P_66_BA22IO_L18N_T2U_N11_AD2N_66_BA25IO_L18P_T2U_N10_AD2P_66_AY25

    IO_L19N_T3L_N1_DBC_AD9N_66_BC23IO_L19P_T3L_N0_DBC_AD9P_66_BB23

    IO_L20N_T3L_N3_AD1N_66_BE22IO_L20P_T3L_N2_AD1P_66_BD22IO_L21N_T3L_N5_AD8N_66_BC24IO_L21P_T3L_N4_AD8P_66_BB24

    IO_L22N_T3U_N7_DBC_AD0N_66_BF22IO_L22P_T3U_N6_DBC_AD0P_66_BF21

    IO_L23N_T3U_N9_66_BE23IO_L23P_T3U_N8_66_BD23

    IO_T3U_N12_66_BD21IO_L24N_T3U_N11_66_BF24IO_L24P_T3U_N10_66_BE24

    XCVU190FLGC2104BANK 66

    SOC_FLGC2104_IRON

    SOC_VU190_FLGC2104_IRONWOOD

    U1

    BC28BD28BD27BE25BF25BE27BE28BC26BD26BF26BF27BC25BD25BA29BB29BA26BB26BA27BB27AY29AY30AW27AW28BB28AY27AY28AV29AV30AW30AU28AV28AT30AT31AT29AU29AT27AU27AV26AW26AN30AP30AR27AR28AR29AR30AM29AN29AM31AN31AP31AN28AP28AM28

    AM30AR31AT28AW29AY26BC27BF28 VCCO_67_BF28

    VCCO_67_BC27VCCO_67_AY26VCCO_67_AW29VCCO_67_AT28VCCO_67_AR31VCCO_67_AM30

    VREF_67_AM28IO_L1N_T0L_N1_DBC_67_AP28IO_L1P_T0L_N0_DBC_67_AN28

    IO_T0U_N12_VRP_67_AP31IO_L2N_T0L_N3_67_AN31IO_L2P_T0L_N2_67_AM31

    IO_L3N_T0L_N5_AD15N_67_AN29IO_L3P_T0L_N4_AD15P_67_AM29

    IO_L4N_T0U_N7_DBC_AD7N_67_AR30IO_L4P_T0U_N6_DBC_AD7P_67_AR29

    IO_L5N_T0U_N9_AD14N_67_AR28IO_L5P_T0U_N8_AD14P_67_AR27IO_L6N_T0U_N11_AD6N_67_AP30IO_L6P_T0U_N10_AD6P_67_AN30

    IO_L7N_T1L_N1_QBC_AD13N_67_AW26IO_L7P_T1L_N0_QBC_AD13P_67_AV26

    IO_L8N_T1L_N3_AD5N_67_AU27IO_L8P_T1L_N2_AD5P_67_AT27

    IO_L9N_T1L_N5_AD12N_67_AU29IO_L9P_T1L_N4_AD12P_67_AT29

    IO_L10N_T1U_N7_QBC_AD4N_67_AT31IO_L10P_T1U_N6_QBC_AD4P_67_AT30

    IO_L11N_T1U_N9_GC_67_AV28IO_L11P_T1U_N8_GC_67_AU28

    IO_T1U_N12_67_AW30IO_L12N_T1U_N11_GC_67_AV30IO_L12P_T1U_N10_GC_67_AV29

    IO_L13N_T2L_N1_GC_QBC_67_AY28IO_L13P_T2L_N0_GC_QBC_67_AY27

    IO_T2U_N12_67_BB28IO_L14N_T2L_N3_GC_67_AW28IO_L14P_T2L_N2_GC_67_AW27

    IO_L15N_T2L_N5_AD11N_67_AY30IO_L15P_T2L_N4_AD11P_67_AY29

    IO_L16N_T2U_N7_QBC_AD3N_67_BB27IO_L16P_T2U_N6_QBC_AD3P_67_BA27

    IO_L17N_T2U_N9_AD10N_67_BB26IO_L17P_T2U_N8_AD10P_67_BA26IO_L18N_T2U_N11_AD2N_67_BB29IO_L18P_T2U_N10_AD2P_67_BA29

    IO_L19N_T3L_N1_DBC_AD9N_67_BD25IO_L19P_T3L_N0_DBC_AD9P_67_BC25

    IO_L20N_T3L_N3_AD1N_67_BF27IO_L20P_T3L_N2_AD1P_67_BF26IO_L21N_T3L_N5_AD8N_67_BD26IO_L21P_T3L_N4_AD8P_67_BC26

    IO_L22N_T3U_N7_DBC_AD0N_67_BE28IO_L22P_T3U_N6_DBC_AD0P_67_BE27

    IO_L23N_T3U_N9_67_BF25IO_L23P_T3U_N8_67_BE25

    IO_T3U_N12_67_BD27IO_L24N_T3U_N11_67_BD28IO_L24P_T3U_N10_67_BC28

    XCVU190FLGC2104BANK 67

    SOC_FLGC2104_IRON

    SOC_VU190_FLGC2104_IRONWOOD

    QDR2_18B_D8

    QDR2_18B_D9QDR2_18B_D10

    QDR2_18B_D11

    QDR2_18B_Q11

    QDR2_18B_Q13

    QDR2_18B_RPS_B

    QDR2_18B_WPS_B

    QDR2_18B_BWS1_B

    QDR2_18B_A0

    QDR2_18B_A1

    QDR2_18B_A2

    QDR2_18B_A3

    QDR2_18B_A4

    QDR2_18B_A5

    QDR2_18B_A6QDR2_18B_A7

    QDR2_18B_A8

    QDR2_18B_A9

    QDR2_18B_A12

    QDR2_18B_A13

    QDR2_18B_A19

    QDR2_18B_A20

    QDR2_18B_A21

    QDR2_18B_BWS0_B

    QDR2_18B_D2

    QDR2_18B_D1

    QDR2_18B_D4QDR2_18B_D6

    QDR2_18B_D3

    QDR2_18B_D5

    QDR2_18B_D12

    QDR2_18B_D13QDR2_18B_D14QDR2_18B_D15

    QDR2_18B_D16QDR2_18B_D17

    QDR2_18B_A16

    QDR2_18B_A15QDR2_18B_A14

    QDR2_18B_A10QDR2_18B_A11

    QDR2_18B_A17

    QDR2_18B_A18

    QDR2_18B_Q7

    NC

    1/16W

    R13531.00K

    1%

    1

    21/16W

    R13511.00K

    1%

    1

    2

    NC

    QDR2_18B_Q2

    QDR2_18B_Q0

    QDR2_18B_Q5QDR2_18B_Q3

    QDR2_18B_Q6

    QDR2_18B_Q8QDR2_18B_Q1

    QDR2_18B_Q4

    QDR2_18B_Q9

    QDR2_18B_Q10

    QDR2_18B_Q12

    QDR2_18B_Q14QDR2_18B_Q16

    QDR2_18B_Q15QDR2_18B_Q17

  • A

    B

    C

    D

    1234

    D

    C

    B

    A

    4 3 2 1

    SHEET SIZE: B

    SHEET OF

    VER:

    REV:

    DRAWN BY:

    TITLE:

    DATE:

    HW-U1-VCU110_REV1_0SCHEM, ROHS COMPLIANTFPGA Bank 68

    6 92

    ASSY P/N: 0431880

    SCH P/N: 0381622TEST P/N: TSS0174

    PCB P/N: 1280790

    09/21/2015:13:58

    BF

    01

    1.0

    VCCO_68_BE31VCCO_68_BB30VCCO_68_BA33VCCO_68_AY36VCCO_68_AV32VCCO_68_AU35VCCO_68_AP34

    VREF_68_AM32IO_L1N_T0L_N1_DBC_68_AP32IO_L1P_T0L_N0_DBC_68_AN32

    IO_T0U_N12_VRP_68_AU36IO_L2N_T0L_N3_68_AT34IO_L2P_T0L_N2_68_AR34

    IO_L3N_T0L_N5_AD15N_68_AT32IO_L3P_T0L_N4_AD15P_68_AR32

    IO_L4N_T0U_N7_DBC_AD7N_68_AT35IO_L4P_T0U_N6_DBC_AD7P_68_AR35

    IO_L5N_T0U_N9_AD14N_68_AR33IO_L5P_T0U_N8_AD14P_68_AP33IO_L6N_T0U_N11_AD6N_68_AT36IO_L6P_T0U_N10_AD6P_68_AR36

    IO_L7N_T1L_N1_QBC_AD13N_68_AW31IO_L7P_T1L_N0_QBC_AD13P_68_AV31

    IO_L8N_T1L_N3_AD5N_68_AU32IO_L8P_T1L_N2_AD5P_68_AU31

    IO_L9N_T1L_N5_AD12N_68_AW35IO_L9P_T1L_N4_AD12P_68_AV35

    IO_L10N_T1U_N7_QBC_AD4N_68_AW36IO_L10P_T1U_N6_QBC_AD4P_68_AV36

    IO_L11N_T1U_N9_GC_68_AV34IO_L11P_T1U_N8_GC_68_AV33

    IO_T1U_N12_68_AW32IO_L12N_T1U_N11_GC_68_AU34IO_L12P_T1U_N10_GC_68_AU33

    IO_L13N_T2L_N1_GC_QBC_68_AY35IO_L13P_T2L_N0_GC_QBC_68_AY34

    IO_T2U_N12_68_BA35IO_L14N_T2L_N3_GC_68_AY33IO_L14P_T2L_N2_GC_68_AW33

    IO_L15N_T2L_N5_AD11N_68_BA32IO_L15P_T2L_N4_AD11P_68_AY32

    IO_L16N_T2U_N7_QBC_AD3N_68_BB34IO_L16P_T2U_N6_QBC_AD3P_68_BA34

    IO_L17N_T2U_N9_AD10N_68_BB33IO_L17P_T2U_N8_AD10P_68_BB32IO_L18N_T2U_N11_AD2N_68_BB36IO_L18P_T2U_N10_AD2P_68_BA36

    IO_L19N_T3L_N1_DBC_AD9N_68_BC30IO_L19P_T3L_N0_DBC_AD9P_68_BC29

    IO_L20N_T3L_N3_AD1N_68_BE30IO_L20P_T3L_N2_AD1P_68_BD30IO_L21N_T3L_N5_AD8N_68_BB31IO_L21P_T3L_N4_AD8P_68_BA31

    IO_L22N_T3U_N7_DBC_AD0N_68_BF29IO_L22P_T3U_N6_DBC_AD0P_68_BE29

    IO_L23N_T3U_N9_68_BD31IO_L23P_T3U_N8_68_BC31

    IO_T3U_N12_68_BA30IO_L24N_T3U_N11_68_BF31IO_L24P_T3U_N10_68_BF30

    XCVU190FLGC2104BANK 68

    BE31BB30BA33AY36AV32AU35AP34

    AM32AP32AN32AU36AT34AR34AT32AR32AT35AR35AR33AP33AT36AR36AW31AV31AU32AU31AW35AV35AW36AV36AV34AV33AW32AU34AU33AY35AY34BA35AY33AW33BA32AY32BB34BA34BB33BB32BB36BA36BC30BC29BE30BD30BB31BA31BF29BE29BD31BC31BA30BF31BF30

    SOC_VU190_FLGC2104_IRONWOOD

    SOC_FLGC2104_IRONU1

    FMC_HPC0_LA08_NFMC_HPC0_LA08_P

    FMC_HPC0_LA02_PFMC_HPC0_LA02_N

    FMC_HPC0_LA07_PFMC_HPC0_LA07_N

    FMC_HPC0_LA04_PFMC_HPC0_LA04_N

    FMC_HPC0_LA03_NFMC_HPC0_LA03_P

    FMC_HPC0_LA00_CC_NFMC_HPC0_LA00_CC_P

    FMC_HPC0_LA10_PFMC_HPC0_LA10_N

    FMC_HPC0_LA09_PFMC_HPC0_LA09_N

    FMC_HPC0_LA06_PFMC_HPC0_LA06_NFMC_HPC0_LA05_PFMC_HPC0_LA05_N

    FMC_HPC0_CLK0_M2C_PFMC_HPC0_CLK0_M2C_N

    FMC_HPC0_LA01_CC_PFMC_HPC0_LA01_CC_N

    FMC_HPC1_LA08_NFMC_HPC1_LA08_P

    FMC_HPC1_LA02_PFMC_HPC1_LA02_N

    FMC_HPC1_LA07_PFMC_HPC1_LA07_N

    FMC_HPC1_LA04_PFMC_HPC1_LA04_N

    FMC_HPC1_LA03_NFMC_HPC1_LA03_PFMC_HPC1_LA00_CC_NFMC_HPC1_LA00_CC_P

    FMC_HPC1_LA01_CC_PFMC_HPC1_LA01_CC_NFMC_HPC1_LA10_PFMC_HPC1_LA10_N

    FMC_HPC1_LA09_PFMC_HPC1_LA09_NFMC_HPC1_LA06_PFMC_HPC1_LA06_N

    FMC_HPC1_LA05_PFMC_HPC1_LA05_N

    FMC_HPC1_CLK0_M2C_PFMC_HPC1_CLK0_M2C_N

    VADJ_1V8_FPGA

    GND

    2

    1

    1%

    R16762401/10W

    VRP_68

    VRP_68

    GND

    VREF_68

    1

    2 DNPDNPC2667

    DNP2

    1

    DNP

    DNPR1674

    DNP

    FMC_HPC0_VREF_A_M2C

    NC

    NC

    NC

  • A

    B

    C

    D

    1234

    D

    C

    B

    A

    4 3 2 1

    SHEET SIZE: B

    SHEET OF

    VER:

    REV:

    DRAWN BY:

    TITLE:

    DATE: 1.0

    01

    BF

    09/21/2015:13:58

    PCB P/N: 1280790

    TEST P/N: TSS0174SCH P/N: 0381622

    ASSY P/N: 0431880

    927

    FPGA Banks 70 71SCHEM, ROHS COMPLIANTHW-U1-VCU110_REV1_0

    FPGA Banks 70 71GND

    GND

    VREF_70

    2

    1240R1072

    1%

    VRP_70

    VCC1V2_FPGA

    GND

    GND

    2

    1240R1073

    1%

    VCC1V2_FPGA

    VREF_71

    VRP_71

    RLD3_36B_QK0_NRLD3_36B_QK0_P

    RLD3_36B_QK2_NRLD3_36B_QK2_P

    RLD3_36B_QK1_NRLD3_36B_QK1_P

    RLD3_36B_QK3_NRLD3_36B_QK3_PVRP_70

    RLD3_36B_QVLD0

    RLD3_36B_DM0

    RLD3_36B_QVLD1

    RLD3_36B_DM1

    RLD3_36B_CK_NRLD3_36B_CK_P

    RLD3_36B_DK1_NRLD3_36B_DK1_P

    RLD3_36B_DK0_NRLD3_36B_DK0_P

    VRP_71

    RLD3_36B_A3

    RLD3_36B_RESET_B

    100

    1%

    R1355 1

    2SYSCLK_300_N

    SYSCLK_300_PSYSCLK_300_NSYSCLK_300_P

    RLD3 MEM_IF

    36-bit RLD3: 1x36-bitDATA[35:0], Multiplexed ADDR

    CPU_RESET

    1/10W

    1/10W1/10W

    RLD3_36B_DQ0

    RLD3_36B_DQ2

    RLD3_36B_DQ3RLD3_36B_DQ8

    GPIO_SW_C

    U1

    B26A26E26D29C29B27B28C27C28A28A29D26D27E27E28F29E29G26F26G28F28J27H27G27H28H29K29J29L26K27K28K26J26L28L29N27M27N28M28M30L30K31J31N29N30K32J32N32M32J30M31L31P27

    A27D28G29H26K30L27N31 VCCO_70_N31

    VCCO_70_L27VCCO_70_K30VCCO_70_H26VCCO_70_G29VCCO_70_D28VCCO_70_A27

    VREF_70_P27IO_L1N_T0L_N1_DBC_70_L31IO_L1P_T0L_N0_DBC_70_M31

    IO_T0U_N12_VRP_70_J30IO_L2N_T0L_N3_70_M32IO_L2P_T0L_N2_70_N32

    IO_L3N_T0L_N5_AD15N_70_J32IO_L3P_T0L_N4_AD15P_70_K32

    IO_L4N_T0U_N7_DBC_AD7N_70_N30IO_L4P_T0U_N6_DBC_AD7P_70_N29

    IO_L5N_T0U_N9_AD14N_70_J31IO_L5P_T0U_N8_AD14P_70_K31IO_L6N_T0U_N11_AD6N_70_L30IO_L6P_T0U_N10_AD6P_70_M30

    IO_L7N_T1L_N1_QBC_AD13N_70_M28IO_L7P_T1L_N0_QBC_AD13P_70_N28

    IO_L8N_T1L_N3_AD5N_70_M27IO_L8P_T1L_N2_AD5P_70_N27IO_L9N_T1L_N5_AD12N_70_L29IO_L9P_T1L_N4_AD12P_70_L28

    IO_L10N_T1U_N7_QBC_AD4N_70_J26IO_L10P_T1U_N6_QBC_AD4P_70_K26

    IO_L11N_T1U_N9_GC_70_K28IO_L11P_T1U_N8_GC_70_K27

    IO_T1U_N12_70_L26IO_L12N_T1U_N11_GC_70_J29IO_L12P_T1U_N10_GC_70_K29

    IO_L13N_T2L_N1_GC_QBC_70_H29IO_L13P_T2L_N0_GC_QBC_70_H28

    IO_T2U_N12_70_G27IO_L14N_T2L_N3_GC_70_H27IO_L14P_T2L_N2_GC_70_J27

    IO_L15N_T2L_N5_AD11N_70_F28IO_L15P_T2L_N4_AD11P_70_G28

    IO_L16N_T2U_N7_QBC_AD3N_70_F26IO_L16P_T2U_N6_QBC_AD3P_70_G26

    IO_L17N_T2U_N9_AD10N_70_E29IO_L17P_T2U_N8_AD10P_70_F29IO_L18N_T2U_N11_AD2N_70_E28IO_L18P_T2U_N10_AD2P_70_E27

    IO_L19N_T3L_N1_DBC_AD9N_70_D27IO_L19P_T3L_N0_DBC_AD9P_70_D26

    IO_L20N_T3L_N3_AD1N_70_A29IO_L20P_T3L_N2_AD1P_70_A28IO_L21N_T3L_N5_AD8N_70_C28IO_L21P_T3L_N4_AD8P_70_C27

    IO_L22N_T3U_N7_DBC_AD0N_70_B28IO_L22P_T3U_N6_DBC_AD0P_70_B27

    IO_L23N_T3U_N9_70_C29IO_L23P_T3U_N8_70_D29

    IO_T3U_N12_70_E26IO_L24N_T3U_N11_70_A26IO_L24P_T3U_N10_70_B26

    XCVU190FLGC2104BANK 70

    BANK MIGRATION:VU160 = BANK 70VU125 = BANK 70VU095 = BANK 69

    SOC_FLGC2104_IRON

    SOC_VU190_FLGC2104_IRONWOOD

    U1

    C22B22D22B25A25C23B23D25C25A24A23D24C24G21F21F24E24F23E23G25F25H23G23E22H22G22J24H24L25K22J22K21J21J25H25L23K23L24K24M21L21P25N25N22M22M26M25P24N24P22N23M23P21

    B24E25F22J23M24N21 VCCO_71_N21

    VCCO_71_M24VCCO_71_J23VCCO_71_F22VCCO_71_E25VCCO_71_B24

    VREF_71_P21IO_L1N_T0L_N1_DBC_71_M23IO_L1P_T0L_N0_DBC_71_N23

    IO_T0U_N12_VRP_71_P22IO_L2N_T0L_N3_71_N24IO_L2P_T0L_N2_71_P24

    IO_L3N_T0L_N5_AD15N_71_M25IO_L3P_T0L_N4_AD15P_71_M26

    IO_L4N_T0U_N7_DBC_AD7N_71_M22IO_L4P_T0U_N6_DBC_AD7P_71_N22

    IO_L5N_T0U_N9_AD14N_71_N25IO_L5P_T0U_N8_AD14P_71_P25IO_L6N_T0U_N11_AD6N_71_L21IO_L6P_T0U_N10_AD6P_71_M21

    IO_L7N_T1L_N1_QBC_AD13N_71_K24IO_L7P_T1L_N0_QBC_AD13P_71_L24

    IO_L8N_T1L_N3_AD5N_71_K23IO_L8P_T1L_N2_AD5P_71_L23IO_L9N_T1L_N5_AD12N_71_H25IO_L9P_T1L_N4_AD12P_71_J25

    IO_L10N_T1U_N7_QBC_AD4N_71_J21IO_L10P_T1U_N6_QBC_AD4P_71_K21

    IO_L11N_T1U_N9_GC_71_J22IO_L11P_T1U_N8_GC_71_K22

    IO_T1U_N12_71_L25IO_L12N_T1U_N11_GC_71_H24IO_L12P_T1U_N10_GC_71_J24

    IO_L13N_T2L_N1_GC_QBC_71_G22IO_L13P_T2L_N0_GC_QBC_71_H22

    IO_T2U_N12_71_E22IO_L14N_T2L_N3_GC_71_G23IO_L14P_T2L_N2_GC_71_H23

    IO_L15N_T2L_N5_AD11N_71_F25IO_L15P_T2L_N4_AD11P_71_G25

    IO_L16N_T2U_N7_QBC_AD3N_71_E23IO_L16P_T2U_N6_QBC_AD3P_71_F23

    IO_L17N_T2U_N9_AD10N_71_E24IO_L17P_T2U_N8_AD10P_71_F24IO_L18N_T2U_N11_AD2N_71_F21IO_L18P_T2U_N10_AD2P_71_G21

    IO_L19N_T3L_N1_DBC_AD9N_71_C24IO_L19P_T3L_N0_DBC_AD9P_71_D24

    IO_L20N_T3L_N3_AD1N_71_A23IO_L20P_T3L_N2_AD1P_71_A24IO_L21N_T3L_N5_AD8N_71_C25IO_L21P_T3L_N4_AD8P_71_D25

    IO_L22N_T3U_N7_DBC_AD0N_71_B23IO_L22P_T3U_N6_DBC_AD0P_71_C23

    IO_L23N_T3U_N9_71_A25IO_L23P_T3U_N8_71_B25

    IO_T3U_N12_71_D22IO_L24N_T3U_N11_71_B22IO_L24P_T3U_N10_71_C22

    XCVU190FLGC2104BANK 71

    BANK MIGRATION:VU160 = BANK 71VU125 = BANK 71VU095 = BANK 70

    SOC_FLGC2104_IRON

    SOC_VU190_FLGC2104_IRONWOOD

    MDC_CFP4MDIO_CFP4PMOD0_1_LSPMOD0_5_LSPMOD0_2_LS

    PMOD0_0_LSPMOD0_7_LSPMOD0_3_LS

    PMOD0_4_LSPMOD0_6_LS

    SYSMON_MUX_ADDR1_LSSYSMON_MUX_ADDR0_LS

    SYSMON_MUX_ADDR2_LS

    MAXIM_CABLE_B_FPGA

    GPIO_LED_0_LSGPIO_LED_1_LS

    GPIO_LED_3_LSGPIO_LED_4_LS

    GPIO_LED_2_LS

    GPIO_LED_5_LS

    SI5328_INT_ALM_LS

    GPIO_LED_6_LS

    GPIO_LED_7_LS

    RLD3_36B_DQ33RLD3_36B_DQ28

    RLD3_36B_DQ35

    RLD3_36B_DQ34RLD3_36B_DQ27

    RLD3_36B_DQ13

    RLD3_36B_DQ16

    RLD3_36B_DQ17

    RLD3_36B_DQ20RLD3_36B_DQ25

    RLD3_36B_WE_BRLD3_36B_BA2

    RLD3_36B_DQ1

    RLD3_36B_DQ4

    RLD3_36B_DQ6

    RLD3_36B_DQ7

    RLD3_36B_DQ5

    RLD3_36B_DQ12

    RLD3_36B_DQ9

    RLD3_36B_DQ10

    RLD3_36B_DQ11

    RLD3_36B_DQ15

    RLD3_36B_DQ14

    RLD3_36B_DQ19

    RLD3_36B_DQ22

    RLD3_36B_DQ23

    RLD3_36B_DQ18

    RLD3_36B_DQ21RLD3_36B_DQ24

    RLD3_36B_DQ26

    RLD3_36B_DQ29

    RLD3_36B_DQ30

    RLD3_36B_DQ31

    RLD3_36B_DQ32

    RLD3_36B_CS_B

    RLD3_36B_A0

    RLD3_36B_A4

    RLD3_36B_A5RLD3_36B_A8

    RLD3_36B_A9

    RLD3_36B_A10

    RLD3_36B_A13

    RLD3_36B_A14

    RLD3_36B_A17

    RLD3_36B_A18

    RLD3_36B_REF_BRLD3_36B_BA0

    RLD3_36B_BA1

    RLD3_36B_BA3

    1/16W

    R10481.00K

    1%

    1

    2

    NC

    1/16W

    R10501.00K

    1%

    1

    2

    NC

  • A

    B

    C

    D

    1234

    D

    C

    B

    A

    4 3 2 1

    SHEET SIZE: B

    SHEET OF

    VER:

    REV:

    DRAWN BY:

    TITLE:

    DATE: 1.0

    01

    BF

    09/21/2015:13:57

    PCB P/N: 1280790

    TEST P/N: TSS0174SCH P/N: 0381622

    ASSY P/N: 0431880

    928

    FPGA Bank 72SCHEM, ROHS COMPLIANTHW-U1-VCU110_REV1_0

    FPGA Bank 72GND

    VREF_72

    VCC1V2_FPGA

    RLD3_18B_DM1

    RLD3_18B_CK_NRLD3_18B_CK_P

    RLD3_18B_DK1_NRLD3_18B_DK1_P

    RLD3_18B_DK0_NRLD3_18B_DK0_P

    RLD3_18B_QK0_NRLD3_18B_QK0_P

    RLD3_18B_QK1_NRLD3_18B_QK1_PVRP_72

    RLD3_18B_DQ4

    RLD3_18B_QVLD0

    RLD3_18B_RESET_B

    RLD3_18B_DM0

    GND

    R1371240

    1%

    1

    2

    VRP_72

    RLD3 MEM_IFDATA[17:0], Multiplexed ADDR

    18-bit RLD3: 1x18-bit

    1/10W

    RLD3_18B_DQ0

    RLD3_18B_DQ6RLD3_18B_DQ8

    RLD3_18B_DQ1

    U1

    B18A18D21A20A19C19C18B21A21D20D19C20B20E19E18G20F20H18G18F19F18H20H19E21J20J19K19K18J15L19L18K16J16M20L20L16L15K17J17P17P16P20N20M16M15P19N19N17M17N15N18M18P15

    C21D18G19K20L17P18 VCCO_72_P18

    VCCO_72_L17VCCO_72_K20VCCO_72_G19VCCO_72_D18VCCO_72_C21

    VREF_72_P15IO_L1N_T0L_N1_DBC_72_M18IO_L1P_T0L_N0_DBC_72_N18

    IO_T0U_N12_VRP_72_N15IO_L2N_T0L_N3_72_M17IO_L2P_T0L_N2_72_N17

    IO_L3N_T0L_N5_AD15N_72_N19IO_L3P_T0L_N4_AD15P_72_P19

    IO_L4N_T0U_N7_DBC_AD7N_72_M15IO_L4P_T0U_N6_DBC_AD7P_72_M16

    IO_L5N_T0U_N9_AD14N_72_N20IO_L5P_T0U_N8_AD14P_72_P20IO_L6N_T0U_N11_AD6N_72_P16IO_L6P_T0U_N10_AD6P_72_P17

    IO_L7N_T1L_N1_QBC_AD13N_72_J17IO_L7P_T1L_N0_QBC_AD13P_72_K17

    IO_L8N_T1L_N3_AD5N_72_L15IO_L8P_T1L_N2_AD5P_72_L16IO_L9N_T1L_N5_AD12N_72_L20IO_L9P_T1L_N4_AD12P_72_M20

    IO_L10N_T1U_N7_QBC_AD4N_72_J16IO_L10P_T1U_N6_QBC_AD4P_72_K16

    IO_L11N_T1U_N9_GC_72_L18IO_L11P_T1U_N8_GC_72_L19

    IO_T1U_N12_72_J15IO_L12N_T1U_N11_GC_72_K18IO_L12P_T1U_N10_GC_72_K19

    IO_L13N_T2L_N1_GC_QBC_72_J19IO_L13P_T2L_N0_GC_QBC_72_J20

    IO_T2U_N12_72_E21IO_L14N_T2L_N3_GC_72_H19IO_L14P_T2L_N2_GC_72_H20

    IO_L15N_T2L_N5_AD11N_72_F18IO_L15P_T2L_N4_AD11P_72_F19

    IO_L16N_T2U_N7_QBC_AD3N_72_G18IO_L16P_T2U_N6_QBC_AD3P_72_H18

    IO_L17N_T2U_N9_AD10N_72_F20IO_L17P_T2U_N8_AD10P_72_G20IO_L18N_T2U_N11_AD2N_72_E18IO_L18P_T2U_N10_AD2P_72_E19

    IO_L19N_T3L_N1_DBC_AD9N_72_B20IO_L19P_T3L_N0_DBC_AD9P_72_C20

    IO_L20N_T3L_N3_AD1N_72_D19IO_L20P_T3L_N2_AD1P_72_D20IO_L21N_T3L_N5_AD8N_72_A21IO_L21P_T3L_N4_AD8P_72_B21

    IO_L22N_T3U_N7_DBC_AD0N_72_C18IO_L22P_T3U_N6_DBC_AD0P_72_C19

    IO_L23N_T3U_N9_72_A19IO_L23P_T3U_N8_72_A20

    IO_T3U_N12_72_D21IO_L24N_T3U_N11_72_A18IO_L24P_T3U_N10_72_B18

    XCVU190FLGC2104BANK 72

    BANK MIGRATION:VU160 = BANK 72VU125 = BANK 72VU095 = BANK 71

    SOC_FLGC2104_IRON

    SOC_VU190_FLGC2104_IRONWOOD

    RLD3_18B_DQ3

    RLD3_18B_DQ13

    RLD3_18B_DQ11

    RLD3_18B_DQ15

    RLD3_18B_DQ9

    RLD3_18B_DQ16RLD3_18B_DQ12

    RLD3_18B_DQ14RLD3_18B_DQ17

    RLD3_18B_DQ10

    RLD3_18B_DQ2RLD3_18B_DQ7

    RLD3_18B_DQ5

    RLD3_18B_A10

    RLD3_18B_A3

    RLD3_18B_A4

    RLD3_18B_A5RLD3_18B_A8

    RLD3_18B_A9

    RLD3_18B_A13

    RLD3_18B_BA0

    RLD3_18B_BA1

    RLD3_18B_BA2

    RLD3_18B_BA3

    RLD3_18B_A18

    RLD3_18B_CS_B

    RLD3_18B_REF_B

    RLD3_18B_WE_B

    RLD3_18B_A17

    RLD3_18B_A14RLD3_18B_A0

    NC

    1/16W

    R10301.00K

    1%

    1

    2

  • A

    B

    C

    D

    1234

    D

    C

    B

    A

    4 3 2 1

    SHEET SIZE: B

    SHEET OF

    VER:

    REV:

    DRAWN BY:

    TITLE:

    DATE: 1.0

    01

    BF

    09/21/2015:13:58

    PCB P/N: 1280790

    TEST P/N: TSS0174SCH P/N: 0381622

    ASSY P/N: 0431880

    929

    FPGA Banks 84 94SCHEM, ROHS COMPLIANTHW-U1-VCU110_REV1_0

    FPGA Banks 84 94

    GPIO_SW_N

    GPIO_SW_E

    GPIO_SW_S

    GPIO_SW_W

    U1

    AP17AR17AM16AN15AP15AV16AV15AN16AP16AT17AU17AT16AU16AP13AR13AU12AU11AR15AR14AR12AT12AT15AT14AT11AU14AU13AM17

    AN17AP14AR11AU15 VCCO_84_AU15

    VCCO_84_AR11VCCO_84_AP14VCCO_84_AN17

    VREF_84_AM17IO_L13N_T2L_N1_GC_QBC_84_AU13IO_L13P_T2L_N0_GC_QBC_84_AU14

    IO_T2U_N12_84_AT11IO_L14N_T2L_N3_GC_84_AT14IO_L14P_T2L_N2_GC_84_AT15

    IO_L15N_T2L_N5_AD11N_84_AT12IO_L15P_T2L_N4_AD11P_84_AR12

    IO_L16N_T2U_N7_QBC_AD3N_84_AR14IO_L16P_T2U_N6_QBC_AD3P_84_AR15

    IO_L17N_T2U_N9_AD10N_84_AU11IO_L17P_T2U_N8_AD10P_84_AU12IO_L18N_T2U_N11_AD2N_84_AR13IO_L18P_T2U_N10_AD2P_84_AP13

    IO_L19N_T3L_N1_DBC_AD9N_84_AU16IO_L19P_T3L_N0_DBC_AD9P_84_AT16

    IO_L20N_T3L_N3_AD1N_84_AU17IO_L20P_T3L_N2_AD1P_84_AT17IO_L21N_T3L_N5_AD8N_84_AP16IO_L21P_T3L_N4_AD8P_84_AN16

    IO_L22N_T3U_N7_DBC_AD0N_84_AV15IO_L22P_T3U_N6_DBC_AD0P_84_AV16

    IO_L23N_T3U_N9_84_AP15IO_L23P_T3U_N8_84_AN15

    IO_T3U_N12_84_AM16IO_L24N_T3U_N11_84_AR17IO_L24P_T3U_N10_84_AP17

    XCVU190FLGC2104BANK 84

    SOC_FLGC2104_IRON

    SOC_VU190_FLGC2104_IRONWOOD

    U1

    AW13AW12AY13AV14AV13BA11BB11AY12BA12BB13BB12AV11AW11AY17BA17BA14BB14BB17BB16BA16BB15AW15AY14BC16AY15BA15AW16

    AV12AY16BA13BC17 VCCO_94_BC17

    VCCO_94_BA13VCCO_94_AY16VCCO_94_AV12

    VREF_94_AW16IO_L1N_T0L_N1_DBC_94_BA15IO_L1P_T0L_N0_DBC_94_AY15

    IO_T0U_N12_94_BC16IO_L2N_T0L_N3_94_AY14IO_L2P_T0L_N2_94_AW15

    IO_L3N_T0L_N5_AD15N_94_BB15IO_L3P_T0L_N4_AD15P_94_BA16

    IO_L4N_T0U_N7_DBC_AD7N_94_BB16IO_L4P_T0U_N6_DBC_AD7P_94_BB17

    IO_L5N_T0U_N9_AD14N_94_BB14IO_L5P_T0U_N8_AD14P_94_BA14IO_L6N_T0U_N11_AD6N_94_BA17IO_L6P_T0U_N10_AD6P_94_AY17

    IO_L7N_T1L_N1_QBC_AD13N_94_AW11IO_L7P_T1L_N0_QBC_AD13P_94_AV11

    IO_L8N_T1L_N3_AD5N_94_BB12IO_L8P_T1L_N2_AD5P_94_BB13

    IO_L9N_T1L_N5_AD12N_94_BA12IO_L9P_T1L_N4_AD12P_94_AY12

    IO_L10N_T1U_N7_QBC_AD4N_94_BB11IO_L10P_T1U_N6_QBC_AD4P_94_BA11

    IO_L11N_T1U_N9_GC_94_AV13IO_L11P_T1U_N8_GC_94_AV14

    IO_T1U_N12_94_AY13IO_L12N_T1U_N11_GC_94_AW12IO_L12P_T1U_N10_GC_94_AW13

    XCVU190FLGC2104BANK 94

    SOC_FLGC2104_IRON

    SOC_VU190_FLGC2104_IRONWOOD

    VCC1V8_FPGAVCC1V8_FPGA

    NCNC

    NCNCNCNCNCNCNCNCNCNCNCNCNCNCNC

    NCNC

    NCNC

    NCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNC

    NCNC

    RX_LOS_MOD3_CFP4_LSRX_LOS_MOD2_CFP4_LSRX_LOS_MOD1_CFP4_LSRX_LOS_MOD0_CFP4_LS

    PCIE_CABLE_FPGA_CPERST_B

    NCNC

  • A

    B

    C

    D

    1234

    D

    C

    B

    A

    4 3 2 1

    SHEET SIZE: B

    SHEET OF

    VER:

    REV:

    DRAWN BY:

    TITLE:

    DATE: 1.0

    01

    BF

    09/21/2015:13:58

    PCB P/N: 1280790

    TEST P/N: TSS0174SCH P/N: 0381622

    ASSY P/N: 0431880

    9210

    FPGA Banks 120 121 122SCHEM, ROHS COMPLIANTHW-U1-VCU110_REV1_0

    21R1231

    1%

    100 MGTAVTT_FPGA

    FPGA Banks 120 121 122

    1/10W

    U1

    BF38BF39BF33BF34BE36BE37BD33BD34BE40BE41BF43BF44BD38BD39BD43BD44AN36AN37AM34AM35BD37BD36MGTAVTTRCAL_LS_BD36

    MGTRREF_LS_BD37MGTREFCLK1N_120_AM35MGTREFCLK1P_120_AM34MGTREFCLK0N_120_AN37MGTREFCLK0P_120_AN36

    MGTYRXN3_120_BD44MGTYRXP3_120_BD43MGTYTXN3_120_BD39MGTYTXP3_120_BD38MGTYRXN2_120_BF44MGTYRXP2_120_BF43MGTYTXN2_120_BE41MGTYTXP2_120_BE40MGTYRXN1_120_BD34MGTYRXP1_120_BD33MGTYTXN1_120_BE37MGTYTXP1_120_BE36MGTYRXN0_120_BF34MGTYRXP0_120_BF33MGTYTXN0_120_BF39MGTYTXP0_120_BF38

    XCVU190FLGC2104BANK 120

    BANK MIGRATION:VU160 = BANK 120

    VU125 = NCVU095 = NC

    SOC_FLGC2104_IRON

    SOC_VU190_FLGC2104_IRONWOOD

    U1

    BC40BC41BC45BC46BB38BB39BB43BB44BA40BA41BA45BA46AY38AY39AY43AY44AL36AL37AK34AK35MGTREFCLK1N_121_AK35

    MGTREFCLK1P_121_AK34MGTREFCLK0N_121_AL37MGTREFCLK0P_121_AL36

    MGTYRXN3_121_AY44MGTYRXP3_121_AY43MGTYTXN3_121_AY39MGTYTXP3_121_AY38MGTYRXN2_121_BA46MGTYRXP2_121_BA45MGTYTXN2_121_BA41MGTYTXP2_121_BA40MGTYRXN1_121_BB44MGTYRXP1_121_BB43MGTYTXN1_121_BB39MGTYTXP1_121_BB38MGTYRXN0_121_BC46MGTYRXP0_121_BC45MGTYTXN0_121_BC41MGTYTXP0_121_BC40

    XCVU190FLGC2104BANK 121

    BANK MIGRATION:VU160 = BANK 121

    VU125 = NCVU095 = NC

    SOC_FLGC2104_IRON

    SOC_VU190_FLGC2104_IRONWOOD

    U1

    AW40AW41AW45AW46AV38AV39AV43AV44AU40AU41AU45AU46AT38AT39AT43AT44AJ36AJ37AH34AH35MGTREFCLK1N_122_AH35

    MGTREFCLK1P_122_AH34MGTREFCLK0N_122_AJ37MGTREFCLK0P_122_AJ36

    MGTYRXN3_122_AT44MGTYRXP3_122_AT43MGTYTXN3_122_AT39MGTYTXP3_122_AT38MGTYRXN2_122_AU46MGTYRXP2_122_AU45MGTYTXN2_122_AU41MGTYTXP2_122_AU40MGTYRXN1_122_AV44MGTYRXP1_122_AV43MGTYTXN1_122_AV39MGTYTXP1_122_AV38MGTYRXN0_122_AW46MGTYRXP0_122_AW45MGTYTXN0_122_AW41MGTYTXP0_122_AW40

    XCVU190FLGC2104BANK 122

    BANK MIGRATION:VU160 = BANK 122

    VU125 = NCVU095 = NC

    SOC_FLGC2104_IRON

    SOC_VU190_FLGC2104_IRONWOOD

    NCNC

    EXAMAX_RX1_PEXAMAX_RX1_N

    EXAMAX_RX2_PEXAMAX_RX2_N

    EXAMAX_RX3_PEXAMAX_RX3_N

    EXAMAX_RX4_PEXAMAX_RX4_N

    EXAMAX_TX1_PEXAMAX_TX1_N

    EXAMAX_TX2_PEXAMAX_TX2_N

    EXAMAX_TX3_PEXAMAX_TX3_N

    EXAMAX_TX4_PEXAMAX_TX4_N

    EXAMAX_SI5328_OUT1_BUF2_C_NEXAMAX_SI5328_OUT1_BUF2_C_P

    NCNC

    EXAMAX_RX5_PEXAMAX_RX5_N

    EXAMAX_RX6_PEXAMAX_RX6_N

    EXAMAX_RX7_PEXAMAX_RX7_N

    EXAMAX_RX8_PEXAMAX_RX8_N

    EXAMAX_TX5_PEXAMAX_TX5_N

    EXAMAX_TX6_PEXAMAX_TX6_N

    EXAMAX_TX7_PEXAMAX_TX7_N

    EXAMAX_TX8_PEXAMAX_TX8_N

    EXAMAX_SI5328_OUT1_BUF1_C_NEXAMAX_SI5328_OUT1_BUF1_C_P

    CFP4_SI5328_OUT1_BUF1_C_NCFP4_SI5328_OUT1_BUF1_C_P

    NCNC

    CFP4_MOD0_RX0_PCFP4_MOD0_RX0_N

    CFP4_MOD0_RX3_PCFP4_MOD0_RX3_N

    CFP4_MOD0_TX0_N

    CFP4_MOD0_TX3_PCFP4_MOD0_TX3_N

    CFP4_MOD0_TX0_P

    CFP4_MOD0_TX2_PCFP4_MOD0_TX2_N

    CFP4_MOD0_TX1_PCFP4_MOD0_TX1_N

    CFP4_MOD0_RX2_PCFP4_MOD0_RX2_N

    CFP4_MOD0_RX1_PCFP4_MOD0_RX1_N

    MGTRREF_120

  • A

    B

    C

    D

    1234

    D

    C

    B

    A

    4 3 2 1

    SHEET SIZE: B

    SHEET OF

    VER:

    REV:

    DRAWN BY:

    TITLE:

    DATE: 1.0

    01

    BF

    09/21/2015:13:58

    PCB P/N: 1280790

    TEST P/N: TSS0174SCH P/N: 0381622

    ASSY P/N: 0431880

    9211

    FPGA Banks 124 125 126 127SCHEM, ROHS COMPLIANTHW-U1-VCU110_REV1_0

    FPGA Banks 124 125 126 127

    100

    1%

    21R1098

    MGTAVTT_FPGA

    1/10W

    BULLSEYE1_GTY_REFCLK0_C_PBULLSEYE1_GTY_REFCLK0_C_NBULLSEYE1_GTY_REFCLK1_C_PBULLSEYE1_GTY_REFCLK1_C_N

    BULLSEYE1_GTY_RX0_PBULLSEYE1_GTY_RX0_N

    BULLSEYE1_GTY_TX0_PBULLSEYE1_GTY_TX0_N

    BULLSEYE1_GTY_RX1_PBULLSEYE1_GTY_RX1_N

    BULLSEYE1_GTY_TX1_PBULLSEYE1_GTY_TX1_N

    BULLSEYE1_GTY_RX2_PBULLSEYE1_GTY_RX2_N

    BULLSEYE1_GTY_TX2_PBULLSEYE1_GTY_TX2_N

    BULLSEYE1_GTY_RX3_PBULLSEYE1_GTY_RX3_N

    BULLSEYE1_GTY_TX3_PBULLSEYE1_GTY_TX3_N

    U1

    AR40AR41AR45AR46AP38AP39AP43AP44AN40AN41AN45AN46AM38AM39AM43AM44AG36AG37AF34AF35MGTREFCLK1N_124_AF35

    MGTREFCLK1P_124_AF34MGTREFCLK0N_124_AG37MGTREFCLK0P_124_AG36

    MGTYRXN3_124_AM44MGTYRXP3_124_AM43MGTYTXN3_124_AM39MGTYTXP3_124_AM38MGTYRXN2_124_AN46MGTYRXP2_124_AN45MGTYTXN2_124_AN41MGTYTXP2_124_AN40MGTYRXN1_124_AP44MGTYRXP1_124_AP43MGTYTXN1_124_AP39MGTYTXP1_124_AP38MGTYRXN0_124_AR46MGTYRXP0_124_AR45MGTYTXN0_124_AR41MGTYTXP0_124_AR40

    XCVU190FLGC2104BANK 124

    SOC_FLGC2104_IRON

    SOC_VU190_FLGC2104_IRONWOOD

    U1

    AL40AL41AL45AL46AK38AK39AK43AK44AJ40AJ41AJ45AJ46AH38AH39AH43AH44AE36AE37AD34AD35AH41AH40MGTAVTTRCAL_LC_AH40

    MGTRREF_LC_AH41MGTREFCLK1N_125_AD35MGTREFCLK1P_125_AD34MGTREFCLK0N_125_AE37MGTREFCLK0P_125_AE36

    MGTYRXN3_125_AH44MGTYRXP3_125_AH43MGTYTXN3_125_AH39MGTYTXP3_125_AH38MGTYRXN2_125_AJ46MGTYRXP2_125_AJ45MGTYTXN2_125_AJ41MGTYTXP2_125_AJ40MGTYRXN1_125_AK44MGTYRXP1_125_AK43MGTYTXN1_125_AK39MGTYTXP1_125_AK38MGTYRXN0_125_AL46MGTYRXP0_125_AL45MGTYTXN0_125_AL41MGTYTXP0_125_AL40

    XCVU190FLGC2104BANK 125

    SOC_FLGC2104_IRON

    SOC_VU190_FLGC2104_IRONWOOD

    U1

    AG40AG41AG45AG46AF38AF39AF43AF44AE40AE41AE45AE46AD38AD39AD43AD44AC36AC37AB34AB35MGTREFCLK1N_126_AB35

    MGTREFCLK1P_126_AB34MGTREFCLK0N_126_AC37MGTREFCLK0P_126_AC36

    MGTYRXN3_126_AD44MGTYRXP3_126_AD43MGTYTXN3_126_AD39MGTYTXP3_126_AD38MGTYRXN2_126_AE46MGTYRXP2_126_AE45MGTYTXN2_126_AE41MGTYTXP2_126_AE40MGTYRXN1_126_AF44MGTYRXP1_126_AF43MGTYTXN1_126_AF39MGTYTXP1_126_AF38MGTYRXN0_126_AG46MGTYRXP0_126_AG45MGTYTXN0_126_AG41MGTYTXP0_126_AG40

    XCVU190FLGC2104BANK 126

    SOC_FLGC2104_IRON

    SOC_VU190_FLGC2104_IRONWOOD

    U1

    AC40AC41AC45AC46AB38AB39AB43AB44AA40AA41AA45AA46Y38Y39Y43Y44AA36AA37Y34Y35MGTREFCLK1N_127_Y35

    MGTREFCLK1P_127_Y34MGTREFCLK0N_127_AA37MGTREFCLK0P_127_AA36

    MGTYRXN3_127_Y44MGTYRXP3_127_Y43MGTYTXN3_127_Y39MGTYTXP3_127_Y38MGTYRXN2_127_AA46MGTYRXP2_127_AA45MGTYTXN2_127_AA41MGTYTXP2_127_AA40MGTYRXN1_127_AB44MGTYRXP1_127_AB43MGTYTXN1_127_AB39MGTYTXP1_127_AB38MGTYRXN0_127_AC46MGTYRXP0_127_AC45MGTYTXN0_127_AC41MGTYTXP0_127_AC40

    XCVU190FLGC2104BANK 127

    SOC_FLGC2104_IRON

    SOC_VU190_FLGC2104_IRONWOOD

    BULLSEYE2_GTY_REFCLK0_C_PBULLSEYE2_GTY_REFCLK0_C_NBULLSEYE2_GTY_REFCLK1_C_PBULLSEYE2_GTY_REFCLK1_C_N

    BULLSEYE2_GTY_RX0_PBULLSEYE2_GTY_RX0_N

    BULLSEYE2_GTY_TX0_PBULLSEYE2_GTY_TX0_N

    BULLSEYE2_GTY_RX1_PBULLSEYE2_GTY_RX1_N

    BULLSEYE2_GTY_TX1_PBULLSEYE2_GTY_TX1_N

    BULLSEYE2_GTY_RX2_PBULLSEYE2_GTY_RX2_N

    BULLSEYE2_GTY_TX2_PBULLSEYE2_GTY_TX2_N

    BULLSEYE2_GTY_RX3_PBULLSEYE2_GTY_RX3_N

    BULLSEYE2_GTY_TX3_PBULLSEYE2_GTY_TX3_N

    1 225V

    0.1UF

    C2542

    1 2

    C2543

    0.1UF

    25V

    1 225V

    0.1UF

    C2544

    1 2

    C2545

    0.1UF

    25V

    BULLSEYE2_GTY_REFCLK0_P

    BULLSEYE2_GTY_REFCLK0_N

    BULLSEYE2_GTY_REFCLK1_N

    BULLSEYE2_GTY_REFCLK1_P

    BULLSEYE2_GTY_REFCLK0_C_P

    BULLSEYE2_GTY_REFCLK0_C_N

    BULLSEYE2_GTY_REFCLK1_C_N

    BULLSEYE2_GTY_REFCLK1_C_P

    1 2

    C2538

    0.1UF

    25V

    1 225V

    0.1UF

    C2539

    1 2

    C2540

    0.1UF

    25V

    1 225V

    0.1UF

    C2541

    BULLSEYE1_GTY_REFCLK0_P

    BULLSEYE1_GTY_REFCLK0_N

    BULLSEYE1_GTY_REFCLK1_N

    BULLSEYE1_GTY_REFCLK1_P

    BULLSEYE1_GTY_REFCLK0_C_P

    BULLSEYE1_GTY_REFCLK0_C_N

    BULLSEYE1_GTY_REFCLK1_C_N

    BULLSEYE1_GTY_REFCLK1_C_P

    CFP4_SI5328_OUT1_BUF2_C_NCFP4_SI5328_OUT1_BUF2_C_P

    CFP4_MOD1_RX0_PCFP4_MOD1_RX0_N

    CFP4_MOD1_RX3_PCFP4_MOD1_RX3_N

    CFP4_MOD1_TX0_N

    CFP4_MOD1_TX3_PCFP4_MOD1_TX3_N

    CFP4_MOD1_TX0_P

    CFP4_MOD1_TX2_PCFP4_MOD1_TX2_N

    CFP4_MOD1_TX1_PCFP4_MOD1_TX1_N

    CFP4_MOD1_RX2_PCFP4_MOD1_RX2_N

    CFP4_MOD1_RX1_PCFP4_MOD1_RX1_N

    NCNC

    NCNC

    CFP4_SI5328_OUT1_BUF3_C_NCFP4_SI5328_OUT1_BUF3_C_P

    CFP4_MOD2_RX0_PCFP4_MOD2_RX0_N

    CFP4_MOD2_RX3_PCFP4_MOD2_RX3_N

    CFP4_MOD2_TX0_N

    CFP4_MOD2_TX3_PCFP4_MOD2_TX3_N

    CFP4_MOD2_TX0_P

    CFP4_MOD2_TX2_PCFP4_MOD2_TX2_N

    CFP4_MOD2_TX1_PCFP4_MOD2_TX1_N

    CFP4_MOD2_RX2_PCFP4_MOD2_RX2_N

    CFP4_MOD2_RX1_NCFP4_MOD2_RX1_P

    MGTRREF_125

  • A

    B

    C

    D

    1234

    D

    C

    B

    A

    4 3 2 1

    SHEET SIZE: B

    SHEET OF

    VER:

    REV:

    DRAWN BY:

    TITLE:

    DATE: 1.0

    01

    BF

    09/21/2015:13:58

    PCB P/N: 1280790

    TEST P/N: TSS0174SCH P/N: 0381622

    ASSY P/N: 0431880

    9212

    FPGA Banks 128 129 130 131SCHEM, ROHS COMPLIANTHW-U1-VCU110_REV1_0

    FPGA Banks 128 129 130 131

    21100

    1%R1099

    MGTAVTT_FPGA

    1/10W

    U1

    W40W41W45W46V38V39V43V44U40U41U45U46T38T39T43T44W36W37V34V35MGTREFCLK1N_128_V35

    MGTREFCLK1P_128_V34MGTREFCLK0N_128_W37MGTREFCLK0P_128_W36

    MGTYRXN3_128_T44MGTYRXP3_128_T43MGTYTXN3_128_T39MGTYTXP3_128_T38MGTYRXN2_128_U46MGTYRXP2_128_U45MGTYTXN2_128_U41MGTYTXP2_128_U40MGTYRXN1_128_V44MGTYRXP1_128_V43MGTYTXN1_128_V39MGTYTXP1_128_V38MGTYRXN0_128_W46MGTYRXP0_128_W45MGTYTXN0_128_W41MGTYTXP0_128_W40

    XCVU190FLGC2104BANK 128

    SOC_FLGC2104_IRON

    SOC_VU190_FLGC2104_IRONWOOD

    U1

    R40R41R45R46P38P39P43P44N40N41N45N46M38M39M43M44U36U37T34T35MGTREFCLK1N_129_T35

    MGTREFCLK1P_129_T34MGTREFCLK0N_129_U37MGTREFCLK0P_129_U36

    MGTYRXN3_129_M44MGTYRXP3_129_M43MGTYTXN3_129_M39MGTYTXP3_129_M38MGTYRXN2_129_N46MGTYRXP2_129_N45MGTYTXN2_129_N41MGTYTXP2_129_N40MGTYRXN1_129_P44MGTYRXP1_129_P43MGTYTXN1_129_P39MGTYTXP1_129_P38MGTYRXN0_129_R46MGTYRXP0_129_R45MGTYTXN0_129_R41MGTYTXP0_129_R40

    XCVU190FLGC2104BANK 129

    SOC_FLGC2104_IRON

    SOC_VU190_FLGC2104_IRONWOOD

    U1

    L40L41L45L46K38K39K43K44J40J41J45J46H38H39H43H44R36R37P34P35D41D40MGTAVTTRCAL_LN_D40

    MGTRREF_LN_D41MGTREFCLK1N_130_P35MGTREFCLK1P_130_P34MGTREFCLK0N_130_R37MGTREFCLK0P_130_R36

    MGTYRXN3_130_H44MGTYRXP3_130_H43MGTYTXN3_130_H39MGTYTXP3_130_H38MGTYRXN2_130_J46MGTYRXP2_130_J45MGTYTXN2_130_J41MGTYTXP2_130_J40MGTYRXN1_130_K44MGTYRXP1_130_K43MGTYTXN1_130_K39MGTYTXP1_130_K38MGTYRXN0_130_L46MGTYRXP0_130_L45MGTYTXN0_130_L41MGTYTXP0_130_L40

    XCVU190FLGC2104BANK 130

    SOC_FLGC2104_IRON

    SOC_VU190_FLGC2104_IRONWOOD

    U1

    G40G41G45G46F38F39F43F44G36G37G31G32F34F35E31E32N36N37M34M35MGTREFCLK1N_131_M35

    MGTREFCLK1P_131_M34MGTREFCLK0N_131_N37MGTREFCLK0P_131_N36

    MGTYRXN3_131_E32MGTYRXP3_131_E31MGTYTXN3_131_F35MGTYTXP3_131_F34MGTYRXN2_131_G32MGTYRXP2_131_G31MGTYTXN2_131_G37MGTYTXP2_131_G36MGTYRXN1_131_F44MGTYRXP1_131_F43MGTYTXN1_131_F39MGTYTXP1_131_F38MGTYRXN0_131_G46MGTYRXP0_131_G45MGTYTXN0_131_G41MGTYTXP0_131_G40

    XCVU190FLGC2104BANK 131

    SOC_FLGC2104_IRON

    SOC_VU190_FLGC2104_IRONWOOD

    CFP4_SI5328_OUT1_BUF4_C_NCFP4_SI5328_OUT1_BUF4_C_P

    CFP4_MOD3_RX0_PCFP4_MOD3_RX0_N

    CFP4_MOD3_RX3_PCFP4_MOD3_RX3_N

    CFP4_MOD3_TX0_N

    CFP4_MOD3_TX3_PCFP4_MOD3_TX3_N

    CFP4_MOD3_TX0_P

    CFP4_MOD3_TX2_PCFP4_MOD3_TX2_N

    CFP4_MOD3_TX1_PCFP4_MOD3_TX1_N

    CFP4_MOD3_RX2_PCFP4_MOD3_RX2_N

    CFP4_MOD3_RX1_NCFP4_MOD3_RX1_P

    CFP4_REC_CLOCK2_C_NCFP4_REC_CLOCK2_C_P

    NCNC

    ILKN_RX1_C_PILKN_RX1_C_N

    ILKN_RX2_C_PILKN_RX2_C_N

    ILKN_RX3_C_PILKN_RX3_C_N

    ILKN_RX0_C_PILKN_RX0_C_NILKN_TX1_PILKN_TX1_N

    ILKN_TX2_PILKN_TX2_N

    ILKN_TX3_PILKN_TX3_N

    ILKN_TX0_PILKN_TX0_N

    ILKN_SI5328_OUT2_BUF1_C_NILKN_SI5328_OUT2_BUF1_C_P

    NCNC

    ILKN_RX11_C_PILKN_RX11_C_N

    ILKN_RX8_C_PILKN_RX8_C_N

    ILKN_RX9_C_PILKN_RX9_C_N

    ILKN_RX10_C_PILKN_RX10_C_NILKN_TX11_PILKN_TX11_N

    ILKN_TX8_PILKN_TX8_N

    ILKN_TX9_PILKN_TX9_N

    ILKN_TX10_PILKN_TX10_N

    ILKN_SI5328_OUT2_BUF3_C_PILKN_SI5328_OUT2_BUF3_C_N

    NCNC

    ILKN_RX4_C_PILKN_RX4_C_N

    ILKN_RX5_C_PILKN_RX5_C_N

    ILKN_RX6_C_PILKN_RX6_C_N

    ILKN_RX7_C_PILKN_RX7_C_N

    ILKN_TX4_PILKN_TX4_N

    ILKN_TX5_PILKN_TX5_N

    ILKN_TX6_PILKN_TX6_N

    ILKN_TX7_PILKN_TX7_N

    ILKN_SI5328_OUT2_BUF2_C_PILKN_SI5328_OUT2_BUF2_C_N

    MGTRREF_130

  • A

    B

    C

    D

    1234

    D

    C

    B

    A

    4 3 2 1

    SHEET SIZE: B

    SHEET OF

    VER:

    REV:

    DRAWN BY:

    TITLE:

    DATE: 1.0

    01

    BF

    09/21/2015:13:58

    PCB P/N: 1280790

    TEST P/N: TSS0174SCH P/N: 0381622

    ASSY P/N: 0431880

    9213

    FPGA Banks 132 133SCHEM, ROHS COMPLIANTHW-U1-VCU110_REV1_0

    FPGA Banks 132 133

    U1

    E40E41E45E46E36E37D43D44C40C41C45C46A40A41B43B44L36L37K34K35MGTREFCLK1N_132_K35

    MGTREFCLK1P_132_K34MGTREFCLK0N_132_L37MGTREFCLK0P_132_L36

    MGTYRXN3_132_B44MGTYRXP3_132_B43MGTYTXN3_132_A41MGTYTXP3_132_A40MGTYRXN2_132_C46MGTYRXP2_132_C45MGTYTXN2_132_C41MGTYTXP2_132_C40MGTYRXN1_132_D44MGTYRXP1_132_D43MGTYTXN1_132_E37MGTYTXP1_132_E36MGTYRXN0_132_E46MGTYRXP0_132_E45MGTYTXN0_132_E41MGTYTXP0_132_E40

    XCVU190FLGC2104BANK 132

    BANK MIGRATION:VU160 = BANK 132VU125 = BANK 132

    VU095 = NC

    SOC_FLGC2104_IRON

    SOC_VU190_FLGC2104_IRONWOOD

    MGTREFCLK1N_133_H35MGTREFCLK1P_133_H34MGTREFCLK0N_133_J37MGTREFCLK0P_133_J36

    MGTYRXN3_133_A32MGTYRXP3_133_A31MGTYTXN3_133_A37MGTYTXP3_133_A36MGTYRXN2_133_B34MGTYRXP2_133_B33MGTYTXN2_133_B39MGTYTXP2_133_B38MGTYRXN1_133_C32MGTYRXP1_133_C31MGTYTXN1_133_C37MGTYTXP1_133_C36MGTYRXN0_133_D34MGTYRXP0_133_D33MGTYTXN0_133_D39MGTYTXP0_133_D38

    XCVU190FLGC2104BANK 133

    BANK MIGRATION:VU160 = BANK 133VU125 = BANK 133

    VU095 = NC

    B38B39B33B34A36A37A31A32J36J37H34H35

    SOC_FLGC2104_IRON

    SOC_VU190_FLGC2104_IRONWOOD

    D38D39D33D34C36C37C31C32

    U1

    ILKN_RX16_C_PILKN_RX16_C_N

    ILKN_RX17_C_PILKN_RX17_C_N

    ILKN_RX18_C_PILKN_RX18_C_N

    ILKN_RX19_C_PILKN_RX19_C_N

    ILKN_TX16_PILKN_TX16_N

    ILKN_TX17_PILKN_TX17_N

    ILKN_TX18_PILKN_TX18_N

    ILKN_TX19_PILKN_TX19_N

    NCNC

    ILKN_SI5328_OUT2_BUF5_C_PILKN_SI5328_OUT2_BUF5_C_NNCNC

    ILKN_RX12_C_PILKN_RX12_C_N

    ILKN_RX13_C_PILKN_RX13_C_N

    ILKN_RX14_C_PILKN_RX14_C_N

    ILKN_RX15_C_PILKN_RX15_C_N

    ILKN_TX12_PILKN_TX12_N

    ILKN_TX13_PILKN_TX13_N

    ILKN_TX14_PILKN_TX14_N

    ILKN_TX15_PILKN_TX15_N

    ILKN_SI5328_OUT2_BUF4_C_PILKN_SI5328_OUT2_BUF4_C_N

  • A

    B

    C

    D

    1234

    D

    C

    B

    A

    4 3 2 1

    SHEET SIZE: B

    SHEET OF

    VER:

    REV:

    DRAWN BY:

    TITLE:

    DATE: 1.0

    01

    BF

    09/21/2015:16:07

    PCB P/N: 1280790

    TEST P/N: TSS0174SCH P/N: 0381622

    ASSY P/N: 0431880

    9214

    FPGA Banks 220 221 222SCHEM, ROHS COMPLIANTHW-U1-VCU110_REV1_0

    21R1232

    1%

    100 MGTAVTT_FPGA

    1 2

    C1572

    0.1UF

    25V

    1 225V

    0.1UF

    C1573

    1 2

    C1574

    0.1UF

    25V

    1 225V

    0.1UF

    C1575

    FMC_HPC1_GBTCLK0_M2C_BUF1_P

    FMC_HPC1_GBTCLK0_M2C_BUF1_N

    FMC_HPC1_GBTCLK1_M2C_BUF1_N

    FMC_HPC1_GBTCLK1_M2C_BUF1_P

    FMC_HPC1_GBTCLK0_M2C_BUF1_C_P

    FMC_HPC1_GBTCLK0_M2C_BUF1_C_N

    FMC_HPC1_GBTCLK1_M2C_BUF1_C_N

    FMC_HPC1_GBTCLK1_M2C_BUF1_C_P

    1 225V

    0.1UF

    C1576

    1 2

    C1577

    0.1UF

    25V

    1 225V

    0.1UF

    C1578

    1 2

    C1579

    0.1UF

    25V

    FMC_HPC0_GBTCLK0_M2C_P

    FMC_HPC0_GBTCLK0_M2C_N

    FMC_HPC0_GBTCLK1_M2C_N

    FMC_HPC0_GBTCLK1_M2C_P

    FMC_HPC0_GBTCLK0_M2C_C_P

    FMC_HPC0_GBTCLK0_M2C_C_N

    FMC_HPC0_GBTCLK1_M2C_C_N

    FMC_HPC0_GBTCLK1_M2C_C_P

    FPGA Banks 220 221 222

    FMC_HPC0_GBTCLK0_M2C_C_PFMC_HPC0_GBTCLK0_M2C_C_N

    FMC_HPC0_GBTCLK1_M2C_C_NFMC_HPC0_GBTCLK1_M2C_C_P

    FMC_HPC0_DP4_M2C_NFMC_HPC0_DP4_M2C_P

    FMC_HPC0_DP4_C2M_PFMC_HPC0_DP4_C2M_N

    FMC_HPC0_DP5_M2C_NFMC_HPC0_DP5_M2C_P

    FMC_HPC0_DP5_C2M_PFMC_HPC0_DP5_C2M_N

    FMC_HPC0_DP6_C2M_PFMC_HPC0_DP6_C2M_N

    FMC_HPC0_DP6_M2C_NFMC_HPC0_DP6_M2C_P

    FMC_HPC0_DP7_C2M_PFMC_HPC0_DP7_C2M_N

    FMC_HPC0_DP7_M2C_NFMC_HPC0_DP7_M2C_P

    NCNCNCNC

    FMC_HPC0_DP1_C2M_N

    FMC_HPC0_DP1_M2C_NFMC_HPC0_DP1_M2C_P

    FMC_HPC0_DP1_C2M_P

    FMC_HPC0_DP0_C2M_PFMC_HPC0_DP0_C2M_NFMC_HPC0_DP0_M2C_PFMC_HPC0_DP0_M2C_N

    FMC_HPC0_DP2_C2M_PFMC_HPC0_DP2_C2M_N

    FMC_HPC0_DP2_M2C_NFMC_HPC0_DP2_M2C_P

    FMC_HPC0_DP3_C2M_PFMC_HPC0_DP3_C2M_NFMC_HPC0_DP3_M2C_PFMC_HPC0_DP3_M2C_N

    FMC_HPC1_GBTCLK0_M2C_BUF1_C_PFMC_HPC1_GBTCLK0_M2C_BUF1_C_N

    FMC_HPC1_GBTCLK1_M2C_BUF1_C_NFMC_HPC1_GBTCLK1_M2C_BUF1_C_P

    1/10W

    U1

    BF9BF8BF14BF13BE11BE10BD14BD13BE7BE6BF4BF3BD9BD8BD4BD3AN11AN10AM13AM12MGTREFCLK1N_220_AM12

    MGTREFCLK1P_220_AM13MGTREFCLK0N_220_AN10MGTREFCLK0P_220_AN11

    MGTHRXN3_220_BD3MGTHRXP3_220_BD4MGTHTXN3_220_BD8MGTHTXP3_220_BD9MGTHRXN2_220_BF3MGTHRXP2_220_BF4MGTHTXN2_220_BE6MGTHTXP2_220_BE7MGTHRXN1_220_BD13MGTHRXP1_220_BD14MGTHTXN1_220_BE10MGTHTXP1_220_BE11MGTHRXN0_220_BF13MGTHRXP0_220_BF14MGTHTXN0_220_BF8MGTHTXP0_220_BF9

    XCVU190FLGC2104BANK 220

    BANK MIGRATION:VU160 = BANK 220

    VU125 = NCVU095 = NC

    SOC_FLGC2104_IRON

    SOC_VU190_FLGC2104_IRONWOOD

    U1

    BC7BC6BC2BC1BB9BB8BB4BB3BA7BA6BA2BA1AY9AY8AY4AY3AL11AL10AK13AK12BD10BD11MGTAVTTRCAL_RS_BD11

    MGTRREF_RS_BD10MGTREFCLK1N_221_AK12MGTREFCLK1P_221_AK13MGTREFCLK0N_221_AL10MGTREFCLK0P_221_AL11

    MGTHRXN3_221_AY3MGTHRXP3_221_AY4MGTHTXN3_221_AY8MGTHTXP3_221_AY9MGTHRXN2_221_BA1MGTHRXP2_221_BA2MGTHTXN2_221_BA6MGTHTXP2_221_BA7MGTHRXN1_221_BB3MGTHRXP1_221_BB4MGTHTXN1_221_BB8MGTHTXP1_221_BB9MGTHRXN0_221_BC1MGTHRXP0_221_BC2MGTHTXN0_221_BC6MGTHTXP0_221_BC7

    XCVU190FLGC2104BANK 221

    BANK MIGRATION:VU160 = BANK 221

    VU125 = NCVU095 = NC

    SOC_FLGC2104_IRON

    SOC_VU190_FLGC2104_IRONWOOD

    U1

    AW7AW6AW2AW1AV9AV8AV4AV3AU7AU6AU2AU1AT9AT8AT4AT3AJ11AJ10AH13AH12MGTREFCLK1N_222_AH12

    MGTREFCLK1P_222_AH13MGTREFCLK0N_222_AJ10MGTREFCLK0P_222_AJ11

    MGTHRXN3_222_AT3MGTHRXP3_222_AT4MGTHTXN3_222_AT8MGTHTXP3_222_AT9MGTHRXN2_222_AU1MGTHRXP2_222_AU2MGTHTXN2_222_AU6MGTHTXP2_222_AU7MGTHRXN1_222_AV3MGTHRXP1_222_AV4MGTHTXN1_222_AV8MGTHTXP1_222_AV9MGTHRXN0_222_AW1MGTHRXP0_222_AW2MGTHTXN0_222_AW6MGTHTXP0_222_AW7

    XCVU190FLGC2104BANK 222

    BANK MIGRATION:VU160 = BANK 222

    VU125 = NCVU095 = NC

    SOC_FLGC2104_IRON

    SOC_VU190_FLGC2104_IRONWOOD

    FMC_HPC1_DP7_C2M_PFMC_HPC1_DP7_C2M_N

    FMC_HPC1_DP6_C2M_PFMC_HPC1_DP6_C2M_N

    FMC_HPC1_DP7_M2C_NFMC_HPC1_DP7_M2C_P

    FMC_HPC1_DP6_M2C_NFMC_HPC1_DP6_M2C_P

    FMC_HPC1_DP5_M2C_NFMC_HPC1_DP5_M2C_P

    FMC_HPC1_DP4_M2C_NFMC_HPC1_DP4_M2C_P

    FMC_HPC1_DP4_C2M_PFMC_HPC1_DP4_C2M_N

    FMC_HPC1_DP5_C2M_PFMC_HPC1_DP5_C2M_N

    MGTRREF_221

  • A

    B

    C

    D

    1234

    D

    C

    B

    A

    4 3 2 1

    SHEET SIZE: B

    SHEET OF

    VER:

    REV:

    DRAWN BY:

    TITLE:

    DATE: 1.0

    01

    BF

    09/21/2015:13:57

    PCB P/N: 1280790

    TEST P/N: TSS0174SCH P/N: 0381622

    ASSY P/N: 0431880

    9215

    FPGA Banks 224 225 226 227SCHEM, ROHS COMPLIANTHW-U1-VCU110_REV1_0

    FPGA Banks 224 225 226 227

    21R1088

    100

    1%

    MGTAVTT_FPGA

    NCNCNCNC

    HMC_SI5328_OUT2_BUF2_C_NHMC_SI5328_OUT2_BUF2_C_P

    NCNC

    NCNCNCNC

    1/10W

    U1

    AR7AR6AR2AR1AP9AP8AP4AP3AN7AN6AN2AN1AM9AM8AM4AM3AG11AG10AF13AF12MGTREFCLK1N_224_AF12

    MGTREFCLK1P_224_AF13MGTREFCLK0N_224_AG10MGTREFCLK0P_224_AG11

    MGTHRXN3_224_AM3MGTHRXP3_224_AM4MGTHTXN3_224_AM8MGTHTXP3_224_AM9MGTHRXN2_224_AN1MGTHRXP2_224_AN2MGTHTXN2_224_AN6MGTHTXP2_224_AN7MGTHRXN1_224_AP3MGTHRXP1_224_AP4MGTHTXN1_224_AP8MGTHTXP1_224_AP9MGTHRXN0_224_AR1MGTHRXP0_224_AR2MGTHTXN0_224_AR6MGTHTXP0_224_AR7

    XCVU190FLGC2104BANK 224

    SOC_FLGC2104_IRON

    SOC_VU190_FLGC2104_IRONWOOD

    U1

    AL7AL6AL2AL1AK9AK8AK4AK3AJ7AJ6AJ2AJ1AH9AH8AH4AH3AE11AE10AD13AD12MGTREFCLK1N_225_AD12

    MGTREFCLK1P_225_AD13MGTREFCLK0N_225_AE10MGTREFCLK0P_225_AE11

    MGTHRXN3_225_AH3MGTHRXP3_225_AH4MGTHTXN3_225_AH8MGTHTXP3_225_AH9MGTHRXN2_225_AJ1MGTHRXP2_225_AJ2MGTHTXN2_225_AJ6MGTHTXP2_225_AJ7MGTHRXN1_225_AK3MGTHRXP1_225_AK4MGTHTXN1_225_AK8MGTHTXP1_225_AK9MGTHRXN0_225_AL1MGTHRXP0_225_AL2MGTHTXN0_225_AL6MGTHTXP0_225_AL7

    XCVU190FLGC2104BANK 225

    SOC_FLGC2104_IRON

    SOC_VU190_FLGC2104_IRONWOOD

    U1

    AG7AG6AG2AG1AF9AF8AF4AF3AE7AE6AE2AE1AD9AD8AD4AD3AC11AC10AB13AB12AH6AH7MGTAVTTRCAL_RC_AH7

    MGTRREF_RC_AH6MGTREFCLK1N_226_AB12MGTREFCLK1P_226_AB13MGTREFCLK0N_226_AC10MGTREFCLK0P_226_AC11

    MGTHRXN3_226_AD3MGTHRXP3_226_AD4MGTHTXN3_226_AD8MGTHTXP3_226_AD9MGTHRXN2_226_AE1MGTHRXP2_226_AE2MGTHTXN2_226_AE6MGTHTXP2_226_AE7MGTHRXN1_226_AF3MGTHRXP1_226_AF4MGTHTXN1_226_AF8MGTHTXP1_226_AF9MGTHRXN0_226_AG1MGTHRXP0_226_AG2MGTHTXN0_226_AG6MGTHTXP0_226_AG7

    XCVU190FLGC2104BANK 226

    SOC_FLGC2104_IRON

    SOC_VU190_FLGC2104_IRONWOOD

    U1

    AC7AC6AC2AC1AB9AB8AB4AB3AA7AA6AA2AA1Y9Y8Y4Y3AA11AA10Y13Y12MGTREFCLK1N_227_Y12

    MGTREFCLK1P_227_Y13MGTREFCLK0N_227_AA10MGTREFCLK0P_227_AA11

    MGTHRXN3_227_Y3MGTHRXP3_227_Y4MGTHTXN3_227_Y8MGTHTXP3_227_Y9

    MGTHRXN2_227_AA1MGTHRXP2_227_AA2MGTHTXN2_227_AA6MGTHTXP2_227_AA7MGTHRXN1_227_AB3MGTHRXP1_227_AB4MGTHTXN1_227_AB8MGTHTXP1_227_AB9MGTHRXN0_227_AC1MGTHRXP0_227_AC2MGTHTXN0_227_AC6MGTHTXP0_227_AC7

    XCVU190FLGC2104BANK 227

    SOC_FLGC2104_IRON

    SOC_VU190_FLGC2104_IRONWOOD

    FMC_HPC1_GBTCLK0_M2C_BUF2_C_PFMC_HPC1_GBTCLK0_M2C_BUF2_C_N

    FMC_HPC1_GBTCLK1_M2C_BUF2_C_NFMC_HPC1_GBTCLK1_M2C_BUF2_C_P

    1 225V

    0.1UF

    C2657

    1 2

    C2658

    0.1UF

    25V

    1 225V

    0.1UF

    C2659

    1 2

    C2660

    0.1UF

    25V

    FMC_HPC1_GBTCLK0_M2C_BUF2_P

    FMC_HPC1_GBTCLK0_M2C_BUF2_N

    FMC_HPC1_GBTCLK1_M2C_BUF2_N

    FMC_HPC1_GBTCLK1_M2C_BUF2_P

    FMC_HPC1_GBTCLK0_M2C_BUF2_C_P

    FMC_HPC1_GBTCLK0_M2C_BUF2_C_N

    FMC_HPC1_GBTCLK1_M2C_BUF2_C_N

    FMC_HPC1_GBTCLK1_M2C_BUF2_C_P

    FMC_HPC1_DP1_C2M_N

    FMC_HPC1_DP1_M2C_NFMC_HPC1_DP1_M2C_P

    FMC_HPC1_DP1_C2M_P

    FMC_HPC1_DP0_C2M_PFMC_HPC1_DP0_C2M_NFMC_HPC1_DP0_M2C_PFMC_HPC1_DP0_M2C_N

    FMC_HPC1_DP3_C2M_PFMC_HPC1_DP3_C2M_N

    FMC_HPC1_DP2_C2M_PFMC_HPC1_DP2_C2M_N

    FMC_HPC1_DP2_M2C_NFMC_HPC1_DP2_M2C_P

    FMC_HPC1_DP3_M2C_PFMC_HPC1_DP3_M2C_N

    HMC_L1RX_13_C_PHMC_L1RX_13_C_N

    HMC_L1RX_14_C_PHMC_L1RX_14_C_N

    HMC_L1RX_15_C_PHMC_L1RX_15_C_NHMC_L1TX_13_PHMC_L1TX_13_N

    HMC_L1TX_14_PHMC_L1TX_14_N

    HMC_L1TX_15_PHMC_L1TX_15_N

    HMC_L1RX_11_C_PHMC_L1RX_11_C_N

    HMC_L1TX_11_PHMC_L1TX_11_N

    HMC_L1RX_4_C_PHMC_L1RX_4_C_N

    HMC_L1RX_5_C_PHMC_L1RX_5_C_N

    HMC_L1RX_6_C_PHMC_L1RX_6_C_N

    HMC_L1RX_7_C_PHMC_L1RX_7_C_N

    HMC_L1TX_4_PHMC_L1TX_4_N

    HMC_L1TX_5_PHMC_L1TX_5_N

    HMC_L1TX_6_PHMC_L1TX_6_N

    HMC_L1TX_7_PHMC_L1TX_7_N

    HMC_L1RX_0_C_PHMC_L1RX_0_C_N

    HMC_L1RX_1_C_PHMC_L1RX_1_C_N

    HMC_L1RX_2_C_PHMC_L1RX_2_C_N

    HMC_L1RX_3_C_PHMC_L1RX_3_C_N

    HMC_L1TX_0_PHMC_L1TX_0_N

    HMC_L1TX_1_PHMC_L1TX_1_N

    HMC_L1TX_2_PHMC_L1TX_2_N

    HMC_L1TX_3_PHMC_L1TX_3_N

    MGTRREF_226

  • A

    B

    C

    D

    1234

    D

    C

    B

    A

    4 3 2 1

    SHEET SIZE: B

    SHEET OF

    VER:

    REV:

    DRAWN BY:

    TITLE:

    DATE: 1.0

    01

    BF

    09/21/2015:13:58

    PCB P/N: 1280790

    TEST P/N: TSS0174SCH P/N: 0381622

    ASSY P/N: 0431880

    9216

    FPGA Banks 228 229 230 231SCHEM, ROHS COMPLIANTHW-U1-VCU110_REV1_0

    FPGA Banks 228 229 230 231

    21

    1%

    100

    R1089

    MGTAVTT_FPGA

    NCNCNCNC

    NCNC

    HMC_SI5328_OUT2_BUF1_C_NHMC_SI5328_OUT2_BUF1_C_P

    NCNC

    NCNC

    NCNCNCNC

    1/10W

    U1

    W7W6W2W1V9V8V4V3U7U6U2U1T9T8T4T3W11W10V13V12MGTREFCLK1N_228_V12

    MGTREFCLK1P_228_V13MGTREFCLK0N_228_W10MGTREFCLK0P_228_W11

    MGTHRXN3_228_T3MGTHRXP3_228_T4MGTHTXN3_228_T8MGTHTXP3_228_T9MGTHRXN2_228_U1MGTHRXP2_228_U2MGTHTXN2_228_U6MGTHTXP2_228_U7MGTHRXN1_228_V3MGTHRXP1_228_V4MGTHTXN1_228_V8MGTHTXP1_228_V9MGTHRXN0_228_W1MGTHRXP0_228_W2MGTHTXN0_228_W6MGTHTXP0_228_W7

    XCVU190FLGC2104BANK 228

    SOC_FLGC2104_IRON

    SOC_VU190_FLGC2104_IRONWOOD

    U1

    R7R6R2R1P9P8P4P3N7N6N2N1M9M8M4M3U11U10T13T12MGTREFCLK1N_229_T12

    MGTREFCLK1P_229_T13MGTREFCLK0N_229_U10MGTREFCLK0P_229_U11

    MGTHRXN3_229_M3MGTHRXP3_229_M4MGTHTXN3_229_M8MGTHTXP3_229_M9MGTHRXN2_229_N1MGTHRXP2_229_N2MGTHTXN2_229_N6MGTHTXP2_229_N7MGTHRXN1_229_P3MGTHRXP1_229_P4MGTHTXN1_229_P8MGTHTXP1_229_P9MGTHRXN0_229_R1MGTHRXP0_229_R2MGTHTXN0_229_R6MGTHTXP0_229_R7

    XCVU190FLGC2104BANK 229

    SOC_FLGC2104_IRON

    SOC_VU190_FLGC2104_IRONWOOD

    U1

    L7L6L2L1K9K8K4K3J7J6J2J1H9H8H4H3R11R10P13P12MGTREFCLK1N_230_P12

    MGTREFCLK1P_230_P13MGTREFCLK0N_230_R10MGTREFCLK0P_230_R11

    MGTHRXN3_230_H3MGTHRXP3_230_H4MGTHTXN3_230_H8MGTHTXP3_230_H9MGTHRXN2_230_J1MGTHRXP2_230_J2MGTHTXN2_230_J6MGTHTXP2_230_J7MGTHRXN1_230_K3MGTHRXP1_230_K4MGTHTXN1_230_K8MGTHTXP1_230_K9MGTHRXN0_230_L1MGTHRXP0_230_L2MGTHTXN0_230_L6MGTHTXP0_230_L7

    XCVU190FLGC2104BANK 230

    SOC_FLGC2104_IRON

    SOC_VU190_FLGC2104_IRONWOOD

    U1

    G7G6G2G1F9F8F4F3G11G10G16G15F13F12E16E15N11N10M13M12D6D7MGTAVTTRCAL_RN_D7

    MGTRREF_RN_D6MGTREFCLK1N_231_M12MGTREFCLK1P_231_M13MGTREFCLK0N_231_N10MGTREFCLK0P_231_N11

    MGTHRXN3_231_E15MGTHRXP3_231_E16MGTHTXN3_231_F12MGTHTXP3_231_F13MGTHRXN2_231_G15MGTHRXP2_231_G16MGTHTXN2_231_G10MGTHTXP2_231_G11MGTHRXN1_231_F3MGTHRXP1_231_F4MGTHTXN1_231_F8MGTHTXP1_231_F9MGTHRXN0_231_G1MGTHRXP0_231_G2MGTHTXN0_231_G6MGTHTXP0_231_G7

    XCVU190FLGC2104BANK 231

    SOC_FLGC2104_IRON

    SOC_VU190_FLGC2104_IRONWOOD

    HMC_L0RX_4_C_PHMC_L0RX_4_C_N

    HMC_L0RX_6_C_PHMC_L0RX_6_C_N

    HMC_L0TX_4_PHMC_L0TX_4_N

    HMC_L0TX_6_PHMC_L0TX_6_N

    HMC_L0RX_8_C_PHMC_L0RX_8_C_N

    HMC_L0RX_9_C_PHMC_L0RX_9_C_N

    HMC_L0RX_10_C_PHMC_L0RX_10_C_N

    HMC_L0RX_11_C_PHMC_L0RX_11_C_N

    HMC_L0TX_8_PHMC_L0TX_8_N

    HMC_L0TX_9_PHMC_L0TX_9_N

    HMC_L0TX_10_PHMC_L0TX_10_N

    HMC_L0TX_11_PHMC_L0TX_11_N

    HMC_L0TX_0_PHMC_L0TX_0_N

    HMC_L0TX_1_PHMC_L0TX_1_N

    HMC_L0TX_2_PHMC_L0TX_2_N

    HMC_L0RX_0_C_PHMC_L0RX_0_C_N

    HMC_L0RX_1_C_PHMC_L0RX_1_C_N

    HMC_L0RX_2_C_PHMC_L0RX_2_C_N

    HMC_L0RX_12_C_PHMC_L0RX_12_C_N

    HMC_L0RX_13_C_PHMC_L0RX_13_C_N

    HMC_L0RX_14_C_PHMC_L0RX_14_C_N

    HMC_L0TX_12_PHMC_L0TX_12_N

    HMC_L0TX_13_PHMC_L0TX_13_N

    HMC_L0TX_14_PHMC_L0TX_14_N

    HMC_L1RX_9_C_PHMC_L1RX_9_C_N

    HMC_L1TX_9_PHMC_L1TX_9_N

    HMC_L1RX_12_C_PHMC_L1RX_12_C_N

    HMC_L1TX_12_PHMC_L1TX_12_N

    HMC_L1RX_8_C_PHMC_L1RX_8_C_N

    HMC_L1TX_8_PHMC_L1TX_8_N

    HMC_L1RX_10_C_PHMC_L1RX_10_C_N

    HMC_L1TX_10_PHMC_L1TX_10_N

    MGTRREF_231

  • A

    B

    C

    D

    1234

    D

    C

    B

    A

    4 3 2 1

    SHEET SIZE: B

    SHEET OF

    VER:

    REV:

    DRAWN BY:

    TITLE:

    DATE: 1.0

    01

    BF

    09/21/2015:13:58

    PCB P/N: 1280790

    TEST P/N: TSS0174SCH P/N: 0381622

    ASSY P/N: 0431880

    9217

    FPGA Bank 232 233SCHEM, ROHS COMPLIANTHW-U1-VCU110_REV1_0

    FPGA Bank 232 233

    NCNC

    NCNC

    U1

    E7E6E2E1E11E10D4D3C7C6C2C1A7A6B4B3L11L10K13K12MGTREFCLK1N_232_K12

    MGTREFCLK1P_232_K13MGTREFCLK0N_232_L10MGTREFCLK0P_232_L11

    MGTHRXN3_232_B3MGTHRXP3_232_B4MGTHTXN3_232_A6MGTHTXP3_232_A7MGTHRXN2_232_C1MGTHRXP2_232_C2MGTHTXN2_232_C6MGTHTXP2_232_C7MGTHRXN1_232_D3MGTHRXP1_232_D4

    MGTHTXN1_232_E10MGTHTXP1_232_E11MGTHRXN0_232_E1MGTHRXP0_232_E2MGTHTXN0_232_E6MGTHTXP0_232_E7

    XCVU190FLGC2104BANK 232

    BANK MIGRATION:VU160 = BANK 232VU125 = BANK 232

    VU095 = NC

    SOC_FLGC2104_IRON

    SOC_VU190_FLGC2104_IRONWOOD

    MGTREFCLK1N_233_H12MGTREFCLK1P_233_H13MGTREFCLK0N_233_J10MGTREFCLK0P_233_J11

    MGTHRXN3_233_A15MGTHRXP3_233_A16MGTHTXN3_233_A10MGTHTXP3_233_A11MGTHRXN2_233_B13MGTHRXP2_233_B14MGTHTXN2_233_B8MGTHTXP2_233_B9

    MGTHRXN1_233_C15MGTHRXP1_233_C16MGTHTXN1_233_C10MGTHTXP1_233_C11MGTHRXN0_233_D13MGTHRXP0_233_D14MGTHTXN0_233_D8MGTHTXP0_233_D9

    XCVU190FLGC2104BANK 233

    BANK MIGRATION:VU160 = BANK 233VU125 = BANK 233

    VU095 = NC

    H12H13J10J11A15A16A10A11B13B14B8B9C15C16C10C11D13D14D8D9

    SOC_VU190_FLGC2104_IRONWOOD

    SOC_FLGC2104_IRONU1

    PCIE_CABLE_CLK_C_NPCIE_CABLE_CLK_C_P

    PCIE_CABLE_RX0_NPCIE_CABLE_RX0_P

    PCIE_CABLE_RX1_NPCIE_CABLE_RX1_P

    PCIE_CABLE_RX2_NPCIE_CABLE_RX2_P

    PCIE_CABLE_RX3_NPCIE_CABLE_RX3_P

    PCIE_CABLE_TX0_C_NPCIE_CABLE_TX0_C_P

    PCIE_CABLE_TX1_C_NPCIE_CABLE_TX1_C_P

    PCIE_CABLE_TX2_C_NPCIE_CABLE_TX2_C_P

    PCIE_CABLE_TX3_C_NPCIE_CABLE_TX3_C_P

    HMC_L0RX_5_C_PHMC_L0RX_5_C_N

    HMC_L0RX_7_C_PHMC_L0RX_7_C_N

    HMC_L0TX_5_PHMC_L0TX_5_N

    HMC_L0TX_7_PHMC_L0TX_7_N

    HMC_L0TX_3_PHMC_L0TX_3_NHMC_L0RX_3_C_PHMC_L0RX_3_C_N

    HMC_L0RX_15_C_PHMC_L0RX_15_C_N

    HMC_L0TX_15_PHMC_L0TX_15_N

    NCNC

    PCIE_CABLE_TX0_C_N

    PCIE_CABLE_TX0_C_P

    PCIE_CABLE_TX0_N

    PCIE_CABLE_TX0_P

    25V

    0.1UF

    C2669

    21

    C2670

    0.1UF

    25V

    21

    PCIE_CABLE_TX1_C_N

    PCIE_CABLE_TX1_C_P

    PCIE_CABLE_TX1_N

    PCIE_CABLE_TX1_P

    1 2

    C2671

    0.1UF

    25V

    1 225V

    0.1UF

    C2672

    PCIE_CABLE_TX2_C_N

    PCIE_CABLE_TX2_C_P

    PCIE_CABLE_TX2_N

    PCIE_CABLE_TX2_P

    25V

    0.1UF

    C2673

    21

    C2674

    0.1UF

    25V

    21

    PCIE_CABLE_TX3_C_N

    PCIE_CABLE_TX3_C_P

    PCIE_CABLE_TX3_N

    PCIE_CABLE_TX3_P

    1 2

    C2675

    0.1UF

    25V

    1 225V

    0.1UF

    C2676

    PCIE_CABLE_CLK_C_N

    PCIE_CABLE_CLK_C_P

    PCIE_CABLE_CLK_N

    PCIE_CABLE_CLK_P

    1 2

    C2677

    0.1UF

    25V

    25V

    0.1UF

    C2678

    21

  • A

    B

    C

    D

    1234

    D

    C

    B

    A

    4 3 2 1

    SHEET SIZE: B

    SHEET OF

    VER:

    REV:

    DRAWN BY:

    TITLE:

    DATE: 1.0

    01

    BF

    09/21/2015:13:57

    PCB P/N: 1280790

    TEST P/N: TSS0174SCH P/N: 0381622

    ASSY P/N: 0431880

    9218

    FPGA Power 1SCHEM, ROHS COMPLIANTHW-U1-VCU110_REV1_0

    FPGA Power 1

    MGTAVCC_FPGA

    MGTAVCC_FPGAMGTAVCC_FPGA

    MGTAVCC_FPGA

    MGTAVCC_FPGA

    MGTAVCC_FPGA

    U1

    AF36AE35AD37AC34AA35W38W34V36U35MGTAVCC_LC_U35

    MGTAVCC_LC_V36MGTAVCC_LC_W34MGTAVCC_LC_W38MGTAVCC_LC_AA35MGTAVCC_LC_AC34MGTAVCC_LC_AD37MGTAVCC_LC_AE35MGTAVCC_LC_AF36

    XCVU190FLGC2104BANK MGTAVCC_LC

    SOC_FLGC2104_IRON

    SOC_VU190_FLGC2104_IRONWOOD

    U1

    T37R34P36N35M37K36H37G34F36MGTAVCC_LN_F36

    MGTAVCC_LN_G34MGTAVCC_LN_H37MGTAVCC_LN_K36MGTAVCC_LN_M37MGTAVCC_LN_N35MGTAVCC_LN_P36MGTAVCC_LN_R34MGTAVCC_LN_T37

    XCVU190FLGC2104BANK MGTAVCC_LN

    SOC_FLGC2104_IRON

    SOC_VU190_FLGC2104_IRONWOOD

    U1

    AL38AL34AJ35AH37AG34MGTAVCC_LS_AG34

    MGTAVCC_LS_AH37MGTAVCC_LS_AJ35MGTAVCC_LS_AL34MGTAVCC_LS_AL38

    XCVU190FLGC2104BANK MGTAVCC_LS

    SOC_FLGC2104_IRON

    SOC_VU190_FLGC2104_IRONWOOD

    U1

    AF11AE12AD10AC13AA12W13W9V11U12MGTAVCC_RC_U12

    MGTAVCC_RC_V11MGTAVCC_RC_W9MGTAVCC_RC_W13MGTAVCC_RC_AA12MGTAVCC_RC_AC13MGTAVCC_RC_AD10MGTAVCC_RC_AE12MGTAVCC_RC_AF11

    XCVU190FLGC2104BANK MGTAVCC_RC

    SOC_FLGC2104_IRON

    SOC_VU190_FLGC2104_IRONWOOD

    U1

    T10R13P11N12M10K11H10G13F11MGTAVCC_RN_F11

    MGTAVCC_RN_G13MGTAVCC_RN_H10MGTAVCC_RN_K11MGTAVCC_RN_M10MGTAVCC_RN_N12MGTAVCC_RN_P11MGTAVCC_RN_R13MGTAVCC_RN_T10

    XCVU190FLGC2104BANK MGTAVCC_RN

    SOC_FLGC2104_IRON

    SOC_VU190_FLGC2104_IRONWOOD

    U1

    AL13AL9AJ12AH10AG13MGTAVCC_RS_AG13

    MGTAVCC_RS_AH10MGTAVCC_RS_AJ12MGTAVCC_RS_AL9

    MGTAVCC_RS_AL13

    XCVU190FLGC2104BANK MGTAVCC_RS

    SOC_FLGC2104_IRON

    SOC_VU190_FLGC2104_IRONWOOD

  • A

    B

    C

    D

    1234

    D

    C

    B

    A

    4 3 2 1

    SHEET SIZE: B

    SHEET OF

    VER:

    REV:

    DRAWN BY:

    TITLE:

    DATE: 1.0

    01

    BF

    09/21/2015:13:58

    PCB P/N: 1280790

    TEST P/N: TSS0174SCH P/N: 0381622

    ASSY P/N: 0431880

    9219

    FPGA Power 2SCHEM, ROHS COMPLIANTHW-U1-VCU110_REV1_0

    MGTAVTT_FPGA

    MGTAVTT_FPGA MGTAVTT_FPGA

    MGTAVTT_FPGA MGTAVTT_FPGA

    MGTAVTT_FPGA

    FPGA Power 2

    U1

    AT41AR38AP40AN39AM41AK40AJ39AG38AF40AE39AD41AC38AB40AA39Y41V40U39MGTAVTT_LC_U39

    MGTAVTT_LC_V40MGTAVTT_LC_Y41MGTAVTT_LC_AA39MGTAVTT_LC_AB40MGTAVTT_LC_AC38MGTAVTT_LC_AD41MGTAVTT_LC_AE39MGTAVTT_LC_AF40MGTAVTT_LC_AG38MGTAVTT_LC_AJ39MGTAVTT_LC_AK40MGTAVTT_LC_AM41MGTAVTT_LC_AN39MGTAVTT_LC_AP40MGTAVTT_LC_AR38MGTAVTT_LC_AT41

    XCVU190FLGC2104BANK MGTAVTT_LC

    SOC_FLGC2104_IRON

    SOC_VU190_FLGC2104_IRONWOOD

    U1

    T41R38P40N39M41L38K40J39H41G38F40E39D37C38B40B36A43MGTAVTT_LN_A43

    MGTAVTT_LN_B36MGTAVTT_LN_B40MGTAVTT_LN_C38MGTAVTT_LN_D37MGTAVTT_LN_E39MGTAVTT_LN_F40MGTAVTT_LN_G38MGTAVTT_LN_H41MGTAVTT_LN_J39MGTAVTT_LN_K40MGTAVTT_LN_L38MGTAVTT_LN_M41MGTAVTT_LN_N39MGTAVTT_LN_P40MGTAVTT_LN_R38MGTAVTT_LN_T41

    XCVU190FLGC2104BANK MGTAVTT_LN

    SOC_FLGC2104_IRON

    SOC_VU190_FLGC2104_IRONWOOD

    U1

    BF40BF37BE39BD41BC38BB40BA39AY41AW38AV40AU39MGTAVTT_LS_AU39

    MGTAVTT_LS_AV40MGTAVTT_LS_AW38MGTAVTT_LS_AY41MGTAVTT_LS_BA39MGTAVTT_LS_BB40MGTAVTT_LS_BC38MGTAVTT_LS_BD41MGTAVTT_LS_BE39MGTAVTT_LS_BF37MGTAVTT_LS_BF40

    XCVU190FLGC2104BANK MGTAVTT_LS

    SOC_FLGC2104_IRON

    SOC_VU190_FLGC2104_IRONWOOD

    U1

    AT6AR9AP7AN8AM6AK7AJ8AG9AF7AE8AD6AC9AB7AA8Y6V7U8MGTAVTT_RC_U8

    MGTAVTT_RC_V7MGTAVTT_RC_Y6MGTAVTT_RC_AA8MGTAVTT_RC_AB7MGTAVTT_RC_AC9MGTAVTT_RC_AD6MGTAVTT_RC_AE8MGTAVTT_RC_AF7MGTAVTT_RC_AG9MGTAVTT_RC_AJ8MGTAVTT_RC_AK7MGTAVTT_RC_AM6MGTAVTT_RC_AN8MGTAVTT_RC_AP7MGTAVTT_RC_AR9MGTAVTT_RC_AT6

    XCVU190FLGC2104BANK MGTAVTT_RC

    SOC_FLGC2104_IRON

    SOC_VU190_FLGC2104_IRONWOOD

    U1

    T6R9P7N8M6L9K7J8H6G9F7E8D10C9B11B7A4MGTAVTT_RN_A4

    MGTAVTT_RN_B7MGTAVTT_RN_B11MGTAVTT_RN_C9MGTAVTT_RN_D10MGTAVTT_RN_E8MGTAVTT_RN_F7MGTAVTT_RN_G9MGTAVTT_RN_H6MGTAVTT_RN_J8MGTAVTT_RN_K7MGTAVTT_RN_L9MGTAVTT_RN_M6MGTAVTT_RN_N8MGTAVTT_RN_P7MGTAVTT_RN_R9MGTAVTT_RN_T6

    XCVU190FLGC2104BANK MGTAVTT_RN

    SOC_FLGC2104_IRON

    SOC_VU190_FLGC2104_IRONWOOD

    U1

    BF10BF7BE8BD6BC9BB7BA8AY6AW9AV7AU8MGTAVTT_RS_AU8

    MGTAVTT_RS_AV7MGTAVTT_RS_AW9MGTAVTT_RS_AY6MGTAVTT_RS_BA8MGTAVTT_RS_BB7MGTAVTT_RS_BC9MGTAVTT_RS_BD6MGTAVTT_RS_BE8MGTAVTT_RS_BF7MGTAVTT_RS_BF10

    XCVU190FLGC2104BANK MGTAVTT_RS

    SOC_FLGC2104_IRON

    SOC_VU190_FLGC2104_IRONWOOD

  • A

    B

    C

    D

    1234

    D

    C

    B

    A

    4 3 2 1

    SHEET SIZE: B

    SHEET OF

    VER:

    REV:

    DRAWN BY:

    TITLE:

    DATE: 1.0

    01

    BF

    09/21/2015:13:58

    PCB P/N: 1280790

    TEST P/N: TSS0174SCH P/N: 0381622

    ASSY P/N: 0431880

    9220

    FPGA Power 3SCHEM, ROHS COMPLIANTHW-U1-VCU110_REV1_0

    MGTVCCAUX

    MGTVCCAUXMGTVCCAUX

    MGTVCCAUX MGTVCCAUX

    MGTVCCAUX

    FPGA Power 3

    U1

    AB36Y37MGTVCCAUX_LC_Y37

    MGTVCCAUX_LC_AB36

    XCVU190FLGC2104BANK MGTVCCAUX_LC

    SOC_FLGC2104_IRON

    SOC_VU190_FLGC2104_IRONWOOD

    U1

    L34J35MGTVCCAUX_LN_J35

    MGTVCCAUX_LN_L34

    XCVU190FLGC2104BANK MGTVCCAUX_LN

    SOC_FLGC2104_IRON

    SOC_VU190_FLGC2104_IRONWOOD

    U1

    AM37AK36MGTVCCAUX_LS_AK36

    MGTVCCAUX_LS_AM37

    XCVU190FLGC2104BANK MGTVCCAUX_LS

    SOC_FLGC2104_IRON

    SOC_VU190_FLGC2104_IRONWOOD

    U1

    AB11Y10MGTVCCAUX_RC_Y10

    MGTVCCAUX_RC_AB11

    XCVU190FLGC2104BANK MGTVCCAUX_RC

    SOC_FLGC2104_IRON

    SOC_VU190_FLGC2104_IRONWOOD

    U1

    L13J12MGTVCCAUX_RN_J12

    MGTVCCAUX_RN_L13

    XCVU190FLGC2104BANK MGTVCCAUX_RN

    SOC_FLGC2104_IRON

    SOC_VU190_FLGC2104_IRONWOOD

    U1

    AM10AK11MGTVCCAUX_RS_AK11

    MGTVCCAUX_RS_AM10

    XCVU190FLGC2104BANK MGTVCCAUX_RS

    SOC_FLGC2104_IRON

    SOC_VU190_FLGC2104_IRONWOOD

  • A

    B

    C

    D

    1234

    D

    C

    B

    A

    4 3 2 1

    SHEET SIZE: B

    SHEET OF

    VER:

    REV:

    DRAWN BY:

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    DATE: 1.0

    01

    BF

    09/21/2015:13:57

    PCB P/N: 1280790

    TEST P/N: TSS0174SCH P/N: 0381622

    ASSY P/N: 0431880

    9221

    FPGA Power 4SCHEM, ROHS COMPLIANTHW-U1-VCU110_REV1_0

    VCCINT_FPGA

    VCCINT_FPGA

    FPGA Power 4

    VCC1V8_FPGA

    VCCINT_FPGA

    U1

    AL27AL25AL23AL21AL19AL17AL15AK28AK26AK24AK22AK20AK18AK16AJ27AJ25AJ23AJ21AJ19AJ17AJ15AH28AH26AH24AH22AH20AH18AH16AG27AG25AG23AG21AG19AF28AF26AF24AF22AF20AF18AE27AE25AE23AE21AD28AD26AD24AD22AD18AC27AC25AC23AC21

    AB28AB26AB24AB22AB18AA27AA25AA23AA21AA19Y28Y26Y24Y22Y20Y18W29W27W25W23W21W19V28V26V24V22V20V18U29U27U25U23U21U19U17U15T28T26T24T22T20T18T16R29R27R25R23R21R19R17R15P28P26VCCINT_P26

    VCCINT_P28VCCINT_R15VCCINT_R17VCCINT_R19VCCINT_R21VCCINT_R23VCCINT_R25VCCINT_R27VCCINT_R29VCCINT_T16VCCINT_T18VCCINT_T20VCCINT_T22VCCINT_T24VCCINT_T26VCCINT_T28VCCINT_U15VCCINT_U17VCCINT_U19VCCINT_U21VCCINT_U23VCCINT_U25VCCINT_U27VCCINT_U29VCCINT_V18VCCINT_V20VCCINT_V22VCCINT_V24VCCINT_V26VCCINT_V28VCCINT_W19VCCINT_W21VCCINT_W23VCCINT_W25VCCINT_W27VCCINT_W29VCCINT_Y18VCCINT_Y20VCCINT_Y22VCCINT_Y24VCCINT_Y26VCCINT_Y28

    VCCINT_AA19VCCINT_AA21VCCINT_AA23VCCINT_AA25VCCINT_AA27VCCINT_AB18VCCINT_AB22VCCINT_AB24VCCINT_AB26VCCINT_AB28

    VCCINT_AC21VCCINT_AC23VCCINT_AC25VCCINT_AC27VCCINT_AD18VCCINT_AD22VCCINT_AD24VCCINT_AD26VCCINT_AD28VCCINT_AE21VCCINT_AE23VCCINT_AE25VCCINT_AE27VCCINT_AF18VCCINT_AF20VCCINT_AF22VCCINT_AF24VCCINT_AF26VCCINT_AF28VCCINT_AG19VCCINT_AG21VCCINT_AG23VCCINT_AG25VCCINT_AG27VCCINT_AH16VCCINT_AH18VCCINT_AH20VCCINT_AH22VCCINT_AH24VCCINT_AH26VCCINT_AH28VCCINT_AJ15VCCINT_AJ17VCCINT_AJ19VCCINT_AJ21VCCINT_AJ23VCCINT_AJ25VCCINT_AJ27VCCINT_AK16VCCINT_AK18VCCINT_AK20VCCINT_AK22VCCINT_AK24VCCINT_AK26VCCINT_AK28VCCINT_AL15VCCINT_AL17VCCINT_AL19VCCINT_AL21VCCINT_AL23VCCINT_AL25VCCINT_AL27

    XCVU190FLGC2104BANK VCCINT

    SOC_FLGC2104_IRON

    SOC_VU190_FLGC2104_IRONWOOD

    U1

    AL29AJ29AG29AE29AC29AA29V30T30P30VCCINT_IO_P30

    VCCINT_IO_T30VCCINT_IO_V30

    VCCINT_IO_AA29VCCINT_IO_AC29VCCINT_IO_AE29VCCINT_IO_AG29VCCINT_IO_AJ29VCCINT_IO_AL29

    XCVU190FLGC2104BANK VCCINT_IO

    SOC_FLGC2104_IRON

    SOC_VU190_FLGC2104_IRONWOOD

    U1

    AK32AH32AF32AE31AD32AC31AB32Y32V32T32P32VCCAUX_P32

    VCCAUX_T32VCCAUX_V32VCCAUX_Y32

    VCCAUX_AB32VCCAUX_AC31VCCAUX_AD32VCCAUX_AE31VCCAUX_AF32VCCAUX_AH32VCCAUX_AK32

    XCVU190FLGC2104BANK VCCAUX

    SOC_FLGC2104_IRON

    SOC_VU190_FLGC2104_IRONWOOD

    U1

    AL31AK30AJ31AH30AG31AF30AD30AB30AA31Y30W31U31R31VCCAUX_IO_R31

    VCCAUX_IO_U31VCCAUX_IO_W31VCCAUX_IO_Y30

    VCCAUX_IO_AA31VCCAUX_IO_AB30VCCAUX_IO_AD30VCCAUX_IO_AF30VCCAUX_IO_AG31VCCAUX_IO_AH30VCCAUX_IO_AJ31VCCAUX_IO_AK30VCCAUX_IO_AL31

    XCVU190FLGC2104BANK VCCAUX_IO

    SOC_FLGC2104_IRON

    SOC_VU190_FLGC2104_IRONWOOD

    U1

    AG17AE17AC17AA17Y16W17W15V16VCCBRAM_V16

    VCCBRAM_W15VCCBRAM_W17VCCBRAM_Y16

    VCCBRAM_AA17VCCBRAM_AC17VCCBRAM_AE17VCCBRAM_AG17

    XCVU190FLGC2104BANK VCCBRAM

    SOC_FLGC2104_IRON

    SOC_VU190_FLGC2104_IRONWOOD

    U1

    A39A38A9A8NC_A8

    NC_A9NC_A38NC_A39

    XCVU190FLGC2104NO CONNECTS

    SOC_FLGC2104_IRON

    SOC_VU190_FLGC2104_IRONWOOD

    VCCINT_FPGA

    VCC1V8_FPGA

    NCNCNCNC

  • A

    B

    C

    D

    1234

    D

    C

    B

    A

    4 3 2 1

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    DATE: 1.0

    01

    BF

    09/21/2015:13:57

    PCB P/N: 1280790

    TEST P/N: TSS0174SCH P/N: 0381622

    ASSY P/N: 0431880

    9222

    FPGA GND1SCHEM, ROHS COMPLIANTHW-U1-VCU110_REV1_0

    FPGA GND1

    GND

    GND

    GND

    GND

    U1

    N5

    N4

    N3

    M46

    M45

    M42

    M40

    M36

    M33

    M29

    M19

    M11

    M7

    M5

    M2

    M1

    L44

    L43

    L42

    L39

    L35

    L33

    L32

    L22

    L14

    L12

    L8

    L5

    L4

    L3

    K46

    K45

    K42

    K41

    K37

    K33

    K25

    K15

    K10

    K6

    K5

    K2

    K1

    J44

    J43

    J42

    J38

    J34

    J33

    J28

    J18

    J14

    J13

    J9

    J5

    J4

    J3

    H46

    H45

    H42

    H40

    H36

    H33

    H32

    H31

    H30

    H21

    H17

    H16

    H15

    H14

    H11

    H7

    H5

    H2

    H1

    G44

    G43

    G42

    G39

    G35

    G33

    G30

    G24

    G17

    G14

    G12

    G8

    G5

    G4

    G3

    F46

    F45

    F42

    F41

    F37

    F33

    F32

    F31

    F30

    F27

    F17

    F16

    F15

    F14

    F10

    F6

    F5

    F2

    F1

    E44

    E43

    E42

    E38

    E35

    E34

    E33

    E30

    E20

    E17

    E14

    E13

    E12

    E9

    E5

    E4

    E3

    D46

    D45

    D42

    D36

    D35

    D32

    D31

    D30

    D23

    D17

    D16

    D15

    D12

    D11

    D5

    D2

    D1

    C44

    C43

    C42

    C39

    C35

    C34

    C33

    C30

    C26

    C17

    C14

    C13

    C12

    C8

    C5

    C4

    C3

    B45

    B42

    B41

    B37

    B35

    B32

    B31

    B30

    B29

    B19

    B17

    B16

    B15

    B12

    B10

    B6

    B5

    B2

    A44

    A42

    A35

    A34

    A33

    A30

    A22

    A17

    A14

    A13

    A12

    A5

    A3

    GND_A3

    GND_A5

    GND_A12

    GND_A13

    GND_A14

    GND_A17

    GND_A22

    GND_A30

    GND_A33

    GND_A34

    GND_A35

    GND_A42

    GND_A44

    GND_B2

    GND_B5

    GND_B6

    GND_B10

    GND_B12

    GND_B15

    GND_B16

    GND_B17

    GND_B19

    GND_B29

    GND_B30

    GND_B31

    GND_B32

    GND_B35

    GND_B37

    GND_B41

    GND_B42

    GND_B45

    GND_C3

    GND_C4

    GND_C5

    GND_C8

    GND_C12

    GND_C13

    GND_C14

    GND_C17

    GND_C26

    GND_C30

    GND_C33

    GND_C34

    GND_C35

    GND_C39

    GND_C42

    GND_C43

    GND_C44

    GND_D1

    GND_D2

    GND_D5

    GND_D11

    GND_D12

    GND_D15

    GND_D16

    GND_D17

    GND_D23

    GND_D30

    GND_D31

    GND_D32

    GND_D35

    GND_D36

    GND_D42

    GND_D45

    GND_D46

    GND_E3

    GND_E4

    GND_E5

    GND_E9

    GND_E12

    GND_E13

    GND_E14

    GND_E17

    GND_E20

    GND_E30

    GND_E33

    GND_E34

    GND_E35

    GND_E38

    GND_E42

    GND_E43

    GND_E44

    GND_F1

    GND_F2

    GND_F5

    GND_F6

    GND_F10

    GND_F14

    GND_F15

    GND_F16

    GND_F17

    GND_F27

    GND_F30

    GND_F31

    GND_F32

    GND_F33

    GND_F37

    GND_F41

    GND_F42

    GND_F45

    GND_F46

    GND_G3

    GND_G4

    GND_G5

    GND_G8

    GND_G12

    GND_G14

    GND_G17

    GND_G24

    GND_G30

    GND_G33

    GND_G35

    GND_G39

    GND_G42

    GND_G43

    GND_G44

    GND_H1

    GND_H2

    GND_H5

    GND_H7

    GND_H11

    GND_H14

    GND_H15

    GND_H16

    GND_H17

    GND_H21

    GND_H30

    GND_H31

    GND_H32

    GND_H33

    GND_H36

    GND_H40

    GND_H42

    GND_H45

    GND_H46

    GND_J3

    GND_J4

    GND_J5

    GND_J9

    GND_J13

    GND_J14

    GND_J18

    GND_J28

    GND_J33

    GND_J34

    GND_J38

    GND_J42

    GND_J43

    GND_J44

    GND_K1

    GND_K2

    GND_K5

    GND_K6

    GND_K10

    GND_K15

    GND_K25

    GND_K33

    GND_K37

    GND_K41

    GND_K42

    GND_K45

    GND_K46

    GND_L3

    GND_L4

    GND_L5

    GND_L8

    GND_L12

    GND_L14

    GND_L22

    GND_L32

    GND_L33

    GND_L35

    GND_L39

    GND_L42

    GND_L43

    GND_L44

    GND_M1

    GND_M2

    GND_M5

    GND_M7

    GND_M11

    GND_M19

    GND_M29

    GND_M33

    GND_M36

    GND_M40

    GND_M42

    GND_M45

    GND_M46

    GND_N3

    GND_N4

    GND_N5

    XCVU190FLGC2104

    BANK GND1

    SOC_FLGC2104_IRON

    SOC_VU190_FLGC2104_IRONWOOD

    U1

    AC5

    AC4

    AC3

    AB46

    AB45

    AB42

    AB41

    AB37

    AB33

    AB31

    AB29

    AB27

    AB25

    AB23

    AB21

    AB17

    AB10

    AB6

    AB5

    AB2

    AB1

    AA44

    AA43

    AA42

    AA38

    AA34

    AA33

    AA32

    AA30

    AA28

    AA26

    AA24

    AA22

    AA20

    AA18

    AA16

    AA15

    AA14

    AA13

    AA9

    AA5

    AA4

    AA3

    Y46

    Y45

    Y42

    Y40

    Y36

    Y33

    Y31

    Y29

    Y27

    Y25

    Y23

    Y21

    Y19

    Y17

    Y15

    Y11Y7Y5Y2Y1

    W44

    W43

    W42

    W39

    W35

    W33

    W32

    W30

    W28

    W26

    W24

    W22

    W20

    W18

    W16

    W14

    W12W8W5W4W3

    V46

    V45

    V42

    V41

    V37

    V33

    V31

    V29

    V27

    V25

    V23

    V21

    V19

    V17

    V15

    V10

    V6

    V5

    V2

    V1

    U44

    U43

    U42

    U38

    U34

    U33

    U32

    U30

    U28

    U26

    U24

    U22

    U20

    U18

    U16

    U14

    U13

    U9

    U5

    U4

    U3

    T46

    T45

    T42

    T40

    T36

    T33

    T31

    T29

    T27

    T25

    T23

    T21

    T19

    T17

    T15

    T11

    T7

    T5

    T2

    T1

    R44

    R43

    R42

    R39

    R35

    R33

    R32

    R30

    R28

    R26

    R24

    R22

    R20

    R18

    R16

    R14

    R12

    R8

    R5

    R4

    R3

    P46

    P45

    P42

    P41

    P37

    P33

    P31

    P29

    P23

    P10

    P6

    P5

    P2

    P1

    N44

    N43

    N42

    N38

    N34

    N33

    N26

    N16

    N14

    N13

    N9

    GND_N9

    GND_N13

    GND_N14

    GND_N16

    GND_N26

    GND_N33

    GND_N34

    GND_N38

    GND_N42

    GND_N43

    GND_N44

    GND_P1

    GND_P2

    GND_P5

    GND_P6

    GND_P10

    GND_P23

    GND_P29

    GND_P31

    GND_P33

    GND_P37

    GND_P41

    GND_P42

    GND_P45

    GND_P46

    GND_R3

    GND_R4

    GND_R5

    GND_R8

    GND_R12

    GND_R14

    GND_R16

    GND_R18

    GND_R20

    GND_R22

    GND_R24

    GND_R26

    GND_R28

    GND_R30

    GND_R32

    GND_R33

    GND_R35

    GND_R39

    GND_R42

    GND_R43

    GND_R44

    GND_T1

    GND_T2

    GND_T5

    GND_T7

    GND_T11

    GND_T15

    GND_T17

    GND_T19

    GND_T21

    GND_T23

    GND_T25

    GND_T27

    GND_T29

    GND_T31

    GND_T33

    GND_T36

    GND_T40

    GND_T42

    GND_T45

    GND_T46

    GND_U3

    GND_U4

    GND_U5

    GND_U9

    GND_U13

    GND_U14

    GND_U16

    GND_U18

    GND_U20

    GND_U22

    GND_U24

    GND_U26

    GND_U28

    GND_U30

    GND_U32

    GND_U33

    GND_U34

    GND_U38

    GND_U42

    GND_U43

    GND_U44

    GND_V1

    GND_V2

    GND_V5

    GND_V6

    GND_V10

    GND_V15

    GND_V17

    GND_V19

    GND_V21

    GND_V23

    GND_V25

    GND_V27

    GND_V29

    GND_V31

    GND_V33

    GND_V37

    GND_V41

    GND_V42

    GND_V45

    GND_V46

    GND_W3

    GND_W4

    GND_W5

    GND_W8

    GND_W12

    GND_W14

    GND_W16

    GND_W18

    GND_W20

    GND_W22

    GND_W24

    GND_W26

    GND_W28

    GND_W30

    GND_W32

    GND_W33

    GND_W35

    GND_W39

    GND_W42

    GND_W43

    GND_W44

    GND_Y1

    GND_Y2

    GND_Y5

    GND_Y7

    GND_Y11

    GND_Y15

    GND_Y17

    GND_Y19

    GND_Y21

    GND_Y23

    GND_Y25

    GND_Y27

    GND_Y29

    GND_Y31

    GND_Y33

    GND_Y36

    GND_Y40

    GND_Y42

    GND_Y45

    GND_Y46

    GND_AA3

    GND_AA4

    GND_AA5

    GND_AA9

    GND_AA13

    GND_AA14

    GND_AA15

    GND_AA16

    GND_AA18

    GND_AA20

    GND_AA22

    GND_AA24

    GND_AA26

    GND_AA28

    GND_AA30

    GND_AA32

    GND_AA33

    GND_AA34

    GND_AA38

    GND_AA42

    GND_AA43

    GND_AA44

    GND_AB1

    GND_AB2

    GND_AB5

    GND_AB6

    GND_AB10

    GND_AB17

    GND_AB21

    GND_AB23

    GND_AB25

    GND_AB27

    GND_AB29

    GND_AB31

    GND_AB33

    GND_AB37

    GND_AB41

    GND_AB42

    GND_AB45

    GND_AB46

    GND_AC3

    GND_AC4

    GND_AC5

    XCVU190FLGC2104

    BANK GND2

    SOC_FLGC2104_IRON

    SOC_VU190_FLGC2104_IRONWOOD

  • A

    B

    C

    D

    1234

    D

    C

    B

    A

    4 3 2 1

    SHEET SIZE: B

    SHEET OF

    VER:

    REV:

    DRAWN BY:

    TITLE:

    DATE: 1.0

    01

    BF

    09/21/2015:13:58

    PCB P/N: 1280790

    TEST P/N: TSS0174SCH P/N: 0381622

    ASSY P/N: 0431880

    9223

    FPGA GND2SCHEM, ROHS COMPLIANTHW-U1-VCU110_REV1_0

    FPGA GND2

    U1

    AN5

    AN4

    AN3

    AM46

    AM45

    AM42

    AM40

    AM36

    AM33

    AM25

    AM15

    AM11

    AM7

    AM5

    AM2

    AM1

    AL44

    AL43

    AL42

    AL39

    AL35

    AL33

    AL32

    AL30

    AL28

    AL26

    AL24

    AL22

    AL20

    AL18

    AL16

    AL14

    AL12

    AL8

    AL5

    AL4

    AL3

    AK46

    AK45

    AK42

    AK41

    AK37

    AK33

    AK31

    AK29

    AK27

    AK25

    AK23

    AK21

    AK19

    AK17

    AK15

    AK10

    AK6

    AK5

    AK2

    AK1

    AJ44

    AJ43

    AJ42

    AJ38

    AJ34

    AJ33

    AJ32

    AJ30

    AJ28

    AJ26

    AJ24

    AJ22

    AJ20

    AJ18

    AJ16

    AJ14

    AJ13

    AJ9

    AJ5

    AJ4

    AJ3

    AH46

    AH45

    AH42

    AH36

    AH33

    AH31

    AH29

    AH27

    AH25

    AH23

    AH21

    AH19

    AH17

    AH15

    AH11

    AH5

    AH2

    AH1

    AG44

    AG43

    AG42

    AG39

    AG35

    AG33

    AG32

    AG30

    AG28

    AG26

    AG24

    AG22

    AG20

    AG18

    AG16

    AG15

    AG14

    AG12

    AG8

    AG5

    AG4

    AG3

    AF46

    AF45

    AF42

    AF41

    AF37

    AF33

    AF31

    AF29

    AF27

    AF25

    AF23

    AF21

    AF19

    AF17

    AF10

    AF6

    AF5

    AF2

    AF1

    AE44

    AE43

    AE42

    AE38

    AE34

    AE33


DNP Introduction

DNP Introduction

Corey R. Peterson DNP, CRNA, Lisa Stephens, DNP, CRNA,

Corey R. Peterson DNP, CRNA, Lisa Stephens, DNP, CRNA,

bahan Influetion dnp

bahan Influetion dnp

Post BSN DNP and Post MSN DNP Programs Making the Recommendations Real 

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Validation Dnp

Validation Dnp

atribut DNP

atribut DNP

Bond Decorate - DNP

Bond Decorate - DNP

2014 DNP Synthesis Project Guidelines - Troy Universitytrojan.troy.edu/.../DNP-Synthesis-Project-Guidelines.pdf · 2016-08-11 · 2014 DNP Synthesis Project Guidelines ... One essential

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Prasan Vidya Mandir, Chengalpattu Domain - Boole(Qualifier 1)...72 Revathi 3 (B) DNP 73 Kripali 3 (B) DNP 74 Keshav 3 (B) DNP 75 Kamaleshvar.r.s 3 (B) DNP 76 Hemeshwaran 3 (B) DNP

Prasan Vidya Mandir, Chengalpattu Domain - Boole(Qualifier 1)...72 Revathi 3 (B) DNP 73 Kripali 3 (B) DNP 74 Keshav 3 (B) DNP 75 Kamaleshvar.r.s 3 (B) DNP 76 Hemeshwaran 3 (B) DNP

VCU110 Evaluation Board User Guide - Xilinx · VCU110 Evaluation Board 7 UG1073 (v1.5) April 19, 2019 Chapter 1: VCU110 Evaluation Board Features ° SMA user clock connector pair

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Help Wanted: The DNP in Mainstream Practice › ... › conferences › dnp › presentations › … · HELP WANTED: THE DNP IN MAINSTREAM PRACTICE Mary Jo Assi, DNP, RN, NEA-BC,

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Dnp Original

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The State of the DNP: Analysis of Four Years of Data 6 th National DNP Conference September 25-27, 2013 David G. O’Dell, DNP Karen Crowley, DNP.

The State of the DNP: Analysis of Four Years of Data 6 th National DNP Conference September 25-27, 2013 David G. O’Dell, DNP Karen Crowley, DNP.

Dnp shelco she culture and behavior in dnp sept 2011

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DNP pROJECT gUIDELINES CON DNP Project...2. Attend the final DNP Project Presentation. 3. Complete final DNP Project paper and presentation grading rubrics. Disseminate DNP Project:

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DNP - Daum

DNP - Daum

System Monitor System Ace Single Ended Differential SMA ... · in out gnd vcco_0 vcco_0 vcco_2 vcc33 vcco_0 vcc1v8 vcc1v8 vcco_0 du7_nc du6_nc du4_nc du5_nc du3_nc du2_nc du0_nc du1_nc

System Monitor System Ace Single Ended Differential SMA ... · in out gnd vcco_0 vcco_0 vcco_2 vcc33 vcco_0 vcc1v8 vcc1v8 vcco_0 du7_nc du6_nc du4_nc du5_nc du3_nc du2_nc du0_nc du1_nc

Dnp enterprise

Dnp enterprise

_PM296-RPM096 DNP

_PM296-RPM096 DNP

DNP Final Project

DNP Final Project