Variation Aware Gate Delay Models

Dinesh Ganesan

• Motivation

• Background

• Finite Point Model for gates

• Results

• Future work

OutlineOutline

MotivationVariability is an emerging design concern

Design tools are just beginning to address variability and reliability concerns

Right combination of better modeling and regular IC fabrics is the best way to resolve IC variability challenges

Background

Physical models• Based on physics of devices• Accurate• Very slow considering the number of transistors in today's design• Eg - TCAD

Empirical models • Device modeled with equations in various regions of operation. • Good accuracy• Slow for chip level simulations• Eg - BSIM3-the current industry standard, PSP, Gummel-Poon, Ebers Moll

Table model • Stored as lookup tables• Does not scale with change in circuit topology• Requires other models for characterization

BSIM

• Given voltages at ports calculates the current/capacitance between the ports

• Model them using equations with physical meaning

• Parameter values obtained from the foundry/fab

• Parameters grow exponentially in today's technology to address the emerging second order effects

Circuit Simulation

• Circuit simulators like SPICE (Simulation Program with Integrated Circuit Emphasis) – a general purpose analog circuit simulator.

• Solve nonlinear equations iteratively• Nodal analysis using Newton Raphson/Secant iteration

for convergence• Use model file like BSIM for obtaining the

voltage/current• Use of BSIM models for complete chip simulation takes

months• Faster models of simulation required

Variations

• As transistor geometry decreases control of device parameters becomes difficult

• Shift from Static timing analysis to Statistical timing analysis

• Device model should be robust to process variations

130nm and above

SSTA

90nm and below

Requirement

• Fast simulation (including Monte Carlo)

• Accurate

• Model device

• Robust to process variations

Current Source Model

Vo

PDN

PUN

Vi1

Vin

Qi_i(Vi,Vo) Idc(Vi,Vo)

io

`

Qi_o(Vi,Vo)

Qo_i(Vi,Vo)

Qo_o(Vi,Vo)

ii

Q

Q

Q Q

Vi Vo

Idc(Vi,Vo) – Current source

Qx_y – Charge at x when y switches

i – input

o - output

Gate Model

Idc – current captures static characteristics

Q – charge – captures the dynamic characteristics

Idc(Vi,Vo)

• Static I-V characteristics of a gate• Obtained using finite point model for pull-up (PUN) and

pull down network (PDN) separately• Gate Idc(Vi,Vo) = PDN Idc(Vi,Vo) + PUN Idc(Vi,Vo)

Qi_i(Vi,Vo) Idc(Vi,Vo)

io

`

Qi_o(Vi,Vo)

Qo_i(Vi,Vo)

Qo_o(Vi,Vo)

ii

Q

Q

Q Q

Vi Vo

Idc(Vi,Vo) – PUN/PDN

• Method similar to finite point model of transistor used, except that Id-Vi is nonlinear in this case

• Two points for Id-Vo and five points for Id-Vi are sufficient to generate the complete IV

• Points obtained by single DC simulation

• Process variations – included in the IV

• Continuous model in all regions required – continuous model for Idc-Vi

Qi_i(Vi,Vo) Idc(Vi,Vo)

io

`

Qi_o(Vi,Vo)

Qo_i(Vi,Vo)

Qo_o(Vi,Vo)

ii

Q

Q

Q Q

Vi Vo

-0.1 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1-10.0µ

0.0

10.0µ

20.0µ

30.0µ

40.0µ

50.0µ

60.0µ

70.0µ

80.0µ

Io

Vi

Vo=Vdd

0.0 0.2 0.4 0.6 0.8 1.0-10.0µ

0.0

10.0µ

20.0µ

30.0µ

40.0µ

50.0µ

60.0µ

70.0µ

80.0µ

Vi

Io

Vo

Points required for the finite point model

Idc - Vo

Idc - Vi

Idc(Vi,Vo)

Qi_i(Vi,Vo) Idc(Vi,Vo)

io

`

Qi_o(Vi,Vo)

Qo_i(Vi,Vo)

Qo_o(Vi,Vo)

ii

Q

Q

Q Q

Vi Vo

0.0 0.2 0.4 0.6 0.8 1.0-80.0µ

-60.0µ

-40.0µ

-20.0µ

0.0

20.0µ

40.0µ

60.0µ

80.0µ

100.0µ

120.0µ

Vout

Iou

t

Vin

SPICE Model

Simulation results for NAND2

Vout

Vin

Q(Vi,Vo)

• Calculate charge at input and output node based on switching at the nodes

• Requires two transient simulations• Charge calculated by monitoring the current at the nodes

during the simulation

Qi_i(Vi,Vo) Idc(Vi,Vo)

io

`

Qi_o(Vi,Vo)

Qo_i(Vi,Vo)

Qo_o(Vi,Vo)

ii

Q

Q

Q Q

Vi Vo

Q(Vi,Vo)

Qi_i(Vi,Vo) Idc(Vi,Vo)

io

`

Qi_o(Vi,Vo)

Qo_i(Vi,Vo)

Qo_o(Vi,Vo)

ii

Q

Q

Q Q

Vi Vo

Calculation of Qo_i & Qi_i

VoPDN

PUN

Vi

t0 t1

Vi

1

0

1

0

..),(_t

t

t

t

dtIdcdtioVoViiQo

Transient simulation

Idc model

1

0

.),(_t

t

dtiiVoViiQi

Repeated for all values of Vi and Vo

Q(Vi,Vo)

Qi_i(Vi,Vo) Idc(Vi,Vo)

io

`

Qi_o(Vi,Vo)

Qo_i(Vi,Vo)

Qo_o(Vi,Vo)

ii

Q

Q

Q Q

Vi Vo

Qo_i calculated from SPICE Idc

Qo_i calculated from Idc model

Qi_i

Q(Vi,Vo)

Qi_i(Vi,Vo) Idc(Vi,Vo)

io

`

Qi_o(Vi,Vo)

Qo_i(Vi,Vo)

Qo_o(Vi,Vo)

ii

Q

Q

Q Q

Vi Vo

Calculation of Qo_o & Qi_o

VoPDN

PUN

Vi

t0 t1

Vo

1

0

1

0

..),(_t

t

t

t

dtIdcdtioVoVioQo

Transient simulation

Idc model

1

0

.),(_t

t

dtiiVoVioQi

Repeated for all values of Vi and Vo

Q(Vi,Vo)

Qi_i(Vi,Vo) Idc(Vi,Vo)

io

`

Qi_o(Vi,Vo)

Qo_i(Vi,Vo)

Qo_o(Vi,Vo)

ii

Q

Q

Q Q

Vi Vo

Qo_o calculated from Idc model

Qi_o

Qo_i calculated from Idc model Qi_i

Q(Vi,Vo) - approximation

Qi_i(Vi,Vo) Idc(Vi,Vo)

io

`

Qi_o(Vi,Vo)

Qo_i(Vi,Vo)

Qo_o(Vi,Vo)

ii

Q

Q

Q Q

Vi Vo

Qo_o -Actual Qo_o -approximated Qo_o -error

Qo_i -Actual Qo_i -approximated Qo_i -error

Charge implementation in VerilogA

Qi_i(Vi,Vo) Idc(Vi,Vo)

io

`

Qi_o(Vi,Vo)

Qo_i(Vi,Vo)

Qo_o(Vi,Vo)

ii

Q

Q

Q Q

Vi Vo

tin tout

gr

Vin = V(tin,gr);

Vout = V(tout,gr);

Qi_i = f1(Vin,Vout);

Qi_o = f2(Vin,Vout);

Qo_i = f3(Vin,Vout);

Qo_o = f4(Vin,Vout);

I(tin,gr) <+ ddt(Qi_is);I(tout,gr) <+ ddt(Qo_os);I(tin,tout) <+ ddt(Qo_is);I(tout,tin) <+ ddt(Qi_os);

Qi_i(Vi,Vo)

io

`

Qi_o(Vi,Vo)

Qo_i(Vi,Vo)

Qo_o(Vi,Vo)

ii

Q

Q

Q Q

Vi Vo

tin tout

gr

Gate charge

Results

0.0 1.0n 2.0n 3.0n 4.0n

300.0p

350.0p

400.0p

450.0p

500.0p

550.0p

Ou

tpu

t Sle

wInput Slew

SPICE CSM

0.0 1.0n 2.0n 3.0n 4.0n

350.0p

400.0p

450.0p

500.0p

550.0p

600.0p

650.0p

700.0p

750.0p

De

lay

Input Slew

SPICE CSM

Delay vs Input slewOutput slew vs Input slew

Results

500.0p 1.0n 1.5n 2.0n 2.5n 3.0n 3.5n 4.0n

0.0

0.2

0.4

0.6

0.8

1.0

Ou

tpu

t Vo

ltag

e

Time

SPICE CSM

500.0p 1.0n 1.5n 2.0n 2.5n 3.0n 3.5n 4.0n

-50.0µ

-40.0µ

-30.0µ

-20.0µ

-10.0µ

0.0

Ou

tpu

t Cu

rre

nt

Time

SPICE CSM

Output voltage vs time Output current vs time

Advantages

• Fast simulation

• Accurate analysis

• Process variations included with ease

• Helps in fast Monte Carlo analysis

Questions???