Variability Analysis and Modeling of the Crosstalk Delay on the Low-Swing Signaling Scheme Using DoE...

8/11/2019 Variability Analysis and Modeling of the Crosstalk Delay on the Low-Swing Signaling Scheme Using DoE Approach

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Variability Analysis and Modeling of the Crosstalk

Delay on the Low-Swing Signaling Scheme using

DoE approach

Nor Muzlifah Mahyuddin

School of Electrical and Electronic Engineering

Universiti Sains Malaysia

Engineering Campus, Nibong Tebal

14300 Penang, [email protected]

Gordon Russell

Dept. of Electrical, Electronic and Computer Engineering

Newcastle UniversityNewcastle-upon-Tyne

NE1 7RU United Kingdom

[email protected]

AbstractThrough aggressive technology scaling, the continuous

demands of devices with interconnect functionality/unit area

have been satisfied but with adversely negative impact on theinterconnect delay. This trend also has made reliability a huge

challenge for the designers. This reliability comes in the form of

process variation which can have significant impact on the

interconnect delay, specifically the crosstalk delay. A statistical

analysis using a Design-of-Experiment method was carried out to

create models which can represent the effect of process variation

on the crosstalk delay; highlighting on the most significant

parameter variations, which are Vdd and wire parameters and

methods to reduce the crosstalk effects.

Keywords-low-swing; design-of-experiment; variability;

crosstalk delay; crosstalk capacitance

I. INTRODUCTION

Technology scaling has always been an important issue formicroprocessor especially in deep submicron regime. Besidesfrom the aggravating effect of the market demands forincreased functionality per unit area on the interconnect delay,there are two other significant performance impacts resultingfrom this, i.e. the variability and the crosstalk effect.

The variations in process and design parameters havesignificantly increased due to the rapid scaling of CMOStechnology which leads to severe variability in circuit

performance and functionality in the nano-metre regime [1].As device sizes continue to scale down into the deepsubmicron regime, manufacturing tools are less reliable intheir control of design parameters. Process variation usuallyarises from limitations imposed by the layers of physics,imperfect tools and properties of materials that are not fullyunderstood [2].

Subsequently, as the feature sizes have been shrinking withprocess technology scaling, the spacing between adjacentinterconnect lines keeps decreasing in every process node.While the lateral width of interconnect wires has been scaleddown significantly, their vertical height has not been scaled in

proportion, which leads to a very rapid increase in the amountof coupling capacitance between the wires. More aggressivetechnology scaling will lead to an increase in the overall

contribution of the coupling capacitances to the totalinterconnects capacitance. Subsequently, as technology

advances, there will be an increase in chip frequency anddecreases in voltage margin, which will exacerbate the impactof crosstalk noise on interconnect delay. All the above trendsconsolidate the needs to include crosstalk effect in thereliability analysis of VLSI circuits.

This paper will discuss on the impact of parametervariations on the crosstalk delay using Design-of-Experiment(DoE) approach where relationships between the parametervariations as well as to the crosstalk delay will be identified.The interconnect scheme to be analysed is the mLVSD schemewhere the preliminary analysis in [3,4] indicated that thisscheme has the best attributes among the low-swing signallingschemes. Section II begins with the method flow for variability

analysis using the DoE method. This method flow can also beimplemented on other low-swing signalling scheme or on theimpact of variability on the crosstalk noise. This is followed bythe analysis and modelling of crosstalk delay on the mLVSDscheme where the most significant parameters will beidentified.

II. WORK FLOW FOR VARIABILITY ANALYSIS

IMPLEMETING DOEMETHOD

The work flow for the variability analysis used in this paperis summarised below:

A. Modeling the parasitic elements of the circuit

The interconnection between driver and receiver in the

signalling scheme is implemented using top layer metal to berealised using UMC 90nm technology. A three-wire signallingarrangement with crosstalk effects is set up for the experimentas shown in Fig.1. The parallel line structures are placed

between two grounded shields. The resistive and capacitiveparasitic elements of the interconnect are calculated using thefollowing equations.

Cwire is the parasitic capacitance, which is a very strongfunction of the geometry. For the configuration of a conductorsurrounded by two adjacent wires as shown in Fig.2, Sakuraiin [5] defines a coupling capacitance as follows


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(1)

(2)

(3)

where kis dielectric permittivity, h is dielectric height and s isseparation between two wires. Cwiredefines a total capacitancefor the middle conductor as the sum of Cg and 2Ccassumingthat there is no signal transition on the two adjacent wires.

Figure 1. Circuit structure for variability analysis on crosstalkeffects

Figure 2. Cross-section of wire capacitance [6]

The resistance can be obtained through [6]

(4)

where is the metal resistivity, le is the interconnect length,while w and t, are the interconnect width and thicknessrespectively. The interconnect model for this work iscalculated to comprise a 567.9 resistor and a 2.2356pFcapacitor to represent an interconnect length of 10mm usingnominal values of interconnect parameters recorded in Table Iat 90nm technology. The wire capacitance is calculated using

the equations given with Cg= 0.307pF and Cc= 0.964pF. Anextra load capacitance, Cl of 0.25pF per mm length ofinterconnect is also distributed along the wire to represent thefan-out.

B. Identify sources of variation

In this work, Plackett-Burman design was carried out on 31device and interconnect parameters associated with the low-swing driver schemes. Through Plackett-Burman screening themain effects or factors has been reduced to 12 as listed in TableII with their 3 variations, these values are in agreement withthose used previously [6].

The device parameters include the threshold voltage, Vtho,gate-oxide thickness, tox and other parameters such as carriermobility, o and effective gate length, Leff, whilst theinterconnect parameters are as mentioned previously.Environmental factors such as Vdd and temperature are alsoincluded in the variability analysis.

TABLE I. NOMINAL VALUES OF INTERCONNECT PARAMETERS

Parameters Nominal values

Interconnect width, w 0.56m

Interconnect thickness, t 0.81m

Interlayer Dielectric height, h 0.94m

Metal resistivity, 21.8n.m

Dielectric permittivity, k 3.25

TABLE II. PARAMETER VALUES AND 3SIGMA VARIATIONS

Technology 90nm

Device

parameters 3

Interconnect

parameters 3Vth 30% k 3%

tox 10% 30%

Leff 16.7% s 20%

o 10% w 20%

Vdd 10% t 10%

Temp (12-70)C h 10%

C. Design of the statistical experiment

DoE techniques are employed in the variability analysis ofthe mLVSD driver scheme in order to build a first order

polynomial approximation for the first set of experiment and asecond order polynomial approximation for the design metric

of interest which is the crosstalk delay. For the 12 inputparameters used for this analysis, DoE technique used hererequires 154 experiments.

D. Record circuit response at each design point

In order to obtain the circuit response for each design point,simulations are carried out using the circuit analyzer(SPECTRE) in Cadence Virtuoso Analog Design Environment.The crosstalk delay were measured and calculated in eachexperiment.

E. Generate polynomial approximations for the circuit

output

The polynomial approximations are obtained through

statistical software called Minitab. The coded polynomialapproximation is used. The input factors in the codedapproximation have normalized values of (-1, 0, +1) whichrepresent (-3, 0, +3), where and are mean andstandard deviations of the input parameters to be tested.

The following sections outline the results obtained from themethodologies used, to analyse the impact of variability on thecrosstalk delay of the mLVSD driver. Design models for thedriver scheme are also discussed for each set of experiments.


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III. ANALYSIS AND MODELING OF CROSSTALK DELAY ON

THE MLVSDDRIVER SCHEME

For simplicity, in the following analysis, 8 sources ofvariations were considered, namely, Vdd, temperature, Vth, Leff, and wire (w, t, h). The wire width and spacing are assumed to

be negatively correlated, letting wbe the independent variable.The same goes for Vth as it is used instead to represent bothVthoand tox. The variables were listed previously in Table 5.4with their 3variations. The wire width used in this analysis isthe minimum wire width in 90nm technology.

Figure 5.13 shows the interconnect structure used in theanalysis of the impact of process variation on crosstalk effects.The DoE method outlined previously is used in this analysis to

build a linear model based on the model in [7]. In this instancethe linear model of the delay of the middle (victim) line inFig.1 is given by

(5)

where x is a variation parameter, which in this case are Vdd,

Temp, Leff, Vth, , w, t and h, and is a regression coefficient.

There are several design methods that can be implementedin mitigating the problems associated with crosstalk delay.The same methods are also considered in the variabilityanalysis of crosstalk delay, namely, buffer insertion andincreased wire spacing. Subsequently, general models for a10mm interconnect were generated for the following cases:minimally spaced wire (s = wmin) with no buffers, minimallyspaced wire with 3 buffers and 3 times minimally spacedwires (s = 3wmin) with no buffers. The accuracy of thesemodels was validated using R

2fits analysis, which was found

to be above 99% for all considered cases. R-squared (R2) is

percentage of response variable variation, which is alwaysbetween 0% and 100%. In general, the higher the R

2, the

better the model fits the data.Similar models are also generated for each crosstalk cases

as shown in Table III indicating effective crosstalkcapacitances for different crosstalk cases. Notes that , and imply 0-to-1, 1-to-0 and no transitions respectively.

TABLE III. EFFECTIVE CROSSTALK CAPACITANCE FOR DIFFERENTCROSSTALK CASES [8]

Crosstalk case Transitions

Effective

Coupling

Capacitance

1 , 0

2,

,1

3

,

, ,

2

4,

, 3

5 , 4

As expected, delay sensitivity to variation parametersincreases from Crosstalk Case 2 to 5 due to the increase in

effective crosstalk capacitance. in Fig.3 represents

delay sensitivity over the variation parameters, where theresults were obtained through Minitab. From Fig.3(a), theresults indicate that both Vdd and have the highest impact on

crosstalk delay variations as both of these parameters have themost significant association with delay. Delay is linearlydependent on the wire resistance as well as being negativelycorrelated to Vdd. Subsequently this result also shows thatdelay sensitivity to wire parameter variations has a very highdata dependency due to the changes in the effective crosstalkcapacitance for each different case. This dependency can bereduced by incorporating 3 buffers on the interconnects, by thesignificant decrease in delay sensitivity to wire parametervariations. By increasing the wire spacing, the dependency ofdelay sensitivity on wire parameters can also be reduced butnot as much as using the buffer insertion method as shown inFig.3(c); however, this method can be used to reduce the delaysensitivity to device parameters. This is because by increasing

the wire spacing, contributing to the decrease in delay byreducing the wire capacitance without affecting its resistance,which causes the contribution of the driver circuitry to theoverall delay to be reduced.

(a) (b) (c)

Figure 3. Delay sensitivity to variability of (a) a minimally spaced wire with no buffer, (b) a minimally spaced wire with 3 buffers

and (c) a 3 times minimally spaced wire with no buffer,


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In addition to the first order model generated, a secondorder model of the crosstalk delay can also be generated. Thismodel comprises interaction and quadratic effects between

parametric variations, where its polynomial approximation isbased on

(6)

wherex is a variation parameter, which in this case are Vdd,

Temp, Leff, Vth, , w, t and h, and is a regressioncoefficient, whilst the three added terms, namely ,

and . The results obtained though Minitab for the non-

linear model are presented in Fig.4 where and

represent the quadratic effect of the parameter whilstrepresents interaction effect.

A comparison between second order and linear coefficientsfrom Fig.3 indicates that the linear coefficients are more

significant. Subsequently most of the non-linear effects can beignored as they have very little impact on the model accuracy.However, as can be seen in Fig.4(a) the quadratic effect of Vthis relatively large representing the only significant parameterfrom the device parameter variations while from theinterconnect parameters, the quadratic effects of wire widthand dielectric thickness are found to be significantly large.This is because of the dependency of voltage swing on Vth,

which can affect the delay significantly, and the quadraticeffects of w and h contribute to the changes in effectivecrosstalk capacitance, hence deviations in crosstalk delay.Additionally, the interaction between Vdd and alsocontribute to the large coefficients for delay sensitivity. FromFig.3(a), both Vdd and are the most significant parameters toaffect delay sensitivity, thus their interaction will have largeimpact on the delay sensitivity.

(a) (b) (c)

Figure 4. The results show the interaction and quadratic coefficients of (a) device and environmental parameter variations and

(b) wire parameter variations; and interaction coefficients of (c) wire and environmental parameter variations.

IV. CONCLUSIONS

An analysis was carried out to investigate the impact ofvariability on crosstalk effects of the low-swing signallingschemes. Both first and second order models were generatedfor crosstalk delay. The results indicated that the delaysensitivities have a high data dependency towards Vdd andwire parameter variations. This dependency can be reducedthrough buffer insertion and wire spacing with the lattermethod being the most effective difference in delay. Resultsfrom the second order model indicated that most of the non-linear effects can be ignored as they are insignificant to

provide an impact on the model accuracy. However, a fewcoefficients such as the quadratic effects of Vth, w and h andthe interaction between Vddand should be considered as theycan be regarded as significant to the crosstalk delay sensitivitycompared to the linear coefficients. Statistical models whichrepresent the crosstalk delay with the interactions of thesignificant parameter variations were developed which can beincorporated into any low-swing signalling scheme to find the

best results in reducing the crosstalk delay in the variabilityenvironment.

REFERENCES

[1] K.A. Bowman, S.G. Duvall, and J.D. Meindl, Impact of die-to-die andwithin-die parameter fluctuations on the maximum clock frequencydistribution for gigascale integration, IEEE Journal of Solid-StateCircuits, vol. 37, 2002, pp. 183-190.

[2] S. Borkar, T. Karnik, S. Narendra, J. Tschanz, A. Keshavarzi, and V.De, Parameter variations and impact on circuits and microarchitecture,Proceedings of the 40th annual Design Automation Conference,Anaheim, CA, USA: ACM, 2003, pp. 338-342.

[3] N. M. Mahyuddin, A Novel Low Swing Voltage Driver Design and theAnalysis of its Robustness to the Effects of Process Variation andExternal Disturbances, Newcastle University, 2011.

[4] N. M. Mahyuddin, G. Russell, and E. G. Chester, Power and

Performance Analysis of Low-Swing Driver Scheme for Onchip GlobalInterconnects, Proceedings of National Conference on Electrical andElectronic Engineering, NCEEE 2012, pp. 114-119, 2012.

[5] K.T. T. Sakurai, Simple formulas for 2 and 3 -D capacitances, IEEETrans. Electron Devices, vol. 30, 1983, pp. 183-185.

[6] B.P. Wong Mittal Anurag, Cao, Y., Starr, G., Nano-CMOS circuit andphysical design, John Wiley & Sons, 2005.

[7] D.C. Montgomery,Design and Analysis of Experiments, Wiley, 2005.

[8] N.H.E. Weste Harris, D., CMOS VLSI Design: A Circuit and SystemsPerspective, 2005.

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