Vacuum tubes Transistor 1948 –Smaller, Cheaper, Less heat dissipation, Made from Silicon (Sand)...

• Vacuum tubes

• Transistor 1948– Smaller, Cheaper, Less heat dissipation, Made from Silicon (Sand)

– Invented at Bell Labs

– Shockley, Brittain, Bardeen

• ICs 1960s

• Microprocessors 1970s

• ENIAC ( Electronic Numerical Integrator And

Computer) was one of the first machines whhich can be considerd as a digital computer, (1946).

5.5 m

24 m

18,000 vacuum tupes.

30 tons.

6 m

200,000 man-hours

• The problem is not only in size, cost …

• The problem is that whenever you want to program it you need to re-wiring & setting many switches.

• Von Neumann or Stored Program concept was the solution.

• The Resulting Computer is software programmed not hardware programmed

What is the microprocessor• compact integrated circuit• very simple machine, endlessly follows the sequence:

• Fetch the next instruction in sequence from memory

• excute the instruction

• go to step 1.

• Complex timing unit

FIGURE 3-2 (a) The nonpipelined microprocessor follows a sequential fetch and execute cycle. (b) The 8086’s pipelined architecture allows the EU to execute instructions without the delays associated with instruction fetching.

John UffenbeckThe 80x86 Family: Design, Programming, and Interfacing, 3e

Copyright ©2002 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458

All rights reserved.

Control Memory

ALURegisters

Early computersseparate functions by separate chips

Control Bus

I/ODevices

Memory

CPU(ALU +Reg +

control)

Data BusAddress Bus

Early microprocessors control, registers, arithmetic logic are integrated in one chip

Modern MicroprocessorsInternal memory (cashe) + advanced BIU unit and memory management

I/ODevices

Memory

Data Bus

Address Bus

Control Bus

Registers, ALU,Fetch,Exe Logic,Bus logic,Cache Memory

Why 8086• All Intel x86 family share the same basic

architecture.• It is used to build the first IBM PC. (its major advantage

which makes the PC possible is separating the execution unit and the BIU allowing instruction execution while fetching the following ones.)

• It is used in the LAB!

HoweverMany concepts will be explained in general with

8086 as Example.

Also, we will point to some of the advanced features of the more modern microprocessors

Some processors improvements

• Protected mode

• Busses

• Internal registers

• Memory management

• Five stage instruction pipeline

• Others

Protected mode• Protected mode ( starts with 286)• Since DOS require programs to be running in real

mode (Memory space is 1MB & One program at a time).

• In real mode, It is like 8086 with a faster clock.

• in protected mode, It supports multiprogram environment by assigning segments for each program.

• In 286,once switched to protected mode can not switch back to real mode. Ability to switch between the modes starts with 386.

• The virtual 8086 mode starts from 386 also.

Busses1-Data Bus

• The microprocessor is usually characterized by its size of its data bus:

4-bit microprocessor (4004) 8- bit microprocessors (8008) 16-bit microprocessor (8086) 32-bit microprocessor (386 &486) 64-bit microprocessor (Pentium & above)

How does that affects the number of parallel memory chips required.

Note: you should differentiate between the size of external data bus size and the internal data bus size (registers).

8088 has 16 bit internal reg. But 8-bit external data bus.386SX has 32 bit internal reg. But 16-bit external data bus.

However, from Pentium and above the registers size is 32 bit while the external data bus is 64 bit.

Note: Internal registers size did not change since the 386 (32 bits).

Busses2- Address bus

• 20 address bus --- max memory size?




• Memory divided into banks (486 example)

data bus remains:16 bit , address bus became 24 bit

Busses3-Control bus

• Control bus signals like: M/IO , WR, RD

What is active low?

Internal registers• 16 bit in 8088 • 32 bit starting from 386• What are the different ways to access the 32 bit registers:

• Mov AL, [xxxx] or Mov AH, [xxxx] (8 bits high or low) • Mov AX, [xxxx] (16 bits) • Mov EAX, [xxxx] (32 bits)

Memory management

• New memory addressing mechanism– Segmentation: not limited to 64K and segment

registers are indirectly used.– Paging: memory is divided to memory blocks

of 4KB each.– Both can use virtual memory.

The 80386 internal Model• MMU:

– Segmentation Unit• In real mode, it generates 20 bit address (How?)• In protected mode, a segment register works as a pointer to a

8 byte descriptor table having the information about segment base address, size, and attributes.

– Descriptor registrars:– a copy of descriptor table for each active segment is stored in MMU

– Paging Unit: access the memory in 4KB pages• Only the most current pages are kept in memory• Other pages swapped out to the hard disk (virtual memory).• Locating a specific page is time consuming, so:• Address of the 32 most recently used pages are stored in the

page cash (TLB translation look aside buffer)

FIGURE 3-11 The processor model for the 80386 microprocessor consists of the bus interface unit (BIU), central processing unit (CPU), and the memory management unit (MMU).




FIGURE 3-9 The 8086 divides its 1 MB of memory address space into four segments, the data, code, stack, and extra segments. The four segment registers DS, CS, SS, and ES point to location 0 of the current segment. In this example, the stack and extra segments are partially overlapped. (From J. Uffenbeck, Microcomputers and Microprocessors: The 8080, 8085, and Z-80, Prentice Hall, Englewood Cliffs, NJ, 1985.)




FIGURE 3-15 80386 Protected Mode addressing. Physical addresses are computed by adding the instruction offset to the segment base address stored in a descriptor table. The upper 13 bits of the segment register are used to point to a specific descriptor. The base address and limit of the descriptor tables are stored in the global and local descriptor table registers (GDTR and LDTR).




FIGURE 3-14 In Protected Mode each segment register points to the base of a descriptor table. Entries in these tables, called descriptors, are eight bytes long and specify the starting address of the segment, its size limit, and its attributes.




FIGURE 3-17 When paging is enabled, linear addresses are translated into physical addresses via the Page Directory and Page Translation tables.




The 80486Five stage instruction pipeline:

– Prefetch (PF) instructions are placed in one of two queues

– Decode stage 1 (D1) to determine the instruction op-code

– Decode stage 2 (D2) to determine the address of instruction operand

– Execution stage (EX) perform the indicated operation

– Writeback Stage updates the registers with the instruction results.

• Instructions follow each other in these five stages(Fig 3-23)

• This reduces instruction cycle time • This more closely resembles a RISC processor. (instruction

require uniform number of clock pulses)

• Testes showed that 486 is about twice as fast as 386 running at the same clock speed.

Some other processors improvements

• On board cache memory

• Floating point unit

• New instructions

• Address pipelining – The address of the next memory location is output

during the current cycle

• Burst mode (will be covered in chapter 7)

Vacuum tubes Transistor 1948 –Smaller, Cheaper, Less heat dissipation, Made from Silicon (Sand)...

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