Using Altium’s PDN Analyzer Altium's...Using Altium’s PDN Analyzer Page: 4 The first step in the...

Using Altium’s PDN Analyzer

Adam Gerken

November 2018

Using Altium’s PDN Analyzer Page: 2

Introduction:

Electronics are shrinking at an amazing rate, while becoming more powerful and more efficient

just as rapidly. Flight Circuits is constantly finding new ways to stay ahead of the curve in this

regard and has been able to consistently push the boundaries in product miniaturization. New

parts are released every day that allow designers to shrink the physical footprint of components

on the boards but how do we push the boundaries of PCB size and density while remaining cost

effective?

One area of PCB design that can benefit significantly from advances in technology is power

distribution networks (PDN). Power distribution can consume a significant amount of PCB real

estate, and/or cause the addition of layers which drives the cost of the PCB up and pushes the

profit margins down. Using Altium’s new PDN Analyzer tool, Flight Circuits has been able to

maximize the efficiency of layouts, reduce the cost of boards with complex power distribution

requirements, and do design checks of standard rules for less complex layouts.

IPC-2152 contains guidelines for the current carrying capability of traces and vias but the values

therein are extremely conservative. It also doesn’t consider the complex nature of power

distribution; where the current goes, trace width changes, vias in the traces, etc. A design

completed using IPC-2152 guidelines will almost certainly work just fine, but that design will

likely use more PCB real estate than necessary. This is where the PDN Analyzer can step in

and clearly highlight areas of the design that could be reduced in size, or areas that require

more copper and/or vias to maintain the desired specifications.

For this study we are going to focus on a simple product, with a straight forward power

distribution scheme. We’ll be focusing on the tool itself, the set up, and a quick analysis of the

results. To see how this tool could be used to optimize your product, contact us and we’ll get to

work optimizing your PCB.


Set up:

This analysis can be run at almost any time of the PCB layout process, most likely this tool will

be heavily utilized during the planning of the power distribution as this is when the size and

shape of traces, planes, and board outlines can be modified most easily. It can be used at

various stages, like when vias are placed through a power plane, or component locations are

moved. Where current is coming from and going to is a very important factor. For this study we’ll

be using an already complete board.

This board is for a medical device that has

very tight mechanical packaging, as well

as very strict thermal management needs.

The main use of this tool for this board is

ensuring robustness of the PDN. As you’ll

see, the PDN tool makes doing a double

check of trace sizes, via count, and plane

integrity extremely quick and efficient.

The layer stack for this board is a typical 4 layer, 62

mil thick, with Ground and Power planes on the

inner layers and signal layers on the outside. Vias

are simple through vias and are generally 8mil drills

with 18mil pads.


The first step in the PDN Analyzer is to define the power nets and their voltage level then start

defining the sources and loads. For this assembly there are five major power networks we’ll look

at:

• VDC – DC input voltage

• VBAT – The battery voltage

• VSYS – The system voltage, comes from either VDC or VSYS

• 3V3 and 12V0 – standard power rails, driven by a buck converter and boost converter

respectively

For simplicity’s sake we’ll say that VDC drives VBAT, which is switched by a MOSFET to create

VSYS, then converted to 3.3V and 12.0V.

For each power net we need to define the positive voltage, negative voltage, sources, and

loads.

You can see that we have all these fully defined for our VBAT and VSYS rails. In the properties

for each of these we define selected parameters, such as supply voltage, max supply current,

output resistance, efficiency, voltage drop, etc. All this information should be readily available in

the datasheet of the various devices. We can also define “extensions” of power network as we

have shown above between VBAT and VSYS.

From left to right for this power network we have:

• Source 1 – This is the batteries, they have a nominal voltage of 7.2V.

• Source 2 – This is listed as a VRM, or voltage regulator module. This represents the

charger and is tied to a similar load object on the VDC power rail.

• Series 1 – This is a P-channel MOSFET, and diode that ties VBAT to VSYS.

• Load 1 – This is the regulator that creates 12V0.

• Load 2 – This is the regulator that creates 3V3.

This step is extremely important. The more accurate the supplies and loads are, including what

pins current is coming and going from, the better the results will be.


From the VBAT net we can link the regulators to their respective power rails and add the loads

on those rails. The regulator “Source 1” is the same regulator as “Load 2” on the VSYS rail

above and are linked in the PDN Analyzer so the load on the VSYS rail is dynamically updated

based on the loads placed on the 3.3V rail.

This is the completed setup of the 3.3V rail, showing the regulator on the left, all the loads on

the 3.3V rail, and a simple filter that creates ADC_3V3.

Once the whole system is defined, we should have a block diagram of the overall system and

have completed checks for the Ground, Power, Source, and Loads.


Analysis:

After running the analysis we’re

presented with something like this,

displaying current density in amps

per square millimeter - A/mm2. This

is an overlay of all the power nets,

including ground. This doesn’t give

us very much to go on but we can

already see some areas that we

should start to look at.

Note: For purposes of this

demonstration some traces were

reduced to highlight the analysis.

No boards were shipped in this

initial condition!

The analysis portion of the PDN Analyzer is incredibly powerful and creates an amazingly

detailed report including every pin and via contained in the power net. We’ll skip going through

them all but it is a good idea to look at them and see if there are any pins or vias that seem to

be carrying an elevated amount of current, or have too high of a current density.

We can see from the above image that our range of current density is 0 to 75.6 A/mm2. For the

purpose of this study, we won’t get into what is an acceptable current density, there are far too

many factors when looking at acceptable current density, including thermal characteristics of the

board and environment. Let’s start off by looking for the area of the board that has our maximum

current density of 75.6 A/mm2.

In the analyzer we can turn on “highlight peak values”

to find the culprit of this density. This is a portion of the

trace that carries current from the VBAT rail to the

VSYS rail.

Applying a display filter, we can clearly see the area of

the VBAT net we’re interested in.


Since we don’t want to discuss acceptable current density in this paper, let’s just look at the

voltage drop of this trace.

After switching the view to display voltage and doing a differential probe, we can see the voltage

drop of this trace is just over 8.8mV. This may be acceptable; however it may not be, again

that’s beyond the scope of this study. This trace is in an area of high heat concentration due to

the thermal pad connected to the battery charger just to the right. The more the voltage drop the

more power this trace must dissipate, and the more heat it will create. We want this area to

dissipate heat, not create it so let’s see how much we can improve this without impacting the

design.

Going back to the PCB design panel we can see that the trace can easily be increased in size

from 15mil to 25mil. Let’s make the change and rerun the simulation. We can see below, just

from that simple change we reduced the current density to 45.44 A/mm2 and the voltage drop to

5.7mV. Not bad for a simple change that may have gone unoptimized otherwise. 3.1mV

improvement at 7.2V is just over 22mW less power this trace must dissipate. It’s not much, but

every bit counts, and it goes to show this tool can be used for a multitude of applications.


Let’s look at something that may be

slightly less obvious, the large 3.3V

power plane. This is a large plane

for signal integrity purposes so we

may not worry about current density

or voltage drop at all, this plane

looks pretty good on first inspection.

The maximum current density is

only 4.22 A/mm2, but how can it

even be that much on a plane this

size? Let’s look at vias!

As suspected, the highest power density areas of the 3.3V net are the vias. We can see these

three vias that go form the power regulator to the plane:


The current carrying capacity of these vias was calculated during the initial PCB design, and at

4.2 A/mm2 this analysis was validated, these vias will be well within what they should be. This

was just to highlight that the PDN Analyzer may uncover issues that may not have been thought

of initially, or as in this case, validate the original design intent.

One last thing to consider is ground plane integrity. In this design it’s not an issue but ground

planes can get overloaded easily without a second thought from the designer. This can get

particularly bad if there are cuts in the plane, or concentrations where the current density can

easily become elevated. Even with a ground plane this good, there is still up to a 1mV gradient

across the plane, and up to almost 2mV on some ground vias.


Conclusion:

This was a quick run on a simple board but hopefully shows how powerful this tool can be. This

tool is particularly useful in designs that need to push the boundaries of size and/or designs that

have extreme power requirements. As shown, however, the PDN Analyzer can be used to

validate many different parameters of the design network, including aiding in thermal analysis of

the design. The analysis done in this paper is a very simple subset of the testing and validation

that can be done. It can be used manually as shown or as a go/no-go test, using the input

parameters and tolerances of the power net supplies and loads.

The assembly used for this paper is pretty straight forward and has plenty of room for power

distribution, so it was a good candidate for the quick “double check” analysis used, however the

PDN Analyzer tool can be used in a much more advanced manner to reduce power network

size to the absolute minimum tolerable by the design parameters. Let’s face it, a lot of designs

these days just don’t have the real estate to guess and grossly overestimate the requirements of

a power distribution network.

Flight Circuits will work with you on what the requirements are for your assembly and use

industry leading tools, like the PDN Analyzer, to ensure that your product is designed as

efficiently as possible. Contact us today to see what else we can do!

Adam Gerken

President, Flight Circuits

[email protected]

www.flightcircuits.com

(585) 454-9903
mailto:[email protected]://www.flightcircuits.com/

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