uProccessors

ComputerAn electronic equipment that performs high-speed

arithmetic, logical or transfer operations or that assembles, stores, correlates, or otherwise processes information.

EXAMPLE•A 4-bit adder circuit is a specialized, dedicated computer •Computer Elements are Logic Gates •Addition Function is programmed by the interconnection of wires

Hardware + Software

Early Computer - ENIAC(Electronic Numerical Integrator and Computer)• 1946, Univ. of Pennsylvania

• Constructed by Eckert and Mauchly

• 30 tons

• 1500 sq ft

• 18,000 Vacuum Tubes

• Programmed by connecting:

– switches and cables

• 6000 different switches and cables!

HARDWARE PROGRAMMABLE

Stored Program Concept•John von Neumann (Univ. of Penn.), A.W. Burks, H.H. Goldstein

- wrote paper describing “Stored Programs”

•Based on Theoretical Mathematical model, Turing Machine, Alan

Turing, 1936 –Simple type of computer

•works by reading/writing symbols on tape •tape can move left or right

–Finite State Machine –As powerful (in theory) as any possible computer –Still Used in Computability Theory, find out what they can’t do

•Charles Babbage also proposed a mechanical device that could

store a program, Analytical Engine in 1822

–Never constructed (although he tried)

First Stored Program Computer - EDVAC(Electronic Discrete Variable Automatic Computer)

•Completed in 1952

•Storage: 1000 words

•1 word=10 decimal digits •Programmed using Paper Tape

–Sequential Storage

•Random Access Core Developed

–Random Access

SOFTWARE PROGRAMMABLE

Modern Computer Model

• CPU - Central Processing Unit = Microprocessor– arithmetic, logical, synchronization functions

• Memory - Stores Information (DRAM, ROM)– CPU instructions and Data

• I/O - Input/Output Devices - Peripherals (KBD, PRN)– Interface to Outside World (humans, other machines)

• Bus - Set of Parallel wires (Address Bus, Data Bus)– Transmit instructions/data between CPU/Memory/IO

Fetch and Execute Cycle• 1. CPU issues: (FETCH)

– Memory Read Signal on Control Bus – Location of Desired Memory Data on Address Bus

• 2. Memory issues: (FETCH)– Data Valid Signal on Control Bus – Actual Memory Data on Data Bus

• 3. CPU Stores Data Internally (FETCH)– Contains Registers

• 4. CPU Interprets Data as an Instruction(FETCH/EXECUTE*)– Instruction Decoder Circuit

• 5. CPU Performs the Instruction(EXECUTE)

– May Require more Memory Accesses – May Require Interaction with Peripherals*Some consider step 4. To be part of fetch; others part of Execute

Quantifying Memory

• Measured in the quantity of BInary digiT (BIT) • 1 nybble = 4 bits • 1 byte = 8 bits • 1 word = 16 bits • 1 doubleword = 32 bits • 1 quadword = 64 bits • 1 paragraph = 16 bytes • 1 page = 256 bytes • 1 segment (max) = 65,636 bytes

Standard

Machine Dependent

(8086)

• Capacity Measures1 kilobyte (kB) = 210 bytes 1 megabyte (MB) = 220 bytes 1 gigabyte (GB) = 230 bytes 1 terabyte (TB) = 240 bytes

Inside the CPU - Arithmetic Logic Unit(ALU)

•Combinational Logic Circuit –Two Classes of Inputs:

•Control •Data

–Two Classes of Outputs •Status •Data

General Arithmetic Circuit- Attempt to “Share” logic

Example - Purely combinational - data path between registers - 3-bit ALU

CinX

FA S Y

Cout

CinX

FA S Y

Cout

CinX

FA S Y

Cout

0 1 2 3 s1 s0

0 1 2 3 s1 s0

0 1 2 3 s1 s0

A0

B0

A1

B1

A2

B2

S1 S0

C0

C1

C2

C3

In a higher level diagram:

A

B

CALU

n

n

n+1

CLK

S1

S0

Arithmetic Logic Unit (ALU)

Inside the CPU - Control Unit• FSM - Finite State Machine

– Generates Control Signals • External - Bus Signals • Internal - Register Load/Clear; ALU Control

– Synchronization • Controls when to Fetch/Execute • Generates Timing Signals • Handles External Events - Interrupts

– Generally Composed of Subcircuits• Bus Controller • Memory Controller • Cache Controller

Computer OrganizationPrinciple Components

• CPU - (Central Processing Unit) – Fetch/Execute Machine

• Main Memory – An Array of Storage Locations for Bits – Data and Instructions Stored Here

• Secondary Storage – Memory that is Cheap – Memory that is Slow

• I/O Devices - (Input/Output) – Human and Computer to Communication – Computer and Other Device Communication

Intel x86 MicroprocessorsCPU Name Year Intro. Int. CPU Clock # Trans. Addr. Pins Data Pins

8080 1974 2-3 MHz 4500 8 168086 1978 5-10 MHz 29000 16 20

80286 1982 6-16 MHz 130000 16 2480386 1985 16-33 MHz 275000 32 3280486 1989 25-50 MHz 1.2M 32 32

Pentium 1994 60-200 MHz 3.1M 64 32Pentium Pro 1995 150-200 MHz 5.5M 64 36

Pentium MMX 1997 133-266 MHz 64 32Pentium II 1998 233-500 MHz 7.5M 64Celeron 1998 266-500 MHz 7.5M 64

Pentium III 1999 450-600 MHz 64

http://upload.wikimedia.org/wikipedia/commons/5/52/Intel_4004.jpg

http://en.wikipedia.org/wiki/File:Pentiumd.JPG

Intel x86 Microprocessors• 8086 - 20 bit Addr. Bus - 1MB of Memory • 80286 - 24 Addr. Bus - Added Prot. Mode • 80386 - 32 bit regs/busses - Virtual 86 Mode • 80486 - RISC Core - L1 Cache - FPU • Pentium - Superscalar - Dual Pipeline - Split L1 Cache • Pentium Pro - L2 Cache - Br. Pred. - Spec. Exec. • Pentium MMX - 57 Instructions - Integrated DSP (MMX) • Pentium II - 100 MHz Bus - L2 Cache - MMX • Celeron - 66 MHz Bus - True L2 Cache Integration • Pentium III - 100 MHz Bus - 70 Instr. Streaming SIMD Ext. • ….actual processors: P IV, Centrino, DualCore, Atom,…

Intel x86 Family TreeDesigner Processor Codename Year CPU Clk BUS Clk Clk Mult Voltage Feature Size Tech. Package Pins

Intel 4004 1971 0.1 1 10Intel 8080 1974 2 1 5, 12 6 NMOS DIP 40Intel 8086 1978 4.77 4.77 1 5 3 NMOS, CHMOS DIP 40Intel 8086 1978 8 8 1 5 3 NMOS, CHMOS DIP 40Intel 8086 1978 10 10 1 5 3 NMOS, CHMOS DIP 40Intel 8088 1979 4.77 4.77 1 5 3 NMOS, CHMOS DIP 40Intel 8088 1979 8 8 1 5 3 NMOS, CHMOS DIP 40Intel 80186 1982 8 1 5 NMOS, CHMOS PLCC, PGA,LCC 68Intel 80186 10 1 5 NMOS, CHMOS PLCC, PGA,LCC 68Intel 80186 12.5 1 5 NMOS, CHMOS PLCC, PGA,LCC 68Intel 80188 8 1 5 NMOS, CHMOS PLCC, PGA,LCC 68Intel 80188 10 1 5 NMOS, CHMOS PLCC, PGA,LCC 68Intel 80286 1982 8 1 5 1.5 NMOS PLCC, PGA,LCC 68Intel 80286 1982 10 1 5 1.5 NMOS PLCC, PGA,LCC 68Intel 80286 1982 12.5 1 5 1.5 NMOS PLCC, PGA,LCC 68Intel 80386DX 1985 16 5 1.5 CHMOS PGA 132Intel 80386DX 20 5 CHMOS PGA 132Intel 80386DX 25 5 CHMOS PGA 132Intel 80386DX 33 5 CHMOS PGA 132Intel 80386SX 1988 16 5 1.5 CHMOS PQFP 100Intel 80386SX 1988 20 5 1.5 CHMOS PQFP 100Intel 80486DX 1989 25 5 0.8 CHMOS PGA 168Intel 80486DX 33 5 CHMOS PGA 168Intel 80386SL 1990 20 5 CHMOS PQFP, LGA 196/227Intel 80486SX 1991 16 5 0.8 CHMOS PQFP, PGA 196/168Intel 80486SX 1991 20 5 0.8 CHMOS PQFP, PGA 196/168Intel 80486SX 1991 25 5 0.8 CHMOS PQFP, PGA 196/168Intel 80486DX2 1992 50 25 2 5 0.6 PGA 168Intel 80486DX2 1992 50 25 2 5 0.6 Quad FP 196Intel 80486DX2 1992 66 33 2 5 0.6 PGA 168Intel 80486DX2 1992 66 33 2 5 0.6 Quad FP 196Intel 80486DX4 1994 60 3.3 0.6Intel Pentium 1993 60 60 1 5 0.8 BiCMOS PGA 273Intel Pentium 66 66 1 5 0.8 BiCMOS PGA 273Intel Pentium 75 50 1.5 3.3 0.6 PGA 296Intel Pentium 90 60 1.5 3,3 0.6 PGA 296

80x86 microprocessors• 1972 Intel Corp. 8008 발표

• 1978 8086 발표– 20 bit address instead of 16

– 1MB memory access / 64K

– Bus Interface Unit/ Execution Unit 분리

– instruction fetch/ execution 동시실행

– Internal Registers : Data = 16bits

– HW multiplier/Divider

– External arithmetic processor

8088

• 8bit external Bus

• Can use cheap and simple 8bit memory interface

• 16bit register / 20 bit address bits

• 1982 XT 발표 : 16 K memory, 4.77 MHz

ALU/EXECUT

ADDAH

BH

CH

AL

BL

CL

DL

BP

DI

SI

SP

DH

CS

ES

SS

DS

IP

Instr. Decode; Bus Controller

1

2

3

4

5

6

FLAGS

SYSTEM BUS (Internal)

EU Instruction Queue

BIU

Data BusAddress BusInternal architecture of 8086

microprocessor

80186/80188

• Single Computer in a chip

• 8086(8) + clock generator + timer + interrupt controller + DMA (Direct Memory Access) controller + IO interface

80286

• 16bit data/ 24bit address

• Operation modes: Real mode / protected mode– Real mode : same as 8086

– Protected mode : multitasking programming

– Many segments in memory

– Once in a protected mode, cannot return real mode -> pitfall

80386

• 1985 : 32 bit data/address

• 4GB physical memory access

• Real mode : same as 8086

• Protected mode : descriptor register controls tasks, allocates segment

• Segment size boundary, size

• Virtual Memory support

80386

• Windows, OS/2

• 2 clock cycles for memory access

• Cache

• 16 added instructions

• 386SX : 16bit data/ 24bit address bits

80486

• RISC (Reduced Instruction Set Computer) concept is applied

• Improved 386 performance

• 5 stage pipeline

• 80387 floating point processor

• DX2/DX4 : fast internal bus/slow external bus(clock)

Pentium

• Super-scalar processor

• Separate 2 Pipelines

• Code cache/data cache

• 5 -8 -stage pipeline

• 64 bit external bus

Operating modes for Pentium

• REAL MODE – similar as 8086 with possibility to switch

• PROTECTED MODE– Virtual 8086 multitasking, virtual memory addressing,

• SYTEM MANAGEMENT MODE (SMM):– Standard architectural feature since Intel 387 SL provides an

operating system and application independent power management system

– Activated by an external interrupt SMI# switches the CPU to a separate address space while saving the entire context of the CPU

Advanced technologies used in Pentium (1)• Superscalar execution

– Compared with I486 which can execute only one instruction at a time, Pentium can sometimes execute 2 instructions at a time

• Pipeline architecture– Instructions are executed in 5 stages: this allows the processor to

overlap multiple instructions so that it takes less time to execute two instructions in a row

– Pentium has 2 independent pipelines• Branch target buffer

– Pentium processor fetches the branch target instruction before it executes the branch instruction

• Dual on-chip caches

– two separate caches on chip--one for instructions and one for datawhich allows the processor to fetch data and instructions from the cache simultaneously

• Write-back cach– When data is modified; only the data in the cache is changed. Memory

data is changed only when the processor replaces the modified data in the cache with a different set of data

Advanced technologies used in Pentium (2)

• 64 bit bus– with its 64-bit-wide external data bus (Intel486 has 32-bit external bus) the

processor can handle up to twice the data load of the Intel486 processor at the same clock frequency

• Instruction optimization– The Pentium processor has been optimized to run critical instructions in fewer

clock cycles than the Intel486 processor

• Floating Point Optimization– The Pentium processor executes individual instructions faster through execution

pipelining, which allows multiple floating-point instructions to be executed at

the same time

• Pentium extension– The Pentium processor has fewer instruction set extensions than the Intel486

processors. The Pentium processor also has a set of extensions for multiprocessor (MP) operation. This makes a computer with multiple Pentium

processors possible

Compared with I486:

• separate instruction and data caches

• dual integer pipelines (U and V)

• branch prediction with BTB

• pipelined FPU

• 64 external bus

• about 3 million transistors

Pentium Pro

• Two separate silicon die : processor + second cache(256K or 512K)

• Internal bus : 32 bit

• External data bus : 64 bit

• Address bus : 36bit for 64GB

• 100% compatible with 80x86 programs

• 3 processor instruction + 2 floaingpoint instructions

Improvements in Pentium Pro • Superpipelining: increases the number of execution steps, to 14, from the

Pentium's 5.• Integrated Level 2 Cache: The Pentium Pro features a higher-performance

secondary cache compared to all earlier processors. Instead of using motherboard-based cache running at the speed of the memory bus, it uses an integrated level 2 cache with its own bus, running at full processor speed, typically three times the speed that the cache runs at on the Pentium. The Pentium Pro's cache is also non-blocking, which allows the processor to continue without waiting on a cache miss.

• 32-Bit Optimization: The Pentium Pro is optimized for running 32-bit code (which most modern operating systems and applications use) and so gives a greater performance improvement over the Pentium when using the latest software.

• Wider Address Bus: The address bus on the Pentium Pro is widened to 36 bits, giving it a maximum addressability of 64 GB of memory.

• Greater Multiprocessing: Quad processor configurations are supported with the Pentium Pro compared to only dual with the Pentium.

• Out of Order Completion: Instructions flowing down the execution pipelines can complete out of order.

• Superior Branch Prediction Unit: The branch target buffer is double the size of the Pentium's and its accuracy is increased.

• Register Renaming: This feature improves parallel performance of the pipelines.• Speculative Execution: The Pro uses speculative execution to reduce pipeline stall

time in its RISC core.

http://www.pcguide.com/ref/mbsys/cache/struct_Integrated.htm



http://www.pcguide.com/ref/mbsys/cache/char_Transactional.htm

http://www.pcguide.com/ref/mbsys/cache/char_Transactional.htm

P6 Microarchitecture

• 1st level cache = 8KB instruction cache + 8KB data cache

• 2nd Level cache = 1 MB static RAM, 64 bits bus

• CENTERPIECE =Out of Order Execution called “Dynamic Execution) – 3 functions

• Deep branch prediction (DBP)

• Dynamic Data Flow Analysis (DDFA)

• Speculative Execution (SE) – execute instructions beyind a branch

Pentium 4 • NetBurst Architecture

– 1. Hyper pipeline technology: more pipelines: 20 – 31 pipes

– 2. Rapid Execution Engine: the ALU in the core of the CPU actually operate at twice the core clock frequency

– 3. Execution Trace Cache: It stores decoded micro-operations, so that when executing a new instruction, instead of fetching and decoding the instruction again, the CPU directly accesses the decoded micro-ops from the trace cache, thereby saving a considerable time

• High clock speeds (up to 4 GHz)

• SSE2 and SSE3 instruction sets to accelerate media processing

• Integration of HyperThreading

– make one physical CPU work as two logical and virtual CPUs

• Bigger L2 cache (512KB, 2MB)

• Pipeline: 31 stages

HyperThreading Technology

• The technology enables a single physical processor to execute two or more separate code streams (threads) concurrently logical processors

• The logical processors in an IA-32 processor supporting HT Technology share the core resources of the physical processor. This includes the execution engine and the system bus interface.

• After power up and initialization, each logical processor can be independently directed to execute a specified thread, interrupted, or

halted.

• Figure shows a comparison of a processor that supports HT Technology (implemented with two logical processors) and a traditional dual processor system.

Dual (Multi) Core Processors • Based on core technology: more processors on a single chip they

share some of the resources / external buses, cache

• Dual core - Less power consumtion (50%, peak of 65W)

• Faster on CPU intensive applications (audio/video processing, files scans, etc)

Homework

• Explain the concept of pipeline

• Explain which is the difference in addressing the memory and addressing the peripheral devices

• Explain the role of the “retirement unit” from P6 microarchitecture

• Explain the difference between 1st level cache and 2nd level cache

• Explain the concept of “speculative execution”

• SIMD and SSE2 stand for …… (Explain).

• Explain the concept of HyperThreading

• Which is the number bits allocated for data bus, respectively address bus for the following microprocessors: 8080, Pentium IV, 80484, 80286, 8086, 80186.

(C2)

80x86 Internal Architecture

Computer Operation Model FETCH Instruction - EXECUTE Instruction

FETCH EXECUTE FETCH EXECUTE FETCH EXECUTE

time

FETCH 1) Read Instruction from Memory

2) Decode/Interpret Instruction

3) Increment Instruction Address Register

EXECUTE 1) Control Unit - Input is Decoded Instruction

2) Control Signals Set

3) Data is Processed

8086 Architecture Specifics BIU and EU - Pipelined Arrangement

• BIU - Bus Interface Unit

• Instruction Pipeline

• EU - Execution Unit • Pipeline - Hardware Designed for Parallel Operation

FETCH

EXECUTE

FETCH

EXECUTE

FETCH

EXECUTE WAIT

FETCH FETCH GET DATA

EU

BIU

time

8086 Internal Architecture Execution Model

8086 Overall Architecture BIU and EU - Pipelined Arrangement

EXECUTION

UNIT EU

BUS

INTERFACE

UNIT BIU

System Bus (PC Bus)

Instruction

Pipeline

ALU/EXECUT

ADD AH

BH

CH

AL

BL

CL

DL

BP

DI

SI

SP

DH

CS

ES

SS

DS

IP

Instr. Decode;

Bus Controller

1

2

3

4

5

6

SYSTEM BUS (Internal)

FLAGS

EU Instruction

Queue

BIU

Data Bus Address Bus

Content of the EU:…… Content of the BIU: ….

BIU – Bus Interface Unit

(Resp: signals and data/instruction

control)

• To bring the instructions into the internal QUEUE

• To control the content of the queue

• To computes the address

• To generates the control signals

BIU - contents

• Bloc for controlling the signals

• FIFO memory to implement the 6 bytes queue

• Instruction pointer (next instruction to be executed)

• ALU to calculate the address

• Internal communication registers

• Registers for memory segmentation

EU – Execution Unit

• Decoding of instructions

• ALU

• General registers (accessible by user)

• Internal registers (internal operations)

• Register to store the status and control of the program

CS

DS

SS

ES

AH

BH

CH

DH

AL

BL

CL

DL

IP

SP

BP

SI

DI

0 7

0 15

0 7

0 15

Accumulator

Base

Counter

Data

Code Segment

Data Segment

Stack Segment

Extra Segment

Instruction Pointer

Stack Pointer

Base Pointer

Source Index

Destination Index

}

} }

AX

BX

CX

DX

For 32 bit processors: AX register (16b) EAX (32b)

8086/8088 Register File (cont) Instruction Pointer Register

0 15

IP Contains Address of NEXT Instruction to be Fetched

– Automatically Incremented

– Programmer can Control with jump and branch

AX, BX, CX, DX General Purpose Registers

• Can Be Used Separately as 1-byte Registers

»AX AH:AL

• Temporary Storage to Avoid Memory Access

– Faster Execution

– Avoids Memory Access

• Some Special uses for Certain Instructions

AH

BH

CH

DH

AL

BL

CL

DL

0 7 0 7

Accumulator

Base

Counter

Data

AX, BX, CX, DX General Purpose Registers - Some Specialized Uses

• AX, Accumulator

– Main Register for Performing Arithmetic

– mult/div must use AH, AL

– “accumulator” Means Register with Simple ALU

• BX, Base

– Point to Translation Table in Memory

– Holds Memory Offsets; Function Calls

• CX, Counter

– Index Counter for Loop Control

• DX, Data

– After Integer Division Execution - Holds Remainder

AH

BH

CH

DH

AL

BL

CL

DL

0 7 0 7

Accumulator

Base

Counter

Data

CS, DS, ES, SS - Segment

Registers Contains “Base Value” for Memory Address

• CS, Code Segment

– Used to “point” to Instructions

– Determines a Memory Address (along with IP)

– Segmented Address written as CS:IP

• DS, Data Segment

– Used to “point” to Data

– Determines Memory Address (along with other registers)

– ES, Extra Segment allows 2 Data Address Registers

• SS, Stack Segment

– Used to “point” to Data in Stack Structure (LIFO)

– Used with SP or BP

– SS:SP or SP:BP are valid Segment Addresses

IP, SP, BP, SI, DI - Offset Registers Contains “Index Value” for Memory Address

• IP, Instruction Pointer

– Used to “point” to Instructions

– Determines a Memory Address (along with CS)

– Segmented Address written as CS:IP

• SI, Source Index; DI, Destination Index

– Used to “point” to Data

– Determines Memory Address (along with other registers)

– DS, ES commonly used

• SP, Stack Pointer; BP, Base Pointer

– Used to “point” to Data in Stack Structure (LIFO)

– Used with SP or BP

– SS:SP or SP:BP are valid Segment Addresses

These can also be used as General Registers !!!!!!

8086/8088 Register File (cont) Flags Register

x x x x OF DF IF TF SF ZF x AF x PF x CF

0 15

Status and Control Bits Maintained in Flags Register

– Generally Set and Tested Individually

– 9 1-bit flags in 8086; 7 are unused

Status Flags

• CF Carry Flag Arithmetic Carry

• OF Overflow Flag Arithmetic Overflow

• ZF Zero Flag Zero Result; Equal

Compare

• SF Sign Flag Negative Result; Non-

Equal Compare

• PF Parity Flag Even Number of “1” bits

• AF Auxiliary Carry Used with BCD

Arithmetic

Indicate Current Processor Status

Control Flags Influence the 8086 During Execution Phase

• DF: Direction Flag Increment/Decrement

– used for “string operations”

• IF: Interrupt Flag Enables Interrupts

– allows “fetch-execute” to be interrupted

• TF Trap Flag Allows Single-Step

– for debugging; causes interrupt after each op

MOV AH,[SI]

8086 Segmented Memory

• x86 Memory Partitioned into Segments – 8086: maximum size is 64K (16-bit index reg.) – 8086: can have 4 active segments (CS, SS, DS, ES)

– 8086: 2-data; 1-code; 1-stack – x386: maximum size is 4GB (32-bit index reg.) – x386: can have 6 active segments (4-data; FS, GS)

• Why have segmented memory ???????? •Other microprocessors could only address 64K since they

only had a single 16-bit MemAddrReg (or smaller).

Segments allowed computers to be built that could use more

than 64K memory (but not all at the same time).

8086/8088 Memory Access Registers

CS

DS

SS

ES

IP

SP

BP

SI

DI

0 15

0 15

Code Segment

Data Segment

Stack Segment

Extra Segment

Instruction Pointer

Stack Pointer

Base Pointer

Source Index

Destination Index

}

} }

ADD

CS

ES

SS

DS

IP

Memory System

Address Lines

0000 Index Reg. Segment Reg.

Physical Address

0 0

0

15 15

19

Portion of BIU Circuitry

Dedicated Segment Registers

Dedicated Index Registers

BP

DI

SI

SP

8086 Generating Physical Addresses

Segmented Addressing

CS

ES

SS

DS

IP

BP

DI

SI

SP

• Each Segment must begin at Paragraph Boundary

00000h

00010h

00020h

physical address memory

paragraph 1

paragraph 2

paragraph 3

• Each paragraph has phys. address that is multiple of 10h

• BIU is responsible for appending 0000 to Segment

– only need 16-bit segment registers

Segmented Memory (x86 Style)

CS

ES

SS

DS

Data

Segment

Stack

Segment

Extra

Segment

Code

Segment

Segment

Registers

System

Memory

• Segment Registers: – Point to Base Address

• Index Registers: – Contain Offset Value

– • Notation (Segmented Address):

– CS:IP – DS:SI – ES:DI – SS:BP – SS:SP

00000h

FFFFFh

fragmentation

Memory Storage Organization

• Organized as SEGMENTS – Maximum segment size = 64KB

– (Since 16 bit offsets: 216 = 65,535 = 64KB)

• Maximum Memory Size: – 220 = 1,048,576 = 1MB

• Newer Processors (Pentium) Can Utilize More Memory – Wider Address Registers 32 bits

– 232 = 4,294,967,296 = 4GB

Segmented Memory Example

CS

ES

SS

DS

Data

Segment

Stack

Segment

Extra

Segment

Code

Segment

Segment

Registers

System

Memory

• Logical, Segmented Address: 0FE6:012Bh

• Offset, Index Address: 012Bh

• Physical Address: 0FE60h 65120 + 012Bh 299 0FF8Bh 65149

00000h

FFFFFh

Segmented Memory Aliasing

• Logical, Segmented Address 1: DS:SI = 1234:4321

• Physical Address: 12340h 74560 + 4321h 17185 16661h 91745

• Logical, Segmented Address 2: ES:DI = 1665:0011

• Physical Address: 16650h 91728 + 0011h 00017 16661h 91745

Segment Locations in Physical Memory

• 1 Word = 16 bits • Byte Addressable • Little Endian Arrangement

– MSB (Most Significant Byte) at Higher Address

0727H

0726H

0725H

0724H

0723H

0722H

072CH

072BH

072AH

0729H

0728H

• Base Address = ACEDH

AD5F4H

AD5F3H

AD5F2H

AD5FCH

AD5FBH

AD5FAH

AD5F9H

AD5F8H

AD5F7H

AD5F6H

AD5F5H

• Logical Address = 0724H

• Physical Address

= ACED0H + 0724H

= AD5F4H

• M[ACED:0724]

= M[AD5F4]

= 5502H 02H

18H

A3H

7EH

69H

AAH

2EH

00H

55H

11H

72H

0H 2H 5H 5H

0101 0101 0010 0000

0724H 0725H

hex

binary

0727H

0726H

0725H

0724H

0723H

0722H

072CH

072BH

072AH

0729H

0728H

AD5F4H

AD5F3H

AD5F2H

AD5FCH

AD5FBH

AD5FAH

AD5F9H

AD5F8H

AD5F7H

AD5F6H

AD5F5H

55H

18H

A3H

7EH

69H

AAH

2EH

00H

02H

20H

11H

AD5F1H

AD5F0H

AD5EFH

AD5EEH

AD5EDH

AD5ECH

0721H

0720H

071FH

071EH

071DH

071CH

72H

DEH

ADH

FAH

CEH

CAH

FEH

Assume:

M[DS:DI] Contains a Pointer Value

DS = AD5Fh; DI = 0005h

(All Segments Start on Paragraph Boundary)

SI M[DS:DI]

Then:

Pointer is M[DS:DI] = M[AD5F:0005]

= M[AD5F5] = 0002h

M[DS:SI] = M[DS:(DS:DI)] = M[DS:0002h]

= M[AD5F:0002] = M[AD5F2] = 1120h

Default Segment/Index Pairs

Type of Memory Reference Default Segment Base Alternate Segment Base Offset

Instruction Fetch CS None IP

Stack Operation SS None SP

Variable (except following) DS CS, ES. SS Effective Address

- String Source DS CS, ES, SS SI

- String Destination ES None DI

- BP used as Base Register SS CS, DS, ES Effective Address

- BX Used as Base Register DS CS, ES, SS Effective Address

Homework:

Give several exercises

Keypoints

(C3)

Addressing Modes for

80x86 microprocessors

Addressing modes- Classification

• Register addressing

• Immediate addressing

• Memory addressing • Direct addressing

• Indirect register addressing

• Based addressing (with/without displacement)

• Indexed addressing (with/without displacement)

• Based-indexed adressing (with/without displacement)

• Addrssing on strings of bytes

• Addressing of ports

Exceptions:

-Segm segm

-Segm immediate value

Memory addressing

Addressing on strings of bytes

• Strings of bytes

– Source string (SI), in DS (default)

– Destination string (DI), in ES (default)

• Examples of strings

• Examples how the address is calculated:

– MOVSB, LODSB.

Addressing the ports

• What is a port?

• Input/output on ports

• Which is the address of the port?

– Difference on memory address

• Registers used in addressing

• Examples

• How to switch on a LED? Example.

Instruction encoding (e.g. MOV)

The instruction set

http://burks.brighton.ac.uk/burks/language/asm/asmtut/asm1.htm#toc http://webster.cs.ucr.edu/AoA/DOS/AoADosIndex.html

1) Instructions for data transfer

2) Arithmetic instructions

3) Logic instructions

4) Shifts/rotate instructions + LOOPS

5) Instructions on strings of bytes

6) Instructions for port input/outpus

http://burks.brighton.ac.uk/burks/language/asm/asmtut/asm1.htm

http://webster.cs.ucr.edu/AoA/DOS/AoADosIndex.html

Instructions for data transfer

• MOV

• XCHG

• XLAT

• PUSH/POP

• LEA

• LDS, LES

Arithmetic Instructions (… to be continued)

• ADD, ADC

• INC

• AAA, DAA

• SUB, SBB

• DEC

• AAS, DAS

(C4)

INTRUCTION SET

The instruction set








http://burks.brighton.ac.uk/burks/language/asm/asmtut/asm1.htm

http://webster.cs.ucr.edu/AoA/DOS/AoADosIndex.html

Instructions for data transfer

• MOV

• XCHG

• XLAT

• PUSH/POP

• LEA

• LDS, LES

Important:

-Dest & source – the same size in bits

-Register can not be IP

-Transfer “memory” – “memory” is not possible

-Flags are not changed

Exercises (MOV, XCHG) 1) In AH, byte from the address 0, AL – FFFFF

1) Using direct addressing

2) Using indexed addressing

2) ES=1000, DS=5000, DI=100, SI=200 exchange the values of

mem locations (bytes):

1) Using only MOV

2) Using XCHG

3) Use based with index addressing AX ES:[3000h]

4) Interchange DS with ES

5) AXBXCXDXAX (2 solutions give other solutions)

6) Interchange AX with BX without: MOV, XCHG (**)

7) For laboratory: propose 2-3 exercises similar as above

Exercise XLAT

1) Draw the schematic principle

2) Where is applied: encryption, conversion

3) Example with ASCII codes

4) Write an encryption algorithm – give the solution:

1) Input from port 100h

2) Encrypt

3) Send to the port 200h

LDS, LES - examples

• The schematic explanation (first SI, then

DS)

• LDS SI, adress (LDS BX, address)

• LES DI, address (LES reg,address)

• Example for transfer of strings of bytes

Exercises PUSH, POP

• Save an the stack all register (CALL)

• Exchange BX with CX using push/pop

• AXBXCX using push/pop

• Propose 2-3 problems

Arithmetic Instructions (… to be continued)

• ADD, ADC

• INC

• AAA, DAA

• SUB, SBB

• DEC

• AAS, DAS

(C5)

INTRUCTION SET - 2

The instruction set








Exercise XLAT

• Conversion of the digit from

– AL (0, 1, ...9, A, ...F) in the corresponding

– ASCII code (30h,...39h, 41h, ...46h)

• Give 2 solutions

Example AAA, DAA

• AL=37h, BL=32h (in ASCII)

• The result:

– in binary,

– in ASCII

• DAA instruction for BCD numbers

Example AAA

;Example AAA

MOV AH, 09h

MOV AL, 05h

ADD AL, AH

MOV AH, 0

AAA

; example AAS

MOV AL, 05h

MOV BL, 09h

SUB AL, BL; al=FC (-4)

; convert to BCD, AL = 6, ;

AAS

ADD AL, 30h; convert in

ASCII

Examples

1) AX= BX-CX

2) Substraction on bytes (SBB)

3) (AX,BX) = (AX,BX) – (CX, DX)

4) Al=al-2

5) Mov bx, 0;

Dec bx

On BYTE: AX = AL*operand(8)

On WORD: (DX,AX) = AX*operand(16). Eg:..

Examples MUL • Ex:

val1 DB 3

val2 DW 257

mov al, 0ah

mul val1

mov ax,100h

mul val2

• AX=3*AL (mul + add)

• AX= 5*AL – 7*BL

– 2 solutions

• AL = BCD representation of a number on 2 digits. BL – its binary representation.

mov al,8

mov bl,7

mul bl; AX=38h=56

aam; AX=0506

On BYTE: AL = [AX / operand(8))], AH = the rest

On WORD: AX = [(DX,AX) / operand(16)], DX – the rest

Examples DIV

• AL=AL/3

• BL = BL/2 (give 2 solutions)

• AL= AL/5 – BL/7

– Remarks (AL AX)

Examples:

• AX = AX – BX (sub ax,bx OR neg bx; add ax,bx

mov al,value

mov bl,2

cmp al,bl

jl label

inc bl

label inc bl

Conditional JUMP

JUMP IF less/bellow JL/JB

less or equal/bellow or eq JLE/JBE

equal/zero JE/JZ

not equal/not zero JNE/JNZ

greater or equal/above eq JGE/JAE

greater/above JG/JA

carry/not carry JC/JNC

sign/not sign JS/JNS

Exercises

• AL = max(BL, CL)

• AL = BL+CL (if DL>0), BL-CL (DL<0), 0

• DL = 0 if AL is “odd”, 1 if AL is “even”

• AL = ASCII code (digit from AL)

TEST dest,source

Exercises

mov ax, 0abcdh

and ax,0ffh

or ah, 0fch

xor al,ah

test al,1

• AL = 0 (if BL6=0), 1 (if BL6=1)

• AX=ASCII AL=binary

• DL=Binary AX-ASCII

(C6)

INTRUCTION SET - 3

The instruction set








Instuctions for SHIFT

• Logic (insert 0s)

– Left: SHL reg/mem, {1, CL}

• 1 0 1 1 0 0 0 1

• 0 1 1 0 0 0 1 0

– Right: SHR reg/mem, {1, CL}

• 1 0 1 1 0 0 0 1

• 0 1 0 1 1 0 0 0

• Arithmetic (insert 0s, but keep the SIGN)

– Left: SAL reg/mem, {1, CL}

– Right: SAR reg/mem, {1, CL}

Instuctions for ROTATE

• Without Carry (CY is not rotated)

– Left: ROL reg/mem, {1, CL}

• 1 0 1 1 0 0 0 1

• 0 1 1 0 0 0 1 1

– Right: ROR reg/mem, {1, CL}

• 1 0 1 1 0 0 0 1

• 1 1 0 1 1 0 0 0

• With Carry (CY is included in rotation)

– Left: RCL reg/mem, {1, CL}

• CY=x 1 0 1 1 0 0 0 1

• CY=1 0 1 1 0 0 0 1 x

– Right: RCR reg/mem, {1, CL}

• CY=x 1 0 1 1 0 0 0 1

• CY=1 x 1 0 1 1 0 0 0

Examples

a) mov al, 0ffh

shl al,1

mov cl,3

shl al,cl

------------------

c) mov al, 0fch

mov cl,4

rol al,cl

shr al,cl

b) sal al,1; (mul 2)

sar al,1; (div 2)

Exercises (1)

1) Store in BL the value of bit a4 from AL

a) b)

mov cl,3 and al,00010000b

shl al,cl mov cl,4

mov cl,7 shr al,cl

shr al,cl mov bl,al

mov bl,al

Find out other 2 solutions !!

Exercises (2) 2) AX = ??xy; (x,y=hexa). Obtain AX=0x0y

push cx

mov cl,4

rol ax,cl; AX=?xy?

and ah,0Fh AX=0xy?

shr al,cl; AX=0x0y

pop cx

Propose another solution !!

Exercises (3)

3) AX = 8*AL – 7*BL

mov cl,3

cbw

sal ax,cl

xchg ax,bx

cbw

mov dx,ax

sal ax,cl

sub ax,dx

sub bx,ax

xchg ax,bx

Exercises (4)

4) Counts into DL the number of bits “1” from AX

xor dl,dl

mov cx,16

nextbit rcl ax,1

jnc zerobit

inc dl

zerobit dec cx

jnz nextbit

Propose another 2 solutions !!

Exercises (5)

5) Fill in the first 256 bytes from DS with the values: 00, 01, 02, ..., FFh

mov si,0

mov cx,256

xor al,al

NextByte: mov byte ptr[si],al

inc al

inc si

dec cx

jnz NextByte

LOOP instruction Syntax:

LOOP label

Equivalent with:

DEC CX

JNZ label

Other forms:

LOOPE/LOOPZ and

LOOPNE/LOOPNZ

Examples

mov cx,100

xor ax,ax

et1: add ax,2

loop et1

Instructions to control the FLAGS

Examples: ...some examples.

Example: read from keyboard (port 60h) and write to printer

(port 378h):

in al,60h

mov dx,378h

out dx,al

(!!! Some tests are required: keypressed?, printer busy?...later

on)

Examples IN/OUT

1) Generate a rectangular signal on D0 from port 300h

2) Control the frequency

3) Give the solution to control the duration of the signal

4) Signal with another form

5) Connect a DAC and generate a triangular signal (maximum frequency)

6) A dynamic light: control the speecd

Examples: a) wait for non busy, b) timeout

LODSB(W)

Example LODSB

DX = Sum(DS:SI=100h), i=1...20

xor dx,dx

mov cx,20

mov si,100h

cld

nextbyte: lodsb

cbw

add dx,ax

loop nextbyte

Propose the solution without using LODS

STOSB(W)

Example STOSB

Generate a string of 256 bytes (00, 01, ...FFh) at the address ES:DI=300H

mov di,300h

xor al,al

mov cx,256

cld

sto: stosb

inc al

loop sto

nop

Propose the solution without using STOSB

Examples MOVSB

(transfer 20 bytes from DS:SI=100h to ES:DI=300h)

mov si,100h

mov di,300h

mov cx,20

e: mov al,[si]

mov [di],al

inc si

inc di

dec cx

jnz e

mov si,100h

mov di,300h

mov cx,20

cld

e: MOVSB

loop e

Obs:

REP

MOVSB

Example: returns into BX the offset of the first 00 byte encountered in the

string of 100 bytes found at the address ES:DI=200h

OR 0FFFF if not found.

mov di,200h

mov cx,100

mov al,0

s: cmp al,[di]

je f0

inc di

loop s

mov di,0ffffh

f0: mov bx,di

nop

mov di,200h

mov cx, 100

mov al,0

cld

REPNE

SCASB

jcxnz f

mov di,0

f: dec di

mov bx,di

nop

Exercise

Data Acquisition System:

- Control port, RD/WR: 200h: (START on D0

active in 1, EOC on D7 active in 0)

- data port, RD, 300h

- Read 10.000 samples in ES:DI=100h

MACRO - instructions= a group of instructions identified by a unique name (the name of the

MACRO) and interpreted as a “new instruction”- a MACRO needs to be defined:

name MACRO param_1, ..., param_n....instructions....ENDM

In order to use the MACROs:- They need to be defined- They could be used afterwards

Example 1 (without parameters)• MACRO to store/restore the registersDefinitions: (A) (B)push_regs MACRO pop_regs MACRO

push ax pop dxpush bx pop cx push cx pop bxpush dx pop axENDM ENDM

Usage:.... .....push_regs ; substituted by the above sequence.... ....pop_regs.... ....

Discussion:Advantages (+), Disadvantages (-)

Example 2 (with parameters)• MACRO to FILL in a string of bytes in ES at the address “addr” with the

value 0 (parameters: address and number of bytes )Definition: fill MACRO addr, n

xor al,alcldmov di, addrmov cx, nrepstosbENDM

Usage:.... .....fill 100h, 200h ; substituted by the above sequence.... ....

Example 3 (with parameters)• MACRO to add/subtract 2 numbers n1, n2 of 1 byte into AL (AL=n1+/- n2)Definition: compute MACRO n1, operand, n2

mov al, [n1]cmp [operand], ‘+’jne minusadd al, [n2]jmp final

minus: sub al,[n2]final: nop

ENDMUsage:

mov di DB 20hop DB ‘-’b DB 10h.... .....compute a, op, b ; substituted by the above sequence.... ....

Exercises (homework)

MACRO for:

• Obtaining in AX the sum of a string of bytes (the offset address in DS andthe number of the bytes are the parameters)

• Obtaining in AL the maximum of a string of bytes (the address and thenumber of the bytes are the parameters)

• Returning in CX the length of a string of bytes that ends with 00h (theaddress is transmited as parameter)

CALL - instructions

• The need to substitute sequences of programs which are repeated OR group thefunctionalities in a single software entity

• Example – diagram• Types of CALLS

– Intrasegment (NEAR Calls) - IP– Intersegment (FAR Calls) – CS, IP

Execution Steps1) CALL is classified as NEAR or FAR2) NEAR FAR

– save IP on the stack - save CS on the stack- save IP on the stack

3) JUMP at the address CS:IP4) Execute the sequence, until RET is encountered5) RET execution:

NEAR- get IP from the stack - get IP from the stack

- get CS from the stack6) JUMP at the address CS:IP

ProceduresDefinition:

namep PROC {NEAR or FAR}... ...instructions... ...RET; PAY ATTENTION !!

namep ENDP

Usage:... ...call namep... ...

Example 1 (find_max in a string; receives in SI begining of the stringand the length in CX; returns the max in AL and the index of max in BX)

find_max PROC NEARmov al, byte ptr [si]mov bx,sidec cx

c: cmp al, byte ptr[si +1]jge Okmov al, byte ptr[si+1]mov bx,siinc bx

Ok: inc siloop cRETENDP

Usage:.... ...mov si, offset string1mov cx,lengthcall find_max... ...

Example 2 (strlen – returns in CX the length of a string of bytes finished with00h; receives into DI the begining of the string)

strlen PROCxor cx,cxxor al,alcld

comp: scasbjz exitinc cxjmp comp

exit: retENDP

Usage:str DB ‘un text’, ‘0’.... ...mov di, offset str; (equiv: lea di,str)call strlen... ...

Allocation of memory for variables

DB – define byte, DW – define word, DD-define double wordExamples:

a DB 1b DB 2c DW 1, 2, 3str DB ‘text’, ‘0’len EQU $-Str

Usage:mov al, [a]mov si, offset amov al, [si]mov si, offset str

Organisation of the programs in Assembling Language(*.asm)

PAGE 60,132TITLE ROTITCOMMENT * *STIVA SEGMENT PARA STACK 'STACK'

DW 256 DUP(?)STIVA ENDS;DATA SEGMENT PARA PUBLIC 'DATE'a DB 0DATA ENDS

CODE SEGMENT PARA PUBLIC 'COD'MAIN PROC FAR

ASSUME SS:STIVA,DS:DATA,CS:CODE,ES:NOTHINGpush dsxor ax,axpush ax ;preg.pt.retmov ax,DATAmov ds,ax ;preg. DS

; .....ret

MAIN ENDPCODE ENDS

END MAIN

EXE/COMTASM progr.asm

(progr.obj)

TLINK progr.obj(com/exe – options in TLINK)

THE SYSTEM OF INTERRUPTS

1) Definitions2) Questions (??)3) Classification of interrupts4) The Interrupt Vector Table (IVT)5) The steps to execute a ISR6) The interrupt controller 82597) The sequence for “Interrupt Acknowledge”8) Applications of software interrupts

1) Definitionsa) Need of communication between the uP and the

peripheral devices

b) Idea: to interrupt the execution of the current program

c) Def: Interrupts + Interrupt Service Routine

uP Peripheral devices

2) Questions1) Who can interrupt the uP? (possibilities)

a) Hardwareb) Software Classification of interrupts

2) What happens when an interrupt is accepted?3) How the processor finds the address of ISR?4) Then, which is the difference between a

PROC and ISR?• Address (ISR), address (PROC)• End: ISR (iret), PROC (ret)

3) Classification of interruptsa) Internal interrupts / exceptionsb) Hardware interrupts (from peripheral devices data

transfer; signals are used)• INTR – maskable interrupts

• I=1 (STI)• I=0 (CLI)

• NMI – non-maskable interrupts• NMI

When accepted? - At the end of an instruction cycle !How are the peripheral devices recognised? By a type number which is used by the processor as a pointer in the IVT to obtain the address of the ISR

c) Software interruptsINT k; k=0...255 (type of interrupt)

Classification (cont)

Examples:

INT 10h (video services)

INT 14h (communication on serial interface)

4) The Interrupt Vector Table (IVT)• Implements a mechanism that associates for a specific

interrupt request a service (handler or ISR). It stores the addresses of ISRs

• 256 types of interrupt requests• What we need to obtain an address for ISR

• CS & IP• Many ISRs : k=0 ... 255 (type of interrupts)

• The structure of IVT• Location• Structuring (IP, CS), 256 entries

• The input in the table is the “key k” (interrupt type)• Who delivers the key to the uP? (example of values)

5) The steps to execute a ISR1) Peripheral device interrupt controller (it

associate a key K to the device); K-progr2) I=1?- uP accepts the interrupt INTA and

asks for the key. The key is transmited to theuP.

3) The uP uses the key K to find out the addressof the ISR (associates an ISR to theperipheral devices)

4) uP execute the ISR and then returns to themain program

6) The interrupt controller 8259

Inputs on 8259

Explain:

IRQi signals + connection of 2 controllers 8259 in the system

7) The sequence for “Interrupt Acknowledge”

= a hardware mechanism to send the “key K” from the interrupt controller 8259 to the uP

• The diagram of signals (if INTR and I=1)1) Save on the stack: PSW, CS, IP, I=0, T=02) It follows the sequence of INTA

• 2 machine cycles• ALE• LOCK• INTA (1st activation, 2nd activation) Key K

3) Point into IVT at address k*4 to get the address of ISR4) Jump to ISR and execute it5) IRET – returns in the main program

8) Applications of software interruptsVIDEO SERVICES (INT 10h) – BIOS levelAH =2 (setting the cursor to a specific location)

In: DH = raw, DL=columnExercise: position in the centre of the screen

AH=3 (get current cursor position)Returns in DH=raw, DL=column, CX=the shape of the cursorExercise: Move Relative Nx, Ny

AH=6 (scroll up)In: AL=no of lines for scroll (AL=0, CLS), BH=attribute of blank rawsCH=upper raw, CL=left column, DH=lower raw, DL=right columnExample: Clear Screen

AH= 9 (display a character from AL)AL, BH=video page, BL=atrribute, CX-repExample: Display a string defined in DS, starting in raw 3 column 5

AH=0Eh (display char with increment of cursor)

8) Applications of software interrupts

KEYBOARD SERVICES (INT 16h) – BIOS level

AH =1 (test if keypressed)Return Z=0 if Keypressed, Z=1 if not Keypressed

AH=0 (read the character)Returns in AH the scane code and in AL the ASCII code of the Key.

Exercise: Read a string and display it, until ESC is pressed

DOS services (INT 21h)

INT 21h (cont)

Documentation: INT 1Ah, INT 14h, INT 17h, INT 13h

INSTALLING OWN

Interrupt Service Routines

1) Why?

2) How to do?

3) Examples

1) Why?

• To change or adapt an existing BIOS service:

– Keyboard: to capture a combination of keys

– Timer: to count real time events related to a specific

process (ADC).

– Mouse related procedures

– Etc? Discussions.

• The install a peripheral-specific procedure:

– ADC or DAC

– Own applications

– Examples?

2) How to do?

STEPS:

(the scheme)

1) Write the own ISR

2) Reserve memory in DS for old values from IVT and save

IP and CS of previous routine at these locations (CLI)

3) Upload in IVT the new values for IP and CS of the own

ISR

4) NOW the interrupts may come (STI)

5) ... The program is executed ...

6) CLI and restore the old values of IP and CS into IVT, then

STI.

2.1) Write the own ISR

iroutine PROC FAR

...

...

mov al,20h (EOI for 8259)

out 20h, al

iret

iroutine ENDP

2.2) Save the old IP and CS from IVT

CS_Old DW ?

IP_Old DW ?

....

....

; save the old IP and CS from IVT

cli

xor ax,ax

mov es,ax

mov di, k*4; k=type of interrupt

mov ax, word ptr es:[di]

mov [CS_Old],ax

add di,2

mov ax, word ptr es:[di]

mov [IP_Old],ax

OR 2.2) Save the old IP and CS from IVT

(using INT 21h)CS_Old DW ?

IP_Old DW ?

....

....

; save the old IP and CS from IVT

cli

mov ah,35h

mov al,k

int 21h; in ES the SEGMENT, in BX the OFFSET

mov [CS_Old],es

mov [IP_Old],bx

2.3) Install in IVT the new values for IP and CS

mov di,k*4

mov ax, segment iroutine

mov es:[di],ax

add di,2

mov ax, offset iroutine

mov es:[di],ax

STI

OR 2.3) Install in IVT the new values for IP

and CS (INT 21h, AH=25h)

mov ah,25h

mov al,k

mov ax,segment iroutine

mov ds,ax

mov bx, offset iroutine

int 21h

STI

2.6) Restore the old values of IP and CS

mov ax, [CS_Old]

mov ds,ax

mov bx, [IP_Old]

mov ah,25h

mov al,k

int 21h

ELE 3230 - Chapter 5 1

Chapter 58088 Pin Assignment

(*Brey:ch9; Hall:ch7; Triebel:ch7)

ELE 3230Microprocessors and Computer

Systems

2

Pin Layout of the 8088Microprocessor

• Nine pins have functions which dependon the state of :

=high - 8088 operates in MINIMUM MODE

=low - 8088 operates in MAXIMUM MODE

• minimum mode: - 8088 directlygenerates the control signals necessaryfor accessing memory and IO ports.

• maximum mode:- external supportchips are needed to generate controlsignals; the processor can work in asystem containing other processors

MXMN/

MXMN/

MXMN/

GND 1A14 2A13 3A12 4A11 5A10 6A9 7A8 8AD7 9AD6 10AD5 11AD4 12AD3 13AD2 14AD1 15AD0 16NMI 17INTR 18CLK 19GND 20

40 Vcc39 A1538 A16/S337 A17/S436 A18/S535 A19/S63433323130292827262524232221

MXMN/ RD

TESTREADYRESET

40 LEAD

8088CPU

SS0 (High)

HOLD )GT0 / RQ(HLDA )GT1 / RQ(WR ) LOCK(

MIO/ )S2(RDT/ ) S1(

DEN ) S0(ALE (QS0)INTA (QS1)

Min Mode (Max Mode)


Signals Common to Both Minimumand Maximum Modes

Common signalsName Function Type

AD7 – AD0 Address/data bus Bidirectional, 3-state

A15 – A8 Address bus Output,3-state

A19/S6 – A16/S3 Address/status Output,3-state

Minimum/maximumMode control Input

Read control Output,3-state

Wait on test control Input

READY Wait state control InputRESET System reset Input

NMI NomaskableInterrupt request Input

INTR Interrupt request InputCLK System clock InputVCC +5V Input

GND Ground Input

RD

MN/MX

TEST


Unique Minimum-mode SignalsMinimum mode signals (MN/ = VCC )Name Function Type

HOLD Hold request InputHLDA Hold acknowledge Output

Write control Output,3-state

IO/memory control Output,3-state

Datatransmit/receive

Output,3-state

Data enable Output,3-state

Status line Output,3-state

ALE Address latchenable

Output

Interruptacknowledge

Output

MX

WR

MIO/

RDT/

DEN

SSO

INTA


Unique Maximum-mode Signals

Maximum mode signals (MN/ = GND)Name Function Type

Request/grant busaccess control

Bidirectional

Bus priority lockcontrol

Output,3-state

Bus cycle status Output,3-state

QS1, QS2 Instruction queuestatus

Output

MX

0 GT1,/RQ

LOCK

S0-S2


Maximum-Mode of 8088INIT Multibus

S0S1S2LOCK

CLK AEN

CRQLCK

IOB

RESBSYSB/RESB

ANYREQ

8289Busarbiter

AEN IOB

CLK AEN IOBS0S1S2

8288BuscontrollerDEN

DT/RALE

MRDCMWTCAMWCIORCIOWCAIOWCINTAMCE/PDENALE

DENDT/R

A0-A15,A16/S3-A19/S6

D0-D7

RDREADYQS1,QS0

CLKVcc GND

CLK

LOCKS0

S1

S2

Interruptinterface

INTRTEST

NMIRESET

8088MPU

MN/MX

RQ/GT1 RQ/GT0

Local bus control

BUSYCBRQBPROBPRNBREQBCLK


Maximum-Mode of 8088

❚ 8288 Bus Controller❙ In maximum-mode, the signal to control memory, I/O, and interrupt

interface is produced by 8288.

❙ are no longer produced by8088, instead 8288 generates

INTA and ALE,,DEN ,RDT/ ,MIO/ WR,

INTAAIOWCIOWCIORCAMWCMWTCMRDC -- memory read command

-- memory write command-- advanced memory write command-- I/O read command-- I/O write command-- advanced I/O write command-- interrupt acknowledge command


Bus Status Codes

Status InputsS1 S0 CPU Cycle 8288 Command

0 0 0 Interrupt Acknowledge INTA0 0 1 Read I/O Port IORC0 1 0 Write I/O Port AIOWC,IOWC0 1 1 Halt None1 0 0 Instruction Fetch MRDC1 0 1 Read Memory MRDC1 1 0 Write Memory AMWCMWTC,1 1 1 Passive None

S2

❚ 8288 produces the commands according to the outputbits from 8088.012 SSS


Queue Status Codes

QS1 QS0 Queue Status0 (low) 0 No Operation. During the last

clock cycle, nothing was takenfrom the queue.

0 1 First Byte. The byte takenfrom the queue was the firstbyte of the instruction.

1 (high) 0 Queue Empty. The queue hasbeen reinitialized as a result ofthe execution of a transferinstruction.

1 1 Subsequent Byte. The bytetaken from the queue was asubsequent byte of theinstruction.

❚ Two new signals are produced by 8088 in maximum-mode : QS0and QS1. The two-bit code tells the external circuitry what type ofinformation was removed from the queue in the previous cycle.


Pin Diagram

386DX processor view from pin side Top view for 386SX processor


8088 Pin FunctionsThe 8088 pins may be grouped into the following nine categories:

1. Power Supply and Clock (VCC, GND and CLK)❚ VCC=5 volts (5 or 10% tolerance)❚ Maximum current needed is 340mA (10 mA for CMOS version)❚ BOTH ground (GND) pins must be connected to 0V.❚ CLK input needs a periodic rectangular waveform with rise and fall times

of less than 10ns. Clock frequency must be between 2 and 5 MHz. (seech06, clock chip 8284).

2. Minimum/Maximum Mode pin❚ Minimum mode selected when is connected to +5V)MX(MN/


3. Status Pins - in maximum mode onlyThe status pins are outputs which are used by the 8288 bus controller to generatecontrol signals according to the following table:

8088 Pin Functions

S2 S1 S0 Meaning0 0 0 Interrupt acknowledge (INTA)0 0 1 I/O read0 1 0 I/O write0 1 1 HALT1 0 0 Code access (fetching instruction)1 0 1 Memory read1 1 0 Memory write1 1 1 Passive state (not used)

( , )S0 S1, and S2


8088 Pin Functions

4. Bus Master Control of the local bus is transferred to other devices with aid of the

following signals: Minimum Mode - HOLD and HLDA (hold acknowledge) Maximum Mode - request/grant❚ HOLD is an input (in minimum mode only) which tells the processor to

suspend operations and allow other devices to access the system bus.Program execution only resumes when HOLD=0.

❚ HLDA (hold acknowledge) is an output which informs other devices in thesystem that the 8088 is in a HOLD state. When another device wants toaccess the bus, it waits for HLDA=1.

(HOLD, HLDA, RQ/GT0, RQ/GT1 and LOCK)

LOCK and )GT1/RQ ,GT0/RQ(


8088 Pin Functions

4. Bus Master (cont.)❚ Request and Grant pins are used only in maximum

mode and function both as inputs (to accept requests) and outputs (togrant requests). When another device wants to become the BUSMASTER (i.e. take control of the local bus) it issues a request by pullingone of the request pins to a low logic state for one clock cycle. After arequest is received, the 8088 enters a HOLD state and sends a grantsignal on the same pin.

❚ is an output pin in maximum mode and informs other devices thatthey cannot takeover the local bus

)GT1/RQ and GT0/RQ(

.GT1/RQ overpriority higher a has GT0/RQ

LOCK

(HOLD, HLDA, RQ/GT0, RQ/GT1 and LOCK)


8088 Pin Functions

5. Interrupt pins (NMI, INTR and INTA)Interrupt acknowledge pin is available only in minimum mode. NMI(non-maskable interrupt) and INTR (interrupt request) are present in bothmodes.

❚ The NMI (non-maskable interrupt) is an input which accepts a rising edgeto trigger the interrupt. It cannot be disabled by software. Interrupt number2 is generated by an NMI.

❚ INTR is an input which accepts a high logic level as an interrupt request.Provided the interrupt flag in the FLAGS register is enabled, the processorwill respond to the interrupt request in the same way as it processes ansoftware INT instruction.

❚ acknowledges an interrupt request and indicates to the interruptingdevice that it should place an 8-bit interrupt number on the data bus

)INTA(

INTA


8088 Pin Functions

6. RESET is an input which resets and initializes the processor. After aRESET the processor reads memory location FFFF0h for an instruction.

7. Bus control pinsA group of 7 pins generate the control signals for data transfer to and fromthe data and address bus in minimum mode. In maximum mode only two(RD and READY) of these 7 functions are available directly (the other busprotocol signals are generated from the status pins).The seven pins in this group include:

❚ READY - an input to tell the processor that the selected memory or I/Oport is ready to complete a read or write operation. If READY is notasserted, wait states are added (eg. For slow memory).


8088 Pin Functions

7. Bus control pins (cont.)❚ (read) - an output indicating when the processor is performing read

operation from memory or an I/O port.❚ ALE (addressing latch enable) - an output to demultiplex the address/data

pins. When ALE is high, address information is being sent.❚ (data enable) - an output used with an external tristate buffer to disconnect

the processor data pins from the data bus. (When is low the processordata pins should be connected to the data bus)

❚ (data transmit/receive) - an output indicates direction of data flow❚ (write) - an output to indicate when the processor is putting data into

memory or I/O port❚ - an output indicates whether access is to memory or I/O ports❚ The logic is different between 8086 & 8088.

RD

DENDEN

DT/RWR

IO/M


8088 Pin Functions

8. Address, data pins and address status pins

❚ AD0-AD7 (address/data bus pins) - these pins output both address and datainformation and input data at different times of the bus cycle. Usually anexternal latch stores the address information form these pins before the pinsare switched to carry data. Both the low and high order bytes of a 16-bit dataword must be transferred via these pins.

❚ A8-A15 (address bus pins) - used solely for specifying the address of amemory location or IO port.

❚ A16/S3-A19/S6 (address bus or status pins) - these either carry memoryaddressing information or status information. S6 is always at logic 0. S5describes the state of the interrupt flag in the FLAGS register. S4 and S3describe the segment register being used to generate the physical addressthat was output on the address during the current bus cycle.


8088 Pin Functions

❚ The address pins A0-A15 specify either a 16-bit I/O port number or thefirst 16 bits of a 20-bit address of a memory location.

9. Coprocessor interaction pinsThree pins are used for interactions between the8088 and 8087 arithmetic co-processor to synchronize MPU withexternal hardware.

S4 S3 Segment register0 0 ES0 1 SS1 0 CS or no segment1 1 DS

8. Address, data pins and address status pins (cont.)

(TEST, QS0 and QS1)


8088 Pin Functions9. Coprocessor interaction pins (cont.)❚ is an input pin that is tested by the WAIT instruction. If is low the

WAIT instruction functions as a NOP. If is at logic 1 then the WAITinstruction waits until it goes to logic 0 (MPU enters “idel state”). The pinis often connected directly to a 8087 coprocessor (it must be connect to logic 0if the 8087 is not present)

❚ QS0 and QS1 (queue status) pins provide information on the 8088 internalinstruction queue. The information is used by the 8087 coprocessor. Thequeue status bits indicate the contents of the internal instruction queueaccording to the following table:

QS1 QS0 instruction queue contents0 0 No operation (queue is idle)0 1 First byte of an opcode1 0 Queue is empty1 1 Subsequent byte of an opcode

TEST TESTTEST

TEST


DC characteristics of Pin❚ It is important to know the input and output characteristics

which are required for hardware designer to select propercomponents.

❚ Input characteristics: Output characteristics:Logic Level Voltage Current

0 0.8 V max 10µA max

1 2.0 V min 10µA max

Logic Level Voltage Current

0 0.45 V max 2.0mA max

1 2.4 V min -400µA max

Logic 1

Logic 0

UndeterminedRange

Logic 1

Logic 0

DisallowedRange

Output voltagerangeInput voltage

range

VOH(min)

VOL(max)VIL(max)

VIH(min)


DC characteristics of Pin❚ Noise immunity :

VNL [Low-level (Logic 0) noise immunity] = Vin_low (max)- Vout_low(max)VNH [High-level (Logic 1) noise immunity] = Vout_high(min)-Vin_high(min)

❚ For 8088, VNL is 350mV (=0.8V-0.45V). Typical logic circuit has noiseimmunity 400mV (=0.8V-0.4V).

❚ Smaller noise immunity means 8088 and 8086 would encounter problemwith longer wire or larger load.! recommendation : no more than 10 loads

❚ recommended fan out: Family Fanout Sink Current Source Current

TTL (74XX) 1 -1.6 mA 40 µA TTL (74LSXX) 5 -0.4 mA 20 µA TTL (74SXX) 1 -2.0 mA 50 µATTL (74ALSXX) 10 -0.2 mA 20 µACMOS (74HCXX) 10 -1.0 µA 1.0 µACMOS (CD4XXX) 10 -1.0 µA 1.0 µA

NMOS 10 -10 µA 10 µA


FAQ❚ What are sink and source current, and the sign of the current?

❙ The component source current is the current that it will outputto the next stage device when the component's output pin is high.

❙ The component sink current is the current that it will take in from itsoutput pin when its output is at its logic low state.

❙ The minus sign for sink current is to denote that the current is flowingback the component.

❚ Noise immunity❙ The noise immunity for logic low and high are defined in pp22 of ch05. Pls use these definitions for

the noise immunity.

Please note that noise immunity is the difference between the INPUT and OUTPUT, not differencebetween logic 0 and logic 1. The old slide that I showed in the class is not correct. Let's use thedefinition in your lecture note.

❚


FAQ❚ Why uses the difference between input and output for noise immunity calculation?

❙ Let's take a look at the noise immunity for logic 0.If you look the figure in pp21, the output disallow range is bigger than theundetermined range for the input, and V_IL (max)> V_OL(max).

So if the output of logic 0 from a chip is corrupted with noise dN, the aggregated signalinto the other chip will has a max. value of V_OL(max)+dN.This value should be less than V_IL so that the total amplitude will not fall in theundetermined range. So noise immunity for logic 0 is defined asV_IL(max)-V_OL(max).

By the same token, the noise immunity for logic 1 can be defined.


Chapter 68284 Clock Generator

Bus DemuxBus Cycle

(Brey's ch8; Hall's ch7)

ELE 3230Microprocessors and Computer

Systems


8284 Clock Generator

❚ 8284 is an integrated circuit which generates the CLOCK,READY and RESET signals needed in the 8088.

❚ Internally the 8284 consists of an oscillator circuit (whichneeds an external crystal oscillator), dividers, flip-flops,buffers and logic gates. The external crystal frequency isdivided by 3 to produce the basic clock frequency as shownbelow:

200 ns Min 500 ns Max

6+ 53.9

1.5.60

-.5

10 ns Max 10 ns Max

118.33 nsMin

68.66 nsMin



Internal Block Diagram of the 8284 clock generator

EFI

D

CKQ RESET

RES

÷3

SYNC

÷2

SYNCPCLK

F/C

RDY1

AEN1

RDY2

AEN2

READY

CK

D Q

FF2

CK

D Q

FF1

ASYNC

CRYSTALOSCILLATOR

OSC

X1

X2

CLK

CSYNC



CSYNC 1 PCLK 2

3 RDY1 4READY 5 RDY2 6 7 CLK 8 GND 9

18 Vcc17 X116 X21514 EFI1312 OSC1110 RESET

8284A

CF/

ASYNC

RES

AEN1

AEN2


8284 Output Pins❚ PCLK - peripheral clock outputs clock signal which is at half the

frequency of the main CLK output.

❚ CLK - clock outputs a 33% duty cycle periodic clock which runs atone third the frequency as the EFI or crystal frequency.

❚ OSC - oscillator output provides a buffered periodic waveformrunning at the crystal frequency. Output is suitable for driving theEFI input of another 8284.

❚ RESET - generates an output suitable for the reset input of the 8088.

❚ READY - generates READY signal suitable for 8088 READY input.


Relation between CLK and PCLK

OSC

CLK

PCLK


8284 Input Pins❚ VCC, GND - power supply pins

❚ RDY1 and RDY2 - bus ready accepts input of the bus ready signal

❚ AEN1, AEN2 - address enable (qualifies RDY1 and RDY2)

❚ - ready synchronization select (selects one or two stages of synchronization for the RDY1 and RDY2 inputs

❚ X1, X2 - crystal inputs (for connection of external clock signal input)

❚ EFI - external frequency input (external clock signal input)

❚ CSYNC - clock synchronization used with the EFI to synchronize the clock output in multiprocessor systems. MUST BE GROUNDED if the crystal oscillator is used.

❚ - frequency/crystal (selects crystal oscillator or EFI as source)

❚ - reset input (accept input from a switch for generating reset)

ASYNC

F/C

RES


Example - A simple 8284 circuit

• If WAIT states for slow memory or IO peripherals are needed, the circuit must bemodified.

• The 8284 can be used simply to generated the CLOCK signal as shown below:5V

5V

5V

RDY1 RDY2EFIF/CCSYNCAEN1AEN2

ASYNC

X1

X2 RES

RESET

READY

CLK

8284

RESET

READY

CLK

8088

Reset Switch 100nF

4.7K

4.7K

4.7K

510

510 15MHz

9

Minimum Mode System BlockDiagram Vcc

Vcc

GND

GND

Address /data Address

Data

IR0-7

CLK MXMN/READY MIO/RESET RD

WR 8088 INTA CPU

RDT/ DEN ALE

A8-A19INTR

T

OE 8286 Transceiver

EN

8259A Interrupt controller

INT

STBOE

8282 Latch (1, 2 or 3)

WEOE

2142 RAM (2)

OE

27162 PROM

CS WR RD

Peripheral

8284ARES clock generator

AD0-AD7


Demultiplexing the Address andData Bus

❚ Address and data bus are multiplexed in 8086 (AD0-AD15) and 8088(AD0-AD7) to reduce the number of pinsrequired.

❚ Address and Data need to be demultiplexed from thebus. (Why not leave it multiplexed?)

❚ How to maintain a stable address throughout a read orwrite cycle?


Demultiplexing the Address andData Bus on 8088

• Two transparent latches (74LS373) are used for demultiplexed.

• ALE indicates when address information is on AD0-AD7. In maximum mode, ALE isgenerated by the bus controller.

Minimum modeaddress/datademultiplexing

G ‘373 OE

8088

A19/S6A18/S5A17/S4A16/S3

A15A14A13A12A11A10A9A8

ALE

MN/MX

+5V

RD

AD0

AD7AD6AD5AD4AD3AD2AD1

IO/M

WR

A13

A3

A19A18A17A16A15A14

A12A11A10A9

A6

A8A7

A5A4

A2A1A0

Address bus

D7D6D5D4D3D2D1D0

WRRDIO/M

Data bus

Control bus

OE‘373

G


Latches

❚ The address and data bus of the 8088 are multiplexed on pinsAD0 to AD7. Address information are contained on AD0-AD7only when ALE (address latch enable) is asserted.

❚ External Latches are needed to store (“latch”) the addressinginformation before AD0-AD7 change to carrying data. A latchsimply consists of a D-type flip-flop with additional logic toselect when to read and output data.


Latches and flip-flops

D CK Q QX 0 N

Q NQ0 1 0 11 1 1 0

S R D CK Q Q1 1 1 ↑ 1 01 1 0 ↑ 0 11 1 X 0 N

Q NQ1 1 X 1 N

Q NQ0 1 X X 1 01 0 X X 0 10 0 X X • •

D latch

D flip-flop

D Q

CK

Q

Q

Q

S

D

CK

R


Latches(cont.)

❚ Integrated circuits containing many latches (one latch isneeded per bit) are available to perform the latching functionof an address line e.g. 8282, 74LS373.

❚ These packages typically have a single input, called “strobe”(STB), “latch enable” (LE) or “Gate” (G), which qualifies thedata (i.e. passes the data to the flip-flops only when it thestrobe or gate input is high).

❚ Some latches also have an “output enable” (OE) input whichqualifies the output data (when OE is low, the outputs areopen circuit).


8088 Fan-out and Buffers

❚ In order to drive the system buses, which typically have manydevices attached and with large capacitance, the addressand data output pins must be buffered.

❚ A buffer merely amplifies the output current.❚ Demultiplexed pins are already buffered by latches (e.g.

74LS373).❚ Un-multiplexed address pins can be buffered by 74LS245

octal bi-directional buffer and 74LS244 uni-directional buffer.

16

Example: 8088 Fully Buffered Buses

A13

A3

• signals are available from the 8088 in minimum modemode only. They must be derived from the bus controller when the 8088operates in maximum mode.

DT/R, DEN and ALE

Example of busbuffering in 8088(minimum modesystem)

OE

‘373G

A19A18A17A16A15A14

A12A11A10A9

A6

A8A7

A5A4

A2A1A0

BufferedAddress bus

G ‘373 OE

WRRDIO/M Buffered

Control bus‘244

D7D6D5D4D3D2D1D0

BufferedData bus

A7A6A5A4A3A2A1A0

B7B6B5B4B3B2B1B0

8088 A19/S6A18/S5A17/S4A16/S3

A15A14A13A12A11A10A9A8

ALE

AD4

AD0

AD7AD6AD5

AD3AD2AD1

RDIO/M

WR

DT/R DEN G DIR

‘244

OE

OE

17

Bidirectional Buffers

❚ Information is transferred in both directions on the data bus - hence the databus buffer must be bidirectional.

❚ A bidirectional buffer has a “direction” (DIR) input which indicates the directionof data transfer. The direction input to the buffer can be taken from the(data transmit/receive) output of the 8088 (minimum mode system) or buscontroller (maximum mode 8088 system).

❚ Examples of bidirectional buffers include the 74LS245 and 8286.

RDT/

DIREN

Outputs/inputsInputs/outputs


8088 Fan-out and Buffers

❚ The output pins of the 8088 have a limited fan out (the output current canonly drive a finite number of derives and large capacitive loading on theoutput will cause problems with dynamic signals

Logic family Sink current(mA)

Source Current(µA)

fanout from8088

TTL (74XX) -1.6 40 1TTL (74LSXX) -0.4 20 5TTL (74SXX) -2 50 1TTL (74ALSXX) -0.2 20 10CMOS (74HCXX) -0.001 1 10CMOS (CD4XXX) -0.001 1 10NMOS -0.01 10 10

Recommended 8088 Fan-out

Q: Pros and cons of buffer?

19

Example of Basic 8086 System Timing

MEMORY ACCESS TIME

T1 T2 T3 TWAIT T4 T1 T2 T3 TWAIT T4

(4+NWAIT)=TCY (4+NWAIT)=TCY

CLK

ALE

M/IO

S7-S3A19-A16BHE

A19-A16BHE S7-S3ADDR/STATUS

WAIT

READY

WAIT

READY

READY

BUS RESERVERED

FOR DATA INA15-A0 D15-D0

VALID A15-A0 DATA OUT D15-D0

RD

ADDR/DATA

DT/R

DEN

WR


Bus Timing of the 8088

❚ Access to memory and I/O operates in bus-cycles. Bus cycles are periodsof time equal to four system clocking periods (1 clock period is oftencalled a T state). For instance, if the 8088 operates at 5MHz, the buscycle rate (which is maximum rate of data transfer) is at 5/4 MHz.

Example of BUS READ CYCLE

❚ The basic steps of the read cycle (simplified) are:

1. Put memory address on the address bus (T1)

2. Issue a read memory signal (T2-T3)

3. Read the data from the data bus (T3)

)RD(


Bus Timing of the 8088 READ CycleExample - 8088/8086 Read bus cycle (simplified)

VALID ADDRESS

ONE BUS CYCLE

T1 T2 T3 T4

ADDRESS DATA FROM MEMORY

CLK

ADDRESS

ADDRESS/DATA

RD


Bus Timing Diagrams (General)

❚ To transfer data without error on the system bus, the signals in the busmust change and hold the values within a certain period of time in a buscycle.

❚ Physically, a system bus consists of conducting wires or tracks on circuitboard. These have distributed inductance and capacitance which tend todistort the signal waveforms.

❚ Long system buses can have clock skew (there is a delay in signalsreceived by distant peripherals - and their clock is slightly out of phasewith the clock received by the microprocessor).

❚ The rise-time, fall-time, and duration of signals must be within thespecifications of the device or microprocessor - otherwise errors will occurin transferring data. The manufacturer’s data sheet contain importantinformation on the timing requirements which can be quite demanding.


Bus Cycle Operation

❚ T1 - start of bus cycle. Actions include setting control signals (or S0-S2status lines) to give the required values for ALE, and , and putting a valid address onto the address bus.

RDT/ IO/M

❚ T2 - the or control signals are issued, is asserted and in the case of a write, data is put onto the data bus. The turns on the data bus buffers to connect the cpu to the external data bus. The READY input to the cpu is sampled at the end of T2 andif READY is low, a wait state TW (one or more) is inserted before T3begins.

WRRD DENDEN


Bus Cycle Operation

❚ T3 - this clock period is provided to allow memory to access the data. Ifthe bus cycle is a read cycle, the data bus is sampled at the end ofT3.

❚ T4 - all bus signals are deactivated in preparation for the next clock cycle. The 8088 also finishes sampling the data (in a read cycle) inthis period. For the write cycle, the trailing edge of the signal transfers data to the memory or I/O, which activates and write when returns to logic 1 level.

WR

WR


Read Cycle Timing

❚ The most important information contained in the read timing diagram is theamount of the time allowed for getting data from memory.

❚ Memory chips usually have a specified memory access time.❚ The memory access time is defined as the interval from when a valid

address is put on the address bus (near the start of T1) to the time when thedata is read (near the end of T3). The permitted memory access time istherefore less than three T states if no wait states are added.

❚ To find the exact access time permitted by the read timing diagram:1. Find the maximum interval necessary for a valid address to appear after the

start of T1. This interval is given the symbol TCLAV (clock-to-address valid)the microprocessor data sheet (For a 5MHz 8088, TCLAV=110ns)


Read Cycle Timing (cont.)

2. Valid data must appear on the data bus before the end of T3 in order toallow the data to be read. The minimum time interval before the end of T3for valid data to appear is given the symbol TDVCL (data valid-to clock)and is specified as 30ns for the 5MHz 8088.

3. The maximum memory access time=3T-TCLAV-TDVCL which, for the5MHz 8088, is 600-110-30=460ns. Actually the memory access time mustbe less than this since there will be propagation delays in going throughbuffers (about another 40ns).

Read Cycle Timing Information fromData Sheet


Bus Timing of 8088 Write Bus Cycle

VALID ADDRESS

ONE BUS CYCLE

T1 T2 T3 T4

ADDRESS DATA WRITE TO MEMORY

CLK

ADDRESS

ADDRESS/DATA

WR


❚ Write bus cycle (simplified) consists of :1. Put memory address on the address bus (T1)2. Issue a write to memory signal (T2-T3)3. Send data to data bus (T2-T3) and write to memory

❚ Actual (non-simplified) read and write bus cycle include changes on othersignals such as M/IO, ALE, DEN, DT/R and READY. The actual cycleswill be investigated in detail later.

❚ T4 in the bus cycle is used to deactivate all the signals in preparation forthe next bus cycle (it is also the time when the 8088 samples the READYsignal to see if extra wait states are needed)

Example - 8088/8086 Write BusCycle (simplified)

)(WR


Write Cycle Timing❚ Write cycle is very similar to the read cycle. Main differences are

1. Strobe is replaced by 2. Data bus contains data for memory rather than data from memory 3. =1instead of =0

❚ The most critical of the write timing diagram is the time interval betweenthe point when becomes logic 1 and the time when data are removedfrom the data bus, since data are only written after the trailing edge of thestrobe. This critical time interval is given the label TWHDX and isspecified as 88ns for 5MHz 8088.

RD WR

RDT/ RDT/

WR


Write Cycle Timing

TW

TCLAX

T1 T2 T3 T4

VCH

VCL

CLK(8284 Output)

AD7-AD0

DEN

WR

WRITE CYCLENOTE 1

TCH1CH2 TCL2CL1

TCLAVTCLDV TCHDX

TCVCTV AD0TCVCTV

TCVCTV

TWLWH

TCVCTX

TWHDX

AD7-AD0 DATA OUT


READY and the WAIT state❚ If the access time for a memory device is longer than the memory

access time calculated, need to give extra clock periods, wait stateTw, for memory.

❚ The READY input is sampled at the end of T2 and again, if applicable,in the middle of Tw. If READY is a logic 0 on 1-to-0 clock transition,then Tw is inserted between T2 and T3. And will check for logic 1 on0-to-1 clock transition in the middle of Tw to see if it shall go back T3.

❚ During the wait state, signals on the buses remain the same as theywere at the start of the WAIT state.

❚ By having the WAIT state, slow memory and devices has at least onemore cycle (200ns for 5 MHz 8088) to get its data output.

❚ The READY signal is synchronized by the clock generator 8284A.


READY and RDY input timing

CLK

READY

T2 TW T3

8ns 30ns

CLK

RDY

T2 TW T3

35ns0ns

(b) 8284 RDY Input Timing

(a) 8088/86 READY Input Timing


Maximum Mode Bus Buffering andDemultiplexing

❚ 8288 bus controller generates control signals needed by interrupt controllersand peripheral devices (memory)

8284A

RDY

CLK READY RESET

8088

AD0-AD7 A8-A19

CLK

8288

STB LS373

DIR

LS245

WAIT STATEGENERATOR

RES

GND0S1S2S

0S1S2S

DEN

ALEDT/R

E

GND

Vcc

ADDR

DATA


Vcc

NC

GND

GND

Address/data Address

Data

IR0-7

MXMN/ 0S 1SCLK 2SREADYRESET

8088MPU

70 ADAD − 198 AA −

INTR

T

OE 8286

Transceiver

EN

8259A Interrupt controller

INT

STB

OE

8282 Latch (1, 2 or 3)

WEOE

2142 RAM (2)

OE

27162 PROM

CS WR RD

Peripheral

8284ARES clock

generator

CLK MRDC

0S MWTC

1S AMWC2S IORC

DEN IOWCRDT/ IOWCA

ALE INTA

Maximum Mode System BlockDiagram

GND

NC

8288Bus Ctrl


8088/8086 (maximum mode)Read Bus Cycle (detailed)

Bus master (8088) actions Slave (memory) ActionsS0-S2 changed for ALEOutput A0-A19 (ALE asserted) Decode address, negate RDY =0, change to DEN Put data on data busWait until READY asserted Assert RDYRead data from data busset to 111

RDT/

S2-S0

S2-S0

One bus cycle

CLK

S2 S0* S2 S0- S2 S0- InactiveAddress/dataand BHE/S7

BHE, A19-A16S7 - S3 Float

Address/data(AD15-AD0) A15 - A0

Data in D15 - D0*ALE

*MRDC or IORC

*DT/R

*DEN

T1 T4T3T2


8088/8086 (maximum mode)Write Bus Cycle (detailed)

Bus master (8088) actions Slave (memory) ActionsS0-S2 changed for ALEOutput A0-A19 (ALE asserted) Decode address, negate RDY =1, change to DENOutput data onto data busWait until READY asserted Store dataread data, set to 111 Assert RDY

RDT/ S2-S0

S2-S0

Address/data(AD15-AD0)

T1 T4T3T2One bus cycle

CLK

S2 S0* S2 S0* S2 S0* InactiveAddress/dataand BHE/S7

BHE, A19-A16S7 - S3 Float

*ALE

*AMWC or AIOWC

A15 - A0 Data in D15 - D0

*MWTC or IOWC*DEN

M. Krishna Kumar MAM/M1/LU4/V1/2004 1

Pin Diagram of 8085

20

19181716

1514

13

1211

1

2345678

910

21

2223

242526272829

30

403938373635343332

31

8085 A

VSS

AD7

AD6

AD5

X1X2

OUTSODSIDTRAPRST 7.5RST 6.5RST 5.5INTR_____

INTAAD0

AD1

AD2

AD3

AD4

RESET

A8

VccHOLDHLDACLK ( OUT) _________________

RESET IN

S1___

RD

ALES0

READY __

IO / M

___

WR

A9

A10

A11

A15

A14

A13

A12

Serial i/p, o/p signals

DMA


Signal Groups of 8085

Multiplexed address / data bus

GND

VssVcc

+ 5 V

X1 X2

XTAL

4

5

SOD

SID

RESET OUT CLK OUT

____

WR

____

RD

___

IO / M

S0

S1

ALE

A8

A15High order Address bus

AD0

AD7

HLDA______

INTA

READYHOLD ______________

RESET IN

INTRRESET 5.5RESET 6.5RESET 7.5

TRAP


GND

+5V

X1

X2

TIMING AND CONTROLCLK

GEN

CLK OUT READY

CONTROL

RD

ALE

S0 S1 RESET OUT

IO / M HOLD HLDA

DMASTATUS

RESET IN

ARITHEMETIC LOGIC UNIT ( ALU)

(8)

ACCUMULATOR TEMP REG(8)

(8)

FLAG ( 5)

FLIP FLOPS

INTERRUPT CONTROL SERIAL I / O CONTROL

SID SIOTRAP

INTR

INTA RES

5 . 5

RES

6 . 5

RES

7 . 5

8 BIT INTERNAL DATA BUS

INSTRUCTION REGISTER ( 8 )

MULTIPLXER

R

E

G.

S

E

L

E

C

T

ADDRESS BUFFER ( 8 )

DATA / ADDRESS BUFFER ( 8 )

INSTRUCTION DECODER AND MACHINE ENCODING

W ( 8 )

TEMP . REG.B REG ( 8 )

D REG ( 8 )H REG ( 8 )

STACK POINTERPROGRAM COUNTER ( 16 )INCREAMENT / DECREAMENT

ADDRESS LATCH ( 16 )

( 16 )

AD7 – AD0 ADDRESS / BUFFER BUS

A 15 – A8 ADDRESS BUS

C REG ( 8 )

E REG ( 8 )L REG ( 8 )

WR


CYPACS Z

D0D1D2D3D4D5D6D7

Flag Registers

General Purpose RegistersINDIVIDUAL

COMBININATON

B, C, D, E, H, L

B & C, D & E, H & L


AH AL

BH BL

CH CL

DH DL

SP

BP

SI

DI

ES

CS

SS

DS

IP

1

∑ADDRESS BUS

( 20 ) BITS

DATA BUS

( 16 ) BITS

BUS

CONTROL LOGIC

8

0

8

6

BUS

2 3 4 65

INSTRUCTION QUEUE

8 BIT

Q BUS

EU CONTROL SYSTEM

ALU DATA BUS

16 BITS

TEMPORARY REGISTERS

ALU

FLAGS

GENERAL REGISTERS

EXECUTION UNIT ( EU )

BUS INTERFACE UNIT ( BIU)

Fig:


20

19181716

1514

13

1211

1

2345678

910

21

2223

242526272829

30

403938373635343332

31

8086

CPU

GND

CLK

INTR

NMI

GNDAD14

AD13

AD12

AD11

AD10

AD9AD8AD7

AD6

AD5

AD4

AD3

AD2

AD1

AD0

RESET

VCC

AD15

A16 / S3

A17 / S4

____

MN/MX___

RD

_______

LOCK

A19/S6

___

(WR)

READY

______

TEST

QS1

____

S2___

S1 _____

(DEN)(ALE)

A18 / S5

_____

BHE / S7

_____ _____

RQ / GT0 ( HOLD)___ _____

RQ / GT1 ( HLDA)____

(M / IO )___

(DT / R)___

S0 QS0 ________

(INTA)

Pin Diagram of 8086


CLK

GNDVCC

8086

MPU

INTR_____

INTA

______

TEST

NMI

RESET

HOLD

HLDA

VCC

____

MN / MX

INTERRUPT

INTERFACE

DMA

INTERFACE

MODE SELECT READY

_____

DEN

_____

WR

____

RD

__

DT / R

__

M / IO

ALE___

BHE / S7

MEMORY I / O

CONTROLS

D0 - D15

A0 - A15, A16 / S3 – A19/S6

ADDRESS / DATA BUS


Signal Description of 8086

• The Microprocessor 8086 is a 16-bit CPU available in different clock rates and packaged in a 40 pin CERDIP or plastic package.

• The 8086 operates in single processor or multiprocessor configuration to achieve high performance. The pins serve a particular function in minimum mode (single processor mode ) and other function in maximum mode configuration (multiprocessor mode ).

• The 8086 signals can be categorised in three groups. The first are the signal having common functions in minimum as well as maximum mode.


• The second are the signals which have special functions for minimum mode and third are the signals having special functions for maximum mode.

• The following signal descriptions are common for both modes.• AD15-AD0 : These are the time multiplexed memory I/O

address and data lines.• Address remains on the lines during T1 state, while the data is

available on the data bus during T2, T3, Tw and T4.• These lines are active high and float to a tristate during

interrupt acknowledge and local bus hold acknowledge cycles.

Signal Description of 8086 (cont..)


• A19/S6,A18/S5,A17/S4,A16/S3 : These are the time multiplexed address and status lines.

• During T1 these are the most significant address lines for memory operations.

• During I/O operations, these lines are low. During memory or I/O operations, status information is available on those lines for T2,T3,Tw and T4.

• The status of the interrupt enable flag bit is updated at the beginning of each clock cycle.



• The S4 and S3 combinedly indicate which segment register is presently being used for memory accesses as in below fig.

• These lines float to tri-state off during the local bus hold acknowledge. The status line S6 is always low .

• The address bit are separated from the status bit using latches controlled by the ALE signal.

Alternate DataStack

Code or noneData

Indication S4 S3

0011

0

01

1



• BHE/S7 : The bus high enable is used to indicate the transfer of data over the higher order ( D15-D8 ) data bus as shown in table. It goes low for the data transfer over D15-D8 and is used to derive chip selects of odd address memory bank or peripherals. BHE is low during T1 for read, write and interrupt acknowledge cycles, whenever a byte is to be transferred on higher byte of data bus. The status information is available during T2, T3 and T4. The signal is active low and tristated during hold. It is low during T1 for the first pulse of the interrupt acknowledge cycle.

Upper byte from or to odd addressWhole word0

01

0

01

Lower byte from or to even addressUpper byte from or to even address

None

Indication BHE A0

1 1



• RD – Read : This signal on low indicates the peripheral that the processor is performing s memory or I/O read operation. RD is active low and shows the state for T2, T3, Tw of any read cycle. The signal remains tristated during the hold acknowledge.

• READY : This is the acknowledgement from the slow device or memory that they have completed the data transfer. The signal made available by the devices is synchronized by the 8284A clock generator to provide ready input to the 8086. the signal is active high.



• INTR-Interrupt Request : This is a triggered input. This is sampled during the last clock cycles of each instruction to determine the availability of the request. If any interrupt request is pending, the processor enters the interrupt acknowledge cycle.

• This can be internally masked by resulting the interrupt enable flag. This signal is active high and internally synchronized.

• TEST : This input is examined by a ‘WAIT’ instruction. If the TEST pin goes low, execution will continue, else the processor remains in an idle state. The input is synchronized internally during each clock cycle on leading edge of clock.



• NMI- Nonmaskable interrupt : This is an edge triggered input which causes a Type 2 interrupt. The NMI is not maskable internally by software. A transition from low to high initiates the interrupt response at the end of the current instruction. This input is internally synchronized.

• RESET : This input causes the processor to terminate the current activity and start execution from FFF0H. The signal is active high and must be active for at least four clock cycles. It restarts execution when the RESET returns low. RESET is also internally synchronized.

• Vcc +5V power supply for the operation of the internal circuit.• GND ground for internal circuit.



• CLK- Clock Input : The clock input provides the basic timing for processor operation and bus control activity. Its an asymmetric square wave with 33% duty cycle.

• MN/MX : The logic level at this pin decides whether the processor is to operate in either minimum or maximum mode.

• The following pin functions are for the minimum modeoperation of 8086.

• M/IO – Memory/IO : This is a status line logically equivalent to S2 in maximum mode. When it is low, it indicates the CPU is having an I/O operation, and when it is high, it indicates that the CPU is having a memory operation. This line becomes active high in the previous T4 and remains active till final T4 of the current cycle. It is tristated during local bus “hold acknowledge “.



• INTA – Interrupt Acknowledge : This signal is used as a read strobe for interrupt acknowledge cycles. i.e. when it goes low, the processor has accepted the interrupt.

• ALE – Address Latch Enable : This output signal indicates the availability of the valid address on the address/data lines,and is connected to latch enable input of latches. This signal is active high and is never tristated.

• DT/R – Data Transmit/Receive: This output is used to decide the direction of data flow through the transreceivers (bidirectional buffers). When the processor sends out data, thissignal is high and when the processor is receiving data, this signal is low.



• DEN – Data Enable : This signal indicates the availability of valid data over the address/data lines. It is used to enable thetransreceivers ( bidirectional buffers ) to separate the data from the multiplexed address/data signal. It is active from the middle of T2 until the middle of T4. This is tristated during ‘hold acknowledge’ cycle.

• HOLD, HLDA- Acknowledge : When the HOLD line goes high, it indicates to the processor that another master is requesting the bus access.

• The processor, after receiving the HOLD request, issues the hold acknowledge signal on HLDA pin, in the middle of the next clock cycle after completing the current bus cycle.



• At the same time, the processor floats the local bus and control lines. When the processor detects the HOLD line low, it lowers the HLDA signal. HOLD is an asynchronous input, and is should be externally synchronized.

• If the DMA request is made while the CPU is performing a memory or I/O cycle, it will release the local bus during T4provided :

1. The request occurs on or before T2 state of the current cycle.2. The current cycle is not operating over the lower byte of a

word. 3. The current cycle is not the first acknowledge of an interrupt

acknowledge sequence.



4. A Lock instruction is not being executed.• The following pin function are applicable for maximum

mode operation of 8086.• S2, S1, S0 – Status Lines : These are the status lines which

reflect the type of operation, being carried out by the processor. These become activity during T4 of the previous cycle and active during T1 and T2 of the current bus cycles.

1 1

S2 S1 S0 Indication0

1

000

111

1

11

1

1

1

00 0

0

0

000

Interrupt AcknowledgeRead I/O portWrite I/O portHaltCode Access

PassiveWrite memoryRead memory

1 1



• LOCK : This output pin indicates that other system bus master will be prevented from gaining the system bus, while the LOCK signal is low.

• The LOCK signal is activated by the ‘LOCK’ prefix instruction and remains active until the completion of the next instruction. When the CPU is executing a critical instruction which requires the system bus, the LOCK prefix instruction ensures that other processors connected in the system will not gain the control of the bus.

• The 8086, while executing the prefixed instruction, asserts thebus lock signal output, which may be connected to an external bus controller.



• QS1, QS0 – Queue Status: These lines give information about the status of the code-prefetch queue. These are active during the CLK cycle after while the queue operation is performed.

• This modification in a simple fetch and execute architecture of a conventional microprocessor offers an added advantage of pipelined processing of the instructions.

• The 8086 architecture has 6-byte instruction prefetch queue. Thus even the largest (6-bytes) instruction can be prefetched from the memory and stored in the prefetch. This results in a faster execution of the instructions.

• In 8085 an instruction is fetched, decoded and executed and only after the execution of this instruction, the next one is fetched.



• By prefetching the instruction, there is a considerable speedingup in instruction execution in 8086. This is known as instruction pipelining.

• At the starting the CS:IP is loaded with the required address from which the execution is to be started. Initially, the queue will be empty an the microprocessor starts a fetch operation to bring one byte (the first byte) of instruction code, if the CS:IP address is odd or two bytes at a time, if the CS:IP address is even.

• The first byte is a complete opcode in case of some instruction (one byte opcode instruction) and is a part of opcode, in case of some instructions ( two byte opcode instructions), the remaining part of code lie in second byte.



• But the first byte of an instruction is an opcode. When the first byte from the queue goes for decoding and interpretation, one byte in the queue becomes empty and subsequently the queue is updated.

• The microprocessor does not perform the next fetch operation till at least two bytes of instruction queue are emptied. The instruction execution cycle is never broken for fetch operation.After decoding the first byte, the decoding circuit decides whether the instruction is of single opcode byte or double opcode byte.

• If it is single opcode byte, the next bytes are treated as data bytes depending upon the decoded instruction length, otherwise, the next byte in the queue is treated as the second byte of the instruction opcode.



• The second byte is then decoded in continuation with the first byte to decide the instruction length and the number of subsequent bytes to be treated as instruction data.

• The queue is updated after every byte is read from the queue but the fetch cycle is initiated by BIU only if at least two bytes of the queue are empty and the EU may be concurrently executing the fetched instructions.

• The next byte after the instruction is completed is again the first opcode byte of the next instruction. A similar procedure is repeated till the complete execution of the program.



• The fetch operation of the next instruction is overlapped with the execution of the current instruction. As in the architecture, there are two separate units, namely Execution unit and Bus interface unit.

• While the execution unit is busy in executing an instruction, after it is completely decoded, the bus interface unit may be fetching the bytes of the next instruction from memory, depending upon the queue status.

QS1 QS0 Indication0

1 11

10

00

No operationFirst byte of the opcode from the queueEmpty queueSubsequent byte from the queue



• RQ/GT0, RQ/GT1 – Request/Grant : These pins are used by the other local bus master in maximum mode, to force the processor to release the local bus at the end of the processor current bus cycle.

• Each of the pin is bidirectional with RQ/GT0 having higher priority than RQ/GT1.

• RQ/GT pins have internal pull-up resistors and may be left unconnected.

• Request/Grant sequence is as follows:1. A pulse of one clock wide from another bus master requests

the bus access to 8086.



2. During T4(current) or T1(next) clock cycle, a pulse one clock wide from 8086 to the requesting master, indicates that the 8086 has allowed the local bus to float and that it will enter the ‘hold acknowledge’ state at next cycle. The CPU bus interface unit is likely to be disconnected from the local bus of the system.

3. A one clock wide pulse from the another master indicates to the 8086 that the hold request is about to end and the 8086 may regain control of the local bus at the next clock cycle. Thus each master to master exchange of the local bus is a sequence of 3 pulses. There must be at least one dead clock cycle after each bus exchange.



• The request and grant pulses are active low.• For the bus request those are received while 8086 is

performing memory or I/O cycle, the granting of the bus is governed by the rules as in case of HOLD and HLDA in minimum mode.



General Bus Operation

• The 8086 has a combined address and data bus commonly referred as a time multiplexed address and data bus.

• The main reason behind multiplexing address and data over the same pins is the maximum utilisation of processor pins and it facilitates the use of 40 pin standard DIP package.

• The bus can be demultiplexed using a few latches and transreceivers, when ever required.

• Basically, all the processor bus cycles consist of at least fourclock cycles. These are referred to as T1, T2, T3, T4. The address is transmitted by the processor during T1. It is present on the bus only for one cycle.


• During T2, i.e. the next cycle, the bus is tristated for changing the direction of bus for the following data read cycle. The datatransfer takes place during T3, T4.

• In case, an address device is slow ‘NOT READY’ status the wait status Tw are inserted between T3 and T4. These clock states during wait period are called idle states (Ti), wait states(Tw) or inactive states. The processor used these cycles for internal housekeeping.

• The address latch enable (ALE) signal is emitted during T1 by the processor (minimum mode) or the bus controller (maximum mode) depending upon the status of the MN/MX input.

General Bus Operation ( cont..)


• The negative edge of this ALE pulse is used to separate the address and the data or status information. In maximum mode, the status lines S0, S1 and S2 are used to indicate the type of operation.

• Status bits S3 to S7 are multiplexed with higher order address bits and the BHE signal. Address is valid during T1 while status bits S3 to S7 are valid during T2 through T4.



General Bus Operation Cycle in Maximum Mode

CLK

Memory read cycle Memory write cycleT1 T2 T3 Tw T4 T1 T2 T3 Tw T4

ALE

S2 – S0

Add/stat

WR

DEN

DT/R

READY

RD/INTA

Add/data

A19-A16 S3-S7 A19-A16 S3-S7

BHE BHE

A0-A15 D15-D0 A0-A15 D15-D0

Bus reserveData Out D15 – D0

Wait Wait

ReadyReady

Memory access time

for Data In

Systems Design & Programming Memory I CMPE 310

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Memory TypesTwo basic types:• ROM: Read-only memory• RAM: Read-Write memory

Four commonly used memories:• ROM• Flash (EEPROM)• Static RAM (SRAM)• Dynamic RAM (DRAM)

Generic pin configuration:

A0 A1 AN

O0 O1 ON

Address connection

Output/Input-output connection

...

...

WEWrite

OE

CS

Read

Select


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Memory ChipsThe number of address pins is related to the number of memory locations.

Common sizes today are 1K to 256M locations.Therefore, between 10 and 28 address pins are present.

The data pins are typically bi-directional in read-write memories.The number of data pins is related to the size of the memory location.For example, an 8-bit wide (byte-wide) memory device has 8 data pins.Catalog listing of 1K X 8 indicate a byte addressable 8K memory.

Each memory device has at least one chip select (CS) or chip enable (CE) orselect (S) pin that enables the memory device.

This enables read and/or write operations.If more than one are present, then all must be 0 in order to perform aread or write.


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Memory ChipsEach memory device has at least one control pin.

For ROMs, an output enable (OE) or gate (G) is present.The OE pin enables and disables a set of tristate buffers.

For RAMs, a read-write (R/W) or write enable (WE) and read enable (OE)are present.

For dual control pin devices, it must be hold true that both are not 0at the same time.

ROM:Non-volatile memory: Maintains its state when powered down.There are several forms:ROM: Factory programmed, cannot be changed. Older style.PROM: Programmable Read-Only Memory.

Field programmable but only once. Older style.EPROM: Erasable Programmable Read-Only Memory.

Reprogramming requires up to 20 minutes of high-intensity UV lightexposure.


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Memory ChipsROMs (cont):

Flash EEPROM: Electrically Erasable Programmable ROM.Also called EAROM (Electrically Alterable ROM) and NOVRAM(NOn-Volatile RAM).

Writing is much slower than a normal RAM.

Used to store setup information, e.g. video card, on computer sys-tems.

Can be used to replace EPROM for BIOS memory.


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EPROMsIntel 2716 EPROM (2K X 8):

A7 VCC

2K x 8 EPROM

123456789

2019181716151413

10

2716

1112

21222324

A6A5A4A3A2A1A0

GND

O0O1O2

A8A9VPPCSA10PD/PGMO7O6O5O4O3

Pin(s) Function

A0-A10

PD/PGM

CS

O0-O7

AddressPower down/Program

Chip Select

Outputs

Chip SelectPWR DownProg Logic

YDecoder

XDecoder

CSPD/PGM

Add

ress

Inpu

ts

Data Outputs

OutputBuffers

Y-Gating

16,384Cell Matrix

VPP is used to program the deviceby applying 25V and pulsing PGMwhile holding CS high.


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EPROMs2716 Timing diagram:

Sample of the data sheet for the 2716 A.C. Characteristics.

This EPROM requires a wait state for use with the 8086 (460ns constraint).

Symbol ParameterLimits

Unit Test ConditionMin Typ. Max

tACC1 Addr. to Output Delay 250 450 ns PD/PGM= CS =VIL

tOH Addr. to Output Hold 0 ns PD/PGM= CS =VIL

tDF Chip Deselect to Output Float 0 100 ns PD/PGM=VIL

... ... ... ... ... ... ...

Read Mode (PD/PGM =VIL)

Address

CS

High ZData Out Valid

tACC1

tOH

tDF


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SRAMsTI TMS 4016 SRAM (2K X 8):

Virtually identical to the EPROM with respect to the pinout.However, access time is faster (250ns).

See the timing diagrams and data sheets in text.SRAMs used for caches have access times as low as 10ns.

A7 VCC

2K x 8 SRAM

123456789

2019181716151413

10

TM

S401

6

1112

21222324

A6A5A4A3A2A1A0

GND

DQ1DQ2DQ3

A8A9WGA10SDQ8DQ7DQ6DQ5DQ4

Pin(s) FunctionA0-A10

DQ0-DQ7

G (OE)

S (CS)

AddressData In/Data Out

Read Enable

Chip Select

W (WE) Write Enable


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DRAMsDRAM:

SRAMs are limited in size (up to about 128K X 8).DRAMs are available in much larger sizes, e.g., 64M X 1.

DRAMs MUST be refreshed (rewritten) every 2 to 4 msSince they store their value on an integrated capacitor that losescharge over time.

This refresh is performed by a special circuit in the DRAM whichrefreshes the entire memory using 256 reads.

Refresh also occurs on a normal read, write or during a specialrefresh cycle.

More on this later.

The large storage capacity of DRAMs make it impractical to add therequired number of address pins.

Instead, the address pins are multiplexed.


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DRAMsTI TMS4464 DRAM (64K X 4):

The TMS4464 can store a total of 256K bits of data.

It has 64K addressable locations which means it needs 16 addressinputs, but it has only 8.

The row address (A0 through A7) are placed on the address pins and

strobed into a set of internal latches.The column addres (A8 through A15) is then strobed in using CAS.

A2

VDD

64K x 4 DRAM

123456789

181716151413

10

TM

S446

4

1112

A3A7

WRAS

A6A5A4

VSS

DQ2

DQ1

DQ3

DQ4Pin(s) FunctionA0-A7

DQ0-DQ4

CAS

RAS

AddressData In/Data Out

Column Address Strobe

Row Address Strobe

G Output Enable

G

A1

A0

CAS

W Write Enable


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DRAMsTI TMS4464 DRAM (64K X 4) Timing Diagram:

CAS also performs the function of the chip select input.

Row

RAS

CAS

Column Dont care

Something is inconsistenthere (see MUX below).

A0 A8 A1 A9 A2 A10 A3 A11 A4 A12A5 A13A6 A14 A7 A15

1A 1B 2A 2B 3A 3B 4A 4B 1A 1B 2A 2B 3A 3B 4A 4BRAS

A0

74157 (2-to-1MUX)

A1 A2 A3 A4 A5 A6 A7

1Y 2Y 3Y 4Y 1Y 2Y 3Y 4Y

Address BUS

Inputs to DRAM

0: latch A to Y1: latch B to Y

S S 74157 (2-to-1MUX)


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DRAMsLarger DRAMs are available which are organized as 1M X 1, 4M X 1, 16M X1, 64M X 1 (with 256M X 1 available soon).

DRAMs are typically placed on SIMM (Single In-line Memory Modules)boards.

30-pin SIMMs come in 1M X 8, 1M X 9 (parity), 4M X 8, 4M X 9.72-pin SIMMs come in 1/2/3/8/16M X 32 or 1M X 36 (parity).

5 10 15 20 25 30 35 40 45 50 55 60 65 70

NC

++

VSSVCC DQ0-31

Addr0-11 RASCAS

WPD1-4


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DRAMsPentiums have a 64-bit wide data bus.

The 30-pin and 72-pin SIMMs are not used on these systems.Rather, 64-bit DIMMs (Dual In-line Memory Modules) are the standard.

These organize the memory 64-bits wide.The board has DRAMs mounted on both sides and is 168 pins.

Sizes include 2M X 64 (16M), 4M X 64 (32M), 8M X 64 (64M) and 16M X64 (128M).

The DIMM module is available in DRAM, EDO and SDRAM (andNVRAM) with and without an EPROM.

The EPROM provides information abou the size and speed of thememory device for PNP applications.

Systems Programming 8086/88 Memory Interface II CMPE 310

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Memory Address DecodingThe processor can usually address a memory space that is much larger than the memory space covered by an individual memory chip.

In order to splice a memory device into the address space of the processor, decoding is necessary.

For example, the 8088 issues 20-bit addresses for a total of 1MB of memory address space.

However, the BIOS on a 2716 EPROM has only 2KB of memory and 11 address pins.

A decoder can be used to decode the additional 9 address pins and allow the EPROM to be placed in any 2KB section of the 1MB address space.



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Memory Address Decoding

A0A1

A10

O0O1

O7

... ...

CS

RD of 8088/86

2716

IO/M

A19

A18

A17

A16

A15

A14

A13

A12

A11

Address Bus Data Bus

Logic 0 when A11 through A19 are all 1.

Or MRDC bus signal.

(2K X 8)(Book showsOE connectionfor RD butchip definitiondoes NOT have

EPROM

this pin).



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Memory Address DecodingTo determine the address range that a device is mapped into:

This 2KB memory segment maps into the reset location of the 8086/8088 (FFFF0H).

NAND gate decoders are not often used.Rather the 3-to-8 Line Decoder (74LS138) is more common.

1111 1111 1XXX XXXX XXXX

A19 - A11 A10 - A0

1111 1111 1000 0000 0000 (FF800H)

To

1111 1111 1111 1111 1111 (FFFFFH)



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Memory Address DecodingThe 3-to-8 Line Decoder (74LS138)

Note that all three Enables (G2A, G2B, and G1) must be active, e.g. low, low and high, respectively.

Each output of the decoder can be attached to an 2764 EPROM (8K X 8).

G2A

G2BG1

ABC

01234567E

nab

leS

elec

t In

pu

ts

Ou

tpu

ts

InputsOutput

Enable Select

G2A G2B G1 C B A 0 1 2 3 4 5 6 7

1 X X X X X 1 1 1 1 1 1 1 1X 1 X X X X 1 1 1 1 1 1 1 1X X 0 X X X 1 1 1 1 1 1 1 10 0 1 0 0 0 0 1 1 1 1 1 1 10 0 1 0 0 1 1 0 1 1 1 1 1 10 0 1 0 1 0 1 1 0 1 1 1 1 10 0 1 0 1 1 1 1 1 0 1 1 1 10 0 1 1 0 0 1 1 1 1 0 1 1 10 0 1 1 0 1 1 1 1 1 1 0 1 10 0 1 1 1 0 1 1 1 1 1 1 0 10 0 1 1 1 1 1 1 1 1 1 1 1 0



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Memory Address Decoding

The EPROMs cover a 64KB section of memory.

G2A

G2BG1

ABC

01234567

A0

A12O0

O7

......

CS

2764

A16

A17A18A19

A13

A14

A15

CSCS

CSCS

CSCS

CSRD of 8088/86

Data Bus

Address Bus

F2000-F3FFF

F0000-F1FFF

F4000-F5FFF

F6000-F7FFF

F8000-F9FFF

FA000-FBFFF

FC000-FDFFF

FE000-FFFFF

Address spaceF0000H-FFFFFH

A13 through A15 selecta 2764

A16 through A19 enablethe decoder

(8K X 8)

(Not sure about 2764 pinout,text is in error with 2716)

74L

S13

8

EPROM



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Memory Address DecodingYet a third possibility is a PLD (Programmable Logic Device).PLDs come in three varieties:• PLA (Programmable Logic Array)• PAL (Programmable Array Logic)• GAL (Gated Array Logic)

PLDs have been around since the mid-1970s but have only recently appeared in memory systems (PALs have replaced PROM address decoders).

PALs and PLAs are fuse-programmed (like the PROM).Some are erasable (like the EPROM).

A PAL example (16L8) is shown in the text and is commonly used to decode the memory address, particularly for 32-bit addresses generated by the 80386DX and above.



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Memory Address DecodingAMD 16L8 PAL decoder.

It has 10 fixed inputs (Pins 1-9, 11), two fixed outputs (Pins 12 and 19) and 6 pins that can be either (Pins 13-18).

AND/NOR device with logic expressions (outputs) with up to 16 ANDed inputs and 7 ORed product terms.

O3

1234567

15

11

2019

16

16L

8 1718

I4I5I6I7

VCC

I3I2

O6

O8I1

O4O5

O7

98

10121314

I8I9

GND

O2O1I10

;pins 1 2 3 4 5 6 7 8 9 10A19 A18 A17 A16 A15 A14 A13 NC NC GND

;pins 11 12 13 14 15 16 17 18 19 20NC O8 O7 O6 O5 O4 O3 O2 O1 VCC

Equations:/O1 = A19 * A18 * A17 * A16 * /A15 * /A14 * /A13/O2 = A19 * A18 * A17 * A16 * /A15 * /A14 * A13/O3 = A19 * A18 * A17 * A16 * /A15 * A14 * /A13/O4 = A19 * A18 * A17 * A16 * /A15 * A14 * A13/O5 = A19 * A18 * A17 * A16 * A15 * /A14 * /A13/O6 = A19 * A18 * A17 * A16 * A15 * /A14 * A13/O7 = A19 * A18 * A17 * A16 * A15 * A14 * /A13/O8 = A19 * A18 * A17 * A16 * A15 * A14 * A13

Programmed to decode address lines A19 - A13 onto 8 outputs.



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8088 and 80188 (8-bit) Memory InterfaceThe memory systems “sees” the 8088 as a device with:• 20 address connections (A19 to A0).• 8 data bus connections (AD7 to AD0).• 3 control signals, IO/M, RD, and WR.

We’ll look at interfacing the 8088 with:• 32K of EPROM (at addresses F8000H through FFFFFH).• 512K of SRAM (at addresses 00000H through 7FFFFH).

The EPROM interface uses a 74LS138 (3-to-8 line decoder) plus 8 2732 (4K X 8) EPROMs.

The EPROM will also require the generation of a wait state.The EPROM has an access time of 450ns.The 74LS138 requires 12ns to decode.The 8088 runs at 5MHz and only allows 460ns for memory to access data.A wait state adds 200ns of additional time.



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8088 and 80188 (8-bit) EPROM Memory Interface

The 8088 cold starts execution at FFFF0H. JMP to F8000H occurs here.

G2A

G2BG1

ABC

01234567

A0

A11O0

O7

......

CS

2732

A15

A17A18

A19

A12

A13

A14

CSCS

CSCS

CSCS

CS

RD

Data Bus

Address Bus

Address spaceF8000H-FFFFFH

(4K X 8)

(This is the 2732 pinoutas shown in the text.)

74LS138

OE

A16

WAIT

IO/M

5V

1K

To wait state generator



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8088 and 80188 (8-bit) RAM Memory Interface

A0

A14

O0

O7

... ...CS

A18

A19

CSCSCSCS

CSCSCS

OE

IO/M

WE

CSCSCSCS

CSCSCS

A0

A14

O0

O7

... ...

CSOEWE

Data Bus

(32K

X 8

)

WR

A15A16A17

1G 2G

74L

S24

4B

uff

er

RD

G

Dir

74L

S24

5B

D B

uff

er

G2AG2B

G1

ABC

01234567

G2AG2B

G1

ABC

01234567

Address Bus

74L

S13

8

A14

A9A10A11A12A13

1G 2G74

LS

244

Bu

ffer

A8

G2AG2B

G1

ABC

01234567

A6A7

A0A1A2A3A4A5

1G 2G

74L

S24

4B

uff

er

6225

6

(32K

X 8

)62

256

3

2

74L

S13

8

74L

S13

8

4



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8088 and 80188 (8-bit) RAM Memory InterfaceThe 16 62256s on the previous slide are actually SRAMs.

Access times are on order of 10ns.

Flash memory can also be interfaced to the 8088 (see text).However, the write time (400ms !) is too slow to be used as RAM (as shown in the text).

Parity Checking:Parity checking is used to detect single bit errors in the memory.

The current trend is away from parity checking.

Parity checking adds 1 bit for every 8 data bits.• For EVEN parity, the 9th bit is set to yield an even number of 1’s in all 9

bits.• For ODD parity, the 9th bit is set to make this number odd.

For 72-pin SIMMs, the number of data bits is 32 + 4 = 36 (4 parity bits).



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Parity for Memory Error Detection74AS280 Parity Generator/Checker

This circuit generates EVEN or ODD parity for the 9-bit number placed on its inputs.

Typically, for generation, the 9th input bit is set to 0.

This circuit also checks EVEN or ODD parity for the 9-bit number.In this case, the 9th input bit is connected to the 9th bit of memory.For example, if the original byte has an even # of 1’s (with 9th bit at GND), the parity bit is set to 1 (from the EVEN output).

If the EVEN output goes high during the check, then an error occurred.

A

1234567

98

1413

1074

AS2

801112

IEVEN

ODDGND

VCC

NCH

D

FG

BC

E

9-bit parity generator/checker

Number of inputs Athru I that are HIGH

OutputsEVEN ODD

0, 2, 4, 6, 8

1, 3, 5, 7, 9

H L

L H



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Parity for Memory Error Detection

A0

A14

O0

O7

... ...

CS

A18

OE

RESET

WEWR

A15A16A17

RD

G2AG2B

G1

ABC

01234567

74L

S13

8

(32K

X 8

)62

256

A0

A14

O0

O7

... ...

CSOEWE

(32K

X 8

)62

256

6287

(64K

X 1

)

A0

A15

...

CEWE

ABCDEFGHI

ABCDEFGHI

74L

S28

074

LS

280

EVENODD

EVENODD

74L

S74

Q

Q

D

CLK

DODI

Generator

Checker

IO/M

A19

Dat

a B

us

Clear

NMI

Address Bus



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Error DetectionThis parity scheme can only detect a single bit error.• Block-Check Character (BCC) or Checksum.

Can detect multiple bit errors.This is simply the two’s complement sum (the negative of the sum) of the sequence of bytes.

No error occurred if adding the data values and the checksum produces a 0.

For example:

This is not fool proof. If 45 changes to 44 AND 04 changes to 05, the error is missed.

Compute the sum:

Given 4 hex data bytes: 10, 23, 45, 04

102345047C

Invert and add 1

0111 1100 + 11000 0011 + 11000 0100 = 84H

to get checksum byte: 10234504

1 00

Check is made by addingand checking for 00

84

(discard the carry):



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Error Detection• Cyclic Redundancy Check (CRC).

Commonly used to check data transfers in hardware such as harddrives.Treats data as a stream of serial data n-bits long.

The bits are treated as coefficients of a characteristic polynomial, M(X) of the form:

M X( ) bn bn 1– X bn 2– X2

... b1Xn 1–

b0Xn

+ + + + +=

M X( ) 0 0X1

1X2

0X3

0X4

1X5

1X6

0X7

1X8

+ + + + + + + + +=

where b0 is the least significant bit while bn is the most significant bit.

For the 16-bit data stream: 26F0H = 0010 0110 1111 0000

1X9

1X10

1X11

0X12

0X13

0X14

0X15

+ + + + + +

M X( ) 1X2

1X5

1X6

1X8

1X9

1X10

1X11

+ + + + + +=



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Error Detection• Cyclic Redundancy Check (CRC) (cont.)

The CRC is found by applying the following equation.

G(X) is the called the generator polynomial and has special properties.A commonly used polynomial is:

The remainder R(X) is appended to the data block.When the CRC and R(X) is computed by the receiver, R(X) should be zero.

Since G(X) is of power 16, the remainder, R(X), cannot be of order higher than 15.

Therefore, no more than 2 bytes are needed independent of the data block size.

CRCM X( )X

n

G X( )-------------------- Q X( ) R X( )+= =

Q(X) is the quotientR(X) is the remainder

G X( ) X16

X15

X2

1+ + +=



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Error Detection• Cyclic Redundancy Check (CRC)(cont.)

M X( )X16

G X( )------------------------

X27

X26

X25

X24

X22

X21

X18

+ + + + + +

X16

X15

X2

1+ + +-----------------------------------------------------------------------------------------------------------=

X16

X15

X2

1+ + + X27

X26

X25

X24

X22

X21

X18

+ + + + + +

X27

X26

+ X13

X11

++

X25

X24

X22

X21

X18

+ + + +

X25

X24

+ X11

X9

+

X22

X21

X18

+ + X9

+

+

X22

X21

+ X8

X6

++

X18 X

9X

8X

6+ ++

X13+

+ X13

X18

X17

+ X4

X2

+

X17

X13

+

+

X17

X16

+ X3

X+...

X11

X9

X6

X2

X 1+ + + + +

X13

X11

++

X9

X8

X6

X4

X2

+ + + ++

R X( ) X15

X13

X9

X8

X6

X4

X3

X 1+ + + + + + + +=

Final Solution is:

Value appended is the reverse coefficient value 1101 1010 1100 0101 = DAC5H



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Error CorrectionParity, BCC and CRC are only mechanisms for error detection.

The system is halted if an error is found in memory.

Error correction is starting to show up in new systems.SDRAM has ECC (Error Correction Code).

Correction will allow the system can continue operating.If two errors occur, they can be detected but not corrected.Error correction will of course cost more in terms of extra bits.

Error correction is based on Hamming Codes.There is lots of theory here but our focus will be on implementation.The objective is to correct any single bit errors in an 8-bit data byte.

In other words, we need 4 parity bits to correct single bit errors.Note that the parity bits are at bit positions that are powers of 2.

The data bits of the byte are labeled X3, X5, X6, X7, X9, X10, X11 and X12.The parity bits are labeled P1, P2, P4 and P8.



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Error CorrectionHamming Codes (cont).

P1 is generated by computing the parity of X3, X5, X7, X9, X11, X13, X15.

These numbers have a 1 in bit position 1 of the subscript in binary.

0 0 0 00 0 0 10 0 1 00 0 1 10 1 0 00 1 0 10 1 1 00 1 1 11 0 0 01 0 0 11 0 1 01 0 1 11 1 0 01 1 0 11 1 1 01 1 1 1

P1P2

P3

P4

34

210

56789101112131415

1234

P1 is assigned even parity using X3, X5, X7, X9, X11, X13, X15




Note that each data bit is usedin the parity computation of

Given data byte: 11010010

P1 uses blue bits:

Not used since we are correcting byte data.

1 1 0 1 0 0 1 035679101112

P1 even parity is 1.

P2 uses brown bits:

1 1 0 1 0 0 1 035679101112


1 1 0 1 0 0 1 0

1 1 0 1 0 0 1 0

at least 2 P bits.

P3 uses cyan bits:


P4 uses purple bits:




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Error CorrectionHamming Codes (cont).

110110010011Parity encoded data:

If X10 flips from 0 -> 1, then the check gives the location of the bit error as:

1 1 1 1 1 0 0 1 035679101112

P1 even parity is 0. 1 1 1 1 1 0 0 1 0 P2 even parity is now 1. 0 1 1 1 1 0 0 1 0

1 1 1 1 1 0 0 1 0

P3 even parity is 0. P4 even parity is now 1.

Flipped

P

The position of the bit flip is given by:

Since these are NOT 0,there was an error.

P4P3P2P1 is 1010 or 10 decimal.



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Parity for Memory Error CorrectionThe 74LS636 corrects errors by storing 5 parity bits with each byte of data.

The pinout consists of:• 8 data I/O pins• 5 check bit I/O pins• 2 control pins• 2 error outputs

Single error flag (SEF)Double error flag (DEF).

See the text for an example of its use in a circuit.

CB2

1234567

15

11

2019

16

74L

S636 17

18DB2DB3DB4DB5

VCC

DB1DB0

S0

SEFDEF

CB1CB0

S1

98

10121314

DB6DB7

GND

CB3NCCB4

Systems Design & Programming Memory III CMPE 310

1 (Mar. 6, 2002)UMBCU M B C

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8086 - 80386SX 16-bit Memory InterfaceThese machines differ from the 8088/80188 in several ways:• The data bus is 16-bits wide.• The IO/M pin is replaced with M/IO (8086/80186) and MRDC and MWTC

for 80286 and 80386SX.• BHE, Bus High Enable, control signal is added.• Address pin A0 (or BLE, Bus Low Enable) is used differently.

The 16-bit data bus presents a new problem:The microprocessor must be able to read and write data to any 16-bitlocation in addition to any 8-bit location.

The data bus and memory are divided into banks:

FFFFFFFFFFFD

000003000001

8 MB

8 bitsD15-D8

FFFFFEFFFFFC

000002000000

8 MB

8 bits D7-D0

High bank Low bank

Odd bytes Even bytesBHE selects BLE selects



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8086 - 80386SX 16-bit Memory InterfaceBHE and BLE are used to select one or both:

Bank selection can be accomplished in two ways: Separate write decoders for each bank (which drive CS). A separate write signal (strobe) to each bank (which drive WE).

Note that 8-bit read requests in this scheme are handled by the micropro-cessor (it selects the bits it wants to read from the 16-bits on the bus).

There does not seem to be a big difference between these methods althoughthe book claims that there is.

Note in either method that A0 does not connect to memory and bus wire A1

connects to memory pin A0, A2 to A1, etc.

BHE BLE Function0 0 Both banks enabled for 16-bit transfer0 1 High bank enabled for an 8-bit transfer1 0 Low bank enabled for an 8-bit transfer1 1 No banks selected



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80386SX 16-bit Memory Interface (Separate Decoders)

A0

A15

O0

O7

... ...

CS

A20

CSCSCSCS

CSCSCS

M/IO

CSCSCSCS

CSCSCS

A0

A15

O0

O7... ...

CS

BHE

A17

BLE

G2AG2B

G1

ABC

01234567

74LS

138

G2AG2B

G1

ABC

01234567

(64K X 8)62512

374

LS13

8A18A19

A21A22

A23

Dat

a B

us

D0 to D7

D8 to D15

8038

6SX

Sepa

rate

Dec

oder

s

(64K X 8)62512

WE

OE

MWTC

OE

WE

Address BusA1 to A16

G2AG2B

G1

ABC

01234567

74LS

138

MRDC



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Memory InterfacesSee text for Separate Write Strobe scheme plus some examples of the integra-tion of EPROM and SRAM in a complete system.

It is just an application of what we’ve been covering.

80386DX and 80486 have 32-bit data buses and therefore 4 banks of memory.32-bit, 16-bit and 8-bit transfers are accomplished by different combina-tions of the bank selection signals BE3, BE2, BE1, BE0.

The Address bits A0 and A1 are used within the microprocessor to gener-

ate these signals.They are don’t cares in the decoding of the 32-bit address outside thechip (using a PLD such as the PAL 16L8).

The high clock rates of these processors usually require wait states formemory access.

We will come back to this later.



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Pentium Memory InterfaceThe Pentium, Pentium Pro, Pentium II and III contain a 64-bit data bus.

Therefore, 8 decoders or 8 write strobes are needed as well as 8 memorybanks.

The write strobes are obtained by combining the bank enable signals(BEx) with the MWTC signal.

MWTC is generated by combining the M/IO and W/R signals.BE7

BE6

BE5

BE4MWTC

BE3

BE2

BE1

BE0

WR7

WR6

WR5

WR4

WR3

WR2

WR1

WR0

W/R

M/IO



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Pentium Memory Interface

I1I2I3I4I5I6I7I8I9I10

16L8

O1O2O3O4O5O6O7O8

A29A30A31


16L8

O1O2O3O4O5O6O7O8

A19A20A21A22A23A24A25A26A27A28

A0

A15

O0

O7

... ...

CEOE

2751

2

D0-

D7

D8-

D15

D15

-D23

D24

-D31

D56

-D63

D48

-D55

D40

-D47

D32

-D39

A3-A18

MRDC

A0

A15

O0

O7

... ...

CEOE

2751

2

A0

A15

O0

O7

... ...CEOE

2751

2

A0

A15

O0

O7

... ...

CEOE

2751

2

A0

A15

O0

O7

... ...

CEOE

2751

2

A0

A15

O0

O7... ...

CEOE

2751

2

A0

A15

O0

O7

... ...

CEOE

2751

2

A0

A15

O0

O7

... ...

CEOE

2751

2

(64K

X 8

)

WE WE WE WE

WEWEWEWE

WR

0

WR

1

WR

2

WR

3W

R7

WR

6

WR

5

WR

4



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Pentium Memory InterfaceIn order to map previous memory into addr. space FFF80000H-FFFFFFFFH

Use a 16L8 to do the WR0 - WR7 decoding using MWTC and BE0 - BE7.See the text -- Figure 10-35.

;pins 1 2 3 4 5 6 7 8 9 10A29 A30 A31 NC NC NC NC NC NC GND

;pins 11 12 13 14 15 16 17 18 19 20U2 CE NC NC NC NC NC NC NC VCC

Equations:/CE = /U2 * A29 * A30 * A31


16L8

O1O2O3O4O5O6O7O8

A29A30A31


16L8

O1O2O3O4O5O6O7O8

A19A20A21A22A23A24A25A26A27A28

;pins 1 2 3 4 5 6 7 8 9 10A19 A20 A21 A22 A23 A24 A25 A26 A27 GND

;pins 11 12 13 14 15 16 17 18 19 20A28 U2 NC NC NC NC NC NC NC VCC

Equations:/U2 = A19 * A20 * A21 * A22 * A23 * A24 * A25 *

A26 * A27 * A28



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Memory ArchitectureIn order to build an N-word memory where each word is M bits wide (typi-cally 1, 4 or 8 bits), a straightforward approach is to stack memory:

This approach is not practical.What can we do?

S0

S1

S2

SN-2

SN-1

N w

ords

Word 0

Word 1Word 2 Storage cell

Word N-2Word N-1

Input-Output(M bits)

A word is selected by setting exactlyone of the select bits, Sx, high.

This approach works well for smallmemories but has problems for large

For example, to build a 1Mword

memories.

(where word = 8 bits) memory, requires1M select lines, provided by someoff-chip device.



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Memory ArchitectureAdd a decoder to solve the package problem:

This does not address the memory aspect ratio problem:

The memory is 128,000 time higher than wide (220/23) !Besides the bizarre shape factor, the design is extremely slow since the ver-tical wires are VERY long (delay is at least linear to length).

S0

S1

S2

SN-2SN-1

Word 0Word 1Word 2 Storage cell

Word N-2Word N-1


Dec

oder

A0A1

A2

AK-1

K = log2N

one-hot

Bina

ry e

ncod

ed a

ddre

ss

This reduces thenumber of externaladdress pins from1M to 20.


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Memory ArchitectureThe vertical and horizontal dimensions are usually very similar, for an aspectratio of unity.

Multiple words are stored in each row and selected simultaneously:S0

S1

S2

SN-2SN-1

Storage cell


AKAK+1

AK+2

AL-1

Column address =A0

AK-1

Bit line

Word line

A0 to AK-1

Row address =AK to AL-1

A column decoder is added toselect the desired word from a row.

Column decoder

Row

Dec

oder

Sense ampsand driversnot shown


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Memory ArchitectureThis strategy works well for memories up to 64 Kbits to 256 Kbits.Larger memories start to suffer excess delay along bit and word lines.A third dimension is added to the address space to solve this problem:

Global Data bus

RowAddress

ColumnAddressBlockAddress

Block 0 Block i Block P-1

Globalamplifier/driver

I/O

Address: [Row][Block][Col]

Block selector


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Dynamic RAMDRAM requires refreshing every 2 to 4 ms.

Refreshing occurs automatically during a read or write.Internal circuitry takes care of refreshing cells that are not accessed overthis interval.

This special refresh occurs transparently while other memory componentsoperate and is called transparent refresh or cycle stealing.

A RAS-only cycle strobes a row address into the DRAM, obtained by 7- or 8-bit binary counter.

The capacitors are recharged for the selected row by reading the bits outinternally and then writing them back.

For a 256K X 1 DRAM with 256 rows, a refresh must occur every 15.6us(4ms/256).

For the 8086, a read or write occurs every 800ns.This allows 19 memory reads/writes per refresh or 5% of the time.


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Dynamic RAM

A0A1A2A3A4A5A6A7A8RAS

CAS

Dec

oder

Row

Lat

ches

Col

umn

Latc

hes

8

WE

DINDOUT

MU

X

DirA9(A0 from input pin on RAS)A8

S1S0

MUX256-to-1

MUX256-to-1

MUX256-to-1

MUX256-to-1

64K array(256 X 256)

255254

10

64K array(256 X 256)

64K array(256 X 256)

64K array(256 X 256)

256K X 1 DRAM

A0-A7

A10-A17

Block 0Block 1Block 2Block 3

These signals provide the block address.


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EDO and SDRAM MemoryExtended Data Output memory:

Any memory access in an EDO memory (including a refresh) stores the256 bits in a set of latches.

Any subsequent access to bytes in this set are immediately available(without the decode time and therefore wait states).

This works well because of the principle of spatial locality, and improvessystem performance by 15 to 25 % !

Synchronous Dynamic RAM:Access times are 10ns (for use with 66MHz bus) and 8ns (for use with100MHz bus).

Standard DRAM access times are 60ns.

However, these access times only apply to the 2nd, 3rd and 4th 64-bitreads -- the first takes the same time as a standard DRAM.


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EDO and SDRAM MemorySynchronous Dynamic RAM:

However, this improves performance again, particularly for reads intocache block sizes of 256 bits.

For example, 256 bit transfer takes three bus cycles for the first read andthree for the next three 64-bit words, for a total of 7 bus cycles.

This contrasts with the 3*4 or 12 bus cycles for DRAM or EDO.

Measurements show about a 10% increase in performance.

DRAM Controllers:A DRAM controller is usually responsible for address multiplexing andgeneration of the DRAM control signals.

These devices tend to get very complex.We will focus on a simpler device, the Intel 82C08, which can control twobanks of 256K X 16 DRAM memories for a total of 1 MB.


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DRAM Controllers:Intel 82C08:

Microprocessor bits A1 through A18 (18 bits) drive the 9 Address Low

(AL) and 9 Address High (AH) bits of the 82C08.9 of each of these are strobed onto the address wires A0 through A8 to

the memories.

Either RAS0/CAS0 or RAS1/CAS1 are strobed depending on theaddress.

This drives a 16-bit word onto the High and Low data buses (if WE islow) or writes an 8 or 16 bit word into the memory otherwise.

WE (from the 82C08), BHE and A0 are used to determine if a write is to

be performed and which byte(s) (low or high or both) is to be written.

Address bit A20 through A23 along with M/IO enable these memories to

map onto 1 MByte range (000000H-0FFFFFH).


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DRAM Controllers

A0

A8

O0

O7... ...

RASCAS 41

256A

8

WE

(256K X 8)

Low

Dat

a B

usA0

A8

O0

O7

... ...

RASCAS 41

256A

8

WE

A0

A8

O0

O7

... ...

RASCAS 41

256A

8

WE

Hig

h D

ata

BusA0

A8

O0

O7

... ...

RASCAS 41

256A

8WE


16L8

O1O2O3O4O5O6O7O8

A0A20

R1A0

A8

...

AL0

AL8

...

AH0

AH8

...

WRRESETCLKPCTL

RD

PEBSRFRQPD1

RAS0CAS0RAS1CAS1

AA/XAWE

A1

A18

S0S1

A21A22A23

M/IO

A19

R2

WAIT

82C

08

BHE


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DRAM Controllers:16L8 Programming:

;pins 1 2 3 4 5 6 7 8 9 10WE BHE A0 A20 A21 A22 A23 NC NC GND

;pins 11 12 13 14 15 16 17 18 19 20MIO CE NC NC NC NC LWR HWR PE VCC

Equations:

/HWR = /BHE * /WE


16L8

O1O2O3O4O5O6O7O8

A0A20A21A22A23

M/IO/LWR = /A0 * /WE

/PE = /A20 * /A21 * /A22 * /A23 * MIO

WEPEHWRLWR


Pin Diagram of 8085

20

19181716

1514

13

1211

1

2345678

910

21

2223

242526272829

30

403938373635343332

31

8085 A

VSS

AD7

AD6

AD5

X1X2

OUTSODSIDTRAPRST 7.5RST 6.5RST 5.5INTR_____

INTAAD0

AD1

AD2

AD3

AD4

RESET

A8

VccHOLDHLDACLK ( OUT) _________________

RESET IN

S1___

RD

ALES0

READY __

IO / M

___

WR

A9

A10

A11

A15

A14

A13

A12

Serial i/p, o/p signals

DMA


Signal Groups of 8085

Multiplexed address / data bus

GND

VssVcc

+ 5 V

X1 X2

XTAL

4

5

SOD

SID

RESET OUT CLK OUT

____

WR

____

RD

___

IO / M

S0

S1

ALE

A8

A15High order Address bus

AD0

AD7

HLDA______

INTA

READYHOLD ______________

RESET IN

INTRRESET 5.5RESET 6.5RESET 7.5

TRAP


GND

+5V

X1

X2

TIMING AND CONTROLCLK

GEN

CLK OUT READY

CONTROL

RD

ALE

S0 S1 RESET OUT

IO / M HOLD HLDA

DMASTATUS

RESET IN

ARITHEMETIC LOGIC UNIT ( ALU)

(8)

ACCUMULATOR TEMP REG(8)

(8)

FLAG ( 5)

FLIP FLOPS

INTERRUPT CONTROL SERIAL I / O CONTROL

SID SIOTRAP

INTR

INTA RES

5 . 5

RES

6 . 5

RES

7 . 5

8 BIT INTERNAL DATA BUS

INSTRUCTION REGISTER ( 8 )

MULTIPLXER

R

E

G.

S

E

L

E

C

T

ADDRESS BUFFER ( 8 )

DATA / ADDRESS BUFFER ( 8 )

INSTRUCTION DECODER AND MACHINE ENCODING

W ( 8 )

TEMP . REG.B REG ( 8 )

D REG ( 8 )H REG ( 8 )

STACK POINTERPROGRAM COUNTER ( 16 )INCREAMENT / DECREAMENT

ADDRESS LATCH ( 16 )

( 16 )

AD7 – AD0 ADDRESS / BUFFER BUS

A 15 – A8 ADDRESS BUS

C REG ( 8 )

E REG ( 8 )L REG ( 8 )

WR


CYPACS Z

D0D1D2D3D4D5D6D7

Flag Registers

General Purpose RegistersINDIVIDUAL

COMBININATON

B, C, D, E, H, L

B & C, D & E, H & L


AH AL

BH BL

CH CL

DH DL

SP

BP

SI

DI

ES

CS

SS

DS

IP

1

∑ADDRESS BUS

( 20 ) BITS

DATA BUS

( 16 ) BITS

BUS

CONTROL LOGIC

8

0

8

6

BUS

2 3 4 65

INSTRUCTION QUEUE

8 BIT

Q BUS

EU CONTROL SYSTEM

ALU DATA BUS

16 BITS

TEMPORARY REGISTERS

ALU

FLAGS

GENERAL REGISTERS

EXECUTION UNIT ( EU )

BUS INTERFACE UNIT ( BIU)

Fig:


20

19181716

1514

13

1211

1

2345678

910

21

2223

242526272829

30

403938373635343332

31

8086

CPU

GND

CLK

INTR

NMI

GNDAD14

AD13

AD12

AD11

AD10

AD9AD8AD7

AD6

AD5

AD4

AD3

AD2

AD1

AD0

RESET

VCC

AD15

A16 / S3

A17 / S4

____

MN/MX___

RD

_______

LOCK

A19/S6

___

(WR)

READY

______

TEST

QS1

____

S2___

S1 _____

(DEN)(ALE)

A18 / S5

_____

BHE / S7

_____ _____

RQ / GT0 ( HOLD)___ _____

RQ / GT1 ( HLDA)____

(M / IO )___

(DT / R)___

S0 QS0 ________

(INTA)

Pin Diagram of 8086


CLK

GNDVCC

8086

MPU

INTR_____

INTA

______

TEST

NMI

RESET

HOLD

HLDA

VCC

____

MN / MX

INTERRUPT

INTERFACE

DMA

INTERFACE

MODE SELECT READY

_____

DEN

_____

WR

____

RD

__

DT / R

__

M / IO

ALE___

BHE / S7

MEMORY I / O

CONTROLS

D0 - D15

A0 - A15, A16 / S3 – A19/S6

ADDRESS / DATA BUS



• The Microprocessor 8086 is a 16-bit CPU available in different clock rates and packaged in a 40 pin CERDIP or plastic package.

• The 8086 operates in single processor or multiprocessor configuration to achieve high performance. The pins serve a particular function in minimum mode (single processor mode ) and other function in maximum mode configuration (multiprocessor mode ).

• The 8086 signals can be categorised in three groups. The first are the signal having common functions in minimum as well as maximum mode.


• The second are the signals which have special functions for minimum mode and third are the signals having special functions for maximum mode.

• The following signal descriptions are common for both modes.• AD15-AD0 : These are the time multiplexed memory I/O

address and data lines.• Address remains on the lines during T1 state, while the data is

available on the data bus during T2, T3, Tw and T4.• These lines are active high and float to a tristate during

interrupt acknowledge and local bus hold acknowledge cycles.
