Updated Interconnect Proposal Bob Ross, Teraspeed Labs [email protected] Draft Presented...

1

Updated Interconnect Proposal

Bob Ross, Teraspeed [email protected]

Draft Presented September 23, 2015 at the Interconnect Working Group

Copyright 2015 Teraspeed Labs

2Copyright 2015 Teraspeed Labs

Background

• Simplified from earlier presentations from Randy Wolff, Walter Katz, and Interconnect Task Group chair Michael Mirmak:o http://www.eda.org/ibis/summits/may15/wolff2.pdfo http://www.eda.org/ibis/summits/jan15/katz.pdfo http://www.eda.org/ibis/summits/jun14/katz1.pdfo http://www.eda.org/ibis/summits/may14/wolff.pdfo http://www.eda.org/ibis/summits/jan14/katz.pdfo http://www.eda.org/ibis/summits/may13/wolff.pdfo http://www.eda.org/ibis/summits/jan13/mirmak2.pdfo http://www.eda.org/ibis/summits/jan13/katz.pdf

• Terminology simplificationo No model_name supporto No pre-layout distinctiono Simpler I/O buffer that uses existing IBIS syntax

• Note, “I/O” here is generic for all 21 IBIS [Model] Model_types


Goals

• Update the Interconnect proposal Terminal section based on existing IBIS keyword

• Illustrate locations for Buffer, Pad, Pin• Illustrate pin_name, signal_name, bus_label,

and pad_name qualifiers• Illustrate buffer terminals Buffer_I/O, Puref,

Pdref, (and not shown) Pcref, Gcref, Extref• Illustrate rail locations: Buffer_rail (not

shown), Pad_rail, Pin_rail• Show chart of connections rules including

Aggressor


Definition Example[Pin] signal_name model_name R_pin L_pin C_pin A1 DQ1 DQ A2 DQ2 DQ A3 DQ3 DQ D1 DQS+ DQS D2 DQS- DQS P1 VDD POWER P2 VDD POWER P3 VDD POWER P4 VDD POWER P5 VDD POWER G1 VSS GND G2 VSS GND G3 VSS GND G4 VSS GND G5 VSS GND

[Pin Mapping] pulldown_ref pullup_ref gnd_clamp_ref power_clamp_ref ext_ref A1 VSS VDD NC NC A2 VSS VDD NC NC A3 VSS VDD NC NC D1 VSS VDD NC NC D2 VSS VDD NC NC P1 NC VDD P2 NC VDD P3 NC VDD P4 NC VDD P5 NC VDD G1 VSS NC G2 VSS NC G3 VSS NC G4 VSS NC G5 VSS NC

pin_names

signal_names for POWER/GND pins

bus_labels for implicitly shorted pins or on-die shorted connections for POWER/GND pins

POWER bus_labels = signal_names

GND bus_labels = signal_names


Partial Reference Diagram [Pin, Pad, Buffer] (A3, D1, D2

Omitted)Physical Buffer, its Model and On-Die Interconnect

Pads Pins

A1P1P2P3P4P5G1G2G3G4G5A2

Die

A1

A2

Pdref(A2)

Puref(A2)

Pdref(A1)

Puref(A1)

IBIS buffer model

One-to-one Pin-Pad connection is NOT required


Terminal Syntax[Begin Interconnect Model]… | Other syntax

Number_of_terminals = <number> | List follows<term_number> <terminal_type> <qualifier> <name> <Aggressor>*… | More lines…[End Interconnect Model]______________________________________________________

<qualifier>: pin_name, signal_name from [Pin] keyword, or bus_label from [Pin Mapping] keyword,*Optional <Aggressor> for Buffer_I/O

Convention: “shorted” connectionelectrical connection


Legal InterconnectionsTerminal_Type / Qualifier

pin_name

signal_name bus_label pad_name Aggressor

Buffer_I/O X A

Puref X

PdrefX

Pcref X

Gcref X

Extref X

Buffer_rail Y Y

Pad_I/O X

Pad_rail Y Y Z

Pin_I/O X

Pin_rail Y Y Y

X: I/O pin_names, Y,Z: POWER/GND names, Z: from [Die Supply Pads]A: Optional Aggressor column to assign one or more aggressor buffers


Legal Interconnections

• Pin to on-die buffer• Pin to pad• Pad to on-die buffer

• Note, Pin to pad to on-die buffer is illegal since pad terminals are not needed for external connections


Reference Example Repeated[Pin] signal_name model_name R_pin L_pin C_pin A1 DQ1 DQ A2 DQ2 DQ A3 DQ3 DQ D1 DQS+ DQS D2 DQS- DQS P1 VDD POWER P2 VDD POWER P3 VDD POWER P4 VDD POWER P5 VDD POWER G1 VSS GND G2 VSS GND G3 VSS GND G4 VSS GND G5 VSS GND

[Pin Mapping] pulldown_ref pullup_ref gnd_clamp_ref power_clamp_ref ext_ref A1 VSS VDD NC NC A2 VSS VDD NC NC A3 VSS VDD NC NC D1 VSS VDD NC NC D2 VSS VDD NC NC P1 NC VDD P2 NC VDD P3 NC VDD P4 NC VDD P5 NC VDD G1 VSS NC G2 VSS NC G3 VSS NC G4 VSS NC G5 VSS NC

pin_names



POWER bus_labels = signal_names

GND bus_labels = signal_names


With bus_label = signal_name[Pin] signal_name model_name R_pin L_pin C_pin A1 DQ1 DQ A2 DQ2 DQ A3 DQ3 DQ D1 DQS+ DQS D2 DQS- DQS P1 VDD POWER P2 VDD POWER P3 VDD POWER P4 VDD POWER P5 VDD POWER G1 VSS GND G2 VSS GND G3 VSS GND G4 VSS GND G5 VSS GND

pin_names



New optional Bus_signal_name subparameter indicates that POWER/GND signal_name pins are assumed and do not have to be listed

[Pin Mapping] pulldown_ref pullup_ref gnd_clamp_ref power_clamp_ref ext_ref Bus_signal_name A1 VSS VDD NC NC A2 VSS VDD NC NC A3 VSS VDD NC NC D1 VSS VDD NC NC D2 VSS VDD NC NC


Pin-to-Buffer Interconnect Example using pin_names

[Pin Mapping] not needed, all connections are pin-to-buffer

(Similar to [Package] model direct connection to I/O buffer)

Number_of_Terminals = 12 1 Pin_I/O pin_name A1 | I/O Pin 2 Buffer_I/O pin_name A1 | Buffer Model Nodes 3 Puref pin_name A1 4 Pdref pin_name A1 5 Pin_rail pin_name P1 | POWER Pin 6 Pin_rail pin_name G1 | GND Pin | 7 Pin_I/O pin_name A2 | I/O Pin 8 Buffer_I/O pin_name A2 | Buffer Model Nodes 9 Puref pin_name A2 10 Pdref pin_name A2 11 Pin_rail pin_name P2 | POWER Pin 12 Pin_rail pin_name G2 | GND Pin [End Interconnect Model]


Pin-to-Buffer Interconnect Example

Physical Buffer, its Model and On-Die Interconnect

Pads Pins


Die

A1

A2

Pdref(A2)

Puref(A2)

Pdref(A1)

Puref(A1)


Pin-to-Pad, Pad-to-Buffer

• [Die Supply Pad] keywordo Specifies the supply pad names for each supplyo Supports fewer or more pads than pins

• [Die Supply Pad] signal_name bus_label• <pad_name> <name | NC> <name | NC>

• Is bus_label needed??


Pin-to-Pad Example with using pin_names and

pad_names

[Pin Mapping] not needed

[Die Supply Pads] signal_name bus_label P1a VDD NC P2a VDD NC G1a VSS NC G2a VSS NC [End Die Supply Pads]

Number_of_Terminals = 12 1 Pin_I/O pin_name A1 | Pin I/O 2 Pad_I/O pin_name A1 | Pad I/O 3 Pin_rail pin_name P1 | Pin Terminals 4 Pin_rail pin_name_G1 5 Pad_rail pad_name P1a | Pad Terminals 6 Pad_rail pad_name G1a | 7 Pin_I/O pin_name A2 | Pin I/O 8 Pad_I/O pin_name A2 | Pad I/O 9 Pin_rail pin_name P2 | Pin Terminals 10 Pin_rail pin_name_G2 11 Pad_rail pad_name P2a | Pad Terminals 12 Pad_rail pad_name G2a [End Interconnect Model]


Pin-to-Pad Example using pin_names and pad_names


Pads Pins


Die

A1

A2

Pdref(A2)

Puref(A2)

Pdref(A1)

Puref(A1)

P1a, P2a, G1a, G2a


Pad-to-Buffer Example using pad_names and Buffer Nodes



Number_of_Terminals = 12 1 Buffer_I/O pin_name A1 | Buffer Model Nodes 2 Puref pin_name A1 3 Pdref pin_name A1 4 Pad_I/O pin_name A1 | Pad I/O 5 Pad_rail pad_name P1a | Pad Terminals 6 Pad_rail pad_name G1a | 7 Buffer_I/O pin_name A2 | Buffer Model Nodes 8 Puref pin_name A2 9 Pdref pin_name A2 10 Pad_I/O pin_name A2 | Pad I/O 11 Pad_rail pad_name P2a | Pad Terminals 12 Pad_rail pad_name G2a [End Interconnect Model]


Pad-to-Buffer Example using pad_names and Buffer nodesPhysical Buffer, its Model and On-Die Interconnect

Pads Pins


Die

A1

A2

Pdref(A2)

Puref(A2)

Pdref(A1)

Puref(A1)

P1aP2a

G1aG2a


POWER/GND One-to-Several, Several-to-One Illustrations

• Explicit connections available directly from pin_name and pad_name

• No practical way to use signal_name unless signal_name is defined differently for one pin in several-to-one configurations, e.g., signal_names VDDa, VDDb

• No practical way to define different bus_labels for one-to-several configurations

• Next slides illustrate several cases using pin_name and pad_name directly


Pin-to-Pad One-to-SeveralInterconnect Example


Pads Pins


Die

A1

A2

Pdref(A2)

Puref(A2)

Pdref(A1)

Puref(A1)

P1a, P2a, G1a, G2a


Pin-to-Pad Several-to-OneInterconnect Example


Pads Pins


Die

A1

A2

Pdref(A2)

Puref(A2)

Pdref(A1)

Puref(A1)

P1a, P2a, G1a, G2a


Power Rail Interconnect Example using signal_name

[Pin Mapping] optional if bus_labels are signal_names

Number_of_Terminals = 10 1 Pin_I/O pin_name A1 | I/O Pin 2 Buffer_I/O pin_name A1 | Buffer Model Nodes 3 Puref pin_name A1 4 Pdref pin_name A1 5 Pin_rail signal_name VDD | "shorted" POWER Pins 6 Pin_rail signal_name VSS | "shorted" GND Pin | 7 Pin_I/O pin_name A2 | I/O Pin 8 Buffer_I/O pin_name A2 | Buffer Model Nodes 9 Puref pin_name A2 10 Pdref pin_name A2 [End Interconnect Model]


Pin-to-Buffer Interconnect Example using signal_name

for RailsPhysical Buffer, its Model and On-Die Interconnect

Pads Pins


Die

A1

A2

Pdref(A2)

Puref(A2)

Pdref(A1)

Puref(A1)

VDD

VSS


Example with bus_label Groups[Pin] signal_name model_name R_pin L_pin C_pin

A1 DQ1 DQ A2 DQ2 DQ A3 DQ3 DQ D1 DQS+ DQS D2 DQS- DQS P1 VDD POWER P2 VDD POWER P3 VDD POWER P4 VDD POWER P5 VDD POWER G1 VSS GND G2 VSS GND G3 VSS GND G4 VSS GND G5 VSS GND

pin_names



[Pin Mapping] pulldown_ref pullup_ref gnd_clamp_ref power_clamp_ref ext_ref A1 VSS1 VDD1 NC NC A2 VSS1 VDD1 NC NC A3 VSS2 VDD2 NC NC D1 VSS3 VDD3 NC NC D2 VSS3 VDD3 NC NC P1 NC VDD1 P2 NC VDD1 P3 NC VDD2 P4 NC VDD2 P5 NC VDD3 G1 VSS1 NC G2 VSS1 NC G3 VSS2 NC G4 VSS2 NC G5 VSS3 NC [End Interconnect Model]

POWER bus_labels

GND bus_labels


Power Rail Interconnect Example using signal_names

and bus_labelsNumber_of_Terminals = 12 1 Pin_I/O pin_name A1 | Pin, Pad I/O 2 Pad_I/O pin_name A1 | 3 Pin_rail signal_name VDD 4 Pin_rail signal_name VSS | 5 Pad_rail bus_label VDD1 | Pad Terminals 6 Pad_rail bus_label VDD2 7 Pad_rail bus_label VDD3 8 Pad_rail bus_label VSS1 | Pad Terminals 9 Pad_rail bus_label VSS2 10 Pad_rail bus_label VSS3 | 11 Pin_I/O pin_name A2 | Pin, Pad I/O 12 Pad_I/O pin_name A2 [End Interconnect Model]


Pin-to-Pad Interconnect Example with signal_names

and bus_labelsPhysical Buffer, its Model and On-Die Interconnect

Pads Pins


Die

A1

A2

Pdref(A2)

Puref(A2)

Pdref(A1)

Puref(A1)

VDD

VSS

VDD1 VDD2 VDD3

VSS1 VSS2 VSS3


Power Rail Interconnect Example using bus_labels Only

Number_of_Terminals = 16 1 Pin_I/O pin_name A1 | Pin I/O 2 Pad_I/O pin_name A1 | Pad I/O | 3 Pin_rail bus_label VDD1 | Pin Terminals 4 Pin_rail bus_label VDD2 5 Pin_rail bus_label VDD3 6 Pad_rail bus_label VDD1 | Pad Terminals 7 Pad_rail bus_label VDD2 8 Pad_rail bus_label VDD3 | 9 Pin_rail bus_label VSS1 | Pin Terminals 10 Pin_rail bus_label VSS2 11 Pin_rail bus_label VSS3 12 Pad_rail bus_label VSS1 | Pad Terminals 13 Pad_rail bus_label VSS2 14 Pad_rail bus_label VSS3 | 15 Pin_I/O pin_name A2 | Pin I/O 16 Pad_I/O pin_name A2 | Pad I/O [End Interconnect Model]


Pin-to-Pad Interconnect Example with bus_labels OnlyPhysical Buffer, its Model and On-Die Interconnect

Pads Pins


Die

A1

A2

Pdref(A2)

Puref(A2)

Pdref(A1)

Puref(A1)

VDD1 VDD2 VDD3

VSS1 VSS2 VSS3


Pin-to-Pad Interconnect Example with signal_names

OnlyPhysical Buffer, its Model and On-Die Interconnect

Pads Pins


Die

A1

A2

Pdref(A2)

Puref(A2)

Pdref(A1)

Puref(A1)

VDD

VSS


Conclusions

• Revised syntaxo Makes use of existing [Pin Mapping] for bus labels and defaults,

[Diff Pin], [Series Pin Mapping] for two-node modelso Supports directly all 21 IBIS [Model] Model_typeso Overrides all [Package] model syntax including [Define Package

Model]o Supports IBIS-ISS (an HSPICE subset) and Touchstone electrical

modelso Supports electrical models from pin-to-buffer, pin-to-pad, and pad-

to-buffer (on-die)o I/O buffer 1-to-1 connection assumed, but not so for POWER and

GND interconnections – use pin_name and pad_name for such situations

• Issueso Can two or more [Begin Interconnect Model]s be used together?

(E.g., a pin-to-pad simplified package model and a pad-to-buffer interconnect model with/without a separate buffer to pin path

Updated Interconnect Proposal Bob Ross, Teraspeed Labs [email protected] Draft Presented...

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Transcript of Updated Interconnect Proposal Bob Ross, Teraspeed Labs [email protected] Draft Presented...