UNIVERSITY OF TORONTO FACULTY OF APPLIED SCIENCE...
Transcript of UNIVERSITY OF TORONTO FACULTY OF APPLIED SCIENCE...
UNIVERSITY OF TORONTO
FACULTY OF APPLIED SCIENCE AND ENGINEERING
FINAL EXAMINATION
April. 23, 2019
DURATION: 2:00-4:30 pm
ECE533S —Power Electronics: Switched Mode Power Supplies
Exam Type: C
Examiner - 0. Trescases
Question Mark
1 /23
2 /10
3 /22
Total /55
First Name:
Last Name:
Student #:
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READ ALL QUESTIONS BEFORE STARTING.
ATTEMPT ALL QUESTIONS.
You may use a pen or pencil.
The marks for each question are indicated within brackets []. Show your work: answers
without justification will not receive full marks.
Use the back side of sheets if necessary.
Unless otherwise stated, you may use the small-ripple approximation.
Unless otherwise stated, you may assume the converters to be ideal.
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Last Name:
Question 1: [23 marks]
Consider the Watkins-Johnson dc-dc converter shown below, operating in Continuous Conduction
Mode (CCM). The transistors Qi and Q2 are driven by the same gate drive signal with a duty cycle D.
You may consider all switches to be ideal.
Vg 48V,R2O),C25j1F,L = 100 jtF,j = 250 kHz,
Vg
+
V
The small-signal model for the converter is given by
L 9~4 X(t) + (2Vg V)cl(t) + (P PtWg(O.
C Dt' dt R
19 (t) = (:.. D')t(t)+2lJ(t).
a) [3 marks] Derive the small-signal control-to-output transfer function, Gd(s) for the converter. Give
an analytical expression in the same format as we have used in the course.
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[3 marks] In the provided space above (where the dc-dc converter is shown), draw a complete PWM
closed-loop control system to regulate the output voltage, v(t), making use of the on-chip analog
compensator shown below.
VOUT
R1
(VV)
COMP
Vp2 Rf
cL CF CCF
[2 marks] Derive the analytical transfer function for the compensator, G, in part c), using the form
COMP I (Vref - VREF)
[4 marks] Assuming that R1 = 9 R, and VREF = 3V, find the steady-state closed-loop operating point
(assuming that the system is stable with Vp, = VREF) and plot G1a(s) on the provided axes. Highlight
the important features. Clear mark 'x' and 'o' for any poles and zeroes in the system.
[5 marks] Assume that g,i= 500 tAfV. Find suitable values for RF, CF and CCF (ie: design the
compensator) to achieve a good closed-loop response. (hint: Do not forget the effect of all blocks
that are in the loop that you have drawn for part b)). Sketch the bode plot for your compensator
using the same axes as part d). Clear mark 'x' and 'o' for any poles and zeroes in the system.
[3 marks] Find the exact crossover frequency,J, of the of the compensator loop gain for your design
(IGvd Kpwm Ksense GI=0 dB). What is the maximum recommended value off, for this converter?
[3 marks] Now Repeat part b), drawing the complete system on a new page, if peak current-mode
control is used instead, by sensing the current using a shunt resistor, Rsense. Show explicitly in your
schematic where is the best place to include Is slope compensation required, assuming the same
steady-state conditions as part d)?
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ANSWER FOR 01:
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ANSWER FOR Qi:
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ANSWER FOR 01:
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i•uii i-.iiil iuii
Question 2: [10 marks]
This question contains X unrelated parts.
[2 marks] What is the purpose of this circuit? What is one disadvantage?
N MSBs d[n] 0
UXCO) .L.IDPWMJlF c(t)
— 1 L [~!] MT el[n]
Dither Control
q[n] Logic
[2 mark] Briefly explain the purpose of the NLR block shown below
Input Voltage Bus
PG MGN CFG(0,12) '1(01) £ EN I IUM I Ss I FC(0.1) LD
VTRK
-
Power Management NVM
MOSFET I SYNC I Digital L_.J
Drivers - I GEN I Compensator
DPWM l I I
LI] I j _____
I SYNC PLI
L1> I VSEN ADC
IC REFCN_H__DA
__
ADCs/li<J4II
DOC4— VDD
V c e
SALRT MUX Se ns
12C. SDA — ADC d -
SGL - Communication
LSAto.1 — Sensoj
FIGURE 4. ZL2008 Block Diagram
[2 marks] The measured steady-state response of a boost converter is shown below for open-loop
and closed-loop operation. What is the reason for the drastic increase in output voltage ripple?
VR
BST
SW V(XJT
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Open Loop Closed-Loop Tek Sto Tek Stop
d) [4 marks] As discussed in class, sensing the voltage across a power MOSFET can be used to
provide current protection. as shown below for the MAX 15046 dc-dc controller IC. The partial
datashect for the MOSFETs Q2 is also included. Based on this design. what is the valley current limit
in Q2 (ie: when current flows from source to drain in Q2). in Amps. at -40°C and +125°C (Ti )? Now
repeat this question if there was no temperature compensation in the IC and the LIM reference current
was independent of temperature and equal to 60 ptA. What do you notice?
F
OFF
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Functional Diagram
RI -rLmn HICCUP OSCILLATOR CK
VREF
CK
FB
END Gm HICCUP
LOGIC L+~~
COUP
ENABLE I TiMEOUT COMPARATOR ENABLE
-
RAM VREF COMPTOR +
J1_!-1_nj-I_ BOEP_OK AREF RAMP GENERATOR /111Aj1 PMI
BANDG.HP V_RUM'
-i:::i•--------•
BUM' OK CK RAMP -
GEN
HIGH-
WI OK INTERNAL INTERNAL
I SIDE VOLTAGE I DC-DC CR
PWU ENTIRE REGULATOR OSCILLATOR
CONTROL ARID ENABLE
DHPLENABLE LOGIC HICCUP
__________ LOGIC HICCUP TIMEOUT
-
________I v I Ut_OK
UVLO BUM-OK
0EV ALIRV_OK OW
BGPP..OK IDE jD
V_BRA —41 UVLO SINK umno
I CUREE1g4ENIT + - I COMPARATOR
IRERA(VL SHUTDOWN SABITDOPRI
AND LIlA CURRENT
GENERATOR VALLEY ENABLE
CUENENTUMIE COMPARATOR +
• WUOK MHOK II
BSISI LDARO
VREF JCUERENTI - IBs - P500D
COMPARATOR
AMP = OGV MAX15046
ANT,? 1.24V __EFERENCJ
LIM REFERENCE CURRENT vs. TEMPERATURE
Mq
RUT
DR
LX
CM'
DEN
DL
POND
FR
PS000
GND
öU
75
70
65
I—
LU 60
C)55
50
45
Afl
Note: "LIM reference current" is the bias current generated in the "Thermal shutdown and LIM current generator block" and the current is sent OUT of pin LIM.
-40 -25 -10 5 20 35 50 65 80 95 110 125
TEMPERATURE (°C)
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VISHAY S17460DP Vishay Siliconix
N-Channel 60-V (D-S) Fast Switching MOSFET
PRODUCT SUMMARY
VDS (V) RDs(o ) (c)) l (A
0.0096 at V0 1OV 18 60
0.012atV03 =4.5V 16
FEATURES Halogen-free According to lEG 61249-2-21 Available
TrenchFEt6 Power MOSFETs RoHS New Low Thermal Resistance PowerPAK0 COSPJT
Package with Low 1.07 rem Profile FREE
1.8
V09= 10 = 18 A
3 J
N-C6annd MOSFET
PoserPAK SO -S
-25 0 25 50 75 100 125 150
Tj - Junction Temperature :c
On-Resistance vs. Junction Temperature
ANS\\ER FOR 02:
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ANSWER FOR 02:
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Question 3: [22 marks]
Consider the two-stage Power Factor Correction (PFC) circuit shown below. The boost converter is
designed to operate in CCM. The inner current loop is implemented using fixed-frequency Average
Current Mode Control (ACMC). The input ac supply is 240 V s at 60 Hz. Vrep =24V and Vrep =
400V, C = 250 jiF, L = 150 p.H. The load current of the dc-dc converter is 80A.
Boost converter i3(t) ______________
i5Q) i2(t)
[ i,(:)
VWW C)
L 01
Q vt) c7DD WLoad I
- I I I I - I I I I I -
I '0, (s) Compensator V,10) J and modulator
Compensator
Wide -bandwidth input current controller I Wide-bandwidth output
G(s)
Low-bandwidth. energy-storage
[2 marks] What is the emulated resistance, Re, of the PFC circuit?
[2 marks] What switching frequency should be used to achieve a maximum (over the line
cycle) inductor current ripple of 5 A peak-to-peak.
[3 marks] What is the minimum duty cycle, D, throughout the ac line-cycle (excluding any
dead-zone effects at the zero crossings). Sketch vg(t), v(t), ig(t) and d(t) under this condition for
'/2 of the 60 Hz cycle.
[2 marks] Assume that the dc-dc converter can function properly for v(t)> 0.75 Vrep. If there is
a brief ac power outage, what is the 'hold-time' of the system (ie: for how many equivalent line
cycles of the ac-input can the system operate until going into black-out)?
[4 marks] On the axis provided below sketch (with an X and clear label) the typical location of:
The switching frequency of the dc-dc stage, fe.,
The low-frequency ripple on v(t),J
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The switching frequency of the boost stage, f,2
The natural frequency of the complex conjugate poles in the control-to-output transfer
function of the boost stage,fo
The crossover frequency of the compensated loop gain for the current ioop, Ic)
The crossover frequency of the compensated loop gain for the PFC voltage loop,fc2
The crossover frequency of the compensated loop gain for the dc-dc voltage loop, f,3
f(Hz)
1 10 100 1k 10k lOOk 1M
f) [3 marks] The low-frequency ac equivalent model of the output port of the PFC circuit is
shown below, where R is the small-signal resistance of the load circuit connected at the output
of the PFC stage. Based on the operation of the dc-dc converter, sketch i3 versus v (valid for
frequencies well belowf 3) on the provided axes. Find the value of R for this design at the
operating point.
13
vc
Rectifier output port
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Controller type 82 i2 r2
Average current control with feedforward, Fig. 18.14 VV 0
Current-programmed control, 2P,,. P,,, v2 Fig. 18.16 VV.4 VV
Nonlinear-carrier charge control 2P.11 _______
of boost rectifier, Fig. 18.21 2P
Boost with critical conduction mode 2Pa _P. ___ V 2
control, Fig. 18.20 VVg,,,.
DCM buck-boost. flyback, SEPIC, 2P 2P V 2 or óik converters VV
[3 marks] Based on the provided small-signal model, if the compensator G(s) = K is implemented
as a proportional gain, find K such thatf 2 =10 Hz. Is the PFC outer voltage loop stable with this
choice? Used a clean sketch to justify your answer.
[3 marks] Using the box provided on the following page, draw a new control circuit to implement
Critical Conduction Code (ie: to operate at the boundary of CCM and DCM in each switching
cycle). Is slope-compensation necessary?
1) to gate ofQ1
.i Vcontrol .,
Wide-bandwidth input current controller
BONUS [4 marks] Assuming the same control circuit as part e), find the inductance, L, such that the
minimum switching frequency over one line cycle is 50 kHz. Modify your circuit from part e) to
limit the maximum frequency to 500 kHz (without adding new inputs to the box).
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ANSWER FOR Q3:
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ANSWER FOR Q3:
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ANSWER FOR Q3:
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