University of Oviedo Department of Electrical, Computer and Systems Engineering Doctorate Program in...

DEPARTAMENTO DE INGENERIA ELECTRICA, ELECTRONICA, DE COMPUTADORES Y DE SISTEMAS.

PROGRAMA DE DOCTORADO EN ENERGÍA Y CONTROL DE PROCESOS

TESIS DOCTORAL

ANÁLISIS Y DESARROLLO DE MEJORAS EN CONVERTIDORES PARA DRIVERS LED CON

ESPECIAL ÉNFASIS EN EFICIENCIA Y CONTROL DE FLUJO LUMINOSO

POR

GUIRGUIS ZAKI GUIRGUIS ABDELMESSIH

JUNIO 2020

DIRECTOR: JOSE MARCOS ALONSO ALVAREZ

University of Oviedo

Department of Electrical, Computer and Systems Engineering

Doctorate Program in Process Control, Industrial Electronics and ElectricalEngineering

ANALYSIS AND DEVELOPMENT OFIMPROVED CONVERTERS FOR LEDDRIVERS WITH SPECIAL FOCUS ON

EFFICIENCY AND DIMMING

Guirguis Zaki Guirguis Abdelmessih

This dissertation is submitted for the degree ofElectrical Engineering with International Mention

Advisor: Jose Marcos Alonso. Full Professor. Dept. of Elec.,Computer, & Systems Engineering, University of Oviedo.

June 2020

University of Oviedo

Department of Electrical, Computer and Systems Engineering

ANALYSIS AND DEVELOPMENT OFIMPROVED CONVERTERS FOR LEDDRIVERS WITH SPECIAL FOCUS ON

EFFICIENCY AND DIMMING

Guirguis Zaki Guirguis Abdelmessih

This dissertation is submitted for the degree ofElectrical Engineering with International Mention

Advisor: Jose Marcos Alonso. Full Professor. Dept. of Elec.,Computer, & Systems Engineering, University of Oviedo.

Co-Advisor: Marco Antonio Dalla Costa. Full Professor. FederalUniversity of Santa Maria.

June 2020

I would like to dedicate this thesis to my loving parents.

Declaration

I hereby declare that except where specific reference is made to the work of others, thecontents of this dissertation are original and have not been submitted in whole or in partfor consideration for any other degree or qualification in this, or any other university. Thisdissertation is my own work and contains nothing which is the outcome of work done incollaboration with others, except as specified in the text and Acknowledgements.

Guirguis Zaki Guirguis AbdelmessihJune 2020

Acknowledgements

First of all, I would like to acknowledge and express my sincere appreciation to my advi-sor Prof. Jose Marcos Alonso Alvarez for his valuable and constructive supervision andguidance during the development of this doctoral thesis. His willingness to give his time sogenerously has been very much appreciated.

I would like to thank my co-advisor Prof. Marco Antonio Dalla Costa for his supervi-sion. Also, for giving me the chance to make a stay in the university of Santa Maria to beunder his direct supervision for a duration of six months. The stay was supported from theBrazilian government CAPES/PRINT - n. 41/2017, 88887.364657/2019-00.

I would like also to thank Prof. Ray-Lee Lin for giving me the chance to make a stayin ITRI, Taiwan. Also, I would like to thank my colleagues in Taiwan, Wen-Tien Tsai andYu-Jen Chen for their technical and non-technical support, during my stay in Taiwan.

I would like also to thank Prof. Georges Zissis for the chance he gave me to make a stayin the University of Toulouse, France, to work under his direct supervision.

Special thanks to my research group Efficient Conversion of Energy, Industrial Elec-tronics and Illumination CE3I2, Prof. Antonio Javier Calleja Rodriguez, Prof. EmilioRamon Lopez Corominas, Prof. Javier Ribas Bueno, Prof. Jesus Cardesin Miranda,Prof. Manuel Rico Secades, Dr. Pablo Quintana Barcia, and Nelo Huerta Medina, forgiving such a good support during the full duration of my doctorate.

I am feeling so thankful to my colleagues during my stay in Brazil, Felipe Loose, JeanSantis Brand, Nelson Spode, Renan Duarte, Thais Bolzan, and Theyllor Hentschke deOliveira, for their support and great welcome in Brazil during the complete stay.

I would like to thank my friends in Spain, Andres Suarez Gonzalez, Angel NavarroRodriguez, Bassam Mohamed, Carlos Gomez-Alexandre, Cristina González Moral,Geber Villa Fernandez, Irene Pelaez Acedo, Islam El Sayed, Maria Martinez Gomez,and Ramy Georgious Zaher Georgious, for the good time they gave me during my doctor-ate.

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I would like to acknowledge the government of the Principality of Asturias Spain, as thiswork is supported through research grant Severo Ochoa program of pre-doctoral grants fortraining in research and university teaching, under grant number PA-17-PF-BP16151.

Special thanks to my beloved lifetime friends, Bishoy Youssef, Georges Albert, GeorgesMikhail, John Eskaros, Lucas Nicieza Moro, Mariam Mourad Doss, Mariam SaeedHazkial Gerges, Marian Nathan, Mary Fekry, Michael Magdy, Mina Safwat, MoniqueEssam, Nancy Nabil Eskander, Ramy Fahmy, Sandra Wageeh, Sandra Hany, andSarah Saeed Hazkial Gerges, for the continuous support, encouragement, and qualitytime they provided to me during my work.

I would like to thank my scout leader Emad Makram Ghobrial for his continuouslywillingness of giving the required support and guidance.

Me gustaría agradecer a mi segunda familia, la familia que tuve en España, Sr. JavierFernandez Blanco y Sra. Maria Rosa Rodriguez Suarez, por el amor y el cuidado que meproporcionaron durante toda mi estancia en España, y por darme el sentimiento de familiatan lejos de casa.

Lastly, I would like to thank my whole family uncles, aunts, and cousins for the support,for believing in me, and for the continuous love they provided and keep providing.

I would like to extend my thanks to my father Zaki Guirguis Abdelmessih, the greatrole model and example of giving without waiting for a return. I would like to thank him forbeing my backbone during my whole studies and research.

I can not forget my kind-hearted mother Manal Yaacoub Beshara, who dedicated allher life for her children. I would like to thank her for the non stopping and unconditionallove.

I would like to thank my sister Marianne Zaki Guirguis, her husband Mark El Asmar,and two children John and Eliana for the joy they are continuously adding to my life.

I would like also to thank my brother Yaacoub Zaki Guirguis for being in a great help,and for taking care of the family while I am busy with my research.

At the end of my acknowledgment, I would like to express my great appreciation to theblessings I am continuously receiving from God.

"The Lord will send a blessing on your barns and on everything you put your hand to.The Lord your God will bless you in the land he is giving you." Deuteronomy 28:8.

Abstract

Light-emitting-diodes (LED) were first developed in 1960s. Nowadays, they have becomeone of the most popular lighting sources in a wide variety of applications. This is owing tothe following advantages shown by LEDs: longer lifetime, higher efficacy, smaller size, fastresponse, robustness, reliability, and high color rendering index. The only drawback is thatLEDs cannot be connected directly to the mains. Thus, it is fundamental to drive the LEDsthrough a current-controlled power supply. The aim of this driver is not only to drive theLEDs, but also to fulfill all required standards.

Numerous types of drivers have been presented in the literature. Single-Stage drivers usedas power factor correction (PFC) and constant power control (PC) simultaneously. Moreover,for the sake of a better performance the two-stage LED drivers are proposed. The first stageoperates as a PFC stage, while the second stage operates as a PC stage. A promising solutionfor a compact driver keeping the operation of the two stage converters is the integratedconverters. Integrated converters operate similarly to a two-stage converter but using a singleswitch.

This thesis investigates certain solutions to overcome the issues that the LED driver poses.Firstly, a study of the losses in the integrated buck flyback converter used as high PF LEDdriver is presented. The study proposes a technique to increase the efficiency of the integratedbuck flyback converter by redesigning the converter parameters. Furthermore, it presents acase of study with a step-by-step efficiency enhancement process of an existing driver. Thenew design shows an improvement of the efficiency from 82 % in the old design to 89 % inthe proposed one. Finally, the presented methodology is explained in detail so that it caneasily be applied to other integrated converters.

Secondly, a high PF, low THD LED driver with dimming capability is presented. Thedriver is implemented by using an interleaved capacitor, which is placed between the rectifierand the integrated buck flyback converter. In this way, the line current conduction angle isincreased, which in return increases the PF and decreases the THD. The operation of theproposed converter ensures that one diode of the conventional converter will not conduct,so that it can be removed. Moreover, owing to the continuous power flow, the proposedtechnique makes a significant reduction of the converter output ripple.

xii

Thirdly, an improved dimming technique, to enhance the operation by improving theLED current waveform under PWM dimming is presented. The idea is accomplished by thenew hybrid series parallel PWM dimming technique, through passive and active techniques.The passive technique is made by adding a resistive branch. While, the active method ismade through a new double integrated converter, the integrated buck flyback buck converter.It ensures a constant output current regulation as well as high PF at any dimming ratio.

Fourthly, a high-power-density off-line LED driver is proposed. The proposed AC-DCdriver is the novel integrated buck and boost converter. Besides the high-power-density, theconverter shows good PF and THD. For a further increase of the power-density, a magneticintegration is made by integrating the two inductors of both the buck and boost convertersin one core. Thus, the proposed converter has been named as fully integrated buck andboost converter. In addition, a comparison between two prototypes is presented, one for theintegrated buck and boost converter and another for the fully integrated converter. A patentapplication has been registered for this converter in China, Taiwan and Europe.

Lastly, a dynamic characterization of Organic Light Emitting Diodes (OLED) agingprocess is presented. The aim of this study is to establish a dynamic electrical modelillustrating the OLED characterization over time. In addition, the model is used to examinethe control behavior using simulation, showing its behavior during both transient and steady-state. Furthermore, it is possible to predict the drift of the control system with aging. Thisensures better performance for the OLEDs over its whole lifetime, which in return increasesits lifetime. Moreover, it is presented a methodology to predict the lifetime of the OLED justby measuring the voltage across the OLED at rated current. Moreover, the study presents theeffect of aging on each parameter of the dynamic model.

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Resumen de la Tesis

Los diodos emisores de luz fueron desarrollados por primera vez en los años 1960. En laactualidad, se han convertido en las fuentes de luz más populares en una gran variedad deaplicaciones. Esto se debe a las siguientes ventajas que los caracterizan: alta vida útil, altaeficacia luminosa, tamaño reducido, rápida respuesta, robustez, fiabilidad y elevado índicede reproducción de colores. El principal inconveniente de los diodos LED reside en que nopueden ser alimentados directamente con la red eléctrica. Esto hace fundamental alimentarlos LEDs a través de una fuente de alimentación con control de corriente de salida, tambiénconocida como driver LED. El objetivo de esta fuente de alimentación no es sólo alimentarel LED sino también cumplir los estándares internacionales requeridos para este tipo deequipamientos

En la literatura sobre el tema pueden encontrarse numerosos tipos de drivers LED. Losdrivers de etapa única se emplean como etapas de corrección de factor de potencia (CFP) y deregulación de corriente de salida simultáneamente. Por otro lado, con el objetivo de conseguirmejores prestaciones se han propuesto los convertidores de doble etapa. La primera etapaopera proporcionando CFP y la segunda como etapa de control de potencia de salida. Unasolución prometedora para la implementación de un driver LED compacto viene dada por losconvertidores integrados. Estos convertidores operan de forma similar a los convertidores deuna sola etapa pero emplean un solo interruptor de potencia.

Este trabajo está dedicado a la investigación de ciertas soluciones para superar losinconvenientes que plantean los actuales drivers LED. En primer lugar, se presenta unestudio de pérdidas en el convertidor integrado reductor-retroceso empleado como driverLED de alto factor de potencia (FP). El estudio propone una técnica para mejorar la eficienciadel convertidor integrado reductor-retroceso basada en el rediseño de los parámetros delconvertidor. Además, se presenta un ejemplo de estudio en el que se muestra paso a paso elproceso de mejora de la eficiencia en un driver ya existente. El nuevo diseño muestra unamejora de la eficiencia que pasa del 82 % en el diseño original al 89 % en el nuevo diseñopropuesto. Finalmente, la metodología presentada es explicada en detalle de forma que puedaser fácilmente aplicada a otros convertidores integrados.

En segundo lugar, se presenta un driver LED con alto FP y baja distorsión armónicatotal (DAT) de corriente y con capacidad control de flujo luminoso (dimming). El driver seimplementa por medio de un condensador intercalado que es situado entre el rectificadory el convertidor integrado reductor-retroceso. De esta forma, el ángulo de conducciónes aumentado, lo que permite mejorar tanto el FP como la DAT. El funcionamiento delconvertidor asegura que uno de los diodos del convertidor original no conducirá, pudiendo

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ser eliminado. Además, gracias al continuo flujo de energía, la técnica propuesta permitereducir el rizado de salida.

En tercer lugar, se presenta una técnica de dimming que permite mejorar las formas deonda del LED bajo funcionamiento con modulación de anchura de pulso (MAP). La idea sedesarrolla por medio de una nueva técnica basada en dimming híbrido serie-paralelo, a travésde dos soluciones: pasiva y activa. La técnica pasiva se realiza mediante la adición de unaresistencia en paralelo. La técnica activa está basada en el empleo de la técnica de integraciónde convertidores, desarrollando un nuevo convertidor doblemente integrado, denominadoreductor-retroceso-reductor. El convertidor asegura regulación de corriente del LED ademásde alto FP a cualquier nivel de dimming.

En cuarto lugar, se propone un driver LED de alta densidad de potencia para aplicacionesdesde red eléctrica. El driver está basado en un nuevo convertidor integrado reductor-elevador.Además de la alta densidad de potencia el convertidor proporciona elevado FP y baja DAT.Para conseguir la alta densidad de potencia se propone la integración de los elementosmagnéticos del convertidor reductor y del elevador en un solo núcleo magnético. Se hadenominado así como convertidor reductor-elevador con integración completa, activa ypasiva. Adicionalmente, se realiza una comparación entre dos prototipos diferentes, con y sinintegración magnética. Para este convertidor se ha solicitado una patente en China, Taiwán yEuropa.

Finalmente, se presenta una caracterización dinámica del envejecimiento de LEDs orgáni-cos (OLED). El objeto de este estudio es establecer un modelo eléctrico que permita laevaluación del envejecimiento del OLED durante su vida. El modelo desarrollado permiterealizar simulaciones por computador para evaluar el comportamiento del dispositivo tantoen régimen permanente como transitorio. La metodología propuesta permite predecir la vidaútil del OLED por medio de la medida de tensión del OLED a corriente nominal. El estudiopresenta además el efecto del envejecimiento del OLED sobre cada parámetro del modelo.

Table of contents

List of figures xix

List of tables xxvii

Nomenclature xxix

Acronyms xxxvii

1 Introduction 11.1 Light-emitting diodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

1.1.1 Physical structure . . . . . . . . . . . . . . . . . . . . . . . . . . . 41.1.2 Electrical behavior . . . . . . . . . . . . . . . . . . . . . . . . . . 5

1.1.2.1 Electrical characteristics . . . . . . . . . . . . . . . . . . 51.1.2.2 Electrical representation . . . . . . . . . . . . . . . . . . 6

1.2 Light-emitting diode drivers . . . . . . . . . . . . . . . . . . . . . . . . . 111.2.1 DC to DC LED drivers . . . . . . . . . . . . . . . . . . . . . . . . 111.2.2 AC to DC LED drivers for single phase applications . . . . . . . . 15

1.2.2.1 Single-stage converters . . . . . . . . . . . . . . . . . . 151.2.2.2 Two-stage converters . . . . . . . . . . . . . . . . . . . 161.2.2.3 Integrated converters . . . . . . . . . . . . . . . . . . . . 18

1.2.3 AC to DC LED drivers for three-phase applications . . . . . . . . . 241.2.3.1 Three-phase single-stage converters . . . . . . . . . . . . 241.2.3.2 Three-phase two-stage converters . . . . . . . . . . . . . 27

1.3 LED dimming techniques . . . . . . . . . . . . . . . . . . . . . . . . . . . 281.3.1 Amplitude-modulation dimming . . . . . . . . . . . . . . . . . . . 281.3.2 Pulse-Width-Modulation dimming . . . . . . . . . . . . . . . . . . 29

1.3.2.1 Enable PWM dimming . . . . . . . . . . . . . . . . . . 291.3.2.2 Series PWM dimming . . . . . . . . . . . . . . . . . . . 301.3.2.3 Shunt PWM dimming . . . . . . . . . . . . . . . . . . . 31

xvi Table of contents

1.4 Light-emitting diodes regulations and standards . . . . . . . . . . . . . . . 321.4.1 Energy Star . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321.4.2 IEC 61000 Part 3-2 . . . . . . . . . . . . . . . . . . . . . . . . . . 321.4.3 IEEE 1789-2015 . . . . . . . . . . . . . . . . . . . . . . . . . . . 351.4.4 CISPR 15:2018 © IEC 2018 . . . . . . . . . . . . . . . . . . . . . 37

1.5 Chapters Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391.5.1 Chapter 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391.5.2 Chapter 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391.5.3 Chapter 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401.5.4 Chapter 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401.5.5 Chapter 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411.5.6 Conclusion and future work . . . . . . . . . . . . . . . . . . . . . 41

1.6 List of Publication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411.7 Patent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

2 Integrated Buck Flyback Converter Losses analysis and Efficiency Improve-ment 452.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 462.2 Losses Analysis Methodology for the IBFC . . . . . . . . . . . . . . . . . 48

2.2.1 Bridge Rectifier Losses . . . . . . . . . . . . . . . . . . . . . . . . 482.2.2 Inductor Losses . . . . . . . . . . . . . . . . . . . . . . . . . . . . 512.2.3 Transformer Losses . . . . . . . . . . . . . . . . . . . . . . . . . . 542.2.4 Buck Diode Losses . . . . . . . . . . . . . . . . . . . . . . . . . . 562.2.5 Switch Losses . . . . . . . . . . . . . . . . . . . . . . . . . . . . 572.2.6 Integrated Diodes Losses . . . . . . . . . . . . . . . . . . . . . . . 632.2.7 Flyback Diode Losses . . . . . . . . . . . . . . . . . . . . . . . . 652.2.8 EMI filter Losses . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

2.3 Simulation Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . 672.4 Practical Case Study for Efficiency Improvement . . . . . . . . . . . . . . 692.5 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 732.6 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

3 High PF LED Driver Based on Interleaved Integrated Buck Flyback Converter 813.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 823.2 Derivation of the Interleaved Integrated Buck Flyback Converter . . . . . . 82

3.2.1 Conventional Integrated Buck Flyback Converter . . . . . . . . . . 823.2.2 Proposed Interleaved Integrated Buck Flyback Converter . . . . . . 83

Table of contents xvii

3.3 Operation Principles of the proposed Interleaved Integrated Buck FlybackConverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

3.4 Mathematical Analysis and Average Model . . . . . . . . . . . . . . . . . 913.4.1 Mathematical Analysis . . . . . . . . . . . . . . . . . . . . . . . . 913.4.2 Average Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

3.5 Design Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 963.5.1 Power Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 963.5.2 Control Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

3.6 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1003.7 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

4 Hybrid Series-Parallel PWM dimming technique 1094.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1104.2 Derivation of the Passive Hybrid Series-Parallel PWM dimming technique . 111

4.2.1 Analysis and Average model of Passive HSP-PWM dimming . . . . 1144.2.2 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . 117

4.3 Derivation of the Active Hybrid Series-Parallel PWM dimming technique . 1224.3.1 Operation Principle of the IBFBC . . . . . . . . . . . . . . . . . . 1234.3.2 Mathematical Analysis and Average Model . . . . . . . . . . . . . 128

4.3.2.1 Mathematical Analysis . . . . . . . . . . . . . . . . . . 1284.3.2.2 Design of the converter . . . . . . . . . . . . . . . . . . 1304.3.2.3 Average model . . . . . . . . . . . . . . . . . . . . . . . 133

4.3.3 Laboratory Prototype . . . . . . . . . . . . . . . . . . . . . . . . . 1354.3.3.1 Power converter . . . . . . . . . . . . . . . . . . . . . . 1354.3.3.2 Control and Signals . . . . . . . . . . . . . . . . . . . . 135

4.3.4 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . 1384.4 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

5 Novel LED Driver Based on the Fully Integrated Buck and Boost Converter 1455.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1465.2 Derivation of the Proposed Integrated Buck Boost Converter . . . . . . . . 1475.3 Analysis of the Proposed Integrated Buck and Boost Converter . . . . . . . 149

5.3.1 Operation Principles . . . . . . . . . . . . . . . . . . . . . . . . . 1495.3.2 Mathematical Analysis . . . . . . . . . . . . . . . . . . . . . . . . 1525.3.3 Magnetic Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . 1545.3.4 Average Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

5.4 Design Procedure of the Laboratory Prototype . . . . . . . . . . . . . . . . 159

xviii Table of contents

5.5 Magnetic Simulation and Core Losses Estimation . . . . . . . . . . . . . . 1635.5.1 Magnetic Simulation . . . . . . . . . . . . . . . . . . . . . . . . . 1635.5.2 Core Losses Estimation . . . . . . . . . . . . . . . . . . . . . . . 166

5.6 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1685.7 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181

6 Aging Modeling and Lifetime Prediction of Organic Light Emitting Diodes 1836.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1846.2 OLED Dynamic Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1856.3 Aging OLED Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189

6.3.1 Equivalent Aging Model . . . . . . . . . . . . . . . . . . . . . . . 1896.3.2 Lifetime Prediction . . . . . . . . . . . . . . . . . . . . . . . . . . 191

6.4 Experimental Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . 1926.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196

7 Conclusions 1977.1 Conclusions and main contributions of the Thesis . . . . . . . . . . . . . . 1977.2 Conclusiones y Principales Contribuciones de la Tesis . . . . . . . . . . . . 201

8 Future work 2058.0.1 New Electrolytic Capacitor-less Off-Line LED Driver Based on

Integrated Parallel Buck-Boost and Boost Converter . . . . . . . . 2068.0.1.1 Implementation of the integrated parallel buck-boost and

boost converter . . . . . . . . . . . . . . . . . . . . . . . 2078.0.1.2 Principle of Operation of the integrated parallel buck-boost

and boost converter . . . . . . . . . . . . . . . . . . . . 2098.0.1.3 Mathematical analysis and average model of the integrated

parallel buck-boost and boost converter . . . . . . . . . . 2128.0.1.4 Simulation results of the integrated buck-boost and boost

converter . . . . . . . . . . . . . . . . . . . . . . . . . . 2168.0.2 Complete Model of Organic Light Emitting Diodes Taking into

Account the Aging and Temperature Effect . . . . . . . . . . . . . 2218.0.3 Control Technique for Organic Light Emitting Diodes . . . . . . . 221

References 223

Appendix A Patent Statement 239

List of figures

1.1 LED operation, electric diagram (top), band diagram (bottom). . . . . . . . 51.2 IV characteristics of an LED. . . . . . . . . . . . . . . . . . . . . . . . . . 61.3 LED models (a) Equivalent resistance, (b) Linear model. . . . . . . . . . . 71.4 IV characteristics with linear interpolation based on manufacturer datasheet

values; thereshold and rated voltages. . . . . . . . . . . . . . . . . . . . . 81.5 IV characteristics with linear interpolation based on laboratory measured

values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91.6 Theoretical Equivalent Model of OLED. . . . . . . . . . . . . . . . . . . . 101.7 IV characteristics of OLED showing the three operating intervals. . . . . . 111.8 Electrical diagram of isolated Basic DC to DC converters topologies. (a)

Flyback, (b) Forward, (c) Push-Pull, (d) Half bridge, and (e) Full bridge. . . 121.9 Electrical diagram of non-isolated Basic DC to DC converters topologies. (a)

buck, (b) boost, (c) buck-boost, (d) Cuk, (e) SEPIC, (f) Zeta, and (g) CSC. . 131.10 Structure of LED drivers. (a) Single-stage. (b) Two-stage. (c) Integrated-stage. 151.11 Flyback converter operating as power factor correction and power control. . 161.12 Active filter two-stage converters main scheme. . . . . . . . . . . . . . . . 181.13 Schematic diagram of the integrated double buck-boost converter. . . . . . 191.14 Schematic diagram of the integrated buck and flyback converter. . . . . . . 191.15 Schematic diagram of the integrated buck-boost and flyback converter. . . . 201.16 Schematic diagram of the integrated buck-boost and class E resonant converter. 201.17 Schematic diagram of the integrated flyback and class E resonant converter. 211.18 Schematic diagram of the integrated boost and LLC resonant converter. . . 211.19 Schematic diagram of the integrated boost and LLC resonant converter. . . 221.20 Schematic diagram of the integrated buck-boost and LLC resonant converter. 221.21 Schematic diagram of the three-phase single switch boost converter. . . . . 241.22 Schematic diagram of the three-phase single switch flyback converter. . . . 25

xx List of figures

1.23 Schematic diagram of the three-phase single switch (a) buck converter (b)modified buck with electric isolation. . . . . . . . . . . . . . . . . . . . . . 25

1.24 Schematic diagram of the three-phase multi-switch boost converter. . . . . 261.25 Schematic diagram of the three-phase resonant switched capacitor converter. 261.26 Schematic diagram of the three-phase two stage LED driver without galvanic

isolation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271.27 Classification of ac–dc LED drivers for both single-phase and three-phase ac

power grids. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281.28 Gate signal generation of the enable PWM dimming technique. . . . . . . . 291.29 Single stage LED driver with Series PWM technique applied. . . . . . . . . 301.30 LED driver with Shunt PWM technique applied. . . . . . . . . . . . . . . . 311.31 Harmonic content limit of the IEC 61000-3-2 Class C. . . . . . . . . . . . 341.32 Diagram for definition of flicker index and percent flicker. . . . . . . . . . 361.33 Recommended practices summary. . . . . . . . . . . . . . . . . . . . . . . 37

2.1 Integrated buck flyback converter with the EMI filter connected to it. . . . . 472.2 AC main current in half line-frequency-period range. . . . . . . . . . . . . 492.3 AC main current in multiple of switching-frequency-period range. . . . . . 492.4 Equivalent circuit during the conduction of the switch. . . . . . . . . . . . 572.5 The current of both the buck and the flyback converters. . . . . . . . . . . . 582.6 The current of both the buck and the main switch. . . . . . . . . . . . . . . 582.7 Voltage across the switch obtained by experimental measurement. . . . . . 622.8 The current in the two flyback diodes DFL and DFH . . . . . . . . . . . . . 632.9 Input voltage (red), input current (yellow), and output voltage (green) for the

old IFBC design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 692.10 Efficiency of the IBFC converter with respect to turn ratio. . . . . . . . . . 702.11 (a) Efficiency of the converter and (b) Bulk capacitor voltage, with respect to

Buck and Magnetizing inductances. . . . . . . . . . . . . . . . . . . . . . 712.12 Bulk capacitor voltage of the old design (red), and of the new design (blue). 722.13 New design: Input voltage (red), input current (yellow) and output voltage

(green). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 742.14 Output current of the IBFC new design. . . . . . . . . . . . . . . . . . . . 742.15 Harmonic content of the input current versus IEC 61000-3-2 Class C. . . . 752.16 New design efficiency (blue) sold line calculated and dashed measured, old

design efficiency (red) sold line calculated and dashed measured, referencedesign efficiency (black). . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

2.17 New driver photography. . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

List of figures xxi

2.18 Schematic diagram of the laboratory prototype of the new IBFC design. . . 772.19 A comparison between experimental and theoretical results of the losses in

each component in the converter. . . . . . . . . . . . . . . . . . . . . . . . 78

3.1 Top: bridge voltage and bulk capacitor voltage. Bottom: current after thebridge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

3.2 Interleaved Integrated Buck-Flyback Converter schematic. . . . . . . . . . 843.3 Main current waveforms of the IIBFC operating in DCM, within a high

frequency switching period around the peak line voltage. . . . . . . . . . . 863.4 Equivalent circuits of the IIBFC operating in DCM. . . . . . . . . . . . . . 873.5 A simple magnetic model of the flyback transformer and its currents during

the turn-on interval. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 883.6 Operation of the flyback diodes. (a) if iF > iB, (b) if iF < iB. . . . . . . . . 883.7 Output voltage (top) and currents (bottom) of the IBFC (in blue) and the

Interleaved IBFC (in red). . . . . . . . . . . . . . . . . . . . . . . . . . . . 893.8 LED current of the IIBFC with different output capacitances. . . . . . . . . 903.9 Average model of the Interleaved Buck Flyback converter. . . . . . . . . . 953.10 Bulk capacitor voltage and inductor peak current with respect to the buck

inductance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 953.11 Schematic diagram of the laboratory prototype. . . . . . . . . . . . . . . . 983.12 Flyback current IF at different resonance frequencies, top: 150 kHz (Cint =

150 nF), middle: 40 kHz (Cint = 2.2 µF), and bottom: 10 kHz (Cint = 33 µF). 993.13 Prototype photograph. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1003.14 Top: input current, and bottom: input sinusoidal voltage (green) and bulk

voltage (red). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1013.15 Bottom: input current, and top: bulk capacitor voltage, for the conventional

IBFC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1023.16 Output current (yellow), and output voltage (green), steady-state operation. 1033.17 Output current (yellow), and output voltage (green), start-up operation. . . . 1033.18 Bottom: output flyback current, and top: voltage across the switch. . . . . . 1043.19 Per unit output current with respect to the variation of input voltage. . . . . 1043.20 Power factor with respect to dimming ratio. . . . . . . . . . . . . . . . . . 105

4.1 Simulation results under conventional PWM series dimming: (a) shows LEDlamp current, while the (b) shows the output capacitor voltage. . . . . . . . 111

4.2 IBFC with the LED connected at the output, showing as well its model, andwith the parallel resistive branch. . . . . . . . . . . . . . . . . . . . . . . . 112

xxii List of figures

4.3 Simulation results of the proposed HSP-PWM dimming: (a) shows LEDcurrent, while (b) shows output capacitor voltage. . . . . . . . . . . . . . . 113

4.4 Average model of the IBFC including the proposed passive HSP-PWMdimming technique. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

4.5 HSP-PWM dimming resistance chart. . . . . . . . . . . . . . . . . . . . . 1164.6 Efficiency Chart with respect of resistance factor, for different dimming

ratios; 10 %, 15 %, 20 %, and 25 %. . . . . . . . . . . . . . . . . . . . . . 1174.7 Dimming signal (Upper trace), and lamp current (Lower trace) for dimming

ratio 50 % with four different resistance values. (a) 452 Ω, (b) 990 Ω, (c)2.31 kΩ, (d) Without resistance. . . . . . . . . . . . . . . . . . . . . . . . 119

4.8 (a) Shows the efficiency and (b) shows the wasted energy with respect to thedimming ratio, for three difference resistances values; 452 Ω, 990 Ω, and2.31kΩ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

4.9 Dimming signal (Upper trace), and LED current (Lower trace) for a resistancevalue of 2.31 kΩ with four different dimming ratios. (a) 10 %, (b) 30 %, (c)60 %, and (d) 90 %. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

4.10 Integrated Buck-Flyback-Buck Converter (IBFBC). . . . . . . . . . . . . . 1224.11 Equivalent circuit of IBFBC during the three dimming stages. . . . . . . . 1244.12 Main current waveforms of the proposed IBFBC operating in DCM, within

one dimming frequency, and with a zoom-in showing as well the currents athigh frequency switching period around the peak line voltage. . . . . . . . 125

4.13 Equivalent circuit of IBFBC during all four intervals. . . . . . . . . . . . . 1274.14 The four main power directions of the proposed IBFBC. . . . . . . . . . . 1284.15 Output current ripple with respect to the dimming ratio. . . . . . . . . . . . 1304.16 Output current ripple with respect to the output buck inductance in per unit

value of the estimated value (1.8 mH). . . . . . . . . . . . . . . . . . . . . 1324.17 Variation of the input buck voltage and the main switch duty with respect to

the dimming duty (Ddim). . . . . . . . . . . . . . . . . . . . . . . . . . . . 1334.18 Proposed IBFBC average model split into the three main converters input

buck, flyback, and output buck. . . . . . . . . . . . . . . . . . . . . . . . . 1344.19 Simplified block diagram for the IBFBC. . . . . . . . . . . . . . . . . . . 1354.20 The Full IBFBC control scheme. . . . . . . . . . . . . . . . . . . . . . . . 1374.21 IBFBC laboratory prototype board. . . . . . . . . . . . . . . . . . . . . . . 137

List of figures xxiii

4.22 Gate signal (Upper trace), and lamp current (Lower trace) in nine differentdimming ratios. (A) 2.5 % luminous output (100:2.5), (B) 5 % luminousoutput (100:5), (C) 10 % luminous output (100:10), (D) 25 % luminousoutput (100:25), (E) 30 % luminous output (100:30), (F) 50 % luminousoutput (100:50), (G) 75 % luminous output (100:75), (H) 90 % luminousoutput (100:90), (I) 100 % luminous output (1:1). . . . . . . . . . . . . . . 138

4.23 Measured and calculated values of the Bulk capacitor voltage, with respectto different dimming ratios. . . . . . . . . . . . . . . . . . . . . . . . . . . 139

4.24 Efficiency of the IBFBC as well as the efficiency of the HSP dimming forthree different resistance values, 452 Ω, 990 Ω, and 2.31kΩ, with respect todimming duty. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

4.25 Output power and Efficiency with respect to dimming duty ratio. . . . . . . 1414.26 Breakdown of the converter losses. . . . . . . . . . . . . . . . . . . . . . . 142

5.1 (a) electric diagram of a conventional cascade buck PFC and boost dc-dcLED driver, (b) electric diagram of the Integrated Buck and Boost Converter,and (c) electric diagram and the magnetic structure of the Fully IntegratedBuck and Boost Converter. . . . . . . . . . . . . . . . . . . . . . . . . . . 148

5.2 Equivalent circuits of the IBBC operating in DCM. . . . . . . . . . . . . . 1505.3 Main current waveforms of the IBBC operating in DCM, within a high-

frequency switching period; (a) when iBu > iBo around the peak line voltage,(b) when iBu < iBo for low values of the line voltage. . . . . . . . . . . . . 151

5.4 Equivalent magnetic circuits of the integrated inductors; (a) left side the buckinductor, while right side the boost inductor, (b) the integrated inductor buckand boost. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

5.5 Flux in the integrated core when deactivating buck MMF. Flux in the boostarm (in blue), flux in the central arm (in red), and flux in the buck arm (ingreen). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

5.6 Average model of the proposed FIBBC LED driver. . . . . . . . . . . . . . 1595.7 Schematic diagram of the laboratory prototype. . . . . . . . . . . . . . . . 1635.8 The magnetic flux density in different part of the core in both cases separate

inductors and integrated inductors, in time and frequency domains. . . . . . 1655.9 Core losses estimation for the standalone cores, the integrated core in same

and reverse direction of the flux in the center arm. . . . . . . . . . . . . . . 1675.10 Input current in yellow, and input sinusoidal voltage in green and bulk voltage

in red, for the IBBC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1685.11 Input current in green, and input sinusoidal voltage in purple, for the FIBBC. 169

xxiv List of figures

5.12 Bulk voltage (red), output voltage (green), and output current (yellow), steadystate operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170

5.13 Bulk voltage (red), output voltage (green), and output current (yellow), start-up operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

5.14 The voltage across the MOSFET switch (top), and the current through it(bottom). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

5.15 The buck inductor current (top), and the boost inductor current ( bottom). . 1725.16 Input voltage (blue), bulk voltage (green), and input current (yellow). . . . . 1735.17 Bulk capacitor voltage with respect to input voltage, by calculations (blue),

and from experimental results (red). . . . . . . . . . . . . . . . . . . . . . 1745.18 Power factor of the FIBBC concerning the dimming ratio. . . . . . . . . . . 1745.19 Efficiency with respect to dimming ratio of the IBBC, FIBBC with central

arm flux in same and reverse direction. . . . . . . . . . . . . . . . . . . . . 1755.20 The input current harmonic contents at both input voltages 110 V and 220 V

in comparison with the IEC 61000-3-2 limit. . . . . . . . . . . . . . . . . . 1765.21 The laboratory prototypes; (a) the IBBC prototype, and in (b) the FIBBC

prototype. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1775.22 The manufactured prototypes; (a) the IBBC prototype, and in (b) the FIBBC

prototype. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178

6.1 IV characteristics of the Philips GL-55; in blue the IV characteristics at L100,in red the IV characteristics at L70, in green the IV characteristics at L50,and in black the IV characteristics at L30. . . . . . . . . . . . . . . . . . . 185

6.2 Theoretical Equivalent Model of OLED. . . . . . . . . . . . . . . . . . . . 1866.3 IV characteristics of OLED described on it the three intervals. . . . . . . . 1866.4 The IV curve in logarithmic scale illustrating the three new intervals. . . . . 1886.5 Model parameters as a function of lifetime. . . . . . . . . . . . . . . . . . 1906.6 OLED Lifetime with respect to voltage across the OLED at rated current

(350 mA). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1916.7 IV characteristics at L50 in linear scale, in blue experimental results, and in

red the results from the dynamic model. . . . . . . . . . . . . . . . . . . . 1936.8 IV characteristics at L50 in logarithmic scale, in blue experimental results,

and in red the results from the dynamic model. . . . . . . . . . . . . . . . . 1936.9 Experimental and model I-V characteristics at different lifetime; First plot at

L100, second plot at L70, and third plot at L30. . . . . . . . . . . . . . . . 194

List of figures xxv

6.10 Experimental and model OLED voltage; plot I shows the case of L30 andduty 25%, plot II shows the case of L30 and duty 50%, plot III shows thecase of L30 and duty 75%, plot IV shows the case of L50 and duty 25%, plotV shows the case of L50 and duty 50%, and plot VI shows the case of L50and duty 75%. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195

8.1 The schematic of the proposed parallel integrated converter. . . . . . . . . . 2078.2 The structure of the electrolytic capacitor-less buck-boost and boost converter.2088.3 The structure of the electrolytic capacitor-less integrated parallel buck-boost

and boost converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2088.4 Equivalent circuits of the IPB3C operating in DCM. . . . . . . . . . . . . . 2108.5 Main current waveforms of the IPB3C operating in DCM, within a high-

frequency switching period; (a) when iBB > iBo around the peak line voltage,(b) when iBB < iBo for low values of the line voltage. . . . . . . . . . . . . 211

8.6 Inductor currents waveforms of the IPB3C operating in DCM, and voltageacross the switch, within a high-frequency switching period; (a) when iBB >

iBo around the peak line voltage, (b) when iBB < iBo for low values of the linevoltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212

8.7 Output voltage of the buck-boost PC stage in terms of the inductance ratio(buck-boost inductance over boost inductance LBo/LBB). . . . . . . . . . . . . 214

8.8 Input voltage of the boost RR stage in terms of the inductors ratio (buck-boostinductance over boost inductance LBo/LBB). . . . . . . . . . . . . . . . . . . 214

8.9 Circulating power of the RR stage percentage of LED power in terms of theinductors ratio (buck-boost inductance over boost inductance LBo/LBB). . . . . 215

8.10 Average model of the proposed IPB3C LED driver. . . . . . . . . . . . . . 2168.11 Buck-boost output voltage (blue), boost input voltage (red), and LED voltage

(green). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2178.12 Buck-boost output voltage ripple (blue), boost input voltage ripple (red), and

LED voltage ripple (green). . . . . . . . . . . . . . . . . . . . . . . . . . . 2178.13 LED current (blue), LED current filtered from high frequency ripple (red). . 2188.14 AC main voltage (blue), AC main current (green). . . . . . . . . . . . . . . 2198.15 Buck-boost inductor current (blue), boost inductor current (red). . . . . . . 2198.16 Voltage across the switch (blue), current through the switch (red). . . . . . 220

List of tables

1.1 Summary of Non-Isolated Basic DC to DC Converters . . . . . . . . . . . 141.2 A Summary of Integrated Converters . . . . . . . . . . . . . . . . . . . . . 231.3 ENERGY STAR® Program Applied to LED Lamps . . . . . . . . . . . . . 331.4 Equipment Classification of the IEC 61000 Part 3-2 . . . . . . . . . . . . . 34

2.1 Specification and Components of the Two Drivers . . . . . . . . . . . . . . 672.2 Comparison Between Theoretical Results and Simulation Results of the Two

Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 682.3 Specification and Components of the New Driver Design . . . . . . . . . . 732.4 Theoretical Computation Comparison Between Old and New Driver Designs 78

3.1 Simulation Results of the IIBFC Output Current and Voltage Ripples WithDifferent Output Capacitances . . . . . . . . . . . . . . . . . . . . . . . . 91

3.2 Components of the Laboratory Prototype . . . . . . . . . . . . . . . . . . . 963.3 Comparison Among the Proposed Technique and the Up-to-Date PFC Tech-

niques . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

4.1 Specification and Components of the IBFC Including Passive HSP-PWMDimming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

4.2 Specification and Components of the IBFC Including Active HSP-PWMDimming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

5.1 Components of the Laboratory Prototype of the Fully Integrated Buck andBoost Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

5.2 Comparison Among the Proposed Converter and Found in the LiteratureIntegrated Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179

5.3 Comparison Among the Proposed Converter and Found in the LiteratureIntegrated Converters in Terms of Needed Bulk Capacitor Size and Price . . 180

6.1 PHILIPS GL-55 Main Characteristics . . . . . . . . . . . . . . . . . . . . 189

xxviii List of tables

6.2 Model Parameters of PHILIPS GL-55 at Different Lifetime L100, L70, L50,and L30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190

8.1 Parameters of the simulation of the Integrated Buck-Boost and Boost Converter.2168.2 OLED Samples Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 221

Nomenclature

Roman Symbols

∆i Half of buck inductor current ripple.

∆B Flux density variation.

∆VLED LED voltage variation

δ Flyback-to-Buck angle⟨i f⟩

Average input flyback current current.

⟨iAC⟩ Average AC main current

⟨iAC⟩per Average AC main current per switching period

⟨iDFH ⟩ Average DFH current.

⟨iDFL⟩ Average DFL current.

⟨iDF ⟩ Average flyback diode current.

⟨iDB⟩ Average buck diode current.

⟨iDB⟩per Average buck diode current per switching period.

µo Vacuum permeability.

µr Relative permeability of the core.

ω Line angular frequency equal to 2π fL

Φ Instantaneous flux.

τ Conduction time over switching period

xxx Nomenclature

θ Conduction angle

ε0 Vacuum permittivity (8.8541 e−12 F/m)

εr Relative permittivity of the OLED material (3 to 3.5)

A Cross-section area of the core.

Aact OLED active area

CDS Switch parasitic capacitance drain-to-source.

CGD Switch parasitic capacitance gate-to-drain.

Cint Interleaved capacitance.

COSS Switch parasitic output capacitance COSS =CGD +CDS.

D Duty cycle

D′ Inductor di-energizing duty

DBo Boost diode in integrated buck and boost converter.

DBu Buck diode in integrated buck and boost converter.

Ddim Dimming duty

fL Line frequency

fdim Dimming frequency

fres Interleaved circuit resonant frequency.

fs Switching frequency

g Buck inductor air gap length.

iw Instantaneous current through the winding.

iAC Instantenous AC main current

IBn Average of the normalized buck current.

iBB Intantanuous buck-boost inductor current.

iBo Instantanuous boost inductor current.

Nomenclature xxxi

iBu Instantanuous buck inductor current.

IB Buck inductor average current.

iB Instantaneous buck turn-on current.

IDOFF Switch current at turn-off.

Idim Dimming current

iD Switch current.

iF Instantaneous flyback turn-on current.

ILED LED rated current

IRMS RMS value over line period

IACrms RMS of the AC main current

iBopeak Boost inductor peak current in integrated buck and boost converter.

iBuckp Buck inductor current peak value per switching period

IBuckrms Buck inductor RMS current over line frequency.

iBuckrmsPerBuck inductor current RMS value over switching period

iBupeak Buck inductor peak current in integrated buck and boost converter.

I f ly inputPInput flyback current peak value.

I f ly inputrmsInput flyback current RMS.

I f ly out putPOutput flyback current peak value.

I f ly out putrmsOutput flyback current RMS.

iRMSPer RMS value over switching period

Iswitchrms Switch current RMS over line period

iswitchrmsPerSwitch current RMS over switching period

k & a Core loss coefficients.

K Dimming resistance factor.

xxxii Nomenclature

l Length of the flux path.

le Equivalent length of the core.

Lm Flyback transformer magnetising inductance.

Lw Inductance of the windding.

LBB Buck-Boost inductance.

LBo Boost inductance in integrated buck and boost converter.

LBu Buck inductance in integrated buck and boost converter.

LB Buck inductance

Ldim Output buck converter inductance.

Lki Flyback transformer interleaved winding leakage inductance.

lorg OLED organic layer thickness

LBocrit Boost BCM critical inductance in integrated buck and boost converter.

m Ratio of the buck voltage over the grid voltage m = VBVg

.

N transformer turn ratio. N = Nsec/Nprim

n Number of switching periods inside a half line period

Nw Number of turns of the winding.

NBo Number of turns in boost standalone core.

NBu Number of turns in buck standalone core.

Nind Buck Inductor number of turns.

Nint Transformer interleaved side number of turns.

Ni Transformer turns ratio. Ni = Nint/Nprim

Nprim Transformer primary side number of turns.

Nsec Transformer secondary side number of turns.

PBo Boost operating in DCM power.

Nomenclature xxxiii

PBridge Bridge Losses

Pcond Switch conduction losses.

PDFH Diode DFH losses.

PDFL Diode DFL losses.

PDF Diode DF losses.

PEMI EMI filter losses.

PPC Power of the PC stage.

Pprim Flyback transformer primary winding copper losses.

PRR Power of the RR stage.

Psec Flyback transformer secondary winding copper losses.

Pswitch Switch total losses.

PSW Switch switching losses.

PDB Buck diode Losses.

PEMIcopper EMI filter copper Losses

Pindcopper Buck inductor copper losses.

Pindmag Buck inductor magnetic losses

PowerAC AC main power.

Powerback Output buck converter power.

Power f lyback Flyback converter power.

PowerLED LED power.

Re Reluctance of the core.

Rback Equivalent resistance of output buck converter in DCM.

RBo Boost operating in DCM equivalent resistance.

RB Buck operating in DCM equivelent resistance

xxxiv Nomenclature

RCBo Central arm reluctance of boost standalone core.

RCBu Central arm reluctance of buck standalone core.

Rdyn LED dynamic resistance

ReBo Total reluctance of boost standalone core.

ReBu Total reluctance of buck standalone core.

ReIBoTotal reluctance of boost integrated core.

ReIBuTotal reluctance of buck integrated core.

REMI Parasitic copper resistance of the coupled windings of the EMI filter

Req LED equivelent resistance

RF Flyback operating in DCM equivelent resistance

RGBo Air gap reluctance of boost standalone core.

RGBu Air gap reluctance of buck standalone core.

RHSP HSP-PWM dimming resistance.

RIC Center arm reluctance of integrated core.

RIBo Boost arm reluctance of integrated core.

RIBu Buck arm reluctance of integrated core.

RIGBoAir gap reluctance of boost arm in integrated core.

RIGBuAir gap reluctance of buck arm in integrated core.

Rind Buck inductor parasitic copper resistance.

ROBo Outer arm reluctance of boost standalone core.

ROBu Outer arm reluctance of buck standalone core.

Rprim Flyback transformer primary winding parasitic copper resistance.

Rsec Flyback transformer secondary winding parasitic copper resistance.

t Instantanuous time

Nomenclature xxxv

TL Line period

tdim Dimming time

tOFF Switch turn off-time.

tON Switch turn on-time.

Ts Switching period

VBB Buck-Boost output voltage.

VBo Boost input voltage.

VB Bulk capacitor voltage

VDOFF Switch drain to source voltage at turn-off.

VDON Switch drain to source voltage at turn-on.

vD Switch drain to source voltage.

Vg Input voltage peak value

Vint Voltage across interleave capacitor

vLB Voltage across buck inductor terminals

VLED LED rated voltage

Vth LED threshold voltage

vACBridge Voltage across AC bridge

VthBridge Bridge diodes threshold voltage

VthDBBuck diode Threshold voltage.

VthDFHDiode DFH threshold voltage.

VthDFLDiode DFL threshold voltage.

VthDFDiode DF threshold voltage.

Acronyms

AC Alternating Current.AM Amplitude-Modulation.

BCM Boundary Conduction Mode.

CCM Continuous Conduction Mode.CCT Correlated Color Temperature.CMOS Complementary Metal Oxide Semiconductor.

DC Direct Current.DCM Discontinuous Conduction Mode.DM Differential Mode.DSP Digital Signal Processor.

EMC Electromagnetic Compatibility.EMI Electromagnetic Interference.

FFT Fast Fourier Transform.FIBBC Fully Integrated Buck and Boost Converter.

GaAs Gallium Arsenide.GaAsP Gallium Arsenide Phosphide.GaN Gallium Nitride.GaSb Gallium Antimonide.Ge Germanium.

xxxviii Acronyms

HSP Hybrid Series Parallel.

IBBC Integrated Buck and Boost Converter.IBFBC Integrated Buck Flyback Buck Converter.IBFC Integrated Buck Flyback Converter.IC Integrated Circuit.IEC International Electrotechnical Commission.IIBFC Interleaved Integrated Buck Flyback Converter.IPB3C Integrated Parallel Buck-Boost and Boost Converter.I-V Current-Voltage.InP Indium Phosphide.IR Infrared.

LED Light-Emitting Diode.

MMF Magneto-Motive Force.MOSFET Metal-Oxide Semiconductor Field-Effect Transistor.

OLED Organic Light-Emitting Diode.op-amp Operational Amplifier.

PAS Publicly Available Specifications.PC Power Control.PF Power Factor.PFC Power Factor Correction.PI Proportional–Integral.PPB Pulsating-Power-Buffering.PWM Pulse Width Modulation.

RGB Red-Green-Blue.RMS Root Mean Square.RR Ripple-Reduction.

Acronyms xxxix

Si Silicon.SiC Silicon Carbide.SiGe Silicon-Germanium.SMPS Switched-Mode Power Supplies.

THD Total Harmonic Distortion.TRIAC Triode AC semiconductor switch.

ZCS Zero Current Switching.ZVS Zero Voltage Switching.

Chapter 1

Introduction

Contents1.1 Light-emitting diodes . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

1.1.1 Physical structure . . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.1.2 Electrical behavior . . . . . . . . . . . . . . . . . . . . . . . . . 5

1.1.2.1 Electrical characteristics . . . . . . . . . . . . . . . . . 5

1.1.2.2 Electrical representation . . . . . . . . . . . . . . . . . 6

1.2 Light-emitting diode drivers . . . . . . . . . . . . . . . . . . . . . . . 11

1.2.1 DC to DC LED drivers . . . . . . . . . . . . . . . . . . . . . . . 11

1.2.2 AC to DC LED drivers for single phase applications . . . . . . . 15

1.2.2.1 Single-stage converters . . . . . . . . . . . . . . . . . 15

1.2.2.2 Two-stage converters . . . . . . . . . . . . . . . . . . 16

1.2.2.3 Integrated converters . . . . . . . . . . . . . . . . . . . 18

1.2.3 AC to DC LED drivers for three-phase applications . . . . . . . . 24

1.2.3.1 Three-phase single-stage converters . . . . . . . . . . . 24

1.2.3.2 Three-phase two-stage converters . . . . . . . . . . . . 27

1.3 LED dimming techniques . . . . . . . . . . . . . . . . . . . . . . . . . 28

1.3.1 Amplitude-modulation dimming . . . . . . . . . . . . . . . . . . 28

1.3.2 Pulse-Width-Modulation dimming . . . . . . . . . . . . . . . . . 29

1.3.2.1 Enable PWM dimming . . . . . . . . . . . . . . . . . 29

1.3.2.2 Series PWM dimming . . . . . . . . . . . . . . . . . . 30

1.3.2.3 Shunt PWM dimming . . . . . . . . . . . . . . . . . . 31

2 Introduction

1.4 Light-emitting diodes regulations and standards . . . . . . . . . . . . 32

1.4.1 Energy Star . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

1.4.2 IEC 61000 Part 3-2 . . . . . . . . . . . . . . . . . . . . . . . . . 32

1.4.3 IEEE 1789-2015 . . . . . . . . . . . . . . . . . . . . . . . . . . 35

1.4.4 CISPR 15:2018 © IEC 2018 . . . . . . . . . . . . . . . . . . . . 37

1.5 Chapters Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

1.5.1 Chapter 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

1.5.2 Chapter 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

1.5.3 Chapter 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

1.5.4 Chapter 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

1.5.5 Chapter 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

1.5.6 Conclusion and future work . . . . . . . . . . . . . . . . . . . . 41

1.6 List of Publication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

1.7 Patent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

1.1 Light-emitting diodes 3

In this chapter, an introduction to the Light-Emitting Diode (LED) is presented. Includinga description of the LED physical structure as well as stating most of its electrical characteris-tics. Moreover, a state-of-the-art for LED drivers and their regulations are presented. Finally,the chapter presents a state-of-the-art for light dimming techniques.

1.1 Light-emitting diodes

Electroluminescence as a phenomenon was discovered in 1907 by Henry Joseph Round,using a crystal of Silicon Carbide (SiC) and a cat’s-whisker detector [1–3]. Later on, the firstLED was reported by the Soviet inventor Oleg Losev in 1927 [4]. His research was publishedin Soviet, German and British scientific magazine. The idea had no practical application forseveral decades, as the luminous efficacy was very low [5][6].

The first LED has been explained by Kurt Lehovec, Carl Accardo and Edward Jamgochian,in 1951 using an apparatus employing SiC crystals with a current source of battery or pulsegenerator and with a comparison to a variant, pure, crystal in 1953. Moreover, in 1955Rubin Braunstein reported on infrared emission from Gallium Arsenide (GaAs) and othersemiconductors. Furthermore, he observed infrared emission generated by simple diodestructures using Gallium Antimonide (GaSb), GaAs, Indium Phosphide (InP), and Silicon-Germanium (SiGe) alloys at room temperature and 77 K. Finally, in 1957, Braunsteindemonstrated that the rudimentary devices could be used for non-radio communication acrossa short distance. [7][8]

On August 8, 1962, Biard and Pittman filed a patent titled “Semiconductor Radiant Diode”based on their findings [9]. The LED construction was as follows, zinc diffused p–n junctionwith a spaced cathode contact to allow for efficient emission of infrared light under forwardbias. Later on, the U.S. patent office issued for the GaAs Infrared (IR) light-emitting diode(U.S. Patent US3293513), the first practical LED [10]. In October 1962, they announced thefirst LED commercial product (the SNX-100), which employed a pure GaAs crystal to emit a900 nm light output.

The first visible-spectrum (red) LED was developed in 1962 by Nick Holonyak, Jr. whileworking at General Electric Company [11]. He reported his LED in the journal AppliedPhysics Letters on the December 1, 1962 [12][13]. Furthermore, in 1972, Holonyak inventedthe first yellow LED as well as improve the brightness of red and red-orange LEDs by afactor of ten [14]. First mass-production visible LEDs belongs to Monsanto Company in1968, using Gallium Arsenide Phosphide (GaAsP) in 1968 [15].

The first high-brightness blue LED was demonstrated by Shuji Nakamura of NichiaCorporation in 1994 and was based on InGaN [16]. In 2001 [17] and 2002 [18], processes

4 Introduction

for growing gallium nitride (GaN) LEDs on Silicon (Si) were successfully demonstrated.In January 2012, Osram demonstrated commercial high-power InGaN LEDs grown on Sisubstrates [19].

LEDs have been replacing little by little the conventional sources of light. Nowadays,they have become the most popular lighting source in a wide variety of applications. This isowing to the following advantages shown by the LEDs:

• Longer lifetime, which is usually quoted as 15,000 to 50,000 h for a minimum flux of70% of the initial flux (L70) [20].

• Higher efficacy compared to other light sources, as it is claimed in [21] that theincandescent lamps efficacy ranges between 14 to 17 lm/W, fluorescent tubes 100lm/W, high-pressure sodium lamps reach 120 lm/W; however, the new generation ofLED will have an efficacy up to 250 lm/W even 300 lm/W as stated in [22].

• Other features like a smaller size, fast response, robustness, reliability, and high colorrendering index [23–29].

LEDs can be classified into two main groups [30]:

1. Inorganic LEDs, which are those fabricated from inorganic semiconductors, such asindium-gallium nitride (InGaN) and aluminum gallium arsenide (AlGa), among others.

2. Organic Light-Emitting Diode (OLED), which are fabricated from carbon-based semi-conductors and polymers.

Both types have seen huge improvements in their light output in recent years. However,white inorganic white-phosphor-based LEDs show light efficacy of more than 100 lm/W,while OLEDs for general lighting applications can only be found with ratings of 50 lm/W[31].

1.1.1 Physical structure

As any p-n junction, LEDs consist of a chip of semiconductor material doped with impurities.Thus, the current flows from the p-side (anode) toward the n-side (cathode), and not in thereverse direction. When the sufficient voltage is applied across the p-n junction, the electronsstart to migrate from the cathode to the anode. Immediately, upon the recombination ofan electron with a hole, it falls to a lower energy level, therefore it releases this energydifference in the form of a photon. The bandgap energy of the material forming the p-n


junction is the key element that defines the wavelength of the light emitted as well as itscolor. In Si or Germanium (Ge) diodes, the recombination of the electrons with the holes is anon-radiative transition, as these are indirect bandgap materials. Thus, no optical emissionis produced. LEDs are formed from materials with a direct bandgap with optical radiationin the wavelengths from the ultraviolet, visible, to infrared regions of the electromagneticspectrum. Fig. 1.1 shows in the top the simplified electrical diagram of the LED, while in thebottom it shows the electron operation principles inside the p-n junction.

P-type N-type

hole electron

light

Conduction band

Fermi level

Valence band

Band gap

(forbidden band)Recombination

Fig. 1.1 LED operation, electric diagram (top), band diagram (bottom).

1.1.2 Electrical behavior

1.1.2.1 Electrical characteristics

From an electrical point of view, LEDs allow the current to pass across them in just onedirection, as any normal diode. Therefore, the LED can be considered as a non-linear load,

6 Introduction

following the Current-Voltage (I-V) characteristics shown in Fig. 1.2. The graph is split intothree main regions; The forward region or the conduction region, where the voltage acrossthe LED is in forward-biased, i. e., the voltage polarity is positive from cathode to anode.In the forward region, the current will start to flow with a very small rate compared to thevoltage increase, until it reaches a break point called the threshold voltage. When the voltageacross the LED increases over the threshold voltage value, the current starts to increase witha relatively high ratio compared to the increase in voltage. The reverse region is when thevoltage across the LED is in reverse polarity. In this case, the LED will behave like a diodeand will block the circuit, until a value for the voltage called the breakdown voltage. If thereverse voltage across the LED increases over the breakdown value, the current starts toincrease in the reverse direction and the LED goes to the breakdown operation region.

Breakdown Reverse Forwardi

vVd

Vbr

v

i

Fig. 1.2 IV characteristics of an LED.

1.1.2.2 Electrical representation

To properly design the power converter, the LED load has to be modeled. Many modelingtechniques for the LEDs can be found to simulate its electrical behavior. The models can beclassified, from the simplest to the more accurate model, as the following:

1. Equivalent resistance

As shown in Fig. 1.3(a) it is the simplest model, it only takes into account the equivalentresistance of the LED at the nominal operating point. The value of this resistance is


found by calculating the equivalent resistance that consumes the same amount of powerconsumed by the LED, fixing the output voltage and current to be the same values asthe ones of the LED. In other words, the value of the equivalent resistance is equal tothe rated voltage of the LED divided by the rated LED current. This model is onlyvalid if the LED operates around the nominal power with no dimming applied. Eventhough this technique is not valid to evaluate the ripple of the LED as the ripple inthis equivalent model will be much smaller than the real LED ripple, due to the hugedifference between the equivalent resistance and the dynamic resistance of the LED.Furthermore, this model cannot be used to test the transient behavior. This model isusually employed for average model analysis and power flow calculation, but not forthe analysis of the converter behavior.

(b)

Req=VLED

ILED Rdyn

Vth

D

(a)

VLED

VLED

ILED ILED

Fig. 1.3 LED models (a) Equivalent resistance, (b) Linear model.

2. Linear model

It is the most commonly used model. It is made by modeling the forward characteristicsof the LEDs with linear behavior [32–34]. The model, as shown in Fig. 1.3(b), consistsof a voltage source in series with a resistance. The voltage source represents thethreshold voltage; when the value of the voltage is below it there is no current passingnor light emitted. While the series resistance represents the dynamic resistance of theLED. The value of the dynamic resistance is found from the slope of the line connectingthe threshold voltage point to the rated operation point on the I-V characteristics, asshown in Fig. 1.4. This methodology to determine the linear model parameters can befound using the manufacturer datasheet values, and it can be expressed by the followingexpression:

Rdyn =VLED −Vth

ILED(1.1)

8 Introduction

0 10 20 30 40 50 60-0.1

0

0.1

0.2

0.3

0.4

0.5

0.6

Voltage (Volts)

Cu

rren

t (A

mp

s)

Vth

VLED

Fig. 1.4 IV characteristics with linear interpolation based on manufacturer datasheet values;thereshold and rated voltages.

In literature, many practical methodologies can be found to determine the parametersof the linear model of the LEDs.

One of the most famous methodologies is to apply a fixed value of the current andmeasure the value of the voltage over the LEDs. Later redo this experiment withdifferent values of the current until reaching the value of the rated current (in fixedincrement or logarithmic steps). One precaution is always taken, which is to makethe injected current in the form of a very short duration pulse, to not heat up the LEDand affect the threshold voltage of the LED. Moreover, wait sufficient time betweenmeasurements to not accumulate the heat of two successive measurements. The resultstaken from these sets of experiments are drawn in a figure and interpolated into alinear model as shown in Fig. 1.5. Using this linear model the values of the thresholdvoltage as well as the dynamic resistance can be extracted from the intersection withthe horizontal axes and the slope respectively.


42 43 44 45 46 47 48 49 50 510

0.1

0.2

0.3

0.4

0.5

0.6

Voltage (Volts)

Cu

rren

t (A

mp

s)

Measured Curve

Modeled Curve

Fig. 1.5 IV characteristics with linear interpolation based on laboratory measured values.

3. Dynamic Model (Theoretical Equivalent Model).

The model is presented in [35–37] for OLED but it can be applied for inorganic LED aswell. As shown in Fig. 1.6 the model is composed of a resistance Re in series with threeparallel branches. Each branch represents a different interval in the I-V characteristic,as shown in Fig. 1.7.

The three branches and their corresponding intervals can be explained as follows:

(a) Interval I:

This interval is defined when the voltage across the OLED (VOLED) goes fromzero to the threshold voltage of branch II (Vbi). The OLED forward current at thisinterval is very small and has an I-V characteristic similar to a resistive behavior.This interval is represented by an RC branch (Branch I), which is composedof a resistance Rp in parallel with a capacitor Cg. Cg is the OLED capacitanceand it depends on the OLED dielectric material properties, device area, and thethickness of the dielectric layer [38]. Cg can be found by the following equation:

10 Introduction

Cg =ε0εrAact

lorg(1.2)

(b) Interval II

This interval occurs when VOLED is higher than Vbi and lower than the thresholdvoltage of the third branch (Vo). This interval is represented by branch II, whichis composed of a voltage source Vbi in series with another RC branch. The RCbranch is composed of a resistance Rbi and a capacitor Cd . The voltage sourceVbi represents the threshold voltage of this interval. Cd is the OLED diffusioncapacitance, which depends on OLED bias voltage. This branch is connectedthrough an ideal diode Dbi to fix the current going to the branch and not comingfrom it.

(c) Interval III

This interval conducts when VOLED is higher than Vo . It is modeled by branchIII, which is composed of a voltage source Vo in series with a resistance Rs. Thevoltage source Vo represents the threshold voltage of this interval. This branch isalso connected through an ideal diode Ds . Moreover, this branch is connected tothe previous branch using another ideal diode Dc . This diode is used to transferpower from branch II to branch III and not in the reverse way.

CgRp

Rs Rbi

Vo Vbi

Cd

Re

Anode

Cathode

Dbi

DsDC

Branch I Branch III Branch II

Fig. 1.6 Theoretical Equivalent Model of OLED.

1.2 Light-emitting diode drivers 11

0 1 2 3 4 5 6 7 8 9-0.05

0

0.05

0.1

0.15

0.2

0.25

0.3

0.35

X: 6.329

Y: 0.003489

Voltage (Volts)

Cu

rren

t (A

mp

s)

IV Curve

X: 7.177

Y: 0.03495

I II III

Fig. 1.7 IV characteristics of OLED showing the three operating intervals.

1.2 Light-emitting diode drivers

There is a wide range of LED drivers, the general classification can be done by the differencein the input. Thus, the LED drivers can be classified into the following: Direct Current (DC)to DC LED drivers, and Alternating Current (AC) to DC LED drivers. Moreover, the AC toDC LED drivers can be classified into single-phase and three-phase drivers.

1.2.1 DC to DC LED drivers

Numerous types of DC to DC converters can be found in the literature. A straightforwardclassification is based on whether the converter offers electric isolation or not [1]. The mainconverters that offer isolation are the following: Flyback, Forward, Push-pull, Half-bridge,and Full-bridge [39, 40]. Fig. 1.8 shows the electrical diagram of the five previously statedconverters, which feature electric isolation. These topologies have disadvantages as bothflyback and forward are unidirectional topologies, while the push-pull, half-bridge, andfull-bridge suffers a high number of components. Concerning the non-isolated converters, asby [1, 41], there are seven basic converters, buck, boost, buck-boost, Cuk, SEPIC, Zeta, andCSC [42–45] . Fig. 1.9 shows the electrical diagram of the seven previously stated converters,while TABLE 1.1 summarizes the main characteristics of the basic non-isolated DC to DCconverter [1, 41].

12Introduction

VOCO

M 1

L f

D

Vin

VOCO

M 1

D

Vin

D

D1

2

3VOCO

D

Vin

D1

3

M 1

M 2 D2

D4

VOCOVin

M 1

M 2

D2D1

D3 D4

Flyback Forward Push-Pull

Half Bridge

VOCOVin

M 1

M 2

D2D1

D3 D4

Full Bridge

M 3

M 4

Fig. 1.8 Electrical diagram of isolated Basic DC to DC converters topologies. (a) Flyback, (b) Forward, (c) Push-Pull, (d) Half bridge,and (e) Full bridge.

1.2L

ight-emitting

diodedrivers

13

VOCOVin

BuckM 1

VOCOVin

Boost

M 1VOCOVin

Buck-BoostM 1

VOCOVin

Cuk

M 1VOCOVin

SEPIC

M 1

VOCOVin

ZetaM 1

VOCOVin

CSC

M 1

D1

D1 D1

D1

D1

D1

D1

Fig. 1.9 Electrical diagram of non-isolated Basic DC to DC converters topologies. (a) buck, (b) boost, (c) buck-boost, (d) Cuk, (e)SEPIC, (f) Zeta, and (g) CSC.

14 Introduction

Table 1.1 Summary of Non-Isolated Basic DC to DC Converters

CONVERTER OUTPUT TYPE FEATURES

BuckStep-down

Non-inverted output

• High efficiency• Discontinuous input current• Continuous output current

BoostStep-up

Non-inverted output

• High efficiency• Continuous input current• Discontinuous output current• Switch terminal connected to ground• High peak currents in power components

Buck-boostStep-down/step-up

Inverted output• Discontinuous input/output currents• High electrical stresses on switch and diode

CukStep-down/step-up

Inverted output

• Switch terminal connected to ground• Continuous input/output currents• High number of passive components• High electrical stresses on switch and diode

SEPICStep-down/step-upNon-Inverted output

• Switch terminal connected to ground• High number of passive components• Continuous input current• Discontinuous output current

Zeta converterStep-down/step-upNon-Inverted output

• Switch terminal connected to ground• High number of passive components• Continuous output current• Discontinuous input current

CSCStep-down/step-up

Inverted output

• Low number of passive components• Continuous input current• High electrical stresses on the switch


1.2.2 AC to DC LED drivers for single phase applications

The AC to DC LED drivers, or the drivers directly connected to the grid, are made byusing any of the DC to DC converters in series with a four diodes bridge rectifier. The gridconnected LED drivers can be divided into three main types according to the number ofstages used. Fig. 1.10 shows the main three structures of LED drivers.

Vg

Rectifier

LED

DC/DC

PFC

Vg

Rectifier PFC

LED

DC/DC

Vg

Rectifier PFC

LED

DC/DC

(a)

(b)

(c)

Fig. 1.10 Structure of LED drivers. (a) Single-stage. (b) Two-stage. (c) Integrated-stage.

1.2.2.1 Single-stage converters

In the single-stage driver, the converter has two main duties, to deliver constant current tothe LED, and to ensure a high Power Factor (PF) meanwhile. Thus, not all converters canoperate as single-stage drivers. The most commonly used single-stage drivers are the buckand flyback. Both show great output control with acceptable PF correction, for low and evenmedium power applications, when operating in Discontinuous Conduction Mode (DCM)[1, 46, 47]. Buck is preferred if electrical isolation is not required and if it is a step-downoutput voltage application, otherwise the flyback is requested. Fig. 1.11 shows the electricalschematic of the flyback converter operating as Power Factor Correction (PFC) and PowerControl (PC) stages. Concerning the flyback converter operating in DCM the electric stress is

16 Introduction

high, resulting in higher losses in the switch. However, operating in Continuous ConductionMode (CCM) is not a solution as the PF will decrease. Thus, for better performance or higherpower applications, two-stage drivers are required.

1

VO

DO

M

Vg

Gate

LEMI

CEMI

COD2

D1

D 3 D4

Fig. 1.11 Flyback converter operating as power factor correction and power control.

1.2.2.2 Two-stage converters

For the sake of better performance, the two-stage drivers were proposed. The first stage isdedicated to operating as a PFC stage with just one focus, which is to achieve as high PFas possible, and provide a DC voltage to the second stage. While the second stage duty isto operate as a PC stage controlling the current going to the LED, and trying to filter thelow-frequency ripple as much as possible. Having two converters in the same driver makesthe inventors think about additional features in the drivers, such as, achieving almost unityPF, or increasing the lifetime of the driver by avoiding the electrolytic capacitors, or trying toboost the efficiency by applying Zero Voltage Switching (ZVS) or Zero Current Switching(ZCS) techniques.

Obviously, by increasing the number of components and process the power by two con-verters, the efficiency will drop and cost will increase [1]. Moreover, the system complicationwill increase due to the additional control loop required to control the second switch. Toovercome the efficiency issue many techniques were introduced:

• Soft switching operation

Several techniques are proposed to ensure a soft switching operation, such as Quasi-resonant control method [48, 49], ZVS technique, and ZCS technique [50–52].


• Reducing the energy processed by one of the converters.

In this case, the two converters do not operate in cascaded mode anymore. The mainconverter operates as a PFC stage, while the second converter duty is to handle theripple [53, 54]. Thus, it offers an efficiency enhancement as the power processed bythe second converter is not the full power of the LED and a capacitance reduction.

It is not a simple task to list all two-stage LED drivers, as any combination betweentwo DC/DC converters can be made. For the sake of conciseness, only widely utilizedtopologies will be illustrated. The two-stage converter can be classified into two maincategories depending on its configuration [55]. The first category is the cascaded two-stageconverter. This structure is widely used and it is shown in Fig. 1.10 (b) [56–69]. The secondcategory is when one converter is operating as PFC and PC at the same time and the secondconverter is operating as an active filter to eliminate the output ripple [70–72].

• Cascaded two-stage converters

Many topologies that have the boost converter operating as a PFC stage can be foundin the literature. They find huge interest due to its good input current shaping capabilityand low front-end Electromagnetic Interference (EMI) filter requirements. Most com-patible with the boost converter usually is an isolated converter, such as Flyback [56],LLC resonant converter [61], CLCL resonant converter [49], or electronic transformer.However, this is preferred when a third stage will be used to control LED current [67].The boost converter with a non-isolated converter can also be found in the literature,such as the buck, which does not offer electric isolation, however, it ensures relativelyhigh-efficiency [57, 64–66].

A promising PFC converter is the buck-boost operating in DCM or Boundary Conduc-tion Mode (BCM). It is compatible as well with LLC resonant converter to provideisolation [62, 63]. Some techniques provide the electric isolation with the PFC both inthe first stage, operating with the flyback converter in the first stage [68, 69].

• Active filter two-stage converters

As aforementioned, this technique consists of two converters as well. However, it isnot operating in cascaded mode. The first converter operates as PFC and meanwhiledelivers the power to the output, while the second converter duty is to operate asan active filter to eliminate the output ripple. The main scheme of the active filtertwo-stage converters can be seen in Fig. 1.12. The isolation has to be provided in themain converter, thus the flyback is a good candidate for this type of converters [70, 71],as well as the H-bridge rectifier [72].

18 Introduction

DC/DC

Vdc

DC/DC

VStorage

t

gV

t

StorageV

t

dcV

D2D1

D3 D4

Vg

Fig. 1.12 Active filter two-stage converters main scheme.

1.2.2.3 Integrated converters

Integrated converters appear to present a trade-off between the single-stage and two-stageconverters. Integrated converters consist of two power stages, a PFC stage and a PC stage,however, both stages share the same switch. Thus, integrated converters belong to thesingle-stage converters as they operate with a single switch. However, if the classificationis made by the number of stages that process the power, then the integrated converters inthis classification belong to the two-stage converters. As operating by one switch, integratedconverters lose the ability to use a specific controller to eliminate the ripples or to enhancethe PF. It depends mostly on the design, in order to offer a fair enough operation and followthe standards and recommendations without any special control.

Many integrated techniques to drive LEDs can be found in the literature [73–86]. Inthe following a list of most used integrated converters is presented. Table 1.2 shows thecomparison between their features.

• The integrated double buck-boost converter is shown in Fig. 1.13 [73–75]. It consistsof a buck-boost converter operating in DCM as a PFC stage, and another buck-boostconverter operating in DCM as a PC stage.


CB VB

M 1

VCO O

D5 D6 D7

L1

L2

D2D1

D3 D4

Vg

Fig. 1.13 Schematic diagram of the integrated double buck-boost converter.

• The integrated buck flyback converter is shown in Fig. 1.14 [76–79]. It consists ofa buck converter operating in DCM to provide a good PF, as high as possible, and aflyback converter as a PC stage to provide electric isolation.

VOCOD2D1

D3 D4 M 1

LfCB

LB

Vg

IAC

DFL

DFH

DB

DOut

Fig. 1.14 Schematic diagram of the integrated buck and flyback converter.

• The integrated buck-boost and flyback converter is shown in Fig. 1.15 [80]. It consistsof a buck-boost converter operating in DCM as a PFC stage, and a flyback converter asa PC stage to provide electric isolation.

20 Introduction

VOCO

D2D1

D3 D4 M1

Vg

IAC D6

CB

L1

D5

C1

Fig. 1.15 Schematic diagram of the integrated buck-boost and flyback converter.

• The integrated buck-boost and class E resonant converter is shown in Fig. 1.16 [81, 82].It consists of a buck-boost converter operating in DCM as a PFC stage, and a class Eresonant converter as a PC stage to provide electric isolation.

VO

CO

D2D1

D3 D4 M2

Vg

IAC

D7

Cr

D5

M1

L1CB

L2

D6 Cs

Lr

D8

Fig. 1.16 Schematic diagram of the integrated buck-boost and class E resonant converter.

• The integrated flyback and class E resonant converter is shown in Fig. 1.17 [83].It consists of a flyback converter operating as a PFC stage, and a class E resonant


converter as a PC stage to provide electric isolation. In this converter, the flyback isnot providing electrical isolation as the ground of its output and input are connected.

VO

CO

D2D1

D3 D4 M 1

Vg

D7

Cr

D6

Ls

CB C1

Lr

D8

L2

Ci

L m1D5

L m2

Fig. 1.17 Schematic diagram of the integrated flyback and class E resonant converter.

• The integrated boost and LLC resonant converter in its two configurations are shownin Fig. 1.18 [84] and Fig. 1.19 [85]. It consists of a boost converter operating as a PFCstage, and a LLC resonant converter as a PC stage to provide electric isolation.

VO

CO

D2D1

D3 D4 M 2

Vg

D8

Cr

C2D7

Lr

D9

L 2

C i

Lm

M 1 D6

D5

C1

CB

Fig. 1.18 Schematic diagram of the integrated boost and LLC resonant converter.

22 Introduction

VO

CO

D2D1

D3 D4 M2

Vg

D9

D8

Lr

D10

Lm

M1

D5

CB

Cr

L2

D6

D7

Fig. 1.19 Schematic diagram of the integrated boost and LLC resonant converter.

• The integrated buck-boost and LLC resonant converter are shown in Fig. 1.20 [86].It consists of a buck-boost converter operating as a PFC stage, and an LLC resonantconverter as a PC stage to provide electric isolation.

VO

CO

D2D1

D3 D4 M2

Vg

D11

Cr

C2D8

Lr

D12

C i

Lm

M1 D7

D5

C1

Cb1

L1

Cb2

D6

L2

D10

D9

Fig. 1.20 Schematic diagram of the integrated buck-boost and LLC resonant converter.

1.2L

ight-emitting

diodedrivers

23Table 1.2 A Summary of Integrated Converters

INTEGRATEDDOUBLE

BUCK-BOOST

INTEGRATEDBUCK ANDFLYBACK

INTEGRATEDBUCK-BOOSTAND CLASS E

RESONANT

INTEGRATEDFLYBACK AND

CLASS ERESONANT

INTEGRATEDBOOST AND

LLC RESONANT

INTEGRATEDBUCK-BOOST

AND LLCRESONANT

One switch One switch One switch One switch Two switch Two switch

Two inductors One inductor Three inductors Two inductors One inductor Two inductors

No transformers One transformer One transformer Two transformers One transformer Two transformers

Four diodes Four diodes Six diodes Four diodes Four diodes Six diodes

Two capacitors Two capacitors Four Capacitors Four Capacitors Six Capacitors Five Capacitors

High voltage stressover the switch.

720 V, for outputvoltage 200 V.


Around 700 V, foroutput voltage 48 V.









High bulk capacitorvoltage. 240 V to366 V, for output

voltage 200 V.

High bulk capacitorvoltage. 60 % ofinput voltage, for

output voltage 48 V.

High bulk capacitorvoltage. 160 V, foroutput voltage of

50 V.

High bulk capacitorvoltage. Around200 V, for output

voltage 50 V.

High bulk capacitorvoltage. 430 v, foroutput voltage of

50 V.

High bulk capacitorvoltage. 420 v, foroutput voltage of

50 V.

No electricisolation.

Electric isolation Electric isolation Electric isolation Electric isolation Electric isolation

Power factor 0.96 Power factor 0.96 Power factor 0.99 Not mentioned Power factor 0.98 Power factor 0.995

Efficiency of 85 %,at rated power 70

W.

Efficiency of 80 %,at rated power 100

W.

Efficiency of90.8%, at ratedpower 100 W.

Not mentionedEfficiency of

91.1%, at ratedpower 100 W.

Efficiency of 91%,at rated power 100

W.

24 Introduction

1.2.3 AC to DC LED drivers for three-phase applications

The three-phase drivers are not as widely used as the single-phase application. Thus, it isusually designed to meet a specific application requirement. The reason is that three-phaseis not easily accessible and that the driver cannot be universal due to the huge variationof three-phase grids among countries. Mainly, three-phase is only applicable in industrialinstallation, stadium, conventional centers, etc. On the other hand, the three-phase driversshow a great advantage compared to single-phase drivers. In single-phase, the usage of anelectrolytic capacitor to eliminate the flicker effect is a must unless a special technique ismade. This decreases the lifetime of the converter or increases the complexity of the converter.However, the three-phase grid offers constant instantaneous power, which ensures a nearlyconstant current in the case of an LED load. Moreover, the flicker will occur at six times theline frequency, not at double the line frequency as in single-phase drivers [87].

In the literature, both single-stage and two-stage three-phase drivers can be found.

1.2.3.1 Three-phase single-stage converters

A sub-classification under the single-stage three-phase drivers can be made, mainly into twotypes, the single switch, and multi-switch drivers.

• Single-switch single-stage three-phase driver

One widely used topology is the three-phase boost converter, shown in Fig. 1.21[88–92]. The converter offers many advantages such as operating with a single switch,high PF, low number of components, and straight forward control.

D2D1

D4 D5

Va

D

D3

D6

M1

Vb

Vc

La

Lb

Lc

VOCO

Fig. 1.21 Schematic diagram of the three-phase single switch boost converter.


The three-phase flyback converter, shown in Fig. 1.22 [93, 94] is found in the literature.The flyback converter offers the same advantages as the boost converter. Besides, itoffers electric isolation.

D2

D1

D4

D5

Va

D3

D6

M1

Vb

Vc

VOCO

D9

D8

D7

Fig. 1.22 Schematic diagram of the three-phase single switch flyback converter.

Some other topologies can be found in the literature, such as buck converter or modifiedbuck with electrical isolation, respectively shown in Fig. 1.23 (a) Fig. 1.23 (b) [95].

D2

D1

D4

D5

Va

D

D3

D6

M1

Vb

Vc

La

Lb

Lc

VOCO

L

C

C C

(a)

D2

D1

D4

D5

Va

D3

D6

M1

Vb

Vc

La

Lb

Lc

C

C C

VOCO

LD7

D8(b)

Fig. 1.23 Schematic diagram of the three-phase single switch (a) buck converter (b) modifiedbuck with electric isolation.

26 Introduction

• Multi-switch single-stage three-phase driver

Seeking performance enhancement many techniques were proposed, such as controllingthe shape of the current in each phase by operating with multi-switch instead of justone. Fig. 1.24 shows the same boost three-phase converter but operating with sixswitches trying to achieve unity PF [96]. While [87] presents a low flicker driver usingsix switches three-phase resonant switched capacitor, shown in Fig. 1.25.

Va

Vb

Vc

La

Lb

Lc

VOCO

M 2 M 3M 1

M 5 M 6M 4

Fig. 1.24 Schematic diagram of the three-phase multi-switch boost converter.

D2

D1

D4

D5

D3

D6

VOCO

L

C

VaVbVc

S1 S2 S3

C

C

S4 S5 S6

Fig. 1.25 Schematic diagram of the three-phase resonant switched capacitor converter.


1.2.3.2 Three-phase two-stage converters

The same motive of achieving unity PF, LED flicker-free, boosting the efficiency and moreother features, facilitate the introduction of the two-stage converter in three-phase applications.Shown in Fig. 1.26 shows the schematic proposed by [97] as a modular three-phase LEDdriver without galvanic isolation in the second stage.

D2

D1

D3

D4

Va

Vb

Vc

VOCO

PFC DC/DC

D6

D5

D7

D8

PFC DC/DC

D10

D9

D11

D12

PFC DC/DC

Fig. 1.26 Schematic diagram of the three-phase two stage LED driver without galvanicisolation.

Finally Fig. 1.27 shows a block diagram for the classification for both single-phase andthree-phase LED drivers [98].

28 Introduction

AC-DC LED drivers

Single-phase Three-phase

Passive Single-stage Multi-stage Multi-cell

Single-switch Multi-switch

Active

Multi-stage

Modular

Single-stage

Integrated

Fig. 1.27 Classification of ac–dc LED drivers for both single-phase and three-phase ac powergrids.

1.3 LED dimming techniques

The dimming in LED is to attenuate the output power of the LED and in return controlthe light intensity. Dimming is an essential feature in many lighting applications and it isnecessary in Red-Green-Blue (RGB) LED based lamps in order to change the light color. Bycontrolling the intensity of each color the resultant color of the LED can be controlled. Manydimming techniques can be found in the literature. They can be classified mostly in twogeneral classes, the Amplitude-Modulation (AM) dimming, and the Pulse Width Modulation(PWM) dimming [99–114].

Other LED dimming techniques are found in the literature, like: Triode AC semiconductorswitch (TRIAC) dimming [115–118], and hybrid solution between PWM dimming and AMdimming, named hybrid PWM/AM dimming [119–121]. However, these techniques arespecial configurations of the previously stated techniques.

1.3.1 Amplitude-modulation dimming

AM dimming is made by changing the amplitude of the DC-output current, which in returnwill change the LED output luminous flux, and lighting intensity [99–101]. AM dimming issimple and straightforward. Nevertheless, there is a lot of research made in it, trying to find avery precise control for the output current [99], trying to overcome the communication issues[100], or proposing new ideas such as using resonant converters and varying the resonanttank behavior to vary the output current [102, 103]. However, the AM technique shows a

1.3 LED dimming techniques 29

significant drawback, which is a lack of linearity that can occur at high injection currents, aswell as a noticeable shift in the chromaticity coordinates [104–109].

1.3.2 Pulse-Width-Modulation dimming

PWM dimming is to switch on and off the LED at a fixed DC current value. The controlof the light intensity is made by changing the duty of the dimming. This technique is notaffecting the human eye as long as the dimming switching frequency is above the flickerfrequency. The minimum dimming frequency in order not to notice the flickering and to avoidthe stroboscopic effect is considered to be 120 Hz [105, 106, 109], but authors recommendat least frequencies above 200 [108], 300 [105, 106], or even 400 Hz for some applications[110], so the human eye does not perceive the light pulses—not even in motion—and movingobjects seem not to be still.

Found in literature three PWM dimming techniques:

1.3.2.1 Enable PWM dimming

Enable PWM dimming is made by switching on and off the full converter at a frequencylower than the control frequency, called the dimming frequency. Most drivers are designedto be Switched-Mode Power Supplies (SMPS) applications, which means they have to havean enable/disable or shutdown pin. Thus, it can be switched on and off by a logic-levelsignal, and dimming can be achieved. The most common methodology used to implementthis technique is to combine the control PWM signal with a dimming signal to create theoperational signal. The generation of the gate signal of the enable dimming is illustrated inFig. 1.28.

Gate Signal

Dimming Signal

Final Gate signal with Dimming

D Tm m

DT

T

Tm

Fig. 1.28 Gate signal generation of the enable PWM dimming technique.

30 Introduction

The main drawback is that the enable PWM dimming technique makes the converter toface transient issues with a frequency equals to the dimming switching frequency. This isbecause the whole converter is switched on and off each time the LED is switching. Moreover,if the dimming frequency is very high, the converter would not be able to reach the ratedcurrent or the current in the LED will not reach zero. Thus, a continuous current for theLED will occur. To prevent this issue, a lower dimming frequency is preferred; however, thisis limited by the flicker regulation. These phenomena are clarified by [111] as it shows acomparison for the LED current in enable dimming operation at 200 Hz dimming frequency,and at 100 Hz dimming frequency. It is shown that the output current at 200 Hz dimmingfrequency at a high dimming ratio of 80 % is continuous. Thus, a decrease in the dimmingfrequency to 100 Hz, to dim the output current. However, this low dimming frequency is notacceptable in terms of flicker issues.

1.3.2.2 Series PWM dimming

The series PWM dimming is the most commonly used dimming technique. It is made byadding a switch in series with the LED [112, 113], as shown in Fig. 1.29. The load switcheson and off by the series switch commanded by a PWM signal. The output voltage remainsconstant around the nominal value added to it a voltage ripple that depends on the outputcapacitance value. A modification in the control has to be done, as it should compensate forthe disconnection of the feedback loop when the current in the LED suddenly goes to zero.Moreover, the reference signal should change to the dimming value of the LED current.

D

M1 VOCO

L

Vin

M2

LED

Fig. 1.29 Single stage LED driver with Series PWM technique applied.

1.3 LED dimming techniques 31

The drawback of the series PWM dimming, is that it causes a variation in the outputvoltage, leading to a variation in the LED DC current value. Therefore, the LED currentexperiences high peaks, reaching twice the value of the nominal current. Using this techniquea bulky output capacitor is needed, which can reach 2000 µF [112].

1.3.2.3 Shunt PWM dimming

The Shunt PWM dimming is accomplished by a switch in parallel with the LEDs as shownin Fig. 1.30 [114]. The shunt dimming can be either in the current control mode or voltagecontrol mode.

• Current control mode

In the current control mode, the converter operates as a current source, where current ismaintained constant at the rated value of the LED current. Dimming is accomplishedby shunting this current away from the LED with the parallel switch. This reduces theaverage value of current going to the LED, and in return, the light intensity.

• Voltage control mode

In the voltage control mode, the output voltage switches between the rated voltageand zero when the parallel switch turns on. In this case, as the converter operation issimilar to a voltage source, the output current is defined by the load. When the switchis ON, the inductor current flows through the switch.

This technique offers a great advantage, which is the ability to have a fast switching forthe LED. However, as the converter is kept working, the efficiency is slightly reduced due tothe losses of the extra switch and the circulating power.

VOCO

LEDM2

RSENSER 1

R 2

Zener

To

Controller

Fig. 1.30 LED driver with Shunt PWM technique applied.

32 Introduction

1.4 Light-emitting diodes regulations and standards

Similarly to the traditional lighting, an LED system should comply with associated luminairestandards and international regulations. These standards and regulations pose basic require-ments over LED systems. The regulation and standards can be summarized to the main fourfollowing regulations:

1.4.1 Energy Star

ENERGY STAR® is a US government agency for energy efficiency, providing simple,credible, and unbiased information that consumers and businesses rely on to make well-informed decisions. Trying to boost the efficiency, power density, and lifetime, whiledecreasing the cost of the LED system, the Energy Star program published several LEDstandards [122–124]. The standard starts usually with the included and excluded products.Later comes the effective data with the date in which these specifications start to take effect.Then, it shows the list of future specification revisions. Upon that, the documents presents alist with the definitions that will be used in the standards. An important topic, that has to beincluded, is the test criteria for the product. Later on starts the specifications, TABLE 1.3summarizes the most relevant specifications for LED.

1.4.2 IEC 61000 Part 3-2

International Electrotechnical Commission (IEC) is a worldwide organization for standard-ization comprising all national electrotechnical committees (IEC National Committees). Theobject of IEC is to promote international co-operation on all questions concerning standard-ization in the electrical and electronic fields. To this end and in addition to other activities,IEC publishes International Standards, Technical Specifications, Technical Reports, PubliclyAvailable Specifications (PAS) and Guides (hereafter referred to as “IEC Publication(s)”).

IEC 61000-3-2 Electromagnetic Compatibility (EMC): Limits for harmonic currentemissions is an international standard that limits mains voltage distortion by prescribing themaximum value for harmonic currents from the second harmonic up to and including the40th harmonic current [125]. IEC 61000-3-2 applies to single-phase equipment with a ratedcurrent up to 16 A, for equipment above 16 A IEC 61000-3-2 needs to be applied. The IEC61000 Part 3-2 contain 4 different classes that have different limit values. TABLE 1.4 showsthe equipment classification of the IEC 61000 Part 3-2. As shown in TABLE 1.4 the lightingequipment belongs to Class C. Fig. 1.31 shows the harmonics percentage limit in IEC 61000Part 3-2 Class C.

1.4L

ight-emitting

diodesregulations

andstandards

33Table 1.3 ENERGY STAR® Program Applied to LED Lamps

CHARACTERISTICS ENERGY STAR REQUIREMENTS

Luminous Efficacy• Omidirectional 70 lm/W for CRI > 90 & 80 lm/W for CRI < 90.• Directional 61 lm/W for CRI > 90 & 70 lm/W for CRI < 90.• Decorative 65 lm/W.

Correlated ColorTemperature (CCT)

Nominal CCT:2700 K,3000 K,3500 K, 4000 K or 5000 K.

Color Rendering IndexThe luminary, retrofit kit, or LED light engine shall be capable of meeting or exceeding Ra > 80 andR9 > 0

Lifetime

The LED package(s)/module(s)/array(s), including those incorporated into luminaires, retrofit kitsand LED light engines, shall meet the following L70 rated lumen maintenance life values, in situ:• L70(6k) > 25,000 hours for indoor• L70(6k) > 35,000 hours for outdoor• L70 > 50,000 hours for inseparable luminaries

Source StartLight source shall remain continuously illuminated within 750 milliseconds of application ofelectrical power.

Source Run-Up TimeReported value of time for lamps to reach 80% of stabilized lumen output after application ofelectrical power shall be < 45 seconds

Power Factor• Total luminary input power < 5 watts: PF > 0.5• Total luminary input power > 5 watts: PF > 0.7

Transient protectionPower supply shall comply with IEEE C.62 41-1991, Class A. The line transient shall consist ofseven strikes of a 100-kHz ring wave 2.5-kV level, for both common mode and differential mode.

Operating Frequency Frequency > 120 Hz

DimmingThe luminaire and its components shall provide continuous dimming from 100% to 20% of lightoutput. No emit noise above 24dBA at 1 meter at the minimum output.

WarrantyA warranty must be provided for lamps, covering material repair or replacement for a minimum ofthree (3) years from the date of purchase.

34 Introduction

Table 1.4 Equipment Classification of the IEC 61000 Part 3-2

CLASSES EQUIPMENT

Class A

• Balanced 3-phase equipment.• Household appliances excluding equipment identified as class D.• Tools, excluding portable tools.• Dimmers for incandescent lamp.• audio equipment.• All other equipment, except that stated in one of the followingclasses.

Class B• Portable tools.• Arc welding equipment which is not professional equipment.

Class C • Lighting equipment.

Class D • PC, PC monitors, radio, or TV receivers. Input power P < 600 W.

23 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 390

5

10

15

20

25

30

Harmonic Order

Har

mon

ic D

isto

rtio

n (%

)

IEC 61000−3−2 Class C

Fig. 1.31 Harmonic content limit of the IEC 61000-3-2 Class C.

1.4 Light-emitting diodes regulations and standards 35

1.4.3 IEEE 1789-2015

The IEEE 1789-2015 standard includes a definition of the concept of modulation frequenciesfor LEDs, a discussion on their applications to LED lighting, a description of LED lightingapplications in which modulation frequencies pose possible health risks to users, a discussionof the dimming of LEDs by modulating the frequency of driving currents/voltage, and recom-mendations for modulation frequencies (flicker) for LED lighting and dimming applicationsto help protect against known potential adverse health effects [126].

As by the standards, all light sources modulate light, or flicker, to some degree, usually as aconsequence of their drawing power from ac mains sources. The flicker created by electricallypowered light sources is typically periodic. A periodic waveform can be characterized by atleast four parameters:

• Its amplitude modulation (i.e., a variation in amplitude over a periodic cycle).

• Its average value over a periodic cycle (also called the dc component).

• Its shape or duty cycle (in this recommended practices document duty cycle normallyrefers to the percentage of time spent at maximum value in (PWM) square waves).

• Its periodic frequency.

The viewer’s response to a flickering light depends on all these characteristics; of these,frequency has been the most studied and is better understood.

Fig. 1.32 shows a random LED current on which the maximum and minimum valuesare explained, and Area 1 and Area 2. These terms will be used to determine the followingexpressions:

• Flicker index

Introduced by Eastman and Campbell [127], is defined by Lehman et al. [128] as thearea above the line of average light divided by the total area of the light output curvefor a single cycle. It is expressed as the following:

FlickerIndex =Area1

Area1+Area2(1.3)

• Percent flicker

Also known as peak-to-peak contrast, Michelson contrast, Modulation (%), or modula-tion depth. Referring to Fig. 1.32, percent flicker is defined as:

36 Introduction

PercentFlicker = 100∗ Max−MinMax+Min

= 100∗ A−BA+B

(1.4)

0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.41

2

3

4

5

6

7

Time (Sec)

Cu

rren

t (A

mp

s) Average

Area 2

Area 1

A

Maximum Value

B

Minimum Value

Fig. 1.32 Diagram for definition of flicker index and percent flicker.

Using the modulation (%) the standard created a recommendation region as shown inFig. 1.33. Operating in the shaded area minimizes visual discomfort or annoyance and alsogives low risk for headaches and photosensitive epileptic seizures. Below 90 Hz, Modulation(%) must be less than 0.025×frequency. At or above 90 Hz, Modulation (%) must be below0.08×frequency.

1.4 Light-emitting diodes regulations and standards 37

100

101

102

103

104

10-1

100

101

102

Frequency (Hz)

Mo

du

lati

on

(%

)

Recommended

Operating Area

Mod % = 0.08 * f

Mod % = 0.025 * f

Fig. 1.33 Recommended practices summary.

1.4.4 CISPR 15:2018 © IEC 2018

CISPR 15:2018 applies to the emission (radiated and conducted) of radio-frequency distur-bances from:

• lighting equipment;

• the lighting part of multi-function equipment where this lighting part is a primaryfunction;

• UV and IR radiation equipment for residential and non-industrial applications;

• advertising signs;

• decorative lighting;

• emergency signs.

In recent times the incidence of interference from lighting appliances has increased. Thishas coincided with technological developments in the lighting industry. Thus, CISPR15 has

38 Introduction

been seen as insufficient as it was limited to frequencies up to 30 MHz [129]. However, theninth edition cancels and replaces the eighth edition published in 2013 and its Amendment1:2015.

This edition includes the following significant technical changes with respect to theprevious edition:

1. full editorial revision and restructuring;

2. the restriction to mains and battery operation is deleted in the scope;

3. radiated disturbance limits in the frequency range 300 MHz to 1 GHz have beenintroduced;

4. the load terminals limits and the CDNE (alternative to radiated emissions) limits havechanged;

5. deletion of the insertion-loss requirements and the associated Annex A;

6. introduction of three basic ports: wired network ports, local wired ports and theenclosure port;

7. introduction of a more technology-independent approach;

8. replacement of Annex B (CDNE) by appropriate references to CISPR 16-series ofstandards;

9. modified requirements for the metal holes of the conical housing;

10. new conducted disturbance measurement method for GU10 self-ballasted lamp;

11. addition of current probe measurement method and limits for various types of ports (inaddition to voltage limits and measurement methods);

12. introduction of the term ‘module’ (instead of independent auxiliary) and requirementsfor measurement of modules using a host (reference) system;

13. modified specifications for stabilization times of EUTs;

14. for large EUT (> 1,6 m), addition of the magnetic field measurement method using a60 cm loop antenna at 3 m distance (method from CISPR 14-1) as an alternative to the3 m and 4 m LAS.

1.5 Chapters Overview 39

1.5 Chapters Overview

1.5.1 Chapter 2

This chapter presents a study of the losses in the Integrated Buck Flyback Converter (IBFC)used as high-power-factor LED driver. The study aims to investigate the possibilities ofincreasing the efficiency of the IBFC converter. The procedure of the improvement is doneby obtaining the equations of the current through each component in terms of converterparameters. The current is found in an average value or RMS value, depending on the type ofthe parasitic component, whether it is modeled by a parasitic forward voltage source or by aparasitic resistance, respectively. Using these equations and the parasitic model, the losses ofeach element of the converter are estimated. Moreover, it proposes a technique to increasethe efficiency of the IBFC by redesigning the converter parameters. Furthermore, it presentsa case-study with a step-by-step efficiency enhancement process of an existing driver. Thedriver is operating under universal input conditions, and 38 V output, supplying an LEDluminary of 26.5W. The new design shows an improvement of the efficiency from 82% in theold design to 89% in the proposed one. Moreover, the new design shows an improvement inthe PF and the Total Harmonic Distortion (THD) and a 50% reduction in the output currentripple. Furthermore, a reduction in the number of components has been achieved, as it isfound by the analysis that by adjusting the converter parameters, one diode can be removed.Finally, the presented methodology is explained in detail so that it can easily be applied toother DC-DC converters.

1.5.2 Chapter 3

In this chapter, the work on the IBFC is continued. It presents a solution for a high PF, lowTHD (LED) driver with dimming capability. In addition, the proposed technique ensuresa high PF and low THD at any dimming level. The driver is implemented by using aninterleaved capacitor, which is placed between the rectifier and the IBFC. In this way, theline current conduction angle is increased, which in return increases the PF and decreases theTHD. The operation of the proposed converter ensures that one diode of the conventionalIBFC will not conduct so that it can be removed. Moreover, owing to the continuouspower flow, the proposed technique makes a significant reduction of the converter outputripple. Moreover, the chapter includes the design procedures of a prototype for the proposedconverter supplying an LED luminaire of 37 V/ 0.67 A. The prototype shows a high PF of0.997, small THD of 2.5%, output current ripple of 6%, and efficiency of 80%.

40 Introduction

1.5.3 Chapter 4

This chapter presents a study for a new PWM dimming technique for the IBFC. The techniqueis made in two versions, passive Hybrid Series Parallel (HSP) PWM dimming technique,and active HSP-PWM dimming technique. The passive methodology is made by addinga switch in series with the LED and another parallel path for the current to limit the peakLED current. While the active methodology is made by integrating a buck converter at theoutput of the IBFC. The proposed converter is Integrated Buck Flyback Buck Converter(IBFBC). The IBFBC ensures a constant output current regulation as well as high PF at alldimming ratios. The purpose of the output buck converter is to clear up the discontinuouspower operation created by the PWM dimming. This occurs when the buck converter absorbsthe output power, at LED switched-off, and sends it back to the input. Thus, the IBFBCmaintains the operational enhancement shown by the passive HSP-PWM technique, ensuringgreater efficiency. The chapter includes an explanation for the operating principles of theIBFBC using circuit diagrams as well as an average model for the entire converter. Moreover,it includes a mathematical analysis of the IBFBC power flow. It gives guidance on howto select the optimum value for the output buck inductance. Finally, a 230 V, 50 Hz input,160 V output, 100 W AC–DC converter operating at 100 kHz has been implemented. Theprototype is fully tested to demonstrate both active and passive HSP-PWM technique. Anefficiency ranging 50–86% corresponding to the dimming ratio of 5–100% is reached, where5% dimming refers to an output power of 4 W.

1.5.4 Chapter 5

In this chapter, a high-power-density off-line LED driver is proposed. The proposed AC-DCdriver is the novel Integrated Buck and Boost Converter (IBBC). Besides the high-power-density, the converter shows a high PF and a low THD. The IBBC is a two-stage driver thatfeatures just one controlled switch, which leads to high PF and low THD operation ensuringhigh efficiency, and size and cost reduction. Moreover, the switch current is minimized as itconducts the higher of the buck or boost converter, but not the addition of both as in otherintegrated converters. Moreover, for a further increase in the power-density, a magneticintegration is made by integrating the two inductors of both the buck and boost convertersin one core. Thus, the proposed converter has been named as Fully Integrated Buck andBoost Converter (FIBBC). In this chapter, the IBBC is analyzed, and a design methodology isproposed. Also, it includes a magnetic analysis of the novel FIBBC. In addition, a comparisonbetween two prototypes is presented, one for the IBBC and another for the FIBBC, both ofthem supplying an LED luminaire of 46 V/ 0.575 A. The FIBBC shows a high PF equal

1.6 List of Publication 41

to 0.994, very small THD of 10%, output current ripple of 6 %, and efficiency of 92.62 %,which represents a landmark on the efficiency of integrated converters.

1.5.5 Chapter 6

This chapter presents a high accuracy dynamic model for the OLED. The model is presentedfor different aged OLEDs, showing the aging effect on each model parameter. This modelis done by splitting the characteristics of the OLED into three parts. Thus, the model hasthree operation modes that simulate a behavior similar to the OLED characteristics. Theproposed aging OLED model can be used as a tool to analyze and develop an OLED driverbefore manufacturing. The proposed model can save years of waiting to evaluate the driverbefore going to the market because the behavior of the arrangement driver plus OLED canbe simulated including aging effects. Moreover, it includes a methodology to predict thelifetime of the OLED just by measuring the voltage across the OLED at rated current. Finally,it presents two different experimental verification methodologies for the proposed model onthe Philips GL-55. The model is verified on four different lifetimes OLEDs, namely; L100,L70, L50, and L30. The first verification is to extract the I-V characteristics experimentallyand match it with the model. The second verification is to apply a current square waveformon the OLEDs with different duties. Later on, the voltage across the OLED is matchedexperimentally with the model. Moreover, a study of the effect of aging on each parameter ofthe dynamic model is included.

1.5.6 Conclusion and future work

In this chapter, the conclusion of the work presented in this document is concluded. Moreover,a concise description of future work is illustrated.

1.6 List of Publication

In the following is the list of publication supporting the research presented in this document,starting by the journal publications, then the international conferences publications[130–141];

• G. Z. G. Abdelmessih, J. M. Alonso, M. A. Dalla Costa, Y. Chen and W. Tsai, "FullyIntegrated Buck and Boost Converter as a High-Efficient High-Power-Density Off-LineLED Driver," in IEEE Transactions on Power Electronics, Early Access.

• G. Z. Abdelmessih, J. M. Alonso and M. A. Dalla Costa, "Analysis, design, andexperimentation of the active hybrid-series-parallel PWM dimming scheme for high-

42 Introduction

efficient off-line LED drivers," in IET Power Electronics, vol. 12, no. 7, pp. 1697-1705,19 6 2019.

• G. Z. Abdelmessih, J. M. Alonso and W. Tsai, "Analysis and Experimentation on aNew High Power Factor Off-Line LED Driver Based on Interleaved Integrated BuckFlyback Converter," in IEEE Transactions on Industry Applications, vol. 55, no. 4, pp.4359-4369, July-Aug. 2019.

• G. Z. Abdelmessih, J. M. Alonso and M. A. Dalla Costa, "Loss Analysis for EfficiencyImprovement of the Integrated Buck–Flyback LED Driver," in IEEE Transactions onIndustry Applications, vol. 54, no. 6, pp. 6543-6553, Nov.-Dec. 2018.

• J. M. Alonso, M. S. Perdigão, G. Z. Abdelmessih, M. A. Dalla Costa and Y. Wang,"SPICE Modeling of Variable Inductors and Its Application to Single Inductor LEDDriver Design," in IEEE Transactions on Industrial Electronics, vol. 64, no. 7, pp.5894-5903, July 2017.

• G. Z. Abdelmessih, J. M. Alonso, W. Tsai and M. A. Dalla Costa, "High-Efficient High-Power-Factor Off-Line LED Driver based on Integrated Buck and Boost Converter,"2019 IEEE Industry Applications Society Annual Meeting, Baltimore, MD, USA,2019, pp. 1-6.

• G. Z. Abdelmessih, J. M. Alonso, L. Canale, P. Dupuis, A. Alchaddoud and G. Zissis,"Aging Model for Life Prediction and Simulation of Organic Light-Emitting Diodes(OLEDs)," 2019 IEEE International Conference on Environment and Electrical Engi-neering and 2019 IEEE Industrial and Commercial Power Systems Europe (EEEIC /I&CPS Europe), Genova, Italy, 2019, pp. 1-6.

• G. Z. Abdelmessih, J. M. Alonso and W. Tsai, "Analysis and experimentation on a newhigh power factor off-line LED driver based on interleaved integrated buck flybackconverter," 2018 IEEE Applied Power Electronics Conference and Exposition (APEC),San Antonio, TX, 2018, pp. 429-436.

• G. Z. Abdelmessih and J. M. Alonso, "Loss analysis for efficiency improvement of theintegrated buck-flyback converter for LED driving applications," 2017 IEEE IndustryApplications Society Annual Meeting, Cincinnati, OH, 2017, pp. 1-8.

• J. M. Alonso, M. Perdigão, G. Z. Abdelmessih, M. A. Dalla Costa and Y. Wang,"SPICE-aided design of a variable inductor in LED driver applications," 2016 IEEEIndustry Applications Society Annual Meeting, Portland, OR, 2016, pp. 1-8.

1.7 Patent 43

• G. Z. Abdelmessih and J. M. Alonso, "A new active Hybrid-Series-Parallel PWMdimming scheme for off-line integrated LED drivers with high efficiency and fastdynamics," 2016 IEEE Industry Applications Society Annual Meeting, Portland, OR,2016, pp. 1-8.

• G. Z. Abdelmessih, J. M. Alonso and M. S. Perdigâo, "Hybrid series-parallel PWMdimming technique for integrated-converter-based HPF LED drivers," 2016 51st In-ternational Universities Power Engineering Conference (UPEC), Coimbra, 2016, pp.1-6.

1.7 Patent

The Fully integrated buck and boost converter is patented in three different regions with thefollowing references.

• China Patent: 201811342664.0

• Taiwan Patent: 107138097

• European Patent number, Application number: 19154150.7 - 1201

The statement of the patent is found in Appendix A.

Chapter 2

Integrated Buck Flyback ConverterLosses analysis and EfficiencyImprovement

Contents2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

2.2 Losses Analysis Methodology for the IBFC . . . . . . . . . . . . . . . 48

2.2.1 Bridge Rectifier Losses . . . . . . . . . . . . . . . . . . . . . . . 48

2.2.2 Inductor Losses . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

2.2.3 Transformer Losses . . . . . . . . . . . . . . . . . . . . . . . . . 54

2.2.4 Buck Diode Losses . . . . . . . . . . . . . . . . . . . . . . . . . 56

2.2.5 Switch Losses . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

2.2.6 Integrated Diodes Losses . . . . . . . . . . . . . . . . . . . . . . 63

2.2.7 Flyback Diode Losses . . . . . . . . . . . . . . . . . . . . . . . 65

2.2.8 EMI filter Losses . . . . . . . . . . . . . . . . . . . . . . . . . . 66

2.3 Simulation Verification . . . . . . . . . . . . . . . . . . . . . . . . . . 67

2.4 Practical Case Study for Efficiency Improvement . . . . . . . . . . . . 69

2.5 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

2.6 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

46 Integrated Buck Flyback Converter Losses analysis and Efficiency Improvement

2.1 Introduction

LEDs are known by their significant-high efficacy of output light intensity with respect toinput electrical power. However, the necessity of a driver to drive the LED decreases the totalefficacy of the LED system. As aforementioned, integrated converters show great operationalspecifications. However, their efficiency is questionable. This was the motivation for studyingthe losses of each component of integrated converters, to enhance the efficiency by improvingthe design.

Converter loss analysis and efficiency improvement are the primary concern of researchersin recent days [1]. Different approaches can be found in the literature for efficiency improve-ment. For instance, a trend in research would be to try to improve efficiency by just going tonew technology that offers higher efficiency, going from conventional Si switching devices tonew SiC or Gallium Nitride (GaN) switching devices. A common research line is to comparethe efficiency of the converter using different switching devices [142–149]. Another trendwould be to focus more on the analysis of the device losses trying to create a more accuratemodel so that it imitates the practical model, with a special focus on the switching devices[150–152]. The aim of this work is different; it is focused on making a detailed mathematicalmodel for the losses of the converter in terms of its parameters, so that it would be easy laterto determine the exact cause of the losses and to reduce them.

Fig. 2.1 shows the converter chosen for this deep analysis, which is the IBFC. Fig. 2.1shows the schematic diagram of the IBFC connected to the grid through an EMI filter. Thechoice was made owing to its numerous good features explained as follows [32, 76, 77, 111,153]:

1. High PF

The converter consists of two stages; the flyback working in DCM and its duty isto deliver the power to the output, and the buck converter also operating in DCM toemulate a loss-free resistor to the grid, to increase the PF.

2. Fast output regulation

The operation of integrated converters shows another feature, which is the fast outputvoltage/current regulation.

3. Low bulk voltage

This technique has an advantage over the PFC stage boost-based integrated converters,which is the low bus voltage. For the same input voltage, for instance, 220 Vrms, inbuck-based converters, the voltage over the bulk capacitor will be below this input

2.1 Introduction 47

voltage value, while for boost-based converters it would be higher. This leads tothe usage of a lower bulk capacitor rating with a smaller size, lower series parasiticresistance, if the same capacitance value is used.

4. Input and output isolation

The presence of the flyback converter in the PC stage offers isolation between the inputand output.

5. The main switch handles less current

The integration of the IBFC is a over-voltage integration. Thus, the IBFC shows anadditional feature compared to the over-current integrated converters, such as double-boost and double-buck-boost integrated converters. The main switch of the IBFC doesnot handle the additional current of both converters (buck and flyback) but it handlesonly the highest of them. This feature will be comprehensively explained later on inthe chapter.

VOCOD2D1

D3 D4 M1

LmCB

LB

Vg

iAC

DFL

DFH

DB

DOut

VB

iBuck i fly input i fly output

i switch

iDFH

iD FL

iDB

Fig. 2.1 Integrated buck flyback converter with the EMI filter connected to it.

In the following, it is presented the losses analysis methodology that can be adapted toany converter, not even just integrated converters:

• Expression for the losses in each component

The first step is to find an expression for the losses in each component of the converter.In this step, the model of each component has to be determined, for instance, the diodelosses model will be a voltage source with a voltage value equal to its threshold voltage.In this case, the following step would be to find an expression for the average value


of the current passing through this diode. The second step will change to find theexpression of the Root Mean Square (RMS) of the current if the component loss ismodeled by a resistance. Finally, get the corresponding current expression and useit in the model of the component to determine the expression of the losses in thiscomponent.

• Expression for the current in each component

The current expression at each component is found by the following procedure. First,the current behavior has to be studied. Later on, divide the current scheme into severalintervals depending on its expression at each interval. Consequently, define both thecurrent expression in these intervals and the limits of each interval. Finally, by theintegration of the current expression over its corresponding interval the final expressionof the current is found.

• Losses estimation of the full converter

By adding all the expressions of the losses in each component of the converter, anestimation for the total losses in the converter is found.

2.2 Losses Analysis Methodology for the IBFC

Following the previously stated losses methodology, an estimation for the losses in the IBFCis found. The total losses of the IBFC are split into the losses in the following components:

2.2.1 Bridge Rectifier Losses

The Bridge rectifier is composed of four diodes. The diodes in all this analysis are modeledby just a voltage source. Two of these diodes are conducting in each low-frequency halfcycle. The diode losses due to the high frequency ripple are neglected. Thus, the losses inthis diode can be expressed by the average value of the current passing through them andtheir threshold voltage. The total losses in the bridge are expressed as the following:

PBridge = 2VthBridge ⟨|iAC|⟩ (2.1)

To find an expression for the average value of the AC main current, its scheme andbehavior have to be studied first. A buck converter connected to an AC source through abridge behaves like the following; the converter will be in off-mode when the AC voltage

2.2 Losses Analysis Methodology for the IBFC 49

value is lower than the bulk capacitor voltage, and in on-mode when the AC voltage is higherthan the bulk voltage. Therefore, the AC current will be as shown in Fig. 2.2.

0 0.001 0.002 0.003 0.004 0.005 0.006 0.007 0.008 0.009 0.01-1

0

1

2

3

4

5

6

Time (Sec)

Curr

ent

(Am

p)

AC main current

2π - θ

2π + θ

θConduction angle

Fig. 2.2 AC main current in half line-frequency-period range.

The line-frequency-period range of the AC current shown in Fig. 2.2 is not enough to getthe expression of the current. Thus, a zoom is made to show the AC main current along aswitching-frequency-period range, as shown in Fig. 2.3.

4.98 4.985 4.99 4.995 5 5.005 5.01 5.015 5.02 5.025

x 10-3

0

1

2

3

4

5

6

Time (Sec)

Curr

ent

(Am

p)

AC main current

DTs

iBuckp

Ts

Fig. 2.3 AC main current in multiple of switching-frequency-period range.


Toward the average value of the total AC main current, the following procedure is made:

• The peak current value of the buck current per switching period

It is mandatory to start with an expression for the peak value of the buck current. Theexpression has to be in terms of converter parameters and instantaneous input voltage.Using the voltage difference across the buck inductor for a turn-on switching time, theexpression for this value is found as the following;

iBuckp =(Vgsin(ωt)−VB)

LBDTs (2.2)

• The average value of the buck current over one switching period

As shown in Fig. 2.3 the current is a triangular waveform. Thus, using the peak valueof the current shown in (2.2), an expression for the average value of the buck currentover one switching frequency in terms of converter parameters and time is found as thefollowing:

⟨|iAC|⟩per =iBuckPD

2=

(Vgsin(ωt)−VB)

2LBD2Ts (2.3)

• The average value of the buck current over one line period

Using the expression of the average current per switching period shown in (2.3) in theintegration over the period shown in Fig. 2.2, an expression for the average current isfound as the following:

⟨|iAC|⟩=1π

∫ π+θ

2

π−θ

2

⟨|iAC|⟩perd (ωt) =D2

2πLB fs

(2Vgsin

(θ

2

)−VBθ

)(2.4)

The conduction angle can be found by equaling the input voltage and the bulk capacitorvoltage at the instant where the buck starts to conduct. The expression of the conductionangle is obtained as the following:

θ = π −2sin−1(

VB

Vg

)(2.5)


• The power losses in the bridge

Finally, by substituting (2.4) in (2.1), the following expression for the losses in thebridge is found:

PBridge =2VthBridgeD

2

2πLB fs

(2Vgsin

(θ

2

)−VBθ

)(2.6)

2.2.2 Inductor Losses

The inductor losses are split in winding copper losses and magnetic core losses. The copperlosses are a function of the inductor RMS current and its series resistance, while the corelosses are a function of the magnetic core characteristics and the flux density variation.

In order to estimate the copper losses in the inductor, the RMS value of the current isneeded, as the losses in the inductor are calculated with its series resistance. The currentthrough the inductor has the same behavior as the AC current at low frequency shown in Fig.2.2, as it only conducts within the conduction angle. However, at high frequency, the inductorcurrent is different from the AC current, since the inductor conducts for a while through thebuck diode after the switch turn-off.

In the following a prove for the RMS value of any current at line frequency is presented.This methodology will be used later to get the RMS expression of any current in the converter.In the following the general equation of the RMS current:

I2RMS =

1π

∫ π+θ

2

π−θ

2

it2d (ωt) (2.7)

The integration in the previous equation can be split as the addition of the integrals perswitching periods as the following:

I2RMS =

2TL

(∫ Ts1

0i2t1dt +

∫ Ts2

Ts1

i2t2dt . . .∫ Tsn

Tsn−1

i2tndt

)(2.8)

Knowing that each one of the integration over the switching period in (2.8) is equal to thesquare of the RMS over the switching period multiplied by the switching period, (2.8) can bereformed to the following expression:


I2RMS =

2TL

(Tsi2RMSPer1

+Tsi2RMSPer2. . .Tsi2RMSPern

)=

2Ts

TL

(i2RMSPer1

+ i2RMSPer2. . . i2RMSPern

) (2.9)

The previous expression shown in (2.9) is the arithmetic summation of the RMS valuedivided by the number of high-frequency period inside one line period, which is the integrationof this RMS value over the line period. Thus, (2.9) can be reformed to the followingexpression:

I2RMS =

1π

∫ π+θ

2

π−θ

2

iRMSPer2d (ωt) (2.10)

From this expression, the procedure of finding the RMS value is evident, first determiningthe RMS value of the current per switching period in terms of converter parameters and time,then integrate it over the conduction period.

Applying this to the current in the inductor, the RMS value of the current per switchingperiod is required. The current in the buck inductor operating in DCM is expressed as thefollowing:

i2rmsPer= i2P

τ

3(2.11)

In the case of the current in the buck inductor, τ is the turn-on time added to it the time ofthe de-energizing time of the buck inductor all divided by the switching period. Thus, it isexpressed as the following:

τind =tON

Ts=

DTs +D′Ts

Ts=

Vg sin(ωt)VB

D (2.12)

Substituting (2.2) and (2.12) into (2.11) the following expression for the RMS inductorcurrent is found:

i2BuckrmsPer(ωt) =

D3T 2s Vg

3LB2VB

(Vg sinωt −VB)2 sinωt (2.13)


Finally, integrating (2.13) over the conduction period as shown in (2.10) the RMS valueof current in the buck inductor over line period is found and expressed as the following:

I2Buckrms

=Ts

2D3Vg

3πLB2

[−Vgθ −

2V 2g

3VBsin3 θ

2+

(2V 2

g

VB+2VB

)sin

θ

2−Vg sinθ

](2.14)

Having the RMS value of the current in the inductor, the losses are calculated by thefollowing equation:

Pindcopper = I2Buckrms

Rind

=Ts

2D3VgRind

3πLB2

[−Vgθ −

2V 2g

3VBsin3 θ

2+

(2V 2

g

VB+2VB

)sin

θ

2−Vg sinθ

] (2.15)

The magnetic losses in the inductor are found using the following equation, obtainedfrom the 3C85 ferromagnetic material datasheet [154]:

Pindmag = k∆Ba (2.16)

The flux density variation is found from the following equation:

∆B =Nindµole/µr +g

∆i (2.17)

∆ i is approximated to be half of the peak current in the inductor expressed in (2.2). Theissue is that the integration over the line period will be too difficult as the power of the current,is the core losses coefficient (a), and will not be an integer value. Therefore, in this case, theaverage loss value will be found by the arithmetic addition as the following:

Pindmag = k2π fL

θ fs

Z=i2

∑Z=i1

Nindµole/µr +g

∗

(Vg sin

(2π fL

fsZ)−VB

)2LB

DTs

a

(2.18)

The initial and final values of the arithmetic summation are found by the two followingequations respectively:


i1 = int((π −θ) fs

4π fL

)(2.19)

i2 = int((π +θ) fs

4π fL

)(2.20)

Finally, the total buck inductor losses is calculated by the addition of the copper lossesand the magnetizing losses, as shown in ( 2.15 ), and ( 2.18 ) respectively.

2.2.3 Transformer Losses

The current through the transformer primary winding is the input flyback current operating inDCM. Therefore, the expression of its RMS value can be found by ( 2.11 ), but with differentpeak current, and on-time ratio, as shown in ( 2.21 ), and ( 2.22 ) respectively.

I f ly inputP=

VBDTs

Lm(2.21)

τ f lyprim=

tON

Ts= D (2.22)

Substituting both, ( 2.21 ), and ( 2.22 ), into ( 2.11 ), the following expression for theflyback RMS input current is obtained:

I2f ly inputrms

=VB

2D3Ts2

3Lm2

(2.23)

Having the RMS value of the current in the primary side of the transformer, the copperlosses are calculated by the following equation:

Pprim = I2f ly inputrms

Rprim =VB

2D3Ts2Rprim

3Lm2

(2.24)


The current in the secondary side of the transformer is the output flyback current. Con-sequently, the expression of the RMS current in the secondary side of the transformer canbe found by (2.11), but with different peak current, and on-time ratio, shown in (2.25), and(2.26) respectively.

I f ly out putP=

VBDTs

NLm(2.25)

τ f lysec=

tON

Ts=

NVB

VoD (2.26)

Substituting both, (2.25), and (2.26), into (2.11), the following expression for the flybackRMS input current is obtained:

I2f ly out putrms

=VB

3D3Ts2

3NLm2Vo

(2.27)

Having the RMS value of the current in the secondary side of the transformer, the copperlosses are calculated by the following equation:

Psec = I2f ly out putrms

∗Rsec =VB

3D3Ts2Rsec

3NLm2Vo

(2.28)

Concerning the core losses of the flyback transformer, using the same procedure as forthe core loss in the inductor, the core losses of the flyback is calculated as follows:

Ptransmag = k2 fL

fs

fs/2 fL

∑1

(Nprimµole/µr +g

∗ VBDTs

2Lm

)a(2.29)

Knowing that the IBFC does not have the capability of recycling the energy stored inthe leakage inductance of the transformer, this energy should be considered as a loss inthe converter. However, in this application, the transformer is designed to have a very lowleakage inductance, thus its wasted energy can be neglected.


2.2.4 Buck Diode Losses

The current in the diode of the buck converter is the current in the inductor but only duringthe turn-off. Thus, the peak value of the current per switching period will be the same asstated by (2.2), while the off duty cycle D′ is found by the following expression:

D′ =Vg sin(ωt)

VBD (2.30)

Therefore, the average value of current in the buck diode per switching period is foundby the following expression;

⟨iDB⟩per =iBuckP (D

′−D)

2

=VBTs

2LB

(D′−D

)2

=VBTs

2LB

(Vg sin(ωt)

VBD−D

)2

(2.31)

Finally, the expression for the total average current in the buck diode is obtained byintegrating (2.31) over the conduction angle.

⟨iDB⟩=1π

∫ π+θ

2

π−θ

2

⟨iDB⟩per d (ωt)

=D2VB

2πLB fs

(Vg

2

2VB2 sinθ −

4Vg

VBsin

θ

2+

(Vg

2

2VB2 +1

)θ

) (2.32)

Thus, the losses in the buck diode are calculated by the following expression:

PDB =VthDB⟨|iAC|⟩

=D2VBVthDB

2πLB fs

(Vg

2

2VB2 sinθ −

4Vg

VBsin

θ

2+

(Vg

2

2VB2 +1

)θ

) (2.33)


2.2.5 Switch Losses

The losses in the Metal-Oxide Semiconductor Field-Effect Transistor (MOSFET) are dividedinto conduction losses and switching losses. The conduction loss is determined from theRMS value of the current passing through the switch and the on-resistance of the switch.However, as aforementioned in the introduction, as a last feature for the IBFC, the current inthe switch is the highest of buck and flyback currents. Fig. 2.4 shows the equivalent circuitof the IBFC converter in the case when the switch is conducting. In the case that the flybackcurrent IF is higher than IB, the current in the main switch M1 will be IF , while the currentthrough diode DFL will be (IF − IB) and diode DFH will not conduct. The opposite happensin the case where the buck current is higher, in this case, M1 will handle IB while the diodeDFL will not conduct, and the current in diode DFH will be (IB − IF). Summarizing, thecurrent through switch M1 will be either IB or IF , the higher of them, and the diode in parallelwith the higher current will not conduct, while the diode in parallel with the lower currentwill conduct the difference between both currents.

DFL

DFH

M1

iF

i B

Fig. 2.4 Equivalent circuit during the conduction of the switch.

Knowing that the peak value of the buck current is variable over the line period, while theflyback current peak is constant over the line period, as shown in Fig. 2.5. Thus, the currentthrough the switch will start with the flyback current, then after a given instant, the current inthe buck will take place, and back again to flyback current, as shown in Fig. 2.6.


Fig. 2.5 The current of both the buck and the flyback converters.

2π - δ

2π + δ

δ Flyback-to-Buck angle

Fig. 2.6 The current of both the buck and the main switch.


Thus, the value of the angle at which this event occurs, the δ can be determined byequalizing the peak current of both buck peak current and input flyback at instant π−δ

2 , as thefollowing:

(Vg sin

(π−δ

2

)−VB

)LB

DTs =VBDTs

Lm

(2.34)

Thus, the value of flyback-to-buck angle can be deduced as the following:

δ = π −2sin−1(

VB

Vg

(1+

LB

Lm

))(2.35)

Now, in order to get the value of the RMS current through the switch, the followingequation can be applied:

I2switchrms

=1π

[∫ π−δ

2

0I2

f ly inputrmsdωt +

∫ π+δ

2

π−δ

2

i2switchrmsPerdωt+

∫π

π+δ

2

I2f ly inputrms

dωt] (2.36)

In order to get the RMS value of the current in the switch per switching period, (2.11) isused. Knowing that the peak current in the switch is the same as the one of the AC currentfound in (2.2), and taking into account that the on-time ratio, in this case, is D. Thus, theswitch current RMS per switching period is found by the following expression:

i2switchrmsPer=

D3T 2s

3LB2 (Vg sinωt −VB)

2 (2.37)

Solving (2.36), using the values of the flyback input current RMS in (2.23), and theswitch current RMS per period in (2.37), the total RMS value of the current in the switch canbe deduced as the following:

I2switchrms

=VB

2D3Ts2

3πLm2 (π −δ )+

D3T 2s

3πL2B

(V 2

g

2sinδ −4VgVB sin

δ

2+

(V 2

B +V 2

g

2

)δ

)(2.38)


Thus, the switch conduction losses are found by the following equation:

Pcond = I2switchrms

RON =

[VB

2D3Ts2

3πLm2 (π −δ )

+D3T 2

s

3πL2B

(V 2

g

2sinδ −4VgVB sin

δ

2+

(V 2

B +V 2

g

2

)δ

)]RON

(2.39)

Regarding the MOSFET switching losses, the formula used is the one illustrated in [151]and expressed as the following:

PSW =12

iDvD (tOFF + tON) fs +12

COSSV 2DON

fs (2.40)

The previous equation is the general equation of the switching losses in a Mosfet switch;however, as the converter is operating in DCM, the on losses are neglected. Thus, theswitching losses of the IBFC in this application can be expressed as the following:

PSW =12

IDOFFVDOFF tOFF fs +12

COSSV 2DON

fs (2.41)

Concerning the switching losses, they can be divided into two terms; the first termregarding the turn-off losses, and the second term regarding the parasitic capacitance losses.

Starting with the turn-off losses, the current through the switch is not constant during allthe low-frequency period and the voltage across the switch is not constant either. Thus, theturn-off voltage across the switch is expressed as the following:

VDOFF =

VB +

VoutN i f 0 < ωt < π−θ

2 & π+θ

2 < ωt < π

Vg sinωt +VB +VoutN i f π−θ

2 < ωt < π+θ

2

(2.42)

While the switch turn-off current, it changes between flyback current and buck current,as previously illustrated. Thus, the peak value of the switch current at turn-off is expressed asfollows:


IDOFF =

VBDTs

Lmi f 0 < ωt < π−δ

2 & π+δ

2 < ωt < π

DTs(Vg sinωt−VB)LB

i f π−δ

2 < ωt < π+δ

2

(2.43)

Multiplying (2.42) and (2.43), the following expression is found:

IDOFFVDOFF =

VBDTsLm

(VB +

VoutN

)i f 0 < ωt < π−θ

2 & π+θ

2 < ωt < π

VBDTsLm

(Vg sinωt +VB +

VoutN

)i f π−θ

2 < ωt < π−δ

2 & π+δ

2 < ωt < π+θ

2

DTs(Vg sinωt−VB)LB

(Vg sinωt +VB +

VoutN

)i f π−δ

2 < ωt < π+δ

2

(2.44)

Integrating (2.44) over the line period, the following expression for the first term of theswitching losses is found:

PSW 1 =12

IDOFF VDOFF tOFF fs

=D to f f

2π

[VB

Lm

(VB +

Vout

N

)(π −δ )+

VBVg

Lm

(sin

δ

2− sin

θ

2

)

+1

LB

(V 2

g

2sinδ +

2VoutVg

Nsin

δ

2−δ

(V 2

B +VoutVB

N−

V 2g

2

))] (2.45)

Concerning the value of the voltage used in the second term of the switching losses, itis the voltage across the switch at the turn-on instant. It must be noted that the flyback inDCM presents a resonant behavior that makes the turn-on voltage dependent on the instant atwhich the turn-on process takes place. Fig. 2.7 shows the voltage across the switch from theexperimental results.


0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1x 10

−4

0

20

40

60

80

100

120

140

160

180

200

Time (Sec)

Vol

tage

(V

olts

)

Voltage across the switch

Fig. 2.7 Voltage across the switch obtained by experimental measurement.

As shown in Fig. 2.7, a good approximation in this specific application could be to usethe voltage just before the resonance. Thus, the turn-on voltage can be expressed as thefollowing:

VDON =

VB i f 0 < ωt < π−θ

2 & π+θ

2 < ωt < π

Vg sinωt + VoutN i f π−θ

2 < ωt < π+θ

2

(2.46)

Therefore, multiplying this term by half of the parasitic capacitance COSS and the switch-ing frequency, then integrating the result over the line period, an expression for the secondterm of the switching losses is found, and it is expressed as follows:


Psw2 =12

COSS V 2DON

fs

=COSS fs

2π

[(VB +

Vo

N

)2

(π −θ)+V 2

g

2sinθ +

4VoVg

2sin

θ

2+

(V 2

g

2+

V 2o

N2

)θ

] (2.47)

Thus, by the addition of (2.39), (2.45), and (2.47) an estimation for the amount of theswitching loss can be found:

Pswitch = Pcond +Psw1 +Psw2 (2.48)

2.2.6 Integrated Diodes Losses

As previously explained, diode DFH only conducts when the flyback current is higher thanthe buck current, while DFL conducts in the reverse case, as illustrated in Fig. 2.8.

H

L

Fig. 2.8 The current in the two flyback diodes DFL and DFH .

The current in diode DFL is expressed as the following:


iDFL (ωt) =

i f (ωt) i f 0 < ωt < π−θ

2 & π+θ

2 < ωt < π

iF (ωt)− iAC (ωt) i f π−θ

2 < ωt < π−δ

2 & π+δ

2 < ωt < π+θ

2

(2.49)

The average current through diode DFL is calculated as follows:

⟨iDFL⟩=1π

[⟨i f⟩(π −θ)+2

∫ π−δ

2

π−θ

2

⟨i f − iAC

⟩perωt

](2.50)

The average current of the flyback can be obtained using the input flyback current peakvalue shown in (2.21) as the following:

⟨i f⟩=

I f ly inputPD

2(2.51)

Furthermore,⟨i f − iAC

⟩per is obtained from the integration of the flyback current minus

the AC current, as shown in the following expression:

⟨i f − iAC

⟩per =

1Ts

∫ DTs

0i f − iAC dt

=D2Ts

2

(VB

Lm−

Vg sin(ωt)−VB

LB

) (2.52)

Using (2.51) and (2.52) into (2.50), the DFL average current is calculated as follows:

⟨iDFL⟩=D2Ts

π

(VB (π −δ )

2Lm+

VB (θ −δ )

2LB+

Vg

LB

(sin

δ

2− sin

θ

2

))(2.53)

Thus, by multiplying (2.53) with the threshold voltage of the diode, an estimation of theamount of the switching loss is found:

PDFL =D2TsVthDFL

π

(VB (π −δ )

2Lm+

VB (θ −δ )

2LB+

Vg

LB

(sin

δ

2− sin

θ

2

))(2.54)


Concerning the current in diode DFH , it can be expressed as shown in the followingequation:

iDFH (ωt) =

iAC (ωt)− i f (ωt) π−δ

2 < ωt < π+δ

2

(2.55)

Applying the same procedure made for DFL, the average value of the current throughdiode DFH can be found as shown in the following equation:

⟨iDFH ⟩=1π

∫ π+δ

2

π−δ

2

⟨iAC − i f

⟩per dωt

=D2Ts

2π

(2Vg

LBsin

δ

2−δVB

(1

LB+

1Lm

)) (2.56)

Thus, by multiplying (2.56) with the threshold voltage of the diode, an estimation of theamount of its losses is found:

PDFH =D2TsVthDFH

2π

(2Vg

LBsin

δ

2−δVB

(1

LB+

1Lm

))(2.57)

2.2.7 Flyback Diode Losses

The current through the flyback diode is the output current of the flyback transformer. Thus,its average value can be calculated using the flyback output current peak shown in (2.25)and the off-duty shown in (2.26). The following expression shows the flyback diode currentaverage value:

⟨iDF ⟩=I f ly out putP

τ f lysec

2=

V 2B D2Ts

2LmVout(2.58)

Thus, by multiplying (2.58) by the threshold voltage of the diode, an estimation of theamount of its losses can be found:

PDF =V 2

B D2TsVthDF

2LmVout(2.59)


2.2.8 EMI filter Losses

In order to comply with EMC standards, an EMI filter is needed to filter the electromagneticnoise. Moreover, it reduces the high-frequency content on the current drained from theelectric grid. A passive Differential Mode (DM) EMI filter is used for this purpose, as shownin Fig. 2.1.

As the EMI filter is considered to be a part of the whole converter, thus, the losses ofthe EMI filter have to be studied. It is mainly split into the losses in the coupled windingsand the parallel capacitors. Knowing that the used capacitors are film capacitors with a verylow parasitic resistance, the losses in the parallel capacitors can be neglected. Regarding thecoupled windings, the losses are conduction losses, and magnetizing core losses, however,the magnetizing core losses can be neglected due to the fact that the magnetic flux producedby each winding is equal but in reverse direction, which means that the total flux in the coreis nearly zero.

Regarding the copper losses, it is calculated as the following:

PEMIcopper = 2I2ACrms

REMI (2.60)

Knowing that the current in the EMI filter is the same as the switch current at a differentrange. Thus, the AC current RMS is calculated as the following:

I2ACrms

=1π

∫ π+θ

2

π−θ

2

i2switchrmsPerdωt (2.61)

Using the switch current RMS per switching period shown in (2.37), the equation of theEMI current RMS is found to be as the following:

I2ACrms

=D3T 2

s

3πL2B

(V 2

g

2sinθ −4VgVB sin

θ

2+

(V 2

B +V 2

g

2

)θ

)(2.62)

Thus, by substituting with (2.62) in (2.60) an estimation for the losses is found as thefollowing:

PEMI =2D3T 2

s REMI

3πL2B

(V 2

g

2sinθ −4VgVB sin

θ

2+

(V 2

B +V 2

g

2

)θ

)(2.63)

2.3 Simulation Verification 67

2.3 Simulation Verification

In order to verify the previously illustrated expressions, an ideal simulation for the IBFC usingPSIM software has been carried out. The verification will be made on two different converterssupplying two different luminary loads, to test the equations at different parameters andoperation. On the other hand, all equations got from the previously illustrated analysis willbe used in Matlab to calculate the values of the current in each component in the converterand match them with the values got from the simulation results.

The first driver is intended to supply a luminary load composed of a series of 60 GoldenDragon LEDs from Osram. The input voltage is 220 Vrms and 50 Hz. The rated current ofthe LED is 350 mA, rated voltage is 200.6 V, making an output power of 72 W.

The second driver is designed to supply a luminary load of rated current 0.7 A, ratedvoltage of 38 V, making an output power of 26.5 W. The second converter is designed at aninput voltage of 110 Vrms and 60 Hz.

Table 2.1 illustrates the components parameter, of the two drivers, used in both simulationsand mathematical equations. As shown in Table 2.1, the two drivers show a diversity betweenthem. The driver I shows high input voltage, high switching frequency, high output voltage,and smaller inductances, however, driver II shows more or less the reverse, low input voltage,low switching frequency, low output voltage, and larger inductances.

Table 2.1 Specification and Components of the Two Drivers

Components Driver I Driver II

Input voltage RMS 220 V 110 VInput Frequency 50 Hz 60 HzOutput voltage 200.6 V 38 VOutput current 0.35 mA 0.7 mAOutput power 70.21 W 26.6 W

Operating frequency 100 kHz 40 kHzBuck inductance LB 42 µH 100 µH

Flyback transformer Lm 105 µH 500 µHBulk capacitor CB 470µF/250V 47µF/160V

Output capacitor CO 1µF/250V 470µF/50V

Table 2.2 shows a comparison of the simulation results with the theoretical results for thetwo drivers illustrated in Table 2.1.


Table 2.2 Comparison Between Theoretical Results and Simulation Results of the TwoDrivers

Driver I Driver II

Parameter Theoretical Simulation Theoretical Simulation

Average AC main currentEquation (2.4)

0.2459 A 0.2458 A 0.1823 A 0.1822 A

Buck inductor RMS currentEquation (2.14)

1.1218 A 1.1236 A 0.6534 A 0.6528 A

Input flyback RMS currentEquation (2.23)

0.9589 A 0.9581 A 0.4893 A 0.4878 A

Output flyback RMS currentEquation (2.27)

0.5842 A 0.5841 A 1.6838 A 1.6843 A

Average buck diode currentEquation (2.32)

0.1312 A 0.1307 A 0.0638 A 0.0624 A

Switch current RMSEquation (2.38)

1.1535 A 1.1459 A 0.7782 A 0.7767 A

Average DFH currentEquation (2.53)

0.0624 A 0.0623 A 0.1366 0.1362

Average DFL currentEquation (2.56)

0.1936 A 0.1939 A 0.0728 A 0.0715 A

Average DF currentEquation (2.58)

0.35 A 0.3494 A 0.7 A 0.6999 A

AC main current RMSEquation (2.62)

0.3181 A 0.3177 A 0.2409 A 0.2406 A

As shown in Table 2.2 the equations give accurate results as the simulations. However,there is a negligible error in the fourth decimal digit. The reason is the time step in thesimulation, as a smaller time step gives closer results to equations. Thus, the equations aremore accurate and much faster than the simulation. To prove that the equations are moreaccurate, as shown in Table 2.2, the current of DF is exactly the LED current in the equationresults. However, the simulation is giving an approximated result but not exact.

2.4 Practical Case Study for Efficiency Improvement 69

2.4 Practical Case Study for Efficiency Improvement

In this section, a step-by-step procedure is presented to show how the efficiency improvementof the converter is performed. The study will be made on driver II, its specification, aswell as the component parameters, are presented in Table 2.1. In addition to the efficiencyimprovement, the driver is intended to operate in universal input voltage. The driver waspreviously operating at input voltage 110 V, for this reason, a 650V switch is selected.From simulation and by substituting in (2.42) the maximum voltage across the switch inthe old design varies between 374V to 757 V corresponding to input voltage 90V to 250V,respectively. Thus, an 800V switch is required for universal input voltage operation. Thus, inthe study, a reduction of the voltage across the switch will be made in order to reduce theswitch requirements.

Fig. 2.9 shows the input voltage and current and the LED current. The figure shows thatthe driver is working perfectly. The driver shows an efficiency of 82 %, a power factor equals0.9, and a THD of 21%.

Fig. 2.9 Input voltage (red), input current (yellow), and output voltage (green) for the oldIFBC design.


The improvement process starts by checking all the parameters’ effect on efficiency.A program is built using all the equations previously presented, in order to estimate theefficiency of the converter at different parameters values. The first parameter to check is theturns ratio. Thus, the efficiency is calculated for different values of the turns ratio startingfrom N equals 0.25 to 5. Fig. 2.10, shows the efficiency with respect to the turn ratio. Thestudy shows that as the turn ratio is increasing, the efficiency is also increasing; however,after a given value, the improvement is not effective anymore. The previously chosen turnratio was 0.4; however, for the new design the turn ratio is chosen to be 2.

0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

81

82

83

84

85

86

87

88

X: 0.4Y: 83.8

Turn Ratio N

Eff

icie

ncy

X: 2Y: 86.68

Efficiency

Fig. 2.10 Efficiency of the IBFC converter with respect to turn ratio.

Then, after choosing the new turns ratio, the values of the buck inductance as well as thetransformer magnetizing inductance have to be selected. The variation of any inductancevalue will affect efficiency, bulk capacitor voltage, THD, and PF. The efficiency and the bulkcapacitor voltage with respect to the variation of both inductances are shown in the 3D plotsof Fig. 2.11 (a) and Fig. 2.11 (b), respectively. The criteria for selecting the optimal values isto find the driver design that shows high efficiency and low bulk capacitor voltage. In return,the decrease of the bulk capacitor voltage will enhance both THD and PF.

2.4 Practical Case Study for Efficiency Improvement 71

2550

75100

125150

175200

225

2025

3035

4045

5055

6083

84

85

86

87

88

89

90

Buck inductance (µH)Magnetizing inductance (µH)

X: 105Y: 56Z: 89.27

Eff

icie

ncy

(%

)

(a)

2550

75100

125150

175200

2252025

3035

4045

5055

6020

30

40

50

60

70

80

90

100

Buck inductance (µH)

X: 105Y: 56Z: 58.59

Magnetizing inductance (µH)

Bul

k ca

paci

tor

volt

age

(Vol

t)

(b)

Fig. 2.11 (a) Efficiency of the converter and (b) Bulk capacitor voltage, with respect to Buckand Magnetizing inductances.


As aforementioned, the new design takes into consideration the bulk capacitor voltage,as the magnetic components value will be chosen in order to decrease the bulk capacitorvoltage as much as possible. In return, the PF will increase and the THD will decrease.Moreover, the rating of both the bulk capacitor and the switch will decrease. Furthermore, asthe voltage of the bulk capacitor decreases the conduction angle will increase and in returnthe power delivered from the input will be more continuous and in return, the ripple willdecrease. Thus, the output ripple will decrease, with even lower bulk capacitor price andsize. Fig. 2.11 shows that a good operating point could employ a buck inductance of 105 µHand a magnetizing inductance of 56 µH. The operation point previously selected shows atheoretical efficiency of 89.27 % and a bulk capacitor voltage of 58.59 V. Fig. 2.12 shows thebulk capacitor voltage in the old design compared to the new design. As shown in the figure,the bulk capacitor voltage in the new design is lower than the one of the old design. Moreover,the ripple percentage decreased when compared to the old design ripple percentage.

0 0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04 0.045 0.0550

60

70

80

90

100

110

120

130

Time (sec)

Vol

tage

(V

olts

)

Bulk voltage new designBulk voltage old design

Fig. 2.12 Bulk capacitor voltage of the old design (red), and of the new design (blue).

Moreover, from the analysis, it is found that DFH is conducting only if the buck currentis greater than the flyback current. Therefore, the new design will take into consideration

2.5 Experimental Results 73

to make the peak buck current remain below the flyback peak current; thus, DFH will notconduct and can be removed.

2.5 Experimental Results

Using the parameters found by the efficiency improvement procedure, a prototype has beenbuilt. Table 2.3 shows the parameters and components list of the new design. The newconverter shows an efficiency of 89 %, a power factor of 0.96, and a THD of 16 %.

Table 2.3 Specification and Components of the New Driver Design

Components Value

Input voltage RMS 90-250 VOutput voltage 38 VRated current 0.7 A

EMI filter capacitance 68 nFEMI filter inductance 2.56 mH

Buck inductance ER2510/PC44, LB = 110 µH,20 Turns

Flyback transformerPQ2625/3C90,

Lm = 56 µH,Np = 16 T,Ns = 32 TurnsBridge diodes DB156S

DB&DFL&DFH MURS260T3GDOUT STPS3150

CB 330 µF/63VCO 470 µF/50V

Switch M1 SPA07N60C3

Fig. 2.13 shows the input current and voltage, as well as the output voltage. Moreover, asshown in Fig. 2.13, the output voltage ripple is 515 mV, while in the old design shown inFig. 2.9, the output voltage ripple is 974 mV. Therefore, the output voltage ripple is half theripple obtained in the old design as previously proven by simulation. This leads, as shown inFig. 2.14, to an output current ripple of 5 %, which is necessary because it was an objectivefor this application to operate with an output current low-frequency ripple below 6 %. Thisexplains why a large capacitance has been used. However, for normal operation fulfilling theIEEE Std. 1789-2015, an output capacitance of 100 µF instead of the 470 µF would havebeen enough.


Fig. 2.13 New design: Input voltage (red), input current (yellow) and output voltage (green).

Fig. 2.14 Output current of the IBFC new design.


Furthermore, Fig. 2.15 shows the harmonic content of the input current, compared to thelimits specified by IEC 61000-3-2 Class C regulation. As can be seen, the proposed design isin accordance with IEC 61000-3-2 Class C regulation.

3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 390

5

10

15

20

25

30

Harmonic Order

Har

mon

ic D

isto

rtio

n (%

)

IEC 61000−3−2 Class CIBFC New Design

Fig. 2.15 Harmonic content of the input current versus IEC 61000-3-2 Class C.

Fig. 2.16 shows the measured and calculated efficiency of the new design and the olddesign with respect to the input voltage. Also, it shows the efficiency results presentedin [77] at output power equal 25 W. As can be seen, the efficiency decreases as the inputvoltage increases, which is due to the increase of the voltage across the switch and in return itincreases of the switching losses. However, the design guarantees a higher efficiency withinthe whole universal input voltage range.

Finally, Fig. 2.17 shows the photograph of the final LED driver, which is the same as theold driver just using a smaller bulk capacitor in the new driver. Fig. 2.18 shows the finalschematic of the new design, including the control circuit. As shown, diode DFH is not usedin the final design.


80 100 120 140 160 180 200 220 240 26071

73

75

77

79

81

83

85

87

89

91

Input Voltage (rms)

Eff

icie

ncy

(%)

New design equationsNew design practicalOld design equationsOld design practicalDesign of reference [77] at 25 W

Fig. 2.16 New design efficiency (blue) sold line calculated and dashed measured, old designefficiency (red) sold line calculated and dashed measured, reference design efficiency (black).

EMI filter Buck inductor Flyback transformer

Bulk capacitor Output capacitor

Fig. 2.17 New driver photography.


1

Vg

AUX

VOCO

DO

DB

D

M

LfCB

LB

VgFL

VB

RC S Gate

RT7306RT7306

HV

RHV

0.1 µF

0805

1 µF

0805

10 kΩ / 1206

HV

RG

15 / 0805VCC

RPC

2.7 kΩ / 0805

Gate

CS

CS

VCC

RAUX

10 / 1206

AUX

68 pF

0805

22 µF

35 V

RZCD1

68 kΩ / 0805

RZCD2

6.8 kΩ / 0805

SPA07N60C3

DB156S

MURS260T3G

MURS260T3G

STPS3150

470 µF/ 50 V

330 µF/ 63 V

LEMI

CEMI

105 µH

56 µH

Fig. 2.18 Schematic diagram of the laboratory prototype of the new IBFC design.

Table 2.4 shows a comparison of equations results of the losses in all elements previouslypresented, as well as the bulk capacitor voltage, for both old and new designs. The comparisonshows that most of the losses are in the switch and mostly in the switching losses. Thus,decreasing the voltage across the switch will decrease the switching losses. This explains whyincreasing the turns ratio will increase efficiency, as it will decrease the voltage across theswitch. Furthermore, increasing the ratio of the buck inductance over the flyback magnetizinginductance will decrease the bulk capacitor voltage, and in return will decrease the voltageacross the switch even more. Thus, the switching losses will be decreased. However, thedecrease of the bulk capacitor voltage will increase the value of the current, which willincrease the conduction losses. This illustrates the benefit of the analysis as it shows theeffect of the change of each parameter on the losses of each component and the total losses.


Table 2.4 Theoretical Computation Comparison Between Old and New Driver Designs

PARAMETERS OLD DESIGN NEW DESIGN

Bridge loss 0.4011 W 0.5069 WEMI filter loss 0.03 W 0.035 WInductor loss 0.1073 W 0.1792 W

Transformer loss 1.1019 W 0.2018 WDB loss 0.0925 W 0.2768 W

Switch loss 3.28 W 1.2322 WDFL loss 0.1981 W 0.2768 WDFH loss 0.1056 W NOT USED

DOUT loss 0.4741 W 0.4741 WTotal losses 5.7577 W 3.1827 W

Bulk capacitor voltage 108.06 V 58.59 V

Finally, a comparison for the losses in each component between the results obtained fromthe losses analysis and the practical results is created. Fig. 2.19 shows this comparison.As shown in the figure, the losses analysis is very accurate. However, it seems that thepractical results losses are slightly higher than the estimated ones. It is due to the fact that thecalculation of the current is made in ideal state assumption, however, the practical resultswill give a higher value of the current and in return will create a higher value for the losses.

Bridge EMI Ind Trans D_B Switch D_FH D_FL D_out0

0.15

0.3

0.45

0.6

0.75

0.9

1.05

1.2

1.35

1.5

15.92%

1.09%

5.63% 6.34%8.69%

38.71%

8.69%

14.89%

Pow

er L

osse

s (W

att)

EquationsPractical Results

Fig. 2.19 A comparison between experimental and theoretical results of the losses in eachcomponent in the converter.

2.6 Conclusion 79

2.6 Conclusion

This study proposes a deep analysis of the losses in the IBFC. The equations illustrated inthis chapter show great accuracy. Moreover, the results of the equations are more accuratethan the simulation results, due to the limitation in the simulation sampling time. The useof the equations facilitates the study of the effect of the reactive elements on the converterefficiency.

The study leads to the ability of making enhancement in the efficiency out of the conven-tional design process. The conventional way is usually done by trying to find more efficientswitching devices to substitute the ones in the converter. This way is effective and improvesthe efficiency, however it is costly, and with a limited range of enhancement.

The study presents a practical case study for the efficiency enhancement process of anexisting driver. The driver is operating under universal input conditions, and 38 V output,supplying an LED luminary of 26.5 W. The old design shows an efficiency of 82 %, powerfactor equal to 0.9, and THD of 21 %. The study leads to a change in a few parametervalues: the turn ratio from 0.4 to 2, the magnetizing inductance from 500 µH to 56 µH, thebuck inductance from 100 µH to 110 µH, and the bulk capacitor from a bulky 47 µF/160Vto a smaller size and more effective one of 330 µF/63V . The new design shows a greatenhancement in all aspects; an efficiency of 89 %, power factor equals 0.96, and THD of 16%. Moreover, the output ripple shown by the new design is half of the one shown by the olddriver. Furthermore, a reduction of the number of components is achieved by removing onediode that will not be conducting.

Finally, the losses analysis and efficiency improvement procedure presented in this chaptercan be used to optimize other integrated converters.

Chapter 3

High PF LED Driver Based onInterleaved Integrated Buck FlybackConverter


3.2 Derivation of the Interleaved Integrated Buck Flyback Converter . . 82

3.2.1 Conventional Integrated Buck Flyback Converter . . . . . . . . . 82

3.2.2 Proposed Interleaved Integrated Buck Flyback Converter . . . . . 83

3.3 Operation Principles of the proposed Interleaved Integrated BuckFlyback Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

3.4 Mathematical Analysis and Average Model . . . . . . . . . . . . . . . 91

3.4.1 Mathematical Analysis . . . . . . . . . . . . . . . . . . . . . . . 91

3.4.2 Average Model . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

3.5 Design Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

3.5.1 Power Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

3.5.2 Control Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97


3.7 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

82 High PF LED Driver Based on Interleaved Integrated Buck Flyback Converter

3.1 Introduction

Following the research made on the IBFC to enhance the efficiency and decrease the losses,this chapter will present an improvement of the conventional IBFC to achieve a unity PF.The proposed converter is the Interleaved Integrated Buck Flyback Converter (IIBFC), whichensures good performance and unity PF within all the operation range. The IIBFC is madeby adding a capacitor between the diode bridge and the conventional IBFC converter.

This chapter presents a deep analysis and a further study of the IIBFC. The IIBFC is asingle switch driver, which ensures an operation fulfilling the standards at any dimming ratio.The driver operates with a nearly unity PF and a significant low THD at any dimming ratio.The analysis proves that one diode of the conventional IBFC will not conduct and can beremoved. Thus, the number of components is reduced. Moreover, the driver features isolationbetween input and output. The control is simple as it is made using one single IntegratedCircuit (IC). There is no extra sensor needed so that a simple built-in voltage sensor is enoughto regulate the output current from the primary side. Moreover, the driver features a lowerripple compared to the IBFC, which means that a lower capacitance is needed. In return, thedriver has a more compact size and lower cost. The main drawback is the low efficiencyshown by the driver. However, this is due to the fact that this is a low power application,the output power being only 25 W. Moreover, it is a low voltage, high current application,which decreases as well the efficiency. Furthermore, this is a stand-alone power supply. Thus,the efficiency is measured taking into account the control, switch driver, and sensor losses.However, according to the loss analysis on the IBFC, the efficiency could be increased byredesigning the converter, and without any additional modification of the control circuit.The efficiency can be increased without adding any extra component, only by redesigningthe values of the magnetic component and the turns ratio. The study can be adopted to theIIBFC, and an improvement could be made so that its efficiency can become comparable tothe state-of-the-art driver efficiency.

3.2 Derivation of the Interleaved Integrated Buck FlybackConverter

3.2.1 Conventional Integrated Buck Flyback Converter

The operation of the IBFC is equivalent to the operation of a buck and flyback convertersworking in cascade mode. The flyback converter function is to deliver the power to the output,while the buck converter duty is to improve the input PF. The improvement of PF and THD

3.2 Derivation of the Interleaved Integrated Buck Flyback Converter 83

is made by reducing the bulk capacitor voltage (VB) as much as possible. Fig. 3.1 illustrateshow the voltage level of the bulk capacitor will affect to the PF and THD, taking into accountthat the buck converter will only conduct when the input voltage is higher than the outputvoltage. Thus, a conduction angle for the AC main current appears, as illustrated in thebottom plot of Fig. 3.1. Therefore, decreasing the bulk voltage will increase the conductionangle, and in return, the PF and THD will improve.

Ideally speaking, the more the bulk capacitor voltage is decreased, the more the PF andTHD will improve. However, this is limited by two factors. First, if the voltage of the bulkcapacitor is decreased, the voltage ratio between bulk capacitor voltage and line voltage willdecrease, and in return, the ripple of the bulk capacitor voltage will increase. Moreover,the increasing of the bulk capacitor voltage is done by increasing the buck inductance orby decreasing the magnetizing inductance of the flyback, and both options will be limitedoperating in the CCM of operation.

In this type of converters, usually, researchers investigate the possibility to find a trade-offbetween fulfilling standards and limiting the size and the cost of the converter.

0 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.0180

50

100

150

200

Voltage (

Volts)

0 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.0180

0.1

0.2

0.3

0.4

0.5

Time (Sec)

Curr

ent (A

mps)

|IAC

|

|VGsint|

VB

θConduction angle

T/2 T

Fig. 3.1 Top: bridge voltage and bulk capacitor voltage. Bottom: current after the bridge.

3.2.2 Proposed Interleaved Integrated Buck Flyback Converter

The IIBFC shown in Fig. 3.2, solves all issues found in the conventional IBFC. The idea issimply to add a third winding to the flyback transformer, with the same polarity. This thirdwinding goes to an interleaved capacitor that connects the AC bridge to the buck converter.There is a diode ensuring the direction of the current going to the interleaved capacitor


and not in the reverse direction. The idea of the interleaved capacitor has previously beenproposed in [155], aiming at a higher PF of a buck converter. When the interleaved capacitortechnique is applied to the IBFC, it shows superior advantages, as it ensures a unity PF at anydimming ratio. As previously mentioned, and as shown in Fig. 3.1, the buck converter onlyconducts when the input voltage is higher than the bulk capacitor voltage. The presence ofan interleaved capacitor modifies the operation of the buck converter. In this case, the buckconverter will conduct when the input voltage is higher than the bulk capacitor voltage minusthe interleaved capacitor voltage (Vint), as the following:

vLB = vACBridge − (VB −Vint) (3.1)

As long as the turns ratio of the primary winding and the interleaved winding equals1:1, the interleaved voltage will be equal to the bulk capacitor voltage. Therefore, the buckconverter will conduct continuously, with a conduction angle of 180.

VOCO

DO

DBD2D1

D3 D4 D

D

M1

LmCB

LB

vg

C int

FL

FH

Dint

VB

Vint

vACBridge

Np Ns

Ni

Fig. 3.2 Interleaved Integrated Buck-Flyback Converter schematic.

3.3 Operation Principles of the proposed Interleaved Inte-grated Buck Flyback Converter

Since the proposed converter is a single switch converter, there are only two states, on stateand off state. However, the DCM operation of the buck and flyback splits the off state into

3.3 Operation Principles of the proposed Interleaved Integrated Buck Flyback Converter 85

three intervals. Thus, the converter will have four intervals in total, one for the on state andthree for the off state. Fig. 3.3, and Fig. 3.4 illustrate the main current waveforms within ahigh-frequency switching period, and the equivalent circuits, respectively.

As aforementioned, each switching period can be split into four intervals, which can beexplained as follows:

1. Interval I

The first interval occurs when switch M1 is switched on, as shown in Fig. 3.4 (a).There are two current loops. The buck converter loop represented by the currentcoming from the AC main and going into the buck converter. The role of this loop is tocharge the buck capacitor and meanwhile energize the buck inductance. The flybackloop is represented by the current coming from the buck capacitor and going into thetransformer to energize the magnetizing inductance and also to deliver energy to theinterleave winding. As the interleaved coil is in the same polarity of the main coil, thus,a current is also flowing in the interleaved circuit.

2. Interval II

In the second interval, switch M1 is switched off, as shown in Fig. 3.4 (b). Thus, theenergy stored in the magnetizing inductance of the flyback transformer is deliveredto the output to supply the LED and to charge the output capacitor. Thus, the energystored in the buck inductance is going to the buck capacitor, through the buck diode.

3. Interval III

The third interval, shown in Fig. 3.4 (c), is the same as the second interval, but theenergy stored in the magnetizing inductance is finished. Thus, there is only currentthrough the buck inductor going to the buck capacitor.

4. Interval IV

The fourth interval, as shown in Fig. 3.4 (d), is when there is no current in the entireconverter. However, the current going to the LED is continuous in all intervals owingto the presence of the output capacitor.


t

t

t

t

iM

iF

i O

iB

Ⅰ Ⅱ Ⅲ Ⅳ

DTs Tst1 t2

DTsVg

LB

DTsVB

N Lm

DTsVg

LB

DTsVB

LmDTs

Vg

LB

+

i I

1

Fig. 3.3 Main current waveforms of the IIBFC operating in DCM, within a high frequencyswitching period around the peak line voltage.

3.3O

perationPrinciples

oftheproposed

InterleavedIntegrated

Buck

FlybackC

onverter87

VO

DO

DBD2

D1

D3 D4 D

D

M1

VB

LB

vg

Vint

FL

FH

Dint

iB iOVO

DO

DBD2

D1

D3 D4 D

D

M1

VB

LB

vg

FL

FH

Dint

Vint

iB iF

iI

(a) Interval Ⅰ : 0 < t < DTs (b) Interval Ⅱ : DTs < t < t1

VO

DO

DBD2

D1

D3 D4 D

D

M1

VB

LB

vg

Vint

FL

FH

Dint

iB

(c) Interval Ⅲ : t1 < t < t2

VO

DO

DBD2D1

D3 D4 D

D

M1

VB

LB

vg

Vint

FL

FH

Dint

(d) Interval Ⅳ : t2 < t < Ts

Fig. 3.4 Equivalent circuits of the IIBFC operating in DCM.


Concerning the first interval, it is important to explain which of the two flyback diodes,DFH and DFL, will be conducting. Fig. 3.5 shows a simple magnetic model of the transformerduring turn on, which will be used in the analysis. Concerning the diodes, as shown in Fig.3.6, the conduction will be determined according to the value of the flyback current andthe buck current. As shown in Fig. 3.6 (a), if the flyback current iF is higher than the buckcurrent iB, then DFL will conduct the difference between the two currents, while DFH willnot conduct. Fig. 3.6 (b) shows the case where iB is higher than i f . In this case, the reversewill occur, DFH will conduct the difference between the two currents, while DFL will notconduct.

VB

Dint

iF

i intVint

Lm I Lm ip

Buck

Converter

AC

Bridge

iB

Fig. 3.5 A simple magnetic model of the flyback transformer and its currents during theturn-on interval.

DB

D

D

M1

VB

LBVint

FL

FH

CintiB

iF iB-

iF

DB

D

D

M1

VB

LBVint

FL

FH

Cint iBi F

iB

iB iF-

(a) (b)

Fig. 3.6 Operation of the flyback diodes. (a) if iF > iB, (b) if iF < iB.

3.3 Operation Principles of the proposed Interleaved Integrated Buck Flyback Converter 89

Another advantage shown by the IIBFC is the ripple reduction. Fig. 3.7 shows thesimulation results of a comparison between the output voltage and current ripples of theconventional IBFC and the proposed technique. For better comparison, the values of thecapacitors used in both converters are the same. As can be seen, the ripple is highly reducedin the proposed IIBFC. The voltage ripple is 5 % in the case of the IBFC, and 1 % in the caseof the IIBFC. The current ripple is 25 % in the case of the IBFC, and 5 % in the case of theIIBFC.

0 0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04 0.045 0.0535.5

36

36.5

37

37.5

38

Vol

tage

(V

olts

)

0 0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04 0.045 0.05

0.65

0.7

0.75

0.8

Time (Sec)

Cur

rent

(A

mps

)

Output Voltage of Conventional IBFCOutput Voltage of Interleaved IBFC

Output Current of Conventional IBFCOutput Current of Interleaved IBFC

Fig. 3.7 Output voltage (top) and currents (bottom) of the IBFC (in blue) and the InterleavedIBFC (in red).

Fig. 3.8 shows the simulation results of the output current ripple for the IIBFC usingdifferent output capacitances, to choose the best capacitor that meets the requirements ofa given application. Additionally, Table 3.1 shows the simulation results of the ripplepercentage of the output current and voltage for different capacitances. As an LED driver, thecurrent ripple is more significant due to the low LED series resistance. However, this tablegives an idea of the voltage ripple in case that the application was voltage-ripple oriented andwill operate with a purely resistive load. For this application, an output current ripple of 6 %


is required. Thus, a big output capacitor of 100 µF is required to keep the ripple below thisvalue. Moreover, the driver is designed to supply an LED load, which is characterized bya small dynamic resistance. In other words, a small output voltage variation will lead to ahuge variation in the LED current, and in return a huge luminous variation that will hinderthe human vision. However, to achieve this value of ripple using the conventional IBFC, thecapacitance value should be at least 820µF , which means eight times larger capacitance.The reason for the reduction of the low-frequency ripple is the continuous conduction of theIIBFC. In other words, the small conduction angle of the conventional IBFC creates a periodwhere the buck converter is not conducting, while the power delivered to the output mustbe continuous. This phenomenon increases the gap between the input power and the outputpower, which in return increases the ripple. This is not the case of the proposed IIBFC, as theconverter is intended to have a conduction angle of 180.

0.57

0.61

0.65

0.69

0.73

0.77

Cur

rent

(A

mps

)

LED Current using CO

10 µF


30 µF

0 0.01 0.02 0.03 0.040.57

0.61

0.65

0.69

0.73

0.77

Cur

rent

(A

mps

)

Time (Sec)


56 µF

0 0.01 0.02 0.03 0.04Time (Sec)


100 µF

Fig. 3.8 LED current of the IIBFC with different output capacitances.

3.4 Mathematical Analysis and Average Model 91

Table 3.1 Simulation Results of the IIBFC Output Current and Voltage Ripples With DifferentOutput Capacitances

Capacitor COOutput current ripple

percentageOutput voltage ripple

percentage

10 µF 14.2 % 6.5 %

30 µF 9.5 % 4.3 %

56 µF 7.8 % 3.5 %

100 µF 5.9 % 2.7 %

3.4 Mathematical Analysis and Average Model

3.4.1 Mathematical Analysis

In the following, the analysis of the currents in the converter is presented. The analysis showsthe important design characteristics when both stages, buck and flyback, operate in DCM.For the sake of simplicity, the analysis will consider an ideal converter. An ideal sinusoidalline voltage waveform will also be considered, expressed as vg (t) =Vg sin(2π flt).

In order to determine the operation of the two flyback diodes, DFL and DFH , the peakvalue of both buck and flyback currents have to be determined. Taking into account (3.1), andthat Vint is selected to be equal VB, the peak value of the buck current is expressed as follows:

iB peak =D

fsLBvACBridge

=DVg

fsLB|sin(2π flt)|

(3.2)

Concerning the flyback current, as in the proposed topology contains two secondarywindings, it consists of two terms as shown in Fig. 3.5. The first term is the current stored inthe magnetizing inductance, which will be delivered to the output later during switching off,whose peak value is expressed as the following:

ILmpeak=

VBDfsLm

(3.3)

The second term of the flyback current is the current going to the interleaved capacitor.At steady-state, and considering ideal operation without losses, the power going to the


interleaved capacitor should be equal to the power extracted from it. Thus, the current goingto the interleaved capacitor should be equal to the current of the buck converter during theturn-on interval. Therefore, the peak value of the second term of the flyback current isexpressed as the following:

ip peak =Nint

Nprimiint peak = NiiB peak

=NiDVg

fsLB|sin(2π flt)|

(3.4)

As this design is made to set the interleaved voltage to be equal to the bulk voltage, hencethe turns ratio Ni is chosen to be 1. In return, the second term of the flyback current will beequal to the buck current, and the peak current of the flyback is determined by the addition of(3.3) and (3.4) as the following:

iF peak =VBDfsLm

+DVg

fsLB|sin(2π flt)| (3.5)

In this way, the flyback current is continuously greater than the buck current. Thus, asaforementioned, DFH will never conduct and can be removed, as it conducts only if the buckcurrent is higher than the flyback current. Summarizing, the proposed interleaved techniqueensures a flyback current greater than the buck current and in return DFH is eliminated.

Regarding the operation of the converter, a full DCM has to be ensured. Hence, a studyfor the boundaries is made in order to be able to choose the reactive elements. As thebuck converter is operated in DCM, the input stage will behave as a resistance for the line.Nevertheless, when an interleaved capacitor is used, the resistance value of the buck converteris not affected, however, the average model circuit changes. The resistance is expressed asthe following;

Rg =2LB fs

D2 (3.6)

Therefore, the value of the average line current is calculated as follows:

⟨ig⟩=

vg

Rg

=D2Vg

2LB fssin(2π flt)

(3.7)


Knowing that both voltage and current waveforms will be sinusoidal, the mean inputpower is calculated as the following:

Pg =12

Vg⟨ig⟩

=12

VgD2Vg

2LB fs

=D2V 2

g

4LB fs

(3.8)

Concerning, the flyback power delivered to the output, it is expressed as the following:

PF =VB ⟨iLm⟩

=VB

(12

ILmpeakD) (3.9)

Substituting (3.3) in (3.9), the following expression for the power of the flyback deliveredto the output is found:

PF =D2V 2

B2Lm fs

(3.10)

Concerning the output power, it is found using the equivalent resistance of the LED, asthe following:

POut =V 2

OR

(3.11)

Ideally, the input power will be equal to the flyback power and equal to the output power.Therefore, by equaling the three equations of the power, a relation between the input voltageand the bulk voltage is found, as well as a relation between the bulk capacitor voltage and theoutput voltage, as shown in (3.12) and (3.13) respectively.

Vg

VB=

√2LB

Lm(3.12)

VO

VB= D

√R

2 fsLm(3.13)

The equations of the powers shown in (3.8) and (3.10) represent the two operationconstraints. However, still to ensure full DCM of operation, additional constraints have to be


added, which are the boundaries of the DCM operation. Therefore, t1 shown in Fig. 3.3 has tobe lower than the switching frequency period for a flyback DCM operation. Same conditionhas to verify t2 for a buck DCM operation. The procedure to find those two parameters isto determine two expressions for the peak current, one in terms of the duty cycle and theother one in terms of t1 for the flyback and t2 for the buck. The peak value of the magnetizinginductance current expression in terms of duty cycle was found in (3.3), and it is found alsoin terms of t1 as the following:

ILmpeak=

Nsec

NprimIO Peak

= NVO

Lm(t1 −DTs)

(3.14)

Matching (3.3), and (3.14) the following expression for t1 is found:

t1 = DTs

(VB

ns VO+1)

(3.15)

Likewise, for t2, the peak value of the buck current was found in terms of duty in (3.2),and also it is found in terms of t2 as the following:

IBpeak =VB

LB(t2 −DTs) (3.16)

Matching (3.2) and (3.16), the following expression for t2 is found:

t2 = DTs

(vg

VB+1)

(3.17)

3.4.2 Average Model

For a better illustration of the operation of the IIBFC, an average model has been developed,as illustrated in Fig. 3.9. The average model is useful to understand the power flow in theconverter. Also, it is a faster way to check the magnitude of voltages and currents in all partswithout the high-frequency switching effect.

Using the average model with the previously obtained equations, the relation betweenthe buck voltage and the inductor peak current with respect to the buck inductance has beenplotted, as shown in Fig. 3.10. This figure is drawn using the parameters shown in Table 3.2for a switching frequency of 40 kHz and output power of 25.9 W. It is clear that the voltageand the peak of the buck inductor current decrease as the buck inductance increases. However,this is in DCM but after CCM the behavior changes, at first increases, then decreases in small


deviations. Besides, increasing the inductance after the CCM area is ineffective, because theoperation as well as the PF and THD will be worse. Therefore, the chosen buck inductancewill be 900 µH.

VOC

OVBCB R

FIOIBR

B

VB

Vg

Input Buck Flyback Output LED

R

VInt

IB

Fig. 3.9 Average model of the Interleaved Buck Flyback converter.

200 400 600 800 1000 1200 1400 1600120

140

160

180

200

220

240

260

Buck Inductance (µH)

Bul

k C

apac

itor

Vol

tage

(V

olts

)

200 400 600 800 1000 1200 1400 16001.25

1.5

1.75

2

2.25

2.5

2.75

3

Bu

ck in

du

cto

r p

eak

Cu

rren

t (A

mp

s)

Bulk VoltageBuck inductor peak Current

DCM CCM

Operating Point

Fig. 3.10 Bulk capacitor voltage and inductor peak current with respect to the buck inductance.


Table 3.2 Components of the Laboratory Prototype

COMPONENTS Value

Input voltage RMS 110 V

Output voltage 37 V

Rated current 0.67 A

EMI filter capacitance 68 nF

EMI filter inductance 2.56 mH

Buck inductance ER2510/PC44, LB = 900 µH,60 Turns

Flyback transformerPQ2625/3C90,

Lm = 1.5 mH, Nprim = 25 T, Nsec = 6 T, Nint = 25 T

Bridge Diodes DB156S

DB&DFL&DAUX MURS260T3G

DOUT STPS3150

CB 47 µF / 250 V

CO 100 µF / 50 V

Cint 2.2 µF / 250 V


3.5 Design Procedure

3.5.1 Power Stage

Using the previously determined equations and the average model illustrated in Fig. 3.9,a design is made to supply an LED luminaire of 37 V/ 0.67 A, resulting in 25.9 W ofoutput power. The line voltage is 110 Vrms and line frequency is 60 Hz. Seeking for abetter efficiency, the converter is tested to work under the quasi-resonant technique. Thequasi-resonant technique shows better efficiency as it reduces the switching losses. Onedrawback of this technique is the variable switching frequency operation. Nevertheless, thevalue of the magnetizing inductance can be designed to keep the switching frequency arounda given value without much excursion.

3.5 Design Procedure 97

The selected operating switching frequency is to be around 40 kHz and to ensure thisoperation, the magnetizing inductance will be chosen to fix t1 to be equal to 80 % of theswitching period. This will ensure that the switching frequency will be around 40 kHz.

Concerning the buck inductance value, it will be designed to optimize the operationof the converter. As shown in Fig. 3.10, this will occur at the boundary operating pointbetween DCM and CCM, to decrease the bulk capacitor voltage and the inductor current asmuch as possible. Moreover, the best operation in terms of PF and THD is ensured at DCM.Accordingly, t2 has to be equal to the switching period at the peak input voltage. However,this is in an ideal situation, so a safety margin of 20 % is selected to ensure DCM operationin the practical implementation. Therefore, as shown by the vertical line in Fig. 3.10, theoperating point is a little before the boundary of DCM and CCM.

Applying this constraints to (3.15) and (3.17) related to t1 and t2 respectively, the valuesof the buck inductance, the magnetizing inductance, and the turns ratio are found. Table 3.2shows the parameters of the components used for the laboratory prototype.

3.5.2 Control Stage

The quasi-resonant technique has previously been presented with the flyback converter andit shows an improvement in the efficiency of the flyback [156–158]. The quasi-resonanttechnique is to turn on the switch at the valley value of the voltage across the switch sothat the switching losses are decreased. The same technique is adopted to the IIBFC. TheIC used for the control is the primary-side LED driver controller RT7306 [159]. As astandalone driver, the power of the IC should come from the driver itself. The control IChas a built-in high-voltage startup system just by connecting it through a high resistance tothe converter just after the bridge. Later on, the power is taken from a fourth winding addedto the flyback transformer with reversed polarity to the primary winding. The controller ICshows great advantages such as implementing the quasi-resonant technique, constant outputcurrent regulation, and dimming capability. Furthermore, the IC shows the great advantageof primary-side control. So the output current is controlled by sensing the peak value of theflyback switch current.

The control is made by adding series resistance to the flyback switch to obtain a voltagesignal to the control IC. The series resistance can be calculated from the equations presentedin [159]. However, this control method is not directly applicable to the proposed IIBFC. Thereason is that in the proposed topology, the switch is not carrying the current of the flyback,but also the current going to the interleaved capacitor. As aforementioned, and as shownin Fig. 3.6, the current of the diode DFL is the current of the switch minus the interleavedcurrent. Thus, the current through the diode can be used to get the signal going to the control


IC. The placement of the sensing resistance in series with the diode will create a sensingsignal, but with negative polarity. In order to create a positive signal so that it complies withthe specifications of the control IC, the ground is placed between the resistance and the diode.Fig. 3.11 shows the detailed schematic diagram of the laboratory prototype, in both aspectspower and control.

1

Vg

AUX

VOCO

DO

DB

D

M

LfCB

LB

Vg

C

FL

Dint

VB

Vint

RCS Gate

RT7306RT7306

HV

RHV

0.1 µF

0805

1 µF

0805

10 kΩ / 1206

HV

RG

15 / 0805VCC

RPC

2.7 kΩ / 0805

Gate

CS

CS

VCC

RAUX

10 / 1206

AUX

68 pF

0805

22 µF

35 V

RZCD1

68 kΩ / 0805

RZCD2

6.8 kΩ / 0805

SPA07N60C3

DB156S

MURS260T3G

MURS260T3G

MURS260T3G

STPS3150

100 µF/ 50 V

47 µF/ 250 V

2.2 uF/ 250 V

LEMI

CEMI

900 µH

1.5 mH

int

Fig. 3.11 Schematic diagram of the laboratory prototype.

The interleaved capacitor affects the shape of the flyback current. In return, it influencesthe shape of the signal going to the controller IC. This means that the value of the interleavedcapacitor has to be selected so that it does not disturb the operation of the converter. Analyzingthe behavior of the converter, it is found that the interleaved capacitor with the transformerleakage inductance creates a resonance in the system. The diode added in series with theinterleaved capacitor Dint protects the system from going to unstable operation. However,

3.5 Design Procedure 99

this resonance still affects the flyback current and the signal going to the controller IC. Theresonance frequency is calculated as the following:

fres =1

2π√

LkiCint(3.18)

Using (3.18), Fig. 3.12 is drawn showing the flyback current for different resonancefrequencies. The plots show resonance frequencies from top to bottom of 150 kHz, 40 kHz,and 10 kHz.

0 0.025 0.05 0.075 0.1 0.125 0.15 0.175 0.2−0.25

00.250.5

0.751

1.251.5

1.75

Cur

rent

(A

mps

)

0 0.025 0.05 0.075 0.1 0.125 0.15 0.175 0.2−0.25

00.250.5

0.751

1.251.5

Cur

rent

(A

mps

)

0 0.025 0.05 0.075 0.1 0.125 0.15 0.175 0.2−0.25

00.250.5

0.751

1.251.5

1.75

Time (ms)

Cur

rent

(A

mps

)

Flyback current IF at resonance frequency 150 kHz



Fig. 3.12 Flyback current IF at different resonance frequencies, top: 150 kHz (Cint = 150 nF),middle: 40 kHz (Cint = 2.2 µF), and bottom: 10 kHz (Cint = 33 µF).


As shown in Fig. 3.12 first plot, when the resonance frequency is much higher than theswitching frequency, the current will include fluctuations. Moreover, the peak value of thecurrent is not correctly referring to the output current. This means that the controller will notcorrectly regulate the output LED current. On the other hand, as shown in Fig. 3.12 thirdplot, when the resonance frequency is much lower than the switching frequency, there isno fluctuation in the current. However, still, the peak value of the current is not correctlyreferring to the output current. Furthermore, the low resonance frequency requires the usageof a higher capacitance value, which in return increases the size and cost of the converter,and also creates a high peak in the current during start-up. Concerning Fig. 3.12 second plot,it shows the case of a resonance frequency equal to the switching frequency. It is clear thatthere is no fluctuation, and also the current reflects with the output LED current.

Fig. 3.13 shows the prototype photograph. As can be seen, the converter is very compact.

Bulk capacitor

EMI filter Buck inductor Flyback transformer

Output capacitor

Fig. 3.13 Prototype photograph.


The line voltage and current waveforms, as well as the buck voltage, are shown in Fig. 3.14.As can be seen, the current waveform is a pure sinusoidal waveform, which illustrates thatthe proposed technique ensures that the PF and the THD will satisfy the standards. Analyzingthe input current waveform, the PF is 0.997 and the THD is 2.5 %. The efficiency is found tobe 80 %. Regarding the result of the efficiency, it is fair to justify that this is a low power


application of only 25 W. Moreover, it is a low input and output voltages (110 V and 37V respectively) and high current (0.7 A) application. In addition, the figure of efficiencyincludes all control and power circuitry, since this is a final prototype designed for stand-aloneapplications.

Fig. 3.14 Top: input current, and bottom: input sinusoidal voltage (green) and bulk voltage(red).

Fig. 3.15 shows the case of using the conventional IBFC. As shown, it is clear that theconduction angle is lower. However, the design of this converter was made to decrease thebuck voltage as much as possible (85 V), further than this a CCM operation will occur. ThePF in this case is 0.89 and the THD equal 23 %, which is on the limit of the standards. Thus,there is no more room for improvement using the conventional IBFC. Moreover, as shownalso in Fig. 3.15, the ripple voltage in the buck capacitor is very high, reaching 30 %, whichis not the case of the IIBFC, as it is found to be in the range of 8 % using the same capacitorvoltage rating, as shown in Fig. 3.14.


Fig. 3.15 Bottom: input current, and top: bulk capacitor voltage, for the conventional IBFC.

Fig. 3.16 shows the output voltage and current. The control is working perfectly, as thevoltage and currents are fixed at the desired values of 37 V and 0.67 A. As shown in Fig.3.16, the ripple in the current equals 48 mA, taking into account that most of the ripples areahigh-frequency ripples. Concerning the low-frequency ripple, it is equal to 20 mA. Thus, theripples are in the range required for this specific application. Fig. 3.17 shows the start-upprocess of the converter. As can be seen, it shows a smooth and fast starting up process,without overshoot, or oscillations.

Fig. 3.18 shows the switch voltage and the output flyback current. As shown in Fig. 3.18,the quasi-resonant technique is perfectly implemented, as the turn-off occurs at the voltagevalley, which is the lowest value of the voltage over the switch within the switching period.

Fig. 3.19 shows the regulation curve related to the variation of the output current with theinput voltage. The driver is tested for a variation of ± 20 % of the rated input voltage. Thedriver shows an acceptable operation, as the current is well controlled, with just ± 4 % oferror.

Fig. 3.20 shows the PF with respect to the variation of the dimming ratio. The experi-mental results prove that the interleaved topology will ensure a PF fulfilling the standards atany dimming ratio, reaching a minimum dimming ratio of 10 %.


10 ms/div100 mA/div10 V/div

Fig. 3.16 Output current (yellow), and output voltage (green), steady-state operation.

Off-State Start-Up Steady-State

50 ms/div 100 mA/div 5 V/div

Fig. 3.17 Output current (yellow), and output voltage (green), start-up operation.


Fig. 3.18 Bottom: output flyback current, and top: voltage across the switch.

80 85 90 95 100 105 110 115 1200.95

0.97

0.99

1.01

1.03

1.05

Input voltage percentage

Out

put

curr

ent

p.u.

Fig. 3.19 Per unit output current with respect to the variation of input voltage.


0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 10.92

0.94

0.96

0.98

1

Dimming ratio

Pow

er F

acto

r

Fig. 3.20 Power factor with respect to dimming ratio.

Commenting on Fig. 3.18, it is found that the switch experiences high voltage and currentstresses. This is the case in most of the single-switch integrated converters. This effect is thetrade-off for using a single switch instead of two. Nevertheless, despite the higher stress inthe switch, it is still better than having two switches with two driver circuits and two controlstrategies for both switches. However, by redesigning the parameters of the proposed driver,a reduction in the voltage across the switch can be achieved to reach 300 V. However, thepresented design is not aiming at a decrease in the voltage across the switch as a higherswitch voltage provides other advantages as follows:

• One diode will not conduct and can be removed.

• The decrease in the voltage will lead to a higher ripple on the bus and output voltages.

• Both flyback and buck current peaks will increase, and in return, the ratings of thediodes need to increase. Thus, it is preferable to use a higher rating switch rather thanthree higher rating diodes. Moreover, concerning the switching losses, a soft turn-onswitching is assured, as it operates in DCM, and because a quasi-resonant technique isused the turn-off losses are minimized. On the other hand, higher current in the diodeswould lead to a higher conduction loss.

Finally, a comprehensive comparison with the up-to-date PFC methodologies [160–162]is shown in Table 3.3. All three methodologies aim at absorbing continuous power fromthe AC main to have better THD and PF. In addition, they try to avoid sending the input


power oscillations to the output, to reduce the output ripple. As shown in Table 3.3, theproposed IIBFC has the following promising features compared to the other techniques: i)single switch driver, ii) isolation between input and output, iii) simple control circuitry, iv)only one voltage sensor is required, v) compact size, vi) low cost, and vii) low output ripple.On the other hand, it has a single drawback which is the lower efficiency.

Table 3.3 Comparison Among the Proposed Technique and the Up-to-Date PFC Techniques

Pulsating-Power-Buffering(PPB)

Single-switch PPBsingle-phase PFC

PROPOSED IIBFC

2 switches are used 1 switch is used 1 switch is used

1 inductor 2 inductors 2 inductors

No Isolation No IsolationIsolation between input

and output

Complicated control (DigitalSignal Processor (DSP) is

needed “TMS320F28069”)

Complicated control (DSPis needed “F28069”)

Simple andstraight-forward control(single IC “RT7306”)

Additional board for sensorsis required

Two sensors are requiredOne built-in voltage sensor

is required

High price and Bigger size High price and Bigger sizeLow price and Compact

size

Line voltage (110V) Line voltage (110V) Line voltage (110V)

Output Voltage (100-200V) Output Voltage (120V) Output Voltage (37V)

Medium power application110 W

Medium power application100 W

Low power application 25W

5 % voltage ripple using40 µF

4.7 % voltage ripple using30 µF



High efficiency, 94.7 % atrated power 110 W

Medium efficiency,89 % atrated power 100 W

Low efficiency, 80 % atrated power 25 W

3.7 Conclusion 107

3.7 Conclusion

This chapter has presented a new topology that enhances both PF and THD to be wellbelow the limitations specified by the IEC 61000-3-2 standard. This is done by inserting aninterleaved capacitor between the rectifier and the converter. The converter used to drive theLED is the IIBFC converter. The interleaved capacitor voltage is fixed by a third windingadded to the flyback transformer. Furthermore, the proposed IIBFC reduces the ripple by afactor of five, which means a significant reduction of the output and bulk capacitor voltage.Also, the proposed technique avoids any complex circuitry or any other extra sensors apartfrom those used in the conventional IBFC, since the control technique is the same as thatused for the IBFC. Regarding the power component, the proposed topology offers all thesefeatures by only adding an extra winding in the flyback transformer, a capacitor of 2.2µFand an extra diode. However, the proposed technique ensures that a diode of the conventionalIBFC is not conducting so that it can be removed.

Finally, a prototype working at 110 V, 60 Hz, and 37 V output, driving a LED luminary of25 W, has been designed and implemented to prove the previously illustrated characteristics.Experimental results have proven that the harmonic content of the input current equals 2.5 %,and the power factor equals 0.997 at full power operation. Moreover, the converter meets theIEC-61000-3-2 standard at any dimming ratio, reaching a minimum dimming ratio of 10 %.The converter efficiency is 80 %, which is good considering the simplicity of the converter,the low power of the present application and the good features offered by the converter.

Chapter 4

Hybrid Series-Parallel PWM dimmingtechnique


4.2 Derivation of the Passive Hybrid Series-Parallel PWM dimming tech-nique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

4.2.1 Analysis and Average model of Passive HSP-PWM dimming . . . 114

4.2.2 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . 117

4.3 Derivation of the Active Hybrid Series-Parallel PWM dimming tech-nique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

4.3.1 Operation Principle of the IBFBC . . . . . . . . . . . . . . . . . 123

4.3.2 Mathematical Analysis and Average Model . . . . . . . . . . . . 128

4.3.2.1 Mathematical Analysis . . . . . . . . . . . . . . . . . 128

4.3.2.2 Design of the converter . . . . . . . . . . . . . . . . . 130

4.3.2.3 Average model . . . . . . . . . . . . . . . . . . . . . . 133

4.3.3 Laboratory Prototype . . . . . . . . . . . . . . . . . . . . . . . . 135

4.3.3.1 Power converter . . . . . . . . . . . . . . . . . . . . . 135

4.3.3.2 Control and Signals . . . . . . . . . . . . . . . . . . . 135

4.3.4 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . 138

4.4 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

110 Hybrid Series-Parallel PWM dimming technique

4.1 Introduction

The previous two chapters have presented a study on the IBFC to enhance the efficiencyand decrease the losses, and a modification on the converter structure to achieve a unity PF.Furthermore, this chapter presents a new PWM dimming technique applied to the IBFC.

As aforementioned in the introduction, there are two main dimming techniques, AM andPWM. However, each of them has its own issues. The analog dimming shows a significantdrawback, a lack of linearity can occur at high injection currents, as well as a noticeable shiftin the chromaticity coordinates.

Even though, the PWM dimming has three different types, each of them has its owndrawback.

Starting by the enable dimming, it shows a limitation in the dimming frequency as higherfrequency will show a continuity in the current. Moreover, the converter suffers a transientoperation with the same frequency of the dimming as the whole converter will switch on andoff each time the LED will switch.

Later comes the series PWM dimming, showing pure PWM waveform for the LEDcurrent. However, it produces an overcharge of the output capacitor as the converter operationis continuous. The overvoltage of the capacitor creates a peak in the current of the LED. Fig.4.1 shows the case of a driver supplying an LED with series enable dimming technique. Asshown in the figure the output voltage has a new ripple with the dimming frequency. As thedynamic resistance of the LED is relatively small, any perturbation in the voltage will lead toa huge peak in the LED current. The rated LED current is 350 mA, however, as shown inFig. 4.1 the peak current reaches 560 mA which is 160 % of the rated current. The illustratedphenomena lead to a huge decay in the LED lifetime.

Finally, the Shunt PWM dimming is accomplished by a switch in parallel with the LEDs.The shunt dimming can be either in the current control mode or the voltage control mode.This technique offers a great advantage, which is the ability to have a fast switching for theLED. However, as the converter is kept working, the efficiency is slightly reduced due to thelosses of the extra switch and the circulating power.

The HSP-PWM dimming technique comes to solve these issues and improve the opera-tional performance of the driver while dimming.

4.2 Derivation of the Passive Hybrid Series-Parallel PWM dimming technique 111

(a)

(b)

Fig. 4.1 Simulation results under conventional PWM series dimming: (a) shows LED lampcurrent, while the (b) shows the output capacitor voltage.

4.2 Derivation of the Passive Hybrid Series-Parallel PWMdimming technique

The Series PWM dimming is made by placing a switch in series with the LED. While theparallel PWM Dimming is made by creating a parallel path for the current. However theproposed solution HSP-PWM dimming is made by combining both techniques: a switchwill be connected in series, as well as another switch will be connected in parallel with the


LED while connected in series with a resistance, as shown in Fig. 4.2. Fig. 4.2 shows theequivalent model of the used LEDs, which is a series of 48 Golden Dragon LED.

VOCO

DO

DBD3D2

D4 D5 DFL

DFH

M1

LFCB

LB

Vg

M 2 M3

Dim-refV

69.8

136V

W

Fig. 4.2 IBFC with the LED connected at the output, showing as well its model, and with theparallel resistive branch.

The idea is simple; it is a hybrid solution between the series and parallel PWM dimmingtechniques. The series switch is added to have the advantage offered by the series PWM,which is the instantaneous cut of the LED current. However, the series PWM techniqueleads to an enormous issue, which is that the converter is operating as a power source thatis continuously sending power to the output. However, while the system is operating indimming mode for a given period there will not be a load that will consume this power, whichleads to a variation in the output capacitor voltage and in return a peak in the LED currentwill appear as shown in Fig. 4.1. Therefore, the benefit of the parallel path shows up, bycreating a consumption load of this power in limit the voltage increase and in return limitthe peak current of the LED. The passive-HSP-PWM is made by adding a resistive load inthe parallel branch. The optimal value of the resistance from the operational performancepoint of view is the one that makes the power output constant independent of the dimminglevel. Thus, it would be the equivalent resistance of the LED. In other words, the value ofthis resistance is found by the resistive value that will consume the same LED current at thesame output voltage. It is found by the following expression:


Req =VLED

ILED(4.1)

The simulation previously made for the series PWM is repeated but this time for theproposed HSP-PWM dimming. For a fair comparison, the same parameters are used forthe same dimming ratio. The used resistance in the simulation is the equivalent resistancecalculated from (4.1) equals 460 Ω. Fig. 4.3 shows the results of the of the proposed HSP-PWM dimming technique. As shown in Fig. 4.3 (b) the maximum voltage is 162.5 Volts,which is just 2 Volts higher than the rated voltage. Moreover, it is high switching frequencyripple. Concerning, the current peaks the maximum value is just 370 mA, which is just 105% of the rated current; this means only 5 % of ripple. Comparing these results with the onespreviously obtained from the conventional series PWM dimming, it is clear that the operationis greatly improved as the LED current is now more or less constant without significantpeaks.

(a)

(b)

Fig. 4.3 Simulation results of the proposed HSP-PWM dimming: (a) shows LED current,while (b) shows output capacitor voltage.


4.2.1 Analysis and Average model of Passive HSP-PWM dimming

This section aims to clarify how the value of the parallel branch resistance could be chosen.The addition of the resistance will decrease the efficiency of the system. The equivalentresistance value of the LED, 460 Ω, is optimal from the operational point of view. However,it is the worst from the efficiency point of view, especially at a low dimming ratio. The valueof the resistance can be changed to another one higher. The increase in the resistance valuewill increase the efficiency, however, it will increase the peak current as well. To choose thevalue of the resistance suitable for the application, a study will be made analyzing the effectof the resistance value on the LED current and the efficiency.

In order to study the effect of numerous value of resistance, a faster analysis methodologyneeds to be developed. An average model is developed for the full converter including thenew HSP-PWM dimming technique. However, the part concerning the dimming is kept withits normal switching model, in order to show the dimming switching effect on the outputvoltage ripple. knowing that, the average model will not show the effect of the switchingfrequency ripple on the output voltage nor LED current.

Fig. 4.4 shows the average model of the converter.

VOC O

M2 M 3

69.8

136V

VBCB RF IFI B

RHSP

RB

VB

Vg

Input Buck Flyback Output lamp and Resistance

W

Fig. 4.4 Average model of the IBFC with the new HSP-PWM dimming technique.

Both buck and flyback converters are operating in DCM. The equivalent convertersresistance used in the average model are expressed as the following:


• Buck operating in DCM equivalent resistance

RB =2LB fs

D2 (4.2)

• Flyback operating in DCM equivalent resistance

RF =2L f fs

D2 (4.3)

In order to study the behavior of the converter, the worst case should be determined.Concerning efficiency, the worst case occurs at the least dimming ratio. Thus, the efficiencywill be studied at a dimming ratio of 10 % to illustrate the worst-case efficiency of theconverter. With regard to the peak current, the worst case will be at the higher bus voltagevariation. In the following the methodology to know which dimming ratio will have the worstcurrent peak. The bus voltage variation is determined from the following equation:

∆V =Idimtdim

Co(4.4)

Considering the power delivered to the output, it is constant and the control is not affectedby the dimming, thus, the current going to the capacitor could be the average LED current.Therefore the dimming current is expressed as the following:

Idim = ILEDDdim (4.5)

The dimming time, or the time where the LED is switched-off, is expressed as thefollowing:

tdim =(1−Ddim)

fdim(4.6)

Substituting with (4.6) and (4.5) in (4.4), the final expression for the output voltagevariation is found as the following:

∆V =ILEDDdim (1−Ddim)

fdimCo(4.7)

Found in (4.7) that the voltage variation is a function of the dimming duty. Found as wellthat the formed function is a second-order equation with a maximum value at dimming dutyequal to 0.5. Consequently, the highest peak current will occur at 50 % dimming ratio.

Fig. 4.5 shows a chart of resistances values equal to the multiple of the equivalentresistance value with respect to the wasted power at dimming ratio 10 %, as well as it shows


the value of the peak current at its worst case at dimming ratio 50 %. Fig. 4.5 gives theresistance value in terms of the resistance factor which is defined as follows:

K =RHSP

Req(4.8)

For a better explanation of the use of the resistance chart an example is given. Forinstance, if the LED specifies a maximum peak current of 510 mA, thus the chosen resistancefactor would be 6. This means that the parallel branch resistance would be six times theequivalent resistance, equals 2.76 kΩ. From Fig. 4.5 the maximum peak current at resistancefactor equal to 6 will be 507 mA at a dimming duty 0.5, and the maximum wasted energy willbe 8.43 W at dimming duty 0.1. The advantage that the Chart gives is a degree of freedom tochoose a trade-off between LED peak current value and efficiency.

2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 7 7.5 8 8.5 9 9.5 105

10

15

20

25

30

X: 6

Y: 8.426

Resistance Factor K

Wa

sted

Po

wer

(W

)

2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 7 7.5 8 8.5 9 9.5 10420

440

460

480

500

520

X: 6

Y: 507

Pea

k c

urr

ent

(Am

p)

X: 2

Y: 435

Wasted power at Dimming ratio 10 %

Peak current at Dimming ratio 50 %

Fig. 4.5 HSP-PWM dimming resistance chart.

Fig. 4.6 shows the efficiency of the converter with respect to the resistance factor kfor different dimming ratios; 10 %, 15 %, 20 %, and 25 %. Fig. 4.6 shows that if theapplication minimum dimming ratio is not small, thus, the minimum efficiency of the systemwill be higher, and in return, it will be acceptable to choose a lower resistance to decrease


the maximum peak current further. Shown as well the efficiency value at different dimmingratios for a resistance factor of 6. It shows an efficiency of 40 %, 51.43 %, 60 %, and 66.67% for dimming ratios 10 %, 15 %, 20 %, and 25 % respectively.

2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 7 7.5 8 8.5 9 9.5 1010

20

30

40

50

60

70

80

X: 6

Y: 40

Resistance Factor K

Eff

icie

ncy X: 6

Y: 51.43

X: 6

Y: 60

X: 6

Y: 66.67

Dimming 10 %

Dimming 15 %

Dimming 20 %

Dimming 25 %

Fig. 4.6 Efficiency Chart with respect of resistance factor, for different dimming ratios; 10 %,15 %, 20 %, and 25 %.

4.2.2 Experimental Results

In order to verify the previously illustrated theoretical and simulated results, a laboratoryprototype was built. Table 4.1 shows the parameters and components list of the IBFCincluding the active HSP-PWM dimming technique. The converter switching frequency ischosen to be 100 kHz for smaller reactive elements and reduced output ripple. The ratedpower of the converter design is 56 W, operating with an input voltage of 220 Volts and 50Hz.


Table 4.1 Specification and Components of the IBFC Including Passive HSP-PWM Dimming

Components Value


Output voltage 160.5 V




Buck inductance ETD29/3C85, LB = 42 µH, 20 Turns

Flyback transformer ETD29/3C90, Lm = 105 µH, Np = 20 T, Ns = 40 T

Bridge Diodes MUR160

DB&DFL&DFH MURS260T3G

DOUT STPS3150

CB 470µF / 250 V

CO 1µF / 250 V


Switches M2 & M3 IRFB840

Fig. 4.7 shows the experimental results of the converter. It shows in the upper trace thedimming signal which is at dimming ratio of 50 % and in the lower trace the LED current.Fig. 4.7 shows four different cases for parallel resistance value. Fig. 4.7 (a) shows the case ofusing the equivalent resistance of the LED 460 Ω. It is clear that the LED current is constantwith only the high-frequency ripple, the maximum value of the current, in this case, is 380mA. Fig. 4.7 (b) shows the case of using a resistance a slightly higher than the double (k = 2)of the equivalent resistance 990 Ω, therefore the current starts to have a peak, the peak, inthis case, equals 440 mA. Fig. 4.7 (c) shows the case of using a resistance approximatelyfive times (k = 5) the equivalent Lamp resistance 2.31kΩ, the peak current increases more toreach 519 mA. Finally, Fig. 4.7 (d) shows the case of the series PWM dimming as the testwas made without resistance, as shown the peak current reaches 560 mA.


(B)

(D)(C)

(A)

Dimming

Signal

LED

Current

10

0 m

A/d

iv.

5 V

/div

.

Fig. 4.7 Dimming signal (Upper trace), and lamp current (Lower trace) for dimming ratio50 % with four different resistance values. (a) 452 Ω, (b) 990 Ω, (c) 2.31 kΩ, (d) Withoutresistance.

Fig. 4.8 shows the efficiency as well as the power loss with respect to the dimming ratio.The results presented are obtained from the experimental results for three different resistancevalues 452 Ω, 990 Ω, and 2.31 kΩ. The figure shows that efficiency matches the one obtainedfrom the simulation. Concerning the resistance of 452 Ω the efficiency is not acceptable, asit shows efficiency below 10 % at a dimming ratio of 10 %. Concerning the 2.31 kΩ it showspromising results as it has an almost 40 % efficiency at the lowest dimming ratio of 10 %.Moreover, Fig. 4.8 (b) shows the values of wasted power. This figure aims to illustrate thatthe 40 % efficiency is not a significant issue as it represents a loss of 11 W.


(a)

(b)

Fig. 4.8 (a) Shows the efficiency and (b) shows the wasted energy with respect to the dimmingratio, for three difference resistances values; 452 Ω, 990 Ω, and 2.31kΩ.

This application aims to maximize the efficiency as much as possible, keeping the peakof the LED below 50 % of rated current. Thus, the chosen resistance value is 2.31 kΩ. Fig.4.9 shows the dimming signals (upper plot) and the LED current (lower plot) for a resistancevalue of 2.31 kΩ, at four different dimming ratios. Fig. 4.9 (a) shows the case of 10 %


dimming ratio, Fig. 4.9 (b) shows the case of 30 % dimming ratio, Fig. 4.9 (c) shows thecase of 60 % dimming ratio, while Fig. 4.9 (d) shows the results for 90 % of dimming ratio.

(B)

(D)(C)

(A)

Dimming

Signal

LED

Current

10

0 m

A/d

iv.

5 V

/div

.

Fig. 4.9 Dimming signal (Upper trace), and LED current (Lower trace) for a resistance valueof 2.31 kΩ with four different dimming ratios. (a) 10 %, (b) 30 %, (c) 60 %, and (d) 90 %.

Commenting on the topology, the proposed HSP-PWM dimming technique shows animprovement in the current shape, as well as the limitation of the current peak in the LED.This technique also shows an embedded advantage, which is the usage of a quite smallcapacitance at the bus output voltage. For a longer lifetime driver, this capacitor should bea film capacitor. Thus, the reduction of its capacitance matters in terms of size and price.However, the technique shows the main drawback which is the lack of efficiency. This makesit suitable only for low power applications.


4.3 Derivation of the Active Hybrid Series-Parallel PWMdimming technique

The passive HSP-PWM dimming technique is previously presented, showing enhancementin the driver’s performance. However, the driver shows poor efficiency due to the externalresistance used to decrease the peak of the LED current. It is presented a graph of theefficiency and the peak current with respect to the resistance value. This graph facilitatesthe choice of the right balance between operation and efficiency. However, compromisingefficiency is not an easy choice, even though it is for better performance. This creates themotive to investigate an active HSP-PWM dimming technique.

The IBFBC is proposed to solve this issue, as it maintains the operational progress shownby the HSP-PWM technique, ensuring greater efficiency. Fig. 4.10 shows the schematicof the IBFBC. The resistive branch in the passive HSP-PWM is substituted by an outputbuck converter. To build the output buck converter a diode, inductor, and MOSFET arerequired. The output buck converter is working in DCM. It serves as a power source, itabsorbs the output power, at LED switched-off, and sends it back to the input. This actionhas two advantages. It ensures the same efficiency level, and the output voltage will be nearlyconstant which, in return, eliminates the peaks in the current. In addition, the proposed driverdoes not need any complex circuitry nor any extra sensors. Also, it can be applied to anyother converter.

VOCO

D2D1

D3 D4 M1

LmCB

LB

Vg

IAC

DFL

DFH

DB

DOut

VB

M2

M3

DBO

Ld

Fig. 4.10 Integrated Buck-Flyback-Buck Converter (IBFBC).

4.3 Derivation of the Active Hybrid Series-Parallel PWM dimming technique 123

4.3.1 Operation Principle of the IBFBC

The proposed IBFBC has two operating frequencies, the switching frequency, and thedimming frequency, which makes the analysis of the IBFBC difficult. Thus, for a clearexplanation, the operation of the driver will be studied under each frequency separately.

1. The dimming frequency

The output buck converter operates in DCM, so the operation will be split into threemain stages. Fig. 4.11 shows the schematic of the IBFBC as well as the currentdirection in the converter at the three stages. The main waveforms of the currents inthe converter are shown in Fig. 4.12. Nine plots are shown, the first three represent thegate signal of the three Mosfets, then the following six plots show the currents duringone dimming period, while the inset shows the detailed operation during one switchingperiod. The plots are respectively from top to bottom, the gate signal of M1, the gatesignal of M2, the gate signal of M3, the output buck inductor current, the main switchcurrent, the flyback input current, the output flyback current, the input buck inductancecurrent, and the LED current. An explanation for the three stages is illustrated as thefollowing:

• Stage A: 0 < t < DdimTdim

Shown in Fig. 4.11, stage A, first schematic. During this stage the LED isswitched-off. The output buck converter is operating, and its inductor is energiz-ing. The output back inductor current is shown in Fig. 4.12 fourth graph firststage.

• Stage B: DdimTdim < t < t3

Shown in Fig. 4.11, stage B, second schematic. During this stage the LED isswitched-on. The output buck converter is switched-off; however, the inductor isde-energizing through the diode. The output back inductor current is shown inFig. 4.12 fourth graph second stage.

• Stage C: t3 < t < Tdim

Shown in Fig. 4.11, stage C, third schematic. During this stage the LED isswitched-on. The current in the inductor reaches zero, there is no more current inthe output buck converter. The output back inductor current is shown in Fig. 4.12fourth graph third stage equal to zero.


VO

DO

DBD2D1

D3 D4 D

D

M1

VB

LB

vg

FL

F H

iB i F

Stage B : DdimTdim < t < t3

M2

M3

DBO

LdiBack

iBackiLED

VO

DO

DBD2D1

D3 D4 D

D

M1

VB

LB

vg

FL

FH

iB iF

Stage A : 0 < t < DdimTdim

M2

M3

DBO

Ld

iBack

iBack

VO

DO

DBD2D1

D3 D4 D

D

M1

VB

LB

vg

FL

FH

iB iF

Stage C : t3 < t < Tdim

M2

M3

DBO

Ld

iLED

Fig. 4.11 Equivalent circuit of IBFBC during the three dimming stages.


t

t

t

t

iM1

iF

iO

iB

A B C

DTsVB

N Lm

DTsVB

LB

iLED

Ⅰ Ⅱ Ⅲ Ⅳ

t

t

t

t

iM1

i F

iO

i B

DTs Tst1 t2

Tdim

TDdim

t

iback

M1

M3

M2

dim

3

DTsvg

LB

VB-

Fig. 4.12 Main current waveforms of the proposed IBFBC operating in DCM, within onedimming frequency, and with a zoom-in showing as well the currents at high frequencyswitching period around the peak line voltage.


2. The switching frequency

The converter has just one switch, therefore, there are only two operation modes;on-state, off-state. However, the DCM operation of the buck and the flyback splits theoff-state into three intervals. Thus, the converter has four intervals in total, as illustratedin Fig. 4.12 on the right side. Fig. 4.13 shows the schematic of the IBFBC in its fourintervals. Knowing that the switching frequency is much higher than the dimmingfrequency, thus, the four intervals will repeat many times during each dimming stage.Fig. 4.13 shows the four intervals in the case of stage A where the LED is switchedoff and the output buck is on. An explanation for the four intervals is illustrated as thefollowing:

• Interval I : 0 < t < DTs

In this interval, the main switch M1 is on. The current starts to flow from the inputenergizing the buck inductance. Meanwhile, there is a current flowing from thebulk capacitor energizing the magnetizing inductance of the flyback transformer.This interval ends by the switching-off of switch M1.

• Interval II : DTs < t < t1

In this interval, the main switch M1 is off. The buck inductance starts to de-energize sending the power to the bulk capacitor. While the magnetizing induc-tance is de-energize sending the power to the output. This interval finishes whenone of the two currents goes to zero.

• Interval III : t1 < t < t2

In this interval, the main switch M1 is off. One of the buck inductor and flybacktransformer currents has already reached zero, while the other one has not yet.Fig. 4.12 in the zoom-in part shows Interval III, in this case, the flyback currentis equal to zero and the buck inductor is still sending power to the bulk capacitorthrough the buck diode. This interval ends when the buck current also reacheszero.

• Interval IV : t2 < t < Ts

In this interval, the main switch M1 is off. All the currents in this interval arealready equal to zero. However, the LED current is continuous and conductingdue to the output capacitor. This interval ends with the switching-on of M1.

4.3D

erivationofthe

Active

Hybrid

Series-ParallelPWM

dimm

ingtechnique

127

iO

VO

DO

DBD2D1

D3 D4 D

D

M1

VB

LB

vg

F L

FH

iB iF

(a) Interval Ⅰ : 0 < t < DTs (b) Interval Ⅱ : DTs < t < t1

(c) Interval Ⅲ : t1 < t < t2 (d) Interval Ⅳ : t2 < t < Ts

M2

M3

DBO

Ld

VO

DO

DBD2D1

D3 D4 D

D

M1

VB

LB

vg

FL

FH

iB

M2

M3

DBO

Ld

VO

DO

DBD2D1

D3 D4

D

M1

VB

LB

vg

FL

FH

iB

M2

M3

DB

O

Ld

VO

DO

DBD2D1

D3 D4 D

D

M1

VB

LB

vg

FL

FH

M2

M3

DBO

Ld

iBack

iBackiBack

iBack iBack

iBackiBack

iBack

D

Fig. 4.13 Equivalent circuit of IBFBC during all four intervals.


4.3.2 Mathematical Analysis and Average Model

4.3.2.1 Mathematical Analysis

The analysis considers the converter in its ideal behavior. Thus, the losses due to the switchingand the parasitic elements are neglected. The analysis aims to reveal the effect of addingthe output buck converter. Mainly the variation will take place in the voltage of the bulkcapacitor, and the duty of the main switch. The bulk voltage will identify the rating of thecapacitor. Moreover, a slight duty will make the operation critical. Thus, the study of thesetwo parameters is necessary. The procedure used is to find the equations of the power in eachpart of the converter and match them. The result will be two equations that describe boththe duty and the bulk voltage in terms of driver parameters. Fig. 4.14 shows the main fourpower symbols and directions of the IBFBC; the AC power coming from the grid, the flybackpower, the power going to the LED, and the power delivered back to the input.

VOCO

D2D1

D3 D4 M 1

LmCB

LB

Vg

IAC

DFL

DFH

DB

DOut

VB

M2

M3

DBO

L

PAC

PFlyback

PbackP

LED

d

Fig. 4.14 The four main power directions of the proposed IBFBC.

Ideally, the AC power will be equal to the flyback power subtracting from it the powercoming from the output buck converter. Moreover, the flyback power will be equal to thepower going to the LED and the power of the output buck. Thus, the equations of the powerflow can be expressed as follows:

Power f lyback = PowerLED +Powerback (4.9)

PowerAC = Power f lyback −Powerback = PowerLED (4.10)


In the following the equations of the main converter power are shown:

• The LED power

PowerLED =VoDdimILED (4.11)

• The power of the output buck converter

It is equal to the power in a buck converter operating in DCM.

Powerback =(1−Ddim)

2Vo (Vo −VB)

2Ldim fdim(4.12)

• The power of the flyback converter

Power f lyback =D2V 2

B2Lm fs

(4.13)

• The AC input power

In order to find the final equation of the AC input power the analysis made in [32, 77]is used:

IBn =1

2m

(1− 2sin−1 m

π

)−

√1−m2

π(4.14)

IB = IBn

Vg

RB(4.15)

PAC = IBVB = IBn

VBVg

RB(4.16)

PAC =VBVgD2

2LB fs

(1

2m

(1− 2sin−1 m

π

)−

√1−m2

π

)(4.17)

Substituting (4.11), (4.12), (4.13), and (4.17) in the two equations of the power flow (4.9)and (4.10), the following expressions are obtained:

D2V 2B

2Lm fs=VoDdimILED +

(1−Ddim)2Vo (Vo −VB)

2Ldim fdim(4.18)


VoDdimILED =VBVgD2

2LB fs

(1

2m

(1− 2sin−1 m

π

)−

√1−m2

π

)(4.19)

4.3.2.2 Design of the converter

For better performance, magnetic components must be well selected and designed. Theinput buck inductance and the magnetizing inductance of the flyback transformer are chosento follow two rules. First, they are selected so that the converter operates close to BCM.In addition, the ratio between both of them fixes the value of the bulk voltage. Thus, thevalues of the inductances are chosen to minimize the bulk voltage, for higher PF and lowerTHD. Following these two constraints and applying them in equations (4.18) and (4.19), thecalculated input-buck inductance is 420 µH, and the calculated magnetizing inductance is315 µH. Table 4.2 shows the parameters and components list of the IBFBC including theactive HSP-PWM dimming technique.

Regarding the optimum value of the output buck inductance, Fig. 4.15 illustrates thecurrent ripple with respect to the dimming ratio. As shown in Fig. 4.15, the peak value of theripple will occur at a dimming ratio of 0.5 as well. Thus, the study of the optimum value ofthe output inductance will be carried out at a dimming ratio equal to 0.5.

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 110

20

30

40

50

60

70

Dimming Ratio

Cur

rent

rip

ple

in p

erce

ntag

e of

rat

ed c

urre

nt

LED current ripple

Fig. 4.15 Output current ripple with respect to the dimming ratio.


Table 4.2 Specification and Components of the IBFC Including Active HSP-PWM Dimming

COMPONENTS Value






Buck inductance ETD29/3C85, LB = 420 µH, 20 Turns

Flyback transformerETD29/3C90,

Lm = 315 µH, Lk = 3.6 µH, Np = 20 T,Ns = 40 T

Output buck inductance ETD49/3C95, Lm = 1.8 mH, N = 10 Turns

Bridge Diodes MUR160

DB&DFL&DFH MURS260T3G

DOUT STPS3150

CB 470µF/200V

CO 1µF/200V


Switches M2 & M3 IRFB840

This value is found by getting the inductance that handles half the output power, atdimming ratio 0.5 to make the output power always equal to the rated power. Applying this to(4.12) the value of the inductance is found. However, the value of the bulk capacitor voltageis missing, and there are two ways to estimate it. The first method is to calculate the bulkvoltage in the conventional IBFC without taking into consideration the output buck converter.However, a more accurate method is to calculate the bulk voltage in the entire IBFBC. Thisprocedure is used for this application, a value for the output buck inductance is found to be1.8mH. In order to verify this technique Fig. 4.16 is presented. Fig. 4.16 is obtained from thesimulation by measuring the ripple value at different output-buck inductance values. It shows


the output current ripple with respect to the output-buck inductance. The inductance valuesare in per unit value of the estimated value, in other words, 1 means for this application 1.8mH. Fig. 4.16 shows that the estimated value is acceptable, because when using a valuehigher than this one, up to 1.5 times, enhancement of only 1 % is reached, and below thisvalue, a serious decay in the performance occurs.

0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.512

14

16

18

20

22

24

26

Output buck inductance in pu of the estimated value

Cur

rent

rip

ple

in p

erce

ntag

e of

rat

ed c

urre

nt

LED current ripple

Fig. 4.16 Output current ripple with respect to the output buck inductance in per unit value ofthe estimated value (1.8mH).

Table 4.2 illustrates the drive parameters, used in (4.18) and (4.19), so Fig. 4.17 isperformed. Fig. 4.17 shows the main switching duty variation as well as the bulk voltagevariation with respect to dimming duty (Ddim) variation. The driver is designed so thatthe variation in the bulk voltage remains within the range of the capacitor ratings to avoidde-rating it. Based on this information, the rated voltage of the bulk capacitor and the outputcapacitor is chosen to be 200 V.


0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1130

136

142

148

154

160

Inpu

t B

uck

volt

age

VB (

Vol

ts)

Dimming duty

0 0.2 0.4 0.6 0.8 10

0.1

0.2

0.3

0.4

0.5

Mai

n Sw

itch

dut

y

Bulk Capacitor VoltageDuty

Fig. 4.17 Variation of the input buck voltage and the main switch duty with respect to thedimming duty (Ddim).

4.3.2.3 Average model

The average model has a great advantage as it analyses the converter without the complexityof switching frequency. Fig. 4.18 shows the main scheme of the average model of theproposed IBFBC. The model is split into three main parts that represent the three integratedconverters.

In the following, a concise explanation of the average model of each converter is presented.

1. The input buck converter

The left part of Fig. 4.18 shows the average model of the input buck converter. Vg isthe input AC voltage after rectification. The diode is used to fix the direction of thepower from the AC main to the converter. VB is the buck voltage fixed by the bulkcapacitor, shown in the following partition as CB. Finally, RB is the buck resistance inDCM previously illustrated in 4.2.

2. The flyback converter


The partition in the middle of Fig. 4.18 shows the average model of the flybackconverter. RF is the flyback operating in DCM equivalent resistance as given by (4.3).IB is a current source representing the power coming from the input buck converter.Finally, Iback is a current source representing the power coming from the output buckconverter.

3. The output buck converter

The last partition at the right of Fig. 4.18 represents the average model of the outputbuck converter. Rback is the buck DCM equivalent resistance of the output buckconverter and can be expressed as follows:

Rback =2Ldim fdim

(1−Ddim)2 (4.20)

Finally, the LED is represented by its threshold voltage Vth and its dynamic resistanceRdyn. The dynamic resistance is divided by the dimming duty value to take into account thedimming in the average model.

VOCO

V VB

VBCB R

FIFIB

RBuck

RB

VB

Vg

Input Buck Output Buck

th

Rdyn

Ddim

IF

IB

Iback

Flyback

LED

Fig. 4.18 Proposed IBFBC average model split into the three main converters input buck,flyback, and output buck.


4.3.3 Laboratory Prototype

A laboratory prototype was built to verify the operation of the converter experimentally. Fig.4.19 shows the simplified block diagram of the IBFBC including the main required signalblocks.

Diode

BridgeIBFC

Output

BuckConverter

Ddim

GD

Gg

HC

Ddim

Davg

Vdim-ref

Verror

Vref

Vsense

Vg

Ddim1 -

15 V

Fig. 4.19 Simplified block diagram for the IBFBC.

The prototype can be illustrated under two main divisions;

4.3.3.1 Power converter

The Power components are well-chosen as well as the magnetic elements are well designedand tested to fit the design previously explained. The specifications of the power componentsare illustrated in Table 4.2. The main switching frequency of the converter is 100 kHz; thisis to reduce the inductive and capacitive elements as much as possible. While concerningthe dimming switching frequency, the design was flexible to operate under several dimmingfrequencies of 25 kHz, 12.5 kHz, and 5 kHz.

4.3.3.2 Control and Signals

Fig. 4.20 shows the full scheme control of the converter. In the following is the detailedexplanation of each partition of the control scheme:


1. Current sensor

A resistance of 1Ω is connected in series with the LED. Consequently, the voltage overthis resistance will be equal to the current passing through it. The current sensor takesthe voltage over this resistance and processes it. First, through a low pass filter, thehigh-frequency and the dimming frequency effects are removed to measure the averagevalue of the current in the LED. Second, the filter itself operates as an amplifier, as itmultiplies the average value of the LED current by 10. Thus, the output of the currentsensor will be the average value of the LED current multiplied by 10.

2. Dimming sensor

The dimming sensor is taking the dimming signal going to the MOSFET connected inseries with the LED and processes it. Firstly, through a low pass filter, the dimmingeffect is removed, and the result will be an average value from 0 to 15 V referringto a luminous output from 0 % to 100 %. Secondly, this signal is multiplied by afactor equal to 10 and multiplied by the rated current and divided by 15. This createsa reference signal from 0 to 3.5 V. Thus, the output of the dimming sensor will be areference signal from 0 which refers to zero current and zero luminous output to 3.5 Vwhich refers to rated current multiplied by 10 and full luminous output.

3. Subtraction, controller, and driver

The first stage is a subtraction that subtracts the output of the current sensor, which is theaverage value of the actual current of the LED, from the output of the dimming sensor,which is the reference signal. The result of this subtraction will be the error signalmultiplied by 10. This signal goes to an analog Proportional–Integral (PI) controller,which is made by an Operational Amplifier (op-amp) using the LM358 IC. The outputgoes to a comparator to generate the PWM signal, which is made by the LM3524 IC.The PWM signal goes to a decoupling driver using the HCPL-3120 optocoupler. Inorder to insulate the power stage from the control totally, the optocoupler is used; it ispowered by a separate and isolated power supply.

4. Dimming generator

The dimming signal is generated from the comparison of a dimming reference with asawtooth waveform. As previously mentioned the dimming frequency is 25 kHz, 12.5kHz, 5 kHz, it is clear that all of them are dividers of the main switching frequency.As this sawtooth is generated from dividing the main dimming switching by fouror eight or 20 using the JK Flip-Flop IC 4027. Furthermore, this signal goes to anintegrator circuit using the operational amplifier in the LM358 IC. The reason for using


a frequency divider from the main switching frequency is to avoid extra noise and toensure that both frequencies will be synchronized.

VsenseVs

LM358

8k21k

3k9

10n

Current Sensor, H

LM358

10k10k

10k

Subtractor

10k

V ref

Vsense

Verror

Vref

LM358

20k10k

Controller, C

100n

VerrorLM3524

PWM Generator

15

19 V

Vgate

Main Switch Driver

1k

HCPL-3120

Vdim-ref

10

10

Dd

Dd1 -

TL082

Dimming Generation

DdLM358

3k9

1n

Davg

Dimming Sensor, GD

61k2

12k

Vref

Reference Generator, Gg

15 V

15 V

15 V

Fig. 4.20 The Full IBFBC control scheme.

Finally, the prototype is designed and implemented as shown in Fig. 4.21.

EMI filter

The IBFC The output Buck converter

PWM generatorFilter and controller

Dimming generator

Fig. 4.21 IBFBC laboratory prototype board.


4.3.4 Experimental Results

The experimental results aim to prove practically what is previously demonstrated throughtheory and mathematical models. Initially, the converter is tested at different dimming dutyratios. Fig. 4.22 shows the dimming gate signal and the LED current at each dimming value.The driver is tested to show its operation capability by showing the lowest duty ratio at whichthe converter can operate, as well as the highest. Fig. 4.22 plot (A) shows the case of adimming duty ratio of 2.5 %, which could be considered small duty; not all the LED drivershave the ability to work at this small dimming. Also, it shows the ability to work at all thedimming ratios and even high ones like 90 %, as shown in Fig. 4.22 plot (H). Commentingon the shape of the LED current shown in Fig. 4.22, it is quite good as the DC value ofthe current is constant. Moreover, the turn-off and on processes are quite fast and without

(A) (B) (C)

(D) (E) (F)

(G) (H) (I)

Current

Gate Signal

5 V

/ d

iv2

00

mA

/ d

iv

20 us / div

Fig. 4.22 Gate signal (Upper trace), and lamp current (Lower trace) in nine different dimmingratios. (A) 2.5 % luminous output (100:2.5), (B) 5 % luminous output (100:5), (C) 10 %luminous output (100:10), (D) 25 % luminous output (100:25), (E) 30 % luminous output(100:30), (F) 50 % luminous output (100:50), (G) 75 % luminous output (100:75), (H) 90 %luminous output (100:90), (I) 100 % luminous output (1:1).


any oscillations. The DC value of the current is fixed owing to the second path that theoutput buck converter provides for the current. Thus, the voltage across the capacitor is notexperiencing an increase in the voltage while the LED are turned-off.

Fig. 4.23 shows both measured and calculated values of the bulk capacitor voltage. Themeasurements show a slightly higher voltage value of 10 to 15 Volts. The reason is thatthe calculation is for an ideal system. The calculation is repeated taking into account theinductors’ copper losses, the transformer copper losses, and the conduction losses of alldiodes and main switch. Taking into account these losses, the calculated curve is closer tothe measured curve, which proves that the reason for the difference is the converter losses.However, the main behavior is the same and the increase in the measured voltage over thebulk capacitor is still in the range of the capacitor specifications.

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1100

110

120

130

140

150

160

170

180

Dimming Duty

Bul

k C

apac

itor

Vol

tage

VB (

Vol

ts)

Calculated Bulk Capacitor Voltage without lossesCalculated Bulk Capacitor Voltage with lossesMeasured Bulk Capacitor Voltage

Fig. 4.23 Measured and calculated values of the Bulk capacitor voltage, with respect todifferent dimming ratios.

Secondly, the efficiency of the converter needs to be illustrated. Fig. 4.24 shows theefficiency of the converter at different duty ratios, as well as the efficiency of the HSPdimming technique using the parallel resistance branch previously presented. The converterhas an efficiency of 86.17 % at full-power operation, which is acceptable for this type of


converters containing PFC stage. As can be seen, as the dimming duty ratio decreases, theefficiency decreases. Thus, the lowest efficiency will be 50.65 % at dimming ratio equal to 5%. Compared to the efficiency of the HSP passive dimming, it is clear that both convertersstart from the same efficiency level at full power. However, the results achieved by the IBFBCare far better at low dimming duty ratios. Moreover, the IBFBC even shows a better operatingperformance. As the variation in the LED current of the IBFBC is lower compared to theHSP dimming technique using resistance.

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 10

10

20

30

40

50

60

70

80

90

Dimming Duty Ratio

Eff

icie

ncy

(%)

Resistance Value 452 ΩResistance Value 990 ΩResistance Value 2.31 kΩIBFBC Efficiency

Fig. 4.24 Efficiency of the IBFBC as well as the efficiency of the HSP dimming for threedifferent resistance values, 452 Ω, 990 Ω, and 2.31kΩ, with respect to dimming duty.

Furthermore, an additional advantage is shown by the IBFBC, it is the linear characteris-tics of the output power with respect to the dimming duty ratio. Thus, the output luminousflux with respect to the dimming ratio is linear as well. Fig. 4.25 shows the efficiency andthe output power of the IBFBC at different dimming ratios. Analyzing the data shown inFig. 4.25, it is found that the output power at this very low dimming duty ratio is very low


and equal to 4 W, which is the reason for the low efficiency at these points. As the lowestefficiency which is equal to 50 % indicates just a loss of 4 W.

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 10

20

40

60

80

X: 0.05Y: 3.6

Out

put

Pow

er (

W)

Dimming duty0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

50

60

70

80

90

X: 0.05Y: 50.63

Eff

icie

ncy

(%)

EfficiencyOutput Power

Fig. 4.25 Output power and Efficiency with respect to dimming duty ratio.

A detailed analysis of the losses in all the components of the converter is done to estimatethe percentage of loss in each element. Fig. 4.26 shows the losses in all the componentsof the converter. As shown in Fig. 4.26, the additional buck converter is not affecting theefficiency too much, as the losses of the output buck converter represent only 14.65 % of thetotal losses. The losses are mainly concentrated in the main switch. However, the converteris operating in DCM, which ensures soft-switching during turn-on. According to the lossanalysis on the IBFC previously illustrated, the efficiency can be boosted, by the redesign ofthe converter and without any additional complication in the control circuit.


Bridg

eIn

duct

or

D_B

Switc

hing

Con

duct

ion

D_F

H

D_F

L

D_o

utO

utpu

t Buc

k

0

0.5

1

1.5

2

2.5

Pow

er L

osse

s (W

att)

Tran

sfor

mer

11.03%

14.65%

4.05%

5.97%

1.85%

17.18%

25.22%

3.22%

9.32%7.52%

Fig. 4.26 Breakdown of the converter losses.

4.4 Conclusion

This chapter presents a new HSP-PWM dimming technique, through passive and activetechniques. The passive technique is made by adding a resistive branch. While the activemethod is made through a new double integrated converter the IBFBC. The converter keepsall the advantages given by the IBFC; the high PF correction and the low current handled bythe main switch. The IBFBC ensures a constant output current regulation as well as high PFin all dimming ratios. The converter operates at very low dimming ratios reaching a dimmingratio of 2.5 % and even operates at a high dimming ratio that reaches 95 %. Moreover, theconverter shows a linear characteristic of the output power with respect to the dimming dutyratio. Thus, the output luminous flux and the light intensity with respect to the dimming ratiois linear as well. Finally, the proposed converter does not require any complex circuitry orany extra sensors than the normal IBFC, just an additional diode, an inductor, and a switch.

4.4 Conclusion 143

Furthermore, the technique was tested on the IBFC and shows promising results. Thus itcould be applied to any other topologies.

A universal input voltage, 50 Hz output 160 V, 100 W AC-DC converter operating at 100kHz is implemented in order to verify the active HSP-PWM technique. The practical resultsmatch all theoretical and mathematical analysis. Moreover, an efficiency range of 50 % to86 % corresponding to dimming duties of 5 % to 100 % is reached, where 5 % dimmingcorresponds to an output power of 4 W.

Chapter 5

Novel LED Driver Based on the FullyIntegrated Buck and Boost Converter


5.2 Derivation of the Proposed Integrated Buck Boost Converter . . . . . 147

5.3 Analysis of the Proposed Integrated Buck and Boost Converter . . . . 149

5.3.1 Operation Principles . . . . . . . . . . . . . . . . . . . . . . . . 149

5.3.2 Mathematical Analysis . . . . . . . . . . . . . . . . . . . . . . . 152

5.3.3 Magnetic Analysis . . . . . . . . . . . . . . . . . . . . . . . . . 154

5.3.4 Average Model . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

5.4 Design Procedure of the Laboratory Prototype . . . . . . . . . . . . . 159

5.5 Magnetic Simulation and Core Losses Estimation . . . . . . . . . . . 163

5.5.1 Magnetic Simulation . . . . . . . . . . . . . . . . . . . . . . . . 163

5.5.2 Core Losses Estimation . . . . . . . . . . . . . . . . . . . . . . 166


5.7 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181

146 Novel LED Driver Based on the Fully Integrated Buck and Boost Converter

5.1 Introduction

Power quality figures as PF and THD are overly important; however, power-density andefficiency have the same relevance and, in specific applications, even higher. The passivecomponents such as magnetic and capacitive elements are the bulkiest and lossy componentsin the converter. The two-stage converter has two inductive elements, which decrease bothefficiency and power density. A proposed solution is to integrate both inductive elements inone core. The integrated inductor has previously been proposed in the literature operating ascoupled inductors for multi-channel buck converter [163–168], multi-channel boost converter[169], and differential rectifier/inverter [170]. However, it has never been explored inintegrated converters.

In this chapter, the novel IBBC is proposed. It is a new high-efficient and high-powerdensity converter for LED drivers. The driver ensures high PF and low THD to be far belowthe limitation specified by IEC 61000-3-2 standard at all dimming range. The converter isconstructed by integrating a buck converter operating as a PFC stage with a boost converteroperating as a constant current source.

Furthermore, the proposed topology does not require any coupled inductors nor trans-formers, which means that a spike-less operation is ensured, as well as minimizing windinglosses. Additionally, the proposed technique avoids requiring any complex circuitry or anyadvanced sensors other than the normal ones used in dc-dc converters. Regarding the powercomponents, the proposed topology offers all these features by using only one controlledswitch, which additionally handles low current, as it handles the higher of the buck or boostcurrents but not the addition of both. Two extra diodes are added; however, these diodes arenot continuously conducting so the losses do not harm the converter efficiency.

For further increase of the power-density, a FIBBC is proposed to supply an LED luminaryload of 27W, providing high PF, low THD, low current ripple, high efficiency, and compactdesign. The first integration is made in the controlled switch, which is shared by both stages.The second integration is made in the magnetic components, as both inductors are sharingthe same core. Thus, the proposed converter only includes two capacitors, four diodes, oneground-referenced controlled switch, and one magnetic component, thus featuring affordablelow cost and good reliability.

5.2 Derivation of the Proposed Integrated Buck Boost Converter 147

5.2 Derivation of the Proposed Integrated Buck Boost Con-verter

As previously mentioned, the converter is operating as two buck and boost convertersoperating in cascaded mode. Fig. 5.1 (a) shows the electric diagram of the two convertersbefore integration.

The buck converter role is to operate as a PFC stage, so that it will be operating in DCMto behave as a resistive load at its input terminals. The boost converter role is to operate asa PC stage, in order to properly drive the LED. The benefits gained from this structure arethe following; the buck converter will ensure a high PF and low THD as long as the bulkcapacitor voltage is small enough; thus, having a boost converter at the output of the buckconverter guarantees that the bulk capacitor voltage will be lower than the output voltage.This converter has a double benefit of ensuring good PF and the usage of a low voltagecapacitor rating.

Moreover, to assure good efficiency, the boost converter can be designed to operate witha low input-output voltage ratio. The topology does not include any transformers, whichleads to a further increase of the efficiency, because winding losses and losses associatedwith leakage inductance are minimized and avoided, respectively.

The main disadvantage of this topology is the necessity of two switches, with two gatedriving circuits and two controllers.

The integration of the two converters was the only solution to keep the same operatingbehavior and features, simultaneously avoiding one of the two switches. Fig. 5.1 (b) shows theelectric diagram of the integration of the buck and boost converters, named as IBBC. The inputbuck converter is made up of the following components LBu, DB, DBu, CB, and M1, whilethe output boost converter is made up of the following components, LBo, DOut , DBo, CO,

and M1.For the sake of higher power density and efficiency, the FIBBC is proposed. Fig. 5.1 (c)

shows the electrical diagram and the magnetic structure of the FIBBC. In this case, LBu andLBo will share the same magnetic core, for higher power density. Moreover, the windingsare arranged to generate a reverse direction in the central arm, which in return decreases themagnetic losses and increases the efficiency. Fig. 5.1 shows the magnetic structure of thetwo inductors in a single core.


VOCOD2

D1

D3 D4M1

CB

LBu

Vg

IAC

DB

DOutLBo

M2

VOCO

D2D1

D3D4

M1

CB

LBu

Vg

IAC

DB

DOut

DBo DBu

LBo

VOCOD2

D1

D3 D4 M1

CB

LBu

Vg

IAC

DB

DOut

DBo DBu

LBo

(a)

(b)

(c)

Fig. 5.1 (a) electric diagram of a conventional cascade buck PFC and boost dc-dc LED driver,(b) electric diagram of the Integrated Buck and Boost Converter, and (c) electric diagram andthe magnetic structure of the Fully Integrated Buck and Boost Converter.

5.3 Analysis of the Proposed Integrated Buck and Boost Converter 149

5.3 Analysis of the Proposed Integrated Buck and BoostConverter

5.3.1 Operation Principles

Since the proposed converter is a single switch converter, there are only two main states,on-state, and off-state. However, the DCM operation of the buck and boost converters splitsthe off-state into three intervals. Thus, the converter will have four intervals in total, one forthe on state and three for the off state. Fig. 5.2, and Fig. 5.3 illustrate the equivalent circuits,and the main current waveforms within a high-frequency switching period, respectively.

In the following a concise explanation for each interval:

• Interval I

During this interval, the main switch M1 is in switched-on mode. While the switchis on, both converters are operating. Thus, a current iBu flows in the buck turn-onloop, coming from the AC grid going to the bulk capacitor, while energizing the buckinductance. Meanwhile, a current iBo flows in the boost turn-on loop, coming from thebulk capacitor, and energizing the boost inductor. The current is increasing linearly inboth inductors.

• Interval II

This interval starts with the turn-off of the main switch M1. During this interval,both inductors of buck and boost converters are de-energizing. The buck inductor isde-energizing sending the power to the bulk capacitor through the buck diode. Whilethe boost inductor is de-energizing delivering the power to the output.

• Interval III

Interval II ends and interval III starts when one of the two inductors current goes tozero, and its belonging inductor de-energize completely. Fig. 5.2 Interval III and Fig.5.3 right side shows the interval III for the case where the buck inductor current reacheszero, while, the boost inductor current is still conducting. While interval III in the caseof buck current is higher than the boost current is shown in Fig. 5.3 left side.

• Interval IV

Finally, interval IV represents the period where both inductors are fully discharged.However, concerning the current going to the LED, it is continuous due to the outputcapacitor presence.

150N

ovelLE

DD

riverBased

onthe

FullyIntegrated

Buck

andB

oostConverter

VOCO

D2D1

D3 D4

M1

CB

LBu

Vg

IAC

DB

DOut

DBo DBu

LBo

iBu iBo

iBu iBo-

iBoiBu-

(a) Interval Ⅰ : 0 < t < DTs

VOCOD2

D1

D3 D4

M1

CB

LBu

Vg

IAC

DB

DOut

DBo DBu

LBo

iBu iBo

(b) Interval Ⅱ : DTs < t < t1

VOCOD2

D1

D3 D4

M 1

CB

LBu

Vg

IAC

DB

DOut

DBo

DBu

LBo

iBo

(c) Interval Ⅲ : t1 < t < t2

VOCO

D2D1

D3D4

M1

CB

LBu

Vg

IAC

DB

DOut

DBo DBu

LBo

(d) Interval Ⅳ : t2 < t < Ts

Fig. 5.2 Equivalent circuits of the IBBC operating in DCM.


t

t

t

t

iM

iBu

i

iD

I II III IV

DTs Tst1 t2

DT(v -V )g

LBu

DTsVB

LBo

Bu

Bo

iDBo

iBuiBo-

t

t

t

t

i

iBu

i

iD

I II III IV

DTs Tst1 t2

DTsVB

LBo

Bu

Bo

iDBo

iBuiBo-

iBu iBo

(a) i > i (b) i < iBu Bo BoBu

B

DT(v -V )g

LBu

B s

s

1M1

Fig. 5.3 Main current waveforms of the IBBC operating in DCM, within a high-frequencyswitching period; (a) when iBu > iBo around the peak line voltage, (b) when iBu < iBo for lowvalues of the line voltage.

It must be noted that the conduction of diodes DBu and DBo will be determined accordingto the value of the buck current and the boost current. If the buck current iBu is higher thanthe boost current iBo, then DBu will conduct the difference between the two currents, whileDBo will not conduct, and the current passing through M1 will be iBu as shown in Fig. 5.3left side. In the case that iBo is higher than iBu, the reverse will occur; DBo will conduct thedifference between the two currents, while DBu will not conduct, and the current passingthrough M1 will be iBo as shown in Fig. 5.3 right side.

As illustrated in the operational principle of the IBBC, the converter shows great advan-tages; the main switch handles less current, as it conducts only the higher between the buckcurrent and the boost current, but not the addition of both. The losses are thus distributedamong controlled switch and diodes, which is good because diodes behave as better switchesthan MOSFETs. Furthermore, the two diodes are not conducting continuously; they areoperating in a complementary mode so that only one of them conducts at a time. Moreover,


it conducts the difference between the two converter currents not even the full magnitude ofone of them.

5.3.2 Mathematical Analysis

In the following, the analysis of the currents in the converter is performed, to obtain theimportant design equations, when both stages buck and boost operate in DCM. For the sake ofsimplicity, the analysis will consider the converter in its ideal state. An ideally sinusoidal linevoltage waveform will be considered as input voltage, expressed as vg (t) =Vg sin(2π flt).

The peak value of the buck current can be expressed as follows:

iBu peak =D

fsLBu

(vACBridge −VB

)=

D(Vg |sin(2π flt)|−VB)

fsLBu

(5.1)

Concerning the boost current, it can be expressed as the following:

IBo peak =VBDfsLBo

(5.2)

Regarding the operation of the converter, full DCM operation has to be guaranteed.Hence, a study of the boundaries is made to design the inductive elements. Thus, both buckand boost converters will behave as a resistive load at their inputs. The equivalent resistancevalue of the buck converter can be expressed as the following:

Rg =2LBu fs

D2(5.3)

While the value of the boost input resistance is given by the following expression:

RBo =2LBo fs

D2(

1+ VBVO−VB

) (5.4)

As previously explained and illustrated the mean input power of buck converter operatingin DCM can be calculated as shown in the following equation:


Pg = IBVB

=VgVBD2

2LBu fs

[1

2m

(1− 2

πsin−1 m

)−

√1−m2

π

](5.5)

Concerning the boost power delivered to the output, it can be expressed as follows:

PBo =V 2

BRBo

=D2V 2

B

(1+ VB

VO−VB

)2LBo fs

(5.6)

Regarding the output power, it can be found using the equivalent resistance of the LED,as follows:

POut =V 2

OR

(5.7)

Concerning the voltage ratio of the IBBC, it can be split into two parts. First, the voltageratio of the buck converter is given by;

VB

Vg=

RBo

Rg

[1

2m

(1− 2

πsin−1 m

)−

√1−m2

π

](5.8)

Secondly, the voltage ratio for the boost converter is given by the following expression:

Vo

VB=

1+√

1+ 4D2

Kbo

2(5.9)

where Kbo is given by the following expression:

Kbo =2Lbo fs

R(5.10)


Combining both (5.8) and (5.9) with substituting the value of the boost equivalent resis-tance in (5.4), an expression for the voltage ratio of the IBBC operating as DC-DC converteris found:

Vo

Vg=

2R

Rg

(1+√

1+ 4D2

Kbo

) [ 12m

(1− 2

πsin−1 m

)−

√1−m2

π

](5.11)

5.3.3 Magnetic Analysis

In this section, the magnetic analysis for the conventional two standalone cores and theintegrated inductors is made to study if there will be any change in the operation, and for abetter comparison between the two techniques.

Fig. 5.4 (a) shows the two equivalent magnetic circuits in the case of two standaloneinductors; the one on the left corresponds to the buck inductor and the one on the rightcorresponds to the boost inductor. The equivalent magnetic circuit of the integrated inductoris shown in Fig. 5.4 (b). The right outer arm corresponds to the buck inductor, and the leftouter arm corresponds to the boost inductor.

The integrated inductor is proposed using a PQ core type. However, the analysis is alsovalid for EE cores as well as EFD cores, using the geometric parameters of the correspondingcore. The design is made so that the flux from one inductor does not interact and affectthe operation of the other inductor. For doing that, the design of the integrated inductor ismade by putting the gaps in the outer arms, so that the reluctances of the outer arms aresignificantly higher than the reluctance of the center arm. Thus, the flux generated by eachinductor goes to the center arm so that they do not affect each other.

Simulation is made using the magnetic circuit presented in Fig. 5.4 (b). In order toverify whether there is a magnetic interference between both inductors. The simulation isrun one time removing the source representing the Magneto-Motive Force (MMF) of thebuck inductor and measure the flux in each leg of the core, and another time while removingthe source representing the MMF of the boost inductor and also measuring the flux in eachleg of the core. Fig. 5.5 shows the flux in the three arms of the integrated core in the caseof deactivating the MMF of the buck inductor and testing only the sharing percentages ofthe boost inductor generated flux. As shown in the figure, 99.5 % of the flux goes throughthe center arm. While almost a negligible part of the flux goes to the arm where the buckinductor excites.


Thus, during this study, it will be approximated that there is no interference between thetwo inductors and none of the previously demonstrated equations and operation of the IBBCwill change in the case of the FIBBC.

NBu

iBu.

R

RC

R R

Φ

Φ Φ

NBo

iBo

.

R

R

R R

Φ

Φ Φ

N i.

R

R

R

Φ

Φ

N i.

R

R

Φ

(a)

(b)

Bu

GBu

OBuOBu OBo OBo

C Bo

GBo

IC

IBu

IBuG I

BoG

IBo

IBu IBu IBoIBo

OBu OBu

CBu

OBo OBo

C Bo

IBu IBu

I C

Fig. 5.4 Equivalent magnetic circuits of the integrated inductors; (a) left side the buck inductor,while right side the boost inductor, (b) the integrated inductor buck and boost.


0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 0.18 0.20

1

2

3

4

5

6

7

8

9

10

Flu

x (

w

b )

Time ( msec )

Flux of the Boost arm

Flux in the central arm

Flux in the Buck arm

0.102 0.1021 0.1022 0.1023 0.1024 0.10257

7.02

7.04

7.06

7.08

7.1 X: 0.1022

Y: 7.086

X: 0.1022

Y: 7.057

0.102 0.1021 0.1022 0.1023 0.1024 0.10250.027

0.0275

0.028

0.0285

0.029

X: 0.1022

Y: 0.02844

Fig. 5.5 Flux in the integrated core when deactivating buck MMF. Flux in the boost arm (inblue), flux in the central arm (in red), and flux in the buck arm (in green).

In order to solve the equivalent circuits presented in Fig. 5.4, the following parametersare found. The flux generated by the winding is given by the following expression:

Φ =Nwiw

Re(5.12)

The reluctance of the core is given by the following expression;

Re =l

µµoA(5.13)

To estimate the number of turns of the inductors the following expression is used:


Lw =N2

wRe

(5.14)

The reluctance presented in (5.13) is the total reluctance of the flux path. Applying it tothe magnetic circuit presented in Fig. 5.4 (a) for the buck inductor, the total reluctance isfound by the following expression:

ReBu = RCBu +RGBu +(ROBu//ROBu)

= RCBu +RGBu +ROBu

2

(5.15)

As an approximation, the reluctance of the core is neglected compared to the air gapreluctance. Thus, the number of turns of the buck inductor is found by applying the followingexpression:

NBu =√

LBuRGBu (5.16)

Following the same procedure, the number of turns of the boost inductor is found by thefollowing expression:

NBo =√

LBoRGBo (5.17)

Concerning the integrated core, the magnetic circuit will be split into two parts. Further-more, the outer arm path is neglected since 99.5 % of the flux goes to the center arm. Thus,the total reluctance of the flux path of the buck inductor, in the case of the integrated core, isgiven by the following expression:

ReIBu= RIC +RIBu +RIGBu

(5.18)

Applying the same approximation, the reluctance of the core is neglected compared tothe reluctance of the air gap. Thus, the number of turns of the buck and boost inductors inthe integrated core is given by the following expressions, respectively:


NIBu =√

LBuRIGBu(5.19)

NIBo =√

LBoRIGBo(5.20)

Concerning the values of the inductors, the selection is made under one constraint. As thevalue of the inductance increases the peak value of the current presented in (5.1), and (5.2)decrease, in return, a reduced devices rating is achieved. However, the increase is limited bythe DCM mode of operation. As for a very high inductance value, the converter may operatein CCM. The main duty of the buck converter is to enhance the PF, thus, a DCM is required.Concerning the boost stage, it can operate in both CCM or DCM.

To perfectly choose an operation mode for the boost converter, a simulation has been madeto check with numbers the effect of changing from DCM to CCM. Firstly, to keep the samevalue of the buck inductance, a fifteen times higher boost inductance (1 mH instead of 70 µH)is required to operate in CCM. Secondly, when it is operated in CCM, the low-frequency bulkcapacitor ripple is transferred to the output voltage, which is not recommended for this typeof application. As the intensity of the light is directly proportional to the LED current and,in return, a ripple in the LED current will cause flicker problems. For the same capacitors´values, the current ripple increased from 6 % in DCM to 17 % in CCM. Thus, a bulk capacitorof 2200 µF is needed instead of the 470 µF to keep the same ripple level recommended forthis application.

One advantage shown by the CCM, in both DCM and CCM, the average current in theinductor equals the output current equals 0.575 A. However, the peak current decreases from2 A in the DCM to 1.5 A in the CCM.

Accordingly, to the previous analyses, the DCM is much preferred.Thus, the choice of the inductances’ values will be as the following: firstly, the buck

inductance is chosen to have a BCM at the peak value of the input voltage. Later, the criticalvalue of the boost converter is given by the following expression:

LBocrit =RD(1−D)2

2 fs(5.21)

5.4 Design Procedure of the Laboratory Prototype 159

5.3.4 Average Model

For better illustration of the converter operation, an average model is developed as shownin Fig. 5.6. The average model is useful in terms of understanding the power flow in theconverter. As well as it is a faster way to check, by simulation, the magnitude of the voltagesand currents in all elements without considering the high-frequency switching effect. Thevalues of the buck and boost resistances used in the model are given by (5.3) and (5.4),respectively.

VO

COVB

CB RBo IOIB

R g

VB

Vg

Input Buck Boost Output LED

R

IB

Fig. 5.6 Average model of the proposed FIBBC LED driver.

5.4 Design Procedure of the Laboratory Prototype

Using the previously determined equations and the average model illustrated in Fig. 5.6,two designs are made to supply an LED luminaire of 46 V/ 575 mA, resulting in 26.5 W ofoutput power. The line voltage is 110 Vrms and the line frequency is 60 Hz. The first step inthe design is to select the values of the inductors using the boundary conditions. The valuesof the buck inductance and the boost inductance are 125µH and 70µH, respectively. Later,two designs are made for the inductors.

The first design is made for the case of the two standalone cores for the two inductors.The number of turns is calculated so that the magnetic loss is designed to be equal to the


copper losses in the windings. Thus, the number of turns selected for the buck and boostinductances are 20 turns and 15 turns respectively. Using these values and the values of thecore dimensions in the flux and reluctance equation, the equivalent circuit parameters in Fig.5.4 (a) are found. The chosen core for both buck and boost inductors is the PQ26/20.

To have a fair comparison between both standalone and integrated core, the boost inductornumber of turns in the integrated core is designed to give the same flux density on the outerarm equal to the flux density of the standalone boost inductor.

Using the following equation, the maximum value of the flux density in the standaloneboost inductor is calculated:

NBo =LBo ∗ Imax

Ae ∗Bmax(5.22)

Where, LBo is the boost inductance and equals 70 µH, Imax is the maximum current inthe boost inductor got from the simulation equals 2 A, Ae is the effective area of the centralarm found in the datasheet of the PQ26/20 equals 112mm2. Thus, the maximum value of theflux in the individual boost inductor Bmax is found to be equal to 82 mT.

Later, after having the value of the maximum flux density in the standalone core, thesame procedure is repeated for the integrated core. Thus, substituting in (5.22), but withdifferent effective cross-section area. The chosen core for the integrated magnetics case isthe PQ30/20, its outer arm cross-section equals 88mm2. The number of turns is calculatedto be equal to 20.32 turns. Thus, the chosen number of turns for the boost inductor in theintegrated core is 20 turns.

Concerning the buck number of turns, it is calculated to have a flux density component atswitching frequency equal to the boost flux density at switching frequency. So, (5.22) is usedwith different inductance value 125 µH, the value of the buck inductor current component atswitching frequency 0.891A, and the boost flux density component at the switching frequencyequal to 34.27mT . Thus, the number of turns found to be equal to 38.68. A value of 40 turnsis selected. Using these values and the values of the integrated core dimensions in the fluxand reluctance equations, the equivalent circuit parameters in Fig. 5.4 (b) are found.

The volume of the standalone core PQ26/20 equals 10145mm3, while the volume of theintegrated core PQ32/20 equals 14467mm3. Thus, the integrated design shows a reduction inthe size of the magnetic component by 28.5 %. Table 5.1 shows the values of the prototypecomponents.

5.4 Design Procedure of the Laboratory Prototype 161

Table 5.1 Components of the Laboratory Prototype of the Fully Integrated Buck and BoostConverter

COMPONENTS Value


Output voltage 46 V




Buck inductance standalonePQ26/20/PC44,

LBu = 125 µH, NBu = 20, G = 0.5 mm

Boost inductance standalone PQ26/20/PC44, LBo = 70 µH, NBo = 15, G = 0.5 mm

Integrated corePQ32/20/PC44, LBu = 125 µH, NIBu = 40, LBo =

70 µH, NIBo = 20, GIBu = 1 mm, GIBo = 0.5 mm

Bridge Diodes DB156S

DB&DFL&DAUX MURS260T3G

DOUT STPS3150

CB 470µF/50V

CO 470µF/63V


A great feature shown by the FIBBC is the low voltage of the bulk capacitor. The presenceof the Boost at the output of the integrated converter ensures a bulk capacitor voltage lowerthan the output voltage. Compared to an integrated boost and buck converter will have thehighest bulk capacitor voltage, as it must be higher than both input and output voltage. Inother integrated converters, like integrated buck flyback or double integrated buck-boost, itdepends on the design and it could be higher or lower. However, the proposed integratedbuck and boost converter ensures a bulk capacitor voltage lower than both input and outputvoltages. This feature increases the power density of the FIBBC, as the used capacitor willbe much smaller in size compared to any other technique.

Fig. 5.7 shows the detailed schematic diagram of the laboratory prototype, in both aspectspower and control. The control is made using the LD7838 IC. The operation of this IC canbe described as the following:


• It has an HV start-up pin that is connected through a high resistance to the positiveterminal of the bridge connected to the AC input. The IC is designed to operate undera universal voltage input range.

• As a standalone driver, the power of the IC should come from the driver itself. The ICis powered from the auxiliary winding coupled with the buck inductor.

• The closed-loop feedback is coming from the output of the optocoupler PC817 IC. Thereference is set by setting VOV P trigger level, by selecting the values of the voltagedivider of ZCS resistances following the equation below, found in the datasheet of thecontrol IC:

VOV P ∗NVCC

Ns∗ RZ2

RZ1 +RZ2= 3.5 V (5.23)

• In this case, RZ1 is not added to the design, which means that a resistive value of zerois chosen for this resistance.

• Finally, the control IC generates the control signal to the MOSFET. With typical125 mA / − 500 mA driving capability, an output stage of a Complementary MetalOxide Semiconductor (CMOS) buffer is incorporated to drive a power MOSFETdirectly.

• Moreover, protection is made by limiting the maximum peak value of the current in theMOSFET. Resistance is added in series to the switch and a signal from this resistanceis going to the control IC to the CS pin. The voltage of this pin cannot exceed 0.85V ,thus by selecting the value of this resistance the peak value is fixed, following theequation below:

IPeak (max) =0.85 V

Rs(5.24)

Finally, the controller IC shows great advantages such as constant output current regula-tion and dimming capability.

5.5 Magnetic Simulation and Core Losses Estimation 163

Vg

VOCO

DODB

M1

CB

LBu

Vg

VB

RCS

Gate

HV

CS

SPA07N60C3

DB156S

MURS260T3G

STPS3150

470 µF/ 50 V470 µF/ 50 V

LEMI

CEMI

125 µH

DBo

MURS260T3G DBu

MURS260T3G

70 µH LBo

LD7838LD7838

ZCD

10 kΩ

220 nF

10 nF

COMP

510 Ω

PC817

Vo

Vo

18 kΩ

2 kΩ

82 kΩ

4.7 kΩ

TL431

VCC

CS

0.1 µF

4.7 kΩ 4.7 kΩ

HV

VCC

GATE15 Ω

22 µF

51 Ω

1 µF

100 kΩ

4.7 uF

1 uF

1.03 kΩ

COMP

ZCDVCC1

10 kΩVCC1

Integrated

Magnetics

Fig. 5.7 Schematic diagram of the laboratory prototype.

5.5 Magnetic Simulation and Core Losses Estimation

5.5.1 Magnetic Simulation

As aforementioned, the flux of both inductors goes to the center arm of the integrated inductorcore. The orientation of the inductors is made so that both fluxes are in the opposite directionas shown in the magnetic structure illustrated in Fig. 5.1 (c).

Fig. 5.8 shows the result of the simulation carried out using the circuits presented in Fig.5.4 together with the electrical representation of the full converter to measure the currentthrough the inductors.


Figures 5.8 (a) and 5.8 (b) show the magnetic flux density of the boost inductor, in thecase of standalone, and integrated inductor respectively. As shown in Figures 5.8 (a) and Fig.5.8 (b), the flux is similar in both cases. Moreover, the design is made in order to have a peakvalue as close as possible for a fair comparison between both techniques. Fig. 5.8 (c) showsthe magnetic flux density of the boost arm in the integrated inductor in the frequency domain.It is composed mainly of two components, the DC component and another component at theswitching frequency. The spectrum also shows some small components; one at double theline frequency, and two at the switching frequency plus and minus double the line frequency.Those are representing the low-frequency ripple.

Figures 5.8 (d) and 5.8 (e) show the magnetic flux density of the buck inductor in the caseof standalone and integrated inductor. As can be seen, the integrated core and separate coresshow similar behavior in the flux shape. However, the flux of the integrated core is lowerthan the separate cores, since it is designed to cancel the boost flux. Fig. 5.8 (f) shows themagnetic flux density of the buck arm in the integrated inductor in the frequency domain.In the buck inductor, it has the same components as the boost inductor at DC and at theswitching frequency. However, the components at the line frequency are higher due to theline frequency effect of the buck converter.

Finally, Figures 5.8 (g) and Fig 5.8 (h) show the magnetic flux density in the center armin the integrated inductor. As shown in Figures 5.8 (g) and Fig 5.8 (h), the flux density inthe center arm is much lower than the flux density in both cases the buck and boost arms,due to the opposite flux direction. Fig. 5.8 (i) shows the magnetic flux density in the centerarm of the integrated inductor in the frequency domain. In order to reduce magnetic losses,the design of the integrated inductor is made so that the buck and boost components at theswitching frequency cancel each other.

Fig. 5.8 (i) shows that the center arm does not have any component at the DC andswitching frequency. Unfortunately, the boost flux is not able to cancel the buck flux atdouble the line frequency; however, it decreases it.

As a final comment, the previously design magnetic constraints are perfectly made, as:

• The magnitude of the flux density in the boost integrated core is equal to the magnitudeof the flux of the boost in the standalone core.

• The magnitude of the flux density component at the switching frequency of the buck isequal to the magnitude of the flux density component at the switching frequency of theboost. Moreover, both fluxes in the central arm of the integrated core are in reversedirection. Thus, the central arm flux density component at the switching frequency isalmost zero.

5.5M

agneticSim

ulationand

Core

Losses

Estim

ation165

0

50

100

150

200

250F

lux

Den

sity

(m

T)

(a)

Flux density of the Boost inductor (Standalone)

Flux density of the Boost (Integrated Inductor)

0

50

100

150

200

250

(b)

Flux density of the Boost inductor (Standalone)


0

10

20

30

40

50

(c)

(c)


0

50

100

150

200

250

Flu

x D

ensi

ty (

mT

)

(d)

Flux density of the Buck inductor (Standalone)

Flux density of the Buck (Integrated Inductor)

0

50

100

150

200

250

(e)

Flux density of the Buck inductor (Standalone)


0

10

20

30

40

50

(f)

(f)


0 5 10 15 20 25-50

0

50

100

150

200

Flu

x D

ensi

ty (

mT

)

Time (mSec)

(g)

Flux density in center arm (Integrated Inductor)

12.45 12.475 12.5 12.525 12.55-50

0

50

100

150

200

Time (mSec)

(h)


0

10

20

30

40

50

Frequency (Hz)

0 120

(i)

39880 40000 40120

(i)


Fig. 5.8 The magnetic flux density in different part of the core in both cases separate inductors and integrated inductors, in time andfrequency domains.


5.5.2 Core Losses Estimation

The integration of the magnetics will enhance the power density of the converter. Concerningthe efficiency, the enhancement is not guaranteed. Thus, an estimation for the core losses inthe case of the standalone cores and integrated core in both the same and the reverse directionof the flux in the center arm. The losses are estimated using the per volume losses at eachfrequency with respect to the flux density data presented in the core datasheet [171, 172]. Inthe following are the procedures taken to estimate the core losses.

• Using the magnetic model presented in Fig. 5.4 for the inductors in both casesstandalone and integrated core, the flux density at each part of the core is found asshown in Fig. 5.8.

• The data presented in the datasheet of the per volume losses is for sine wave data. Thus,the waveforms of the flux density are analyzed using the Fast Fourier Transform (FFT)technique to find the sine component at each frequency.

• There is usually a main component at the switching frequency and other componentsaround it at the switching frequency plus and minus multiples of the double of the linefrequency. In this analysis, all these components will be added and consider to be atthe switching frequency.

• The same occurs at multiples of the switching frequency, in this analysis, up to thethird multiple is considered.

• Using the flux density magnitude at each frequency and the data of the per volumelosses, an estimation of the per volume losses value at each part of the converter isfound.

• Multiplying the value of the losses per volume by the volume of each part, an estimationfor the losses is found.

Fig. 5.9 shows the data found by the core losses analysis estimation. As shown in Fig.5.9, the core losses decrease by 1.17 %, due to the slight decrease in the flux density and thevolume reduction, going from the two standalone cores to the integrated core (same direction).Furthermore, going for the reverse direction in the center arm an additional improvement inthe core losses is achieved.

5.5M

agneticSim

ulationand

Core

Losses

Estim

ation167

LBo

LBu L

Integrated core same direction

Volume (mm )Flux density component at 40 kHz (mT)Flux density component at 80 kHz (mT)Flux density component at 120 kHz (mT)Estimated core losses per volume (kW/m )3

3490113.3246.5825.74

700.244Estimated core losses (W)

Estimated Total losses (W) 0.455

317081.15533.25218.179

500.159

3 349048.99

19.92410.617

170.06

LBuLBo

Integrated core reverse direction

3490113.3246.5825.74

650.244

0.317

317032.16513.328

7.564

0.013

349048.9919.92410.617

170.06

LBu

Buck separate core

Volume (mm )Flux density component at 40 kHz (mT)Flux density component at 80 kHz (mT)Flux density component at 120 kHz (mT)Estimated core losses per volume (kW/m )3

2300134.6

53.23729.74

950.219Estimated core losses (W)

Estimated Total losses (W) 0.659

2600127.5350.6728.06

850.221

3 2300134.6

53.23729.74

950.219

Boost separate core

230049.14419.41

1117

0.039

0.117

260046.8518.659.8815

0.039

230049.14419.41

1117

0.039

0.776 W (2.92 % of LED power)

0.463 W (1.75 % of LED power) 0.317 W (1.19 % of LED power)

Bo

Fig. 5.9 Core losses estimation for the standalone cores, the integrated core in same and reverse direction of the flux in the center arm.



The line voltage, as well as the current waveform, are shown in Fig. 5.10 of the IBBC. Asshown in this figure, the current waveform is almost a pure sinusoidal waveform, whichillustrates how the proposed technique ensures that the PF and the THD will be in their bestconditions. Analyzing the input current waveform, the PF is 0.994 and the THD is 10 %.Thus, the FIBBC shows a better PF and THD compared to the IBBC. The efficiency is foundto be 90.5 %, which is a high-efficiency value considering that it is a low power applicationof 26.5 W. Also, in integrated converters, it is difficult to obtain efficiencies higher than 90%. It seems that the fully integrated converter shows higher efficiency than the conventionalintegrated converter.

5 ms/div200 mA/div50 V/div10 V/div

Fig. 5.10 Input current in yellow, and input sinusoidal voltage in green and bulk voltage inred, for the IBBC.

The line voltage, as well as the current waveform, are shown in Fig. 5.11 of the FIBBC.As shown in this figure, the current waveform is nearly the same as the current shown by theIBBC. Thus, the proposed technique ensures that the PF and the THD will be in their best


conditions, the PF is 0.994 and the THD is 10 %. The efficiency of the FIBBC is even higherthan the efficiency shown by the IBBC, if is equal to be 92.62 %.

200 mA/div50 V/div

5 ms/div

Fig. 5.11 Input current in green, and input sinusoidal voltage in purple, for the FIBBC.

Fig. 5.12 shows the bulk capacitor voltage, the output voltage, and the output current.As can be seen, the current is controlled at the desired value, thus, demonstrating thegood operation of the converter. The low-frequency ripple of the output current is in therange of 6 % of the rated current, which means that the converter fulfills the IEEE flickerrecommendation.



Fig. 5.12 Bulk voltage (red), output voltage (green), and output current (yellow), steady stateoperation.

Fig. 5.13 shows the output voltage and current, and the bulk voltage at start-up. As canbe seen in the figure, the control is perfectly working as voltage and currents are reachingthe desired values of 46 V and 0.575 A. Moreover, the converter shows a smooth and faststart-up process.

Fig. 5.14 shows the voltage across the MOSFET switch (top), and the current through it(bottom). As shown in the figure the voltage across the switch is relatively low compared toother integrated converters, which explains the high efficiency of this converter. As can beseen, the voltage across the switch shows a resonance interval at the end of the period, whichis due to the no conduction interval of the DCM operation of the converter. In this case, thecurrent passing through the switch is the buck current as it is higher than the boost current.


Off-State Start-Up Steady-State

Bulk voltage

Output voltage

Output Current


Fig. 5.13 Bulk voltage (red), output voltage (green), and output current (yellow), start-upoperation.

10 µs/div2 A/div100 V/div

Fig. 5.14 The voltage across the MOSFET switch (top), and the current through it (bottom).


Fig. 5.15 shows the two inductors currents. As shown in the figure, the boost inductorcurrent is operating in BCM, which proves the accuracy of the equation (5.21) used in thedesign. Moreover, the buck inductor current, at the peak voltage value, is not entering CCMoperation; thus, confirming that it is well designed. Furthermore, the peak current value ofthe buck and boost inductors are in the designed values, 4 A and 2 A respectively.

10 µs/div2 A/div2 A/div

Fig. 5.15 The buck inductor current (top), and the boost inductor current ( bottom).

Fig. 5.16 shows the converter operating at high input voltage to prove the universaloperation. It is operating with an input voltage of 220 V and rated power. The converteris perfectly operating, with even higher efficiency equal to 93.5 %. One drawback is thedistortion of the current waveform, as the EMI filter is designed for the 110 V operation.However, a great benefit shown by the converter is that the bus capacitor voltage will notincrease too much, as it should be always below the output voltage. Thus, the PF is decreasingdue to the distortion but not so much as the ratio between the bus capacitor voltage and theinput voltage decreases. The PF is found to be 0.98 with a THD equal to 13 %.



Fig. 5.16 Input voltage (blue), bulk voltage (green), and input current (yellow).

To prove the advantage shown by the converter, which is the small increase of the bulkcapacitor voltage all over the universal input voltage range, Fig. 5.17 is presented. Fig.5.17 shows the bulk capacitor voltage with respect to the input voltage, mathematicallyand with experimental results. As shown in the figure the practical results are matchingthe mathematical once, which proves the accuracy of the illustrated operation equations.Furthermore, the figure proves the stated advantage, as, by an increase of 150 V in the inputvoltage, the bulk capacitor voltage increases only 10 V.

Fig. 5.18 shows the PF of the FIBBC with respect to the dimming ratio. The useddimming in this technique is the analog dimming, by changing the reference of the outputcurrent value. As can be seen, the PF is above 0.99 up to 70 % of rated power. Moreover,the PF is above 0.9 for a dimming ratio equal to 20 % of the rated power, which is equal toalmost 5 W.


90 100 110 120 130 140 150 160 170 180 190 200 210 220 230 24030

32

34

36

38

40

42

44B

ulk

ca

pa

cito

r v

olt

ag

e (V

olt

s)

Input Voltage RMS (Volts)

Bulk capacitor voltage calculation results

Bulk capacitor voltage experimental results

Fig. 5.17 Bulk capacitor voltage with respect to input voltage, by calculations (blue), andfrom experimental results (red).

10 20 30 40 50 60 70 80 90 1000.8

0.82

0.84

0.86

0.88

0.9

0.92

0.94

0.96

0.98

1

Po

wer

Fa

cto

r

LED Power (%)

Power Factor of the FIBBC

Fig. 5.18 Power factor of the FIBBC concerning the dimming ratio.


Fig. 5.19 shows the efficiency of the IBBC and FIBBC with the central arm flux in thesame and reverse direction, with respect to the LED power dimming ratio. As can be seen,the efficiency is improved going from the IBBC to the FIBBC, even with the central fluxis in the same direction, and achieve further improvement with the reverse flux direction.The reason for the efficiency improvement of the FIBBC is the less flux density included inthe core, and the effective volume decrease which in return decreases the magnetic losses.Integrating the two magnetic elements does not guarantee an efficiency improvement. As by[173] the integration of the two inductors decreases the efficiency. The claim of integratingthe inductors will increase or decrease the efficiency cannot be generalized, it depends mostlyon the application and the design. However, what can be generalized is size reduction.Concerning the specific presented application, both size reduction and efficiency increasewere achieved. Furthermore, by reversing the polarity of the boost inductor to have the fluxof the boost in the center arm in the opposite direction of the flux of the buck, the efficiencyis boosted even more.

10 20 30 40 50 60 70 80 90 10075

77

79

81

83

85

87

89

91

93

Eff

icie

ncy

(%)

LED Power (%)

IBBC with two separate coresFIBBC center arm flux in same directionFIBBC center arm flux in reverse direction

Fig. 5.19 Efficiency with respect to dimming ratio of the IBBC, FIBBC with central arm fluxin same and reverse direction.


Fig. 5.20 shows the harmonics breakdown of the input current for both input voltages,110 V and 220 V, compared to the IEC61000-3-2 limit. As shown in the figure the converteris following the harmonics standard over the universal input voltage range.

2 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39

3

6

9

12

15

18

21

24

27

30

Har

mon

ic D

isto

rtio

n (%

)

Harmonic Order

IEC61000−3−2 limitHarmonic contents at 110 VHarmonic contents at 220 V

Fig. 5.20 The input current harmonic contents at both input voltages 110 V and 220 V incomparison with the IEC 61000-3-2 limit.

Fig. 5.21 shows a photograph for the PCBs of both drivers, the IBBC in Fig. 5.21 (a)and the FIBBC in Fig. 5.21 (b). As shown in the figure, a size reduction is achieved byintegrating the two inductors in one core.


(a)

(b)

EMI

filter

Buck

inductor

Boost

inductor

Bulk

capacitor

Output

capacitor

EMI filter Buck and Boost

integrated core

Output capacitor

Bulk capacitor

Fig. 5.21 The laboratory prototypes; (a) the IBBC prototype, and in (b) the FIBBC prototype.

Further enhancement in the power density of the driver is achieved by the manufacturedprototypes. These prototypes are implemented using reduced magnetic components. TheEFD 25 is used for the separate cores, and the EFD 30 is used for the integrated core. Thesame PCB layout is used for the IBBC and the FIBBC, just to highlight the size reductionachieved by magnetic integration. However, the FIBBC PCB can be optimized for a morecompact LED driver. The manufactured PCBs are very compact showing a total volumeof 56 cm3. Nevertheless, these PCBs don’t show any size-reduction, the reduction in themagnetic component in the case of the EFD cores reaches 28 %. The total reduction in themagnetic components is equal to 3.5 cm3, which represents 6.25 % of the total PCB size.


Lastly, Fig. 5.22 shows a photograph for the manufacture version of the PCBs of bothdrivers, the IBBC in Fig. 5.22 (a) and the FIBBC in Fig. 5.22 (b). As shown in the figure, thedriver is very compact. Moreover, it shows the size reduction achieved by integrating the twoinductors in one core.

(a)

EMI filter

(b)

EMI filter

Buck

inductor

Buck and

Boost

integrated

core

Boost

inductor

Bulk and Output

capacitors

Fig. 5.22 The manufactured prototypes; (a) the IBBC prototype, and in (b) the FIBBCprototype.

Finally, the proposed Integrated buck and boost converter is compared to found inliterature integrated converters previously illustrated in Table 1.2. Table 5.2 shows the samedata previously presented for the integrated converter added to it the features of the proposedconverter.

5.6E

xperimentalR

esults179

Table 5.2 Comparison Among the Proposed Converter and Found in the Literature Integrated Converters

DOUBLEBUCK-BOOST

BUCK ANDFLYBACK

BUCK-BOOSTAND CLASS E

RESONANT

FLYBACKAND CLASS E

RESONANT

BOOST ANDLLC

RESONANT

BUCK-BOOSTAND LLC

RESONANT

BUCK ANDBOOST

One switch One switch One switch One switch Two switch Two switch One switchTwo inductors One inductor Three inductors Two inductors One inductor Two inductors Two inductors

No transformers One transformer One transformerTwo

transformersOne transformer

Twotransformers

No transformers

Four diodes Four diodes Six diodes Four diodes Four diodes Six diodes Four diodesTwo capacitors Two capacitors Four Capacitors Four Capacitors Six Capacitors Five Capacitors Two capacitorsHigh voltage

over the switch.720 V, for

output voltage200 V.

High voltageover the switch.Around 700 V,

for outputvoltage 48 V.









Low voltageover the switch.160 V to 300 V


High busvoltage. 240 Vto 366 V, for

output voltage200 V.

High busvoltage. 60 %

of input voltage,for output

voltage 48 V.

High busvoltage. 160 V,

for outputvoltage of 50 V.

High busvoltage. Around

200 V, foroutput voltage

50 V.

High busvoltage. 430 v,


High busvoltage. 420 v,


Low busvoltage. 35 V


No electricisolation

Electricisolation

Electric isolationElectricisolation

Electricisolation

Electric isolationNo electricisolation

Power factor0.96

Power factor0.96

Power factor0.99

Not mentionedPower factor

0.98Power factor

0.995Power factor

0.994Efficiency of 85

%, at ratedpower 70 W.

Efficiency of 80%, at rated

power 100 W.

Efficiency of90.8%, at ratedpower 100 W.

Not mentionedEfficiency of

91.1%, at ratedpower 100 W.

Efficiency of91%, at ratedpower 100 W.

Efficiency of92.6%, at ratedpower 26.5 W.


As shown in Table 5.2, the proposed driver shows better features than all integratedconverters or at least similar. Except that it does not provide electric isolation, while othersdo.

Moreover, the converter shows a bulk capacitor voltage of 35 V for an output voltageof 46 V. The converter shows a variation in the bulk capacitor voltage from 32 V to 42 Vcorresponding to a variation in the input AC voltage from 90 V to 240 V. This is one of theadvantages shown by this specific integrated converter compared to the rest of the integratedconverters.

In order to illustrate this specific benefit, a comparison between three different integratedconverters and the proposed Fully integrated converter has been made. All three convertersshow a higher voltage at the bulk capacitor. Knowing that the bulk capacitor has a highcapacitance value, thus, if it operates at high voltage this will make it very bulky andexpensive.

The three converters have an output voltage equal to 48 V and 50 V so it is very similar tothe presented application. Thus, a comparison between the size and price of the capacitor ismade to show with numbers the benefit of the proposed converter. As shown in table 5.3, theintegrated converter showing comparative results to the proposed converter is the integratedbuck-boost and class E, driver. As it shows a bulk capacitor four times the volume of theproposed topology capacitor and seven times its price.

Table 5.3 Comparison Among the Proposed Converter and Found in the Literature IntegratedConverters in Terms of Needed Bulk Capacitor Size and Price

BUCK ANDFLYBACK

BUCK-BOOSTAND CLASS E

RESONANT

FLYBACK ANDCLASS E

RESONANT

BUCK ANDBOOST

High bus voltage.60 % of input

voltage, for outputvoltage 48 V.

High bus voltage.160 V, for outputvoltage of 50 V.

High bus voltage.Around 200 V, for

output voltage 50 V.

Low bus voltage. 35V for output voltage

of 46 V.

470µF/250V 200µF/200V 220µF/250V 470µF/50V

12745 mm3 6168 mm3 6231 mm3 1573 mm3

3.78 $ 1.61 $ 2.61 $ 0.22 $

5.7 Conclusion 181

5.7 Conclusion

This chapter has presented a new high-efficient and high-power density LED drivers. Thedriver ensures high PF and low THD to be far below the limitation specified by IEC 61000-3-2 standard at all dimming range. The converter is constructed by integrating a buckconverter operating as a PFC stage with a boost converter operating as a constant currentsource. Furthermore, the proposed topology does not require any coupled inductors nortransformers, which means that a spike-less operation is ensured, as well as minimizingwinding losses. Additionally, the proposed technique avoids requiring any complex circuitryor any advanced sensors other than the normal ones used in dc-dc converters. Regardingthe power components, the proposed topology offers all these features by using only onecontrolled switch, which additionally handles low current, as it handles the higher of the buckor boost currents but not the addition of both. Two extra diodes are added; however, thesediodes are not continuously conducting so the losses do not harm the converter efficiency.For further increase of the power-density, a magnetic integration is made by integrating thetwo inductors of both the buck converter and boost converter in one core. In this chapter, itis illustrated the operation principles of the FIBBC, as well as a magnetic analysis of theintegration of both inductors in the same core.

Finally, two prototypes working at 110 V, 60 Hz, and 46 V output, driving an LED lumi-nary of 26.5 W, have been designed to illustrate the application of the derived characteristics.Experimental results have proven that the harmonic content of the input current of the FIBBCis equal to 10 %, with a PF of 0.994, so that the converter meets the IEC-61000-3-2 standardand U.S. Energy Star program requirements. The FIBBC shows a high efficiency of 92.62%, compared to 90.5 % of efficiency shown by the IBBC. Moreover, the FIBBC shows animprovement of 2 % in the efficiency within all the dimming range. Furthermore, the FIBBCshows a size reduction in the magnetic component compared to the IBBC of 28.35 %. Thus,the proposed FIBBC shows a compact size driver with higher efficiency.

A patent application has been registered for this converter in three regions under thefollowing references:

• China Patent: 201811342664.0



The statement of the patent can be found in Appendix A.

Chapter 6

Aging Modeling and Lifetime Predictionof Organic Light Emitting Diodes


6.2 OLED Dynamic Model . . . . . . . . . . . . . . . . . . . . . . . . . . 185

6.3 Aging OLED Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189

6.3.1 Equivalent Aging Model . . . . . . . . . . . . . . . . . . . . . . 189

6.3.2 Lifetime Prediction . . . . . . . . . . . . . . . . . . . . . . . . . 191

6.4 Experimental Verification . . . . . . . . . . . . . . . . . . . . . . . . . 192

6.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196

184 Aging Modeling and Lifetime Prediction of Organic Light Emitting Diodes

6.1 Introduction

In 1977 Heeger, MacDiarmid, and Shirakawa published their first article describing polymericconduction [174]. This was the first time electronic devices based on organic materials wereintroduced in the literature. The term organic is associated with the use of polymers, whichare based on some types of carbon composite. The polymer-based electronics are eco-friendly,while its mechanical properties offer more advantages, such as high flexibility and simplemanufacturing. In the early 1950s, electroluminescence was reported in organic materials[175, 176], while the first OLED was developed in 1987 [177]. The first development of theOLED was based on the vacuum evaporation of organic small molecule materials. However,OLEDs on their current form were developed in 1990 [177, 178].

White OLEDs are known by being eco-friendly besides to the following features, as beingthin, lightweight, flexible, bendable, high CRI, no glare with a wide emissive surface, easilydimmable, long life (over 40.000 hours at L70) and their appearance can be made mirror-like, transparent or diffused. However, OLEDs are behind LEDs in terms of performanceparameters, as luminous efficacy, lifetime and cost [35, 179–181].

OLEDs are characterized by a I-V characteristics similar to LEDs. However, OLEDs havea unique characteristic owing to their stacked structure and large emission area. Moreover,OLEDs have a resistive effect in series to the device due to the transparent electrode. Thedissimilarity in the I-V characteristics comes from the carrier transport phenomena, whichproduces a significant capacitive behavior in OLED, as compared to LEDs [182]. Thecapacitive behavior of OLEDs depends on several variables, such as device area, constructionmaterials, forward voltage, and operating frequency [183–186].

The aging estimation of any device can be done by testing a batch of devices togetherand monitoring their failure rate over time [187, 188]. However, concerning this study, thelifetime itself is not as interesting as detecting and monitoring some signature of the agingprocess over time. Therefore, the main goal of this study is the characterization of the agingeffect on the I-V characteristic of the OLED.

As aforementioned, OLEDs are like inorganic LEDs and all semiconductors have theirI-V characteristic. Basically, the I-V characteristic is affected by the operating time of theOLED. Moreover, it is affected by the operating condition of the OLED such as operatingtemperature, electrical stresses, UV radiation, encapsulation quality, and on-off switching.In other words, the I-V characteristic is affected by the operating time and the operationcondition of the OLED. For instance, two OLEDs with the same operating time but underdifferent temperatures will have different I-V characteristics.

6.2 OLED Dynamic Model 185

The focus of this study is on the aging effect of OLEDs. The lifetime of an OLED isdefined as the time required for the luminance at a given current density to decay to 70 %(L70) or 50 % (L50) or 30 % (L30) of its initial value.

Fig. 6.1 shows the I-V characteristics of the Philips GL-55 at different lifetime; Brandnew device (L100), luminance decay of 70 % of its initial value (L70), luminance decay of50 % of its initial value (L50), luminance decay of 30 % of its initial value (L30).

As shown in Fig. 6.1, as the operation time is increasing, the I-V characteristics areshifted toward the right. In other words, as time passes the same level of current injected inthe OLED produces a higher voltage across the OLED. Some of the data presented in Fig.6.1 are taken from [189, 190].

0 1 2 3 4 5 6 7 8 9 100

0.05

0.1

0.15

0.2

0.25

0.3

0.35

0.4The IV curves for the OLED at L100 & L70 & L50 & L30

Voltage (Volts)

Cu

rren

t (A

mp

s)

IV curve at L100IV curve at L70IV curve at L50IV curve at L30

Fig. 6.1 IV characteristics of the Philips GL-55; in blue the IV characteristics at L100, inred the IV characteristics at L70, in green the IV characteristics at L50, and in black the IVcharacteristics at L30.

6.2 OLED Dynamic Model

The model is presented in [35–37] for OLED. The model is showing a good accuracyrepresenting the I-V characteristics of the OLED. Thus, it will be adapted in this study to


represent the aging of the OLED. As shown in Fig. 6.2, the model is composed of resistanceRe in series with three parallel branches. Each branch represents a different interval in theI-V characteristic, as shown in Fig. 6.3.

CgRp

Rs Rbi

Vo Vbi

Cd

Re

Anode

Cathode

Dbi

DsDC

Branch I Branch III Branch II

Fig. 6.2 Theoretical Equivalent Model of OLED.

0 1 2 3 4 5 6 7 8 9-0.05

0

0.05

0.1

0.15

0.2

0.25

0.3

0.35

X: 6.329

Y: 0.003489

Voltage (Volts)

Cu

rre

nt

(Am

ps

)

IV Curve

X: 7.177

Y: 0.03495

I II III

Fig. 6.3 IV characteristics of OLED described on it the three intervals.

6.2 OLED Dynamic Model 187

The three branches and its corresponding intervals can be explained as follows:

1. Interval I:

This interval is defined when the voltage across the OLED (VOLED) goes from zero tothe threshold voltage of branch II (Vbi). The OLED forward current at this interval isvery small and has an I-V characteristic similar to a resistive behavior. This intervalis represented by an RC branch (Branch I), which is composed of resistance Rp inparallel with a capacitor Cg. Cg is the OLED capacitance and it depends on the OLEDdielectric material properties, device area, and the thickness of the dielectric layer [38].Cg can be found by the following equation:

Cg =ε0εrAact

lorg(6.1)

2. Interval II

This interval conducts when VOLED is higher than Vbi and lower than the thresholdvoltage of the third branch (Vo). This interval is represented by branch II, which iscomposed of a voltage source Vbi in series with another RC branch. The RC branch iscomposed of resistance Rbi and a capacitor Cd . The voltage source Vbi represents thethreshold voltage of this interval. Cd is the OLED diffusion capacitance which dependson OLED bias voltage. This branch is connected through an ideal diode Dbi to fix thecurrent going to the branch not coming from it.

3. Interval III

This interval conducts when VOLED is higher than Vo. It is modeled by branch III, whichis composed of a voltage source Vo in series with resistance Rs. The voltage source Vo

represents the threshold voltage of this interval. This branch is also connected throughan ideal diode Ds. Moreover, this branch is connected to the previous branch using anideal diode Dc. This diode is used to transfer power from branch II to branch III andnot in a reverse way.

Following the procedure in [35–37] the model parameters are extracted from the I-Vcharacteristic. However, one difference is made in this procedure, which is the selection ofVbi. As by [37], Vbi is the value of the voltage across the OLED at forward current equal to 1% of the rated current. However, in this work, a different approach is considered. The I-Vcharacteristics of the four samples were measured with a Keithley 2602A source meter unitin voltage mode. These measurements were performed using an ultra-short-pulse (200µs)I-V measurement technique with the source meter, in order to avoid OLED self-heating or


charge accumulation between two consecutive measurements. Normally, the input currentvalues are following a linear distribution starting from a given value (1µA) to an end value(rated current) with a fixed step. In this study, a different methodology is made. The inputcurrent is also starting from a given value (1 nA) and ending value (0.35 A) but following alogarithmic distribution. Moreover, a high number of samples is taken (106samples).

Fig. 6.4, shows the I-V characteristic represented in logarithmic scale for the current axis.As can be seen, by using a logarithmic scale a point where the slope changes abruptly can beidentified. Thus, this operating point is chosen to be the breakpoint between interval I andinterval II.

0 1 2 3 4 5 6 7 8 9

10-8

10-6

10-4

10-2

100

X: 4.994

Y: 6.396e-06

Voltage (Volts)

Cu

rren

t (A

mp

s)

IV Curve

X: 7.177

Y: 0.03495

I II III

Fig. 6.4 The IV curve in logarithmic scale illustrating the three new intervals.

6.3 Aging OLED Model 189

6.3 Aging OLED Model

6.3.1 Equivalent Aging Model

As aforementioned, the commercial OLED selected in this study is the Philips GL-55, whosemain characteristics are shown in Table 6.1 [191]. Four different aged OLEDs were studied:brand new L100, L70, L50, and L30. The I-V characteristics of the four samples havepreviously been illustrated in Fig. 6.1.

The parameters of the model shown in Fig. 6.2 are extracted using the procedure presentedin [37], following proposed methodology presented in previous section to obtain the valueof Vbi. The values of the series resistance Re and the two capacitors Cg and Cd are the samevalues presented in [35]. In this study the following parameters are assumed to be constant:Re, Cg and Cd . This procedure is repeated four times on the four samples to create fourdifferent models representing the four samples. Table 6.2 shows the parameters of the GL-55model at L100, L70, L50, and L30. Fig. 6.5 shows the parameter change with respect todegradation percentage.

Table 6.1 PHILIPS GL-55 Main Characteristics

Characteristic Value

Rated Voltage (V) 7.2

Rated Current (A) 0.39

Rated Power (W) 2.8

Luminous Flux (lm) 55

Efficacy (lm/W) 19.58

CCT (K) 3200

Active Area (m2) 4.11e−3

Total Area (m2) 6.22e−3


Table 6.2 Model Parameters of PHILIPS GL-55 at Different Lifetime L100, L70, L50, andL30

Parameters L100 L70 L50 L30

Re 3 Ω 3 Ω 3 Ω 3 Ω

Cg 519 pF 519 pF 519 pF 519 pF

Cd 910 pF 910 pF 910 pF 910 pF

Rp 0.53 MΩ 0.67 MΩ 0.8 MΩ 0.935 MΩ

Rbi 34.6 Ω 50.7 Ω 59.7 Ω 68.03 Ω

Rs 1.23 Ω 2.3 Ω 2.56 Ω 2.796 Ω

Vbi 5.26 V 5.09 V 4.994 V 4.913 V

Vo 6.591 V 7.025 V 7.177 V 7.395 V

0.6

0.7

0.8

0.9

Res

ista

nce

(M

)

Rp

30

40

50

60

70

Res

ista

nce

(

)

Rbi

100 90 80 70 60 50 40 301

1.5

2

2.5

3

Res

ista

nce

(

)

LXX

Rs

100 90 80 70 60 50 40 304.5

5

5.5

6

6.5

7

7.5

LXX

Volt

ag

e (V

olt

s)

Vbi

Vo

Fig. 6.5 Model parameters as a function of lifetime.

6.3 Aging OLED Model 191

6.3.2 Lifetime Prediction

The lifetime of the OLED can be predicted by measuring the voltage across the OLED ata given current value. Later on, this value can be compared with the values of the voltageacross the OLED with respect to lifetime. Fig. 6.6 shows the OLED lifetime with respectto the voltage across the OLED at rated current (350 mA). Using this figure, the lifetime ofany OLED from the type Philips GL-55 can be predicted if the voltage across the OLED ismeasured at rated current. The effect of the OLED operating temperature has been neglectedin this first work because it would need much more experimentation. In future work, theeffect of the temperature will be considered.

7.8 8 8.2 8.4 8.6 8.8 9 9.2 9.4100

90

80

70

60

50

40

30

LX

X

Voltage (Volts)

Voltage across the OLED VOLED

at rated current (350 mA)

Fig. 6.6 OLED Lifetime with respect to voltage across the OLED at rated current (350 mA).


6.4 Experimental Verification

The proposed model has been simulated with the parameters illustrated in Table 6.2. The I-Vcharacteristics are extracted from each model in the same way as it is extracted experimentallyfrom the four samples. An ultra-short-pulse (200µs) I-V measurement technique is used,to avoid charge accumulation in the capacitors between two consecutive measurements.Fig. 6.7 and Fig. 6.8, show the I-V characteristics at L50 from the experimental resultsand the results found by the model. Fig. 6.7 and Fig. 6.8 show the comparison in normalscale and logarithmic scale, respectively. The curve extracted from the simulated model ismatching the experimental results. The biggest mismatch is in the second interval, however,the performance remains promising. The same procedure is repeated with the remainingsamples. Fig. 6.9 shows the comparison between the experimental results and I-V modelcharacteristics at different lifetime. Fig. 6.9 (a), 6.9 (b) and 6.9 (c) show the experimentaland model I-V characteristics of the OLED at L100, L70 and L30 respectively.

For further verification of the model, an experiment is made on the aged OLED samples.The OLEDs are supplied by a current square waveform. The peak value of the squarewaveform is the rated current shown in Table 6.1, and the frequency is 100 Hz. Threedifferent duty cycles are applied to evaluate if the model emulates the OLED performance.Fig. 6.10 shows the experimental and model voltage across the OLED with respect to time, atdifferent duty cycles and different lifetime. Fig. 6.10 plot I shows the case of an OLED withlifetime L30 and duty ratio 25 %, while Fig. 6.10 plot II shows the same OLED at L30 butwith duty ratio 50 %, finally Fig. 6.10 plot III shows the same OLED at L30 but with dutyratio 75 %. Concerning the results of the tests of the OLED at lifetime L50, it is illustrated inFig. 6.10 plot IV, Fig. 6.10 plot V, and Fig. 6.10 plot VI at duty ratios 25 %, 50 %, and 75 %respectively.

Commenting on the results presented in Fig. 6.10, still the model performance is notmatching exactly the OLED real behavior. However, it is similar enough to study and simulatethe OLED performance.

Moreover, the parameter change with respect to the lifetime shown in Fig. 6.5 is notaccurate as it is drawn using only four points. However, it is still acceptable enough toestimate the model parameters at any lifetime of the OLED. Furthermore, these parameterscan be used to build the model and study its performance at any lifetime.

Finally, the procedure to model any OLED will be done by first inject the rated currentvalue (350 mA) to the OLED and measure the voltage across it. Using this value of voltageand the data presented in Fig. 6.6 an estimation for the lifetime of the OLED is found. Lateron, using this value of the OLED lifetime in Fig. 6.5 an estimation for the parameter of theOLED model is found.

6.4 Experimental Verification 193

0 1 2 3 4 5 6 7 8 9−0.05

0

0.05

0.1

0.15

0.2

0.25

0.3

Voltage (Volts)

Cur

rent

(A

mps

)

Experimental results of IV characteristics at L50Model results of IV characteristics at L50

Fig. 6.7 IV characteristics at L50 in linear scale, in blue experimental results, and in red theresults from the dynamic model.

0 1 2 3 4 5 6 7 8 910

−12

10−10

10−8

10−6

10−4

10−2

Voltage (Volts)

Cur

rent

(A

mps

)

Experimental results of IV characteristics at L50Model results of IV characteristics at L50

Fig. 6.8 IV characteristics at L50 in logarithmic scale, in blue experimental results, and inred the results from the dynamic model.

194A

gingM

odelingand

Lifetim

ePrediction

ofOrganic

LightE

mitting

Diodes

(a) (b) (c)

0 1 2 3 4 5 6 7 8 9 100

0.05

0.1

0.15

0.2

0.25

0.3

0.35

0.4The IV curve for the OLED at L100

Voltage (Volts)

Cu

rren

t (A

mp

s)

Experiment at L100

Model at L100

0 1 2 3 4 5 6 7 8 9 100

0.05

0.1

0.15

0.2

0.25

0.3

0.35


Voltage (Volts)

Experiment at L70

Model at L70

0 1 2 3 4 5 6 7 8 9 100

0.05

0.1

0.15

0.2

0.25

0.3

0.35


Voltage (Volts)

Experiment at L30

Model at L30

Fig. 6.9 Experimental and model I-V characteristics at different lifetime; First plot at L100, second plot at L70, and third plot at L30.

6.4E

xperimentalV

erification195

0 5 10 15 200

1

2

3

4

5

6

7

8

9

10

Volt

age

(Am

ps)

Experimental results of L30 at 25% Duty

Model of L30 at 25% Duty

0 5 10 15 200

1

2

3

4

5

6

7

8

9

10

Volt

age

(Am

ps)



0 5 10 15 200

1

2

3

4

5

6

7

8

9

10

Volt

age

(Am

ps)



0 5 10 15 200

1

2

3

4

5

6

7

8

9

10

Time (mSec)

Volt

age

(Am

ps)



0 5 10 15 200

1

2

3

4

5

6

7

8

9

10

Time (mSec)

Volt

age

(Am

ps)



0 5 10 15 200

1

2

3

4

5

6

7

8

9

10

Time (mSec)

Volt

age

(Am

ps)



I II III

IV V VI

(Volt

s)(V

olt

s)

(Volt

s)(V

olt

s)

(Vo

lts)

(Vo

lts)

Fig. 6.10 Experimental and model OLED voltage; plot I shows the case of L30 and duty 25%, plot II shows the case of L30 and duty50%, plot III shows the case of L30 and duty 75%, plot IV shows the case of L50 and duty 25%, plot V shows the case of L50 andduty 50%, and plot VI shows the case of L50 and duty 75%.


6.5 Conclusion

This study presents a high accuracy dynamic model for the OLED. The model is presentedfor different aged OLEDs, showing the aging effect on each model parameter. This model isdone by splitting the characteristics of the OLED into three parts. Thus, the model has threeoperation modes that simulate a behavior similar to the OLED characteristics.

The proposed aging OLED model can be used as a tool to analyze and develop an OLEDdriver before manufacturing. The proposed model can save years of waiting to evaluate thedriver before going to the market because the behavior of the arrangement driver plus OLEDcan be simulated including aging effects. Moreover, the study presents a methodology topredict the lifetime of the OLED just by measuring the voltage across the OLED at ratedcurrent.

Finally, the study presents two different experimental verification methodologies for theproposed model on the Philips GL-55. The model is verified on four different lifetimesOLEDs, namely; L100, L70, L50, and L30. The first verification is to extract the I-Vcharacteristics experimentally and match it with the model. The second verification is toapply a current square waveform on the OLEDs with different duties. Later on, the voltageacross the OLED is matched experimentally with the model. Moreover, the study presentsthe effect of aging on each parameter of the dynamic model.

Chapter 7

Conclusions

7.1 Conclusions and main contributions of the Thesis

This Ph.D. thesis entitled "Analysis and Development of Improved Converters for LEDDrivers with Special Focus on Efficiency and Dimming" offers LED driver solutions toenhance their operation in several aspects. The thesis document focus, in each of its chapters,on presenting a solution for a given issue. In the following the main contributions presentedin this document:

A deep analysis of the losses in the IBFC is presented. This analysis aims to study thecomponents causing higher percentage losses in the converter. Moreover, the procedureto find the losses equations is comprehensively explained so that the study can easily beadapted to other converters. The study is used to change the parameters of the converter andstudy the effect of this change on the efficiency of the converter.The equations illustratedshow great accuracy. Moreover, the results of the equations are more accurate than thesimulation results, due to the limitation in the simulation sampling time. The use of theequations facilitates the study of the effect of the reactive elements on the converter efficiency.The study leads to the ability to enhance the converter efficiency. A practical case of studyfor the efficiency enhancement process for an existing driver is presented. The driver isoperating under universal input conditions, and 38 V output, supplying an LED luminary of26.5 W. The old design shows an efficiency of 82 %, power factor equal to 0.9, and THDof 21 %. The study leads to a change in a few parameter values: the turn ratio from 0.4 to2, the magnetizing inductance from 500 µH to 56 µH, the buck inductance from 100 µHto 110 µH, and the bulk capacitor from a bulky 47 µF/160V to a smaller size and moreeffective one of 330 µF/63V . The new design shows a great enhancement in all aspects; anefficiency of 89 %, power factor equals 0.96, and THD of 16 %. Moreover, the output rippleshown by the new design is half of the one shown by the old driver. Furthermore, a reduction

198 Conclusions

of the number of components is achieved by removing one diode that will not be conducting.Finally, the losses analysis and efficiency improvement procedure presented in this chaptercan be used to optimize other integrated converters.

A new topology that enhances both PF and THD to be well below the limitations specifiedby the IEC 61000-3-2 standard is presented. This is done by inserting an interleaved capacitorbetween the rectifier and the converter. The used converter to drive the LED is the IBFCconverter. The interleaved capacitor voltage is fixed by a third winding added to the flybacktransformer. Furthermore, the proposed IIBFC reduces the ripple by a factor of five, whichmeans a significant reduction of the output and bulk capacitor voltage. Also, the proposedtechnique avoids any complex circuitry or any other extra sensors apart from those usedin the conventional IBFC, since the control technique is the same. Regarding the powercomponent, the proposed topology offers all these features by only adding an extra windingin the flyback transformer, a capacitor of 2.2µF and an extra diode. However, the proposedtechnique ensures that a diode of the conventional IBFC will not be conducting so that it canbe removed. Finally, a prototype working at 110 V, 60 Hz, and 37 V output, driving a LEDluminary of 25 W, has been designed and implemented to prove the previously illustratedcharacteristics. Experimental results have proven that the harmonic content of the inputcurrent equals 2.5 %, and the power factor equals 0.997 at full power operation. Moreover,the converter meets the IEC-61000-3-2 standard at any dimming ratio, reaching a minimumdimming ratio of 10 %. The converter efficiency is 80 %, which is good considering thesimplicity of the converter, the low power of the present application and the good featuresoffered by the converter.

An improved dimming technique, to enhance the operation by ensuring better currentfor LED is presented. The idea is accomplished by the new HSP-PWM dimming technique,through passive and active techniques. The passive technique is made by adding a resistivebranch. While the active method is made through a new double integrated converter theIBFBC. The converter keeps all the advantages given by the IBFC; the high PF correctionand the low current handled by the main switch. The IBFBC ensures a constant outputcurrent regulation as well as high PF in all dimming ratios. The converter operates at verylow dimming ratios reaching a dimming ratio of 2.5 % and even operates at a high dimmingratio that reaches 95 %. Moreover, the converter shows a linear characteristic of the outputpower with respect to the dimming duty ratio. Thus, the output luminous flux and the lightintensity with respect to the dimming ratio is linear as well. Finally, the proposed converterdoes not recommend any complex circuitry or any extra sensors than the normal IBFC, justan additional diode, and an inductor, and a switch. Furthermore, the technique was testedon the IBFC and shows promising results. Thus it could be applied to any other topologies.

7.1 Conclusions and main contributions of the Thesis 199

A universal input 230 V, 50 Hz output 160 V, 100 W AC-DC converter operating at 100kHz is implemented in order to verify the active HSP-PWM technique. The practical resultsmatch all theoretical and mathematical analysis. Moreover, an efficiency range of 50 % to86 % corresponding to dimming duties of 5 % to 100 % is reached, where 5 % dimmingcorresponds to an output power of 4 W.

A new high-efficient and high-power density converter for LED drivers is presented.The driver ensures high PF and low THD to be far below the limitation specified by IEC61000-3-2 standard at all dimming range. The converter is constructed by integrating a buckconverter operating as a PFC stage with a boost converter operating as a constant currentsource. Furthermore, the proposed topology does not require any coupled inductors nortransformers, which means that a spike-less operation is ensured, as well as minimizingwinding losses. Additionally, the proposed technique avoids requiring any complex circuitryor any advanced sensors other than the normal ones used in dc-dc converters. Regardingthe power components, the proposed topology offers all these features by using only onecontrolled switch, which additionally handles low current, as it handles the higher of the buckor boost currents but not the addition of both. Two extra diodes are added; however, thesediodes are not continuously conducting so the losses do not harm the converter efficiency.For further increase of the power-density, a magnetic integration is made by integrating thetwo inductors of both the buck converter and boost converter in one core. In this chapter, itis illustrated the operation principles of the FIBBC, as well as a magnetic analysis of theintegration of both inductors in the same core. Finally, two prototypes working at 110 V, 60Hz, and 46 V output, driving an LED luminary of 26.5 W, have been designed to illustrate theapplication of the derived characteristics. Experimental results have proven that the harmoniccontent of the input current of the FIBBC is equal to 10 %, with a PF of 0.994, so that theconverter meets the IEC-61000-3-2 standard and U.S. Energy Star program requirements.The FIBBC shows a high efficiency of 92.62 %, compared to 90.5 % of efficiency shownby the IBBC. Moreover, the FIBBC shows an improvement of 2 % in the efficiency withinthe whole dimming range. Furthermore, the FIBBC shows a size reduction in the magneticcomponent compared to the IBBC of 28.35 %. Thus, the proposed FIBBC shows a compactsize driver with higher efficiency.

A patent application has been registered for this converter in three regions under thefollowing references:

• China Patent: 201811342664.0



200 Conclusions

A high accuracy dynamic model for the OLED is illustrated. The model is presentedfor different aged OLEDs, showing the aging effect on each model parameter. This modelis done by splitting the characteristics of the OLED into three parts. Thus, the model hasthree operation modes that simulate a behavior similar to the OLED characteristics. Theproposed aging OLED model can be used as a tool to analyze and develop an OLED driverbefore manufacturing. The proposed model can save years of waiting to evaluate the driverbefore going to the market because the behavior of the arrangement driver plus OLED can besimulated including aging effects. Moreover, the study presents a methodology to predict thelifetime of the OLED just by measuring the voltage across the OLED at rated current. Finally,the study presents two different experimental verification methodologies for the proposedmodel on the Philips GL-55. The model is verified on four different lifetimes OLEDs,namely; L100, L70, L50, and L30. The first verification is to extract the I-V characteristicsexperimentally and match it with the model. The second verification is to apply a currentsquare waveform on the OLEDs with different duties. Later on, the voltage across the OLEDis matched experimentally with the model. Moreover, the study presents the effect of agingon each parameter of the dynamic model.

7.2 Conclusiones y Principales Contribuciones de la Tesis 201

7.2 Conclusiones y Principales Contribuciones de la Tesis

La presente tesis doctoral titulada “Análisis y Desarrollo de Mejoras en Convertidores paraDrivers LED con Especial Énfasis en Eficiencia y Control de Flujo Luminoso,” ofrecesoluciones para drivers LED que mejoran su funcionamiento en diversos aspectos. La tesisdoctoral se centra en cada uno de sus capítulos en presentar una solución a un determinadoproblema. A continuación se resumen las principales contribuciones de este trabajo.

Se ha llevado a cabo un estudio profundo de las pérdidas generadas en el convertidorIBFC. En este análisis se estudia el comportamiento de los componentes que causan lasmayores pérdidas en el convertidor. Además, el procedimiento desarrollado para encontrar laspérdidas en los diversos componentes es explicado con gran detalle de forma que el estudiopueda ser fácilmente extendido a otros convertidores. El estudio realizado permite modificarlos parámetros del convertidor y estudiar su efecto en la eficiencia del mismo. Las ecuacionesobtenidas demostraron una gran precisión de resultados. Incluso los resultados obtenidos apartir de las ecuaciones presentaron mayor precisión que los resultados de simulación, debidoa la limitación existente en el periodo de muestreo de la simulación. El uso de ecuacionesfacilita el estudio del efecto de los elementos reactivos sobre la eficiencia del convertidor.

El estudio realizado permite por tanto mejorar la eficiencia del convertidor. Así, seha presentado un ejemplo de estudio práctico de mejora de eficiencia en un driver LEDprediseñado con anterioridad. El driver opera bajo condiciones de tensión de red universal,con tensión de salida de 38 V, suministrando una potencia a la lámpara LED de 26.5 W. Eldiseño existente presentaba una eficiencia del 82%, un factor de potencia (FP) de 0.9 y unadistorsión armónica total (DAT) del 21%. El estudio realizado dio lugar a la modificación dealgunos parámetros del convertidor. La relación de espiras pasó de 0.4 a 2, la inductanciamagnetizante pasó de 500 µH a 56 µH, la inductancia del convertidor reductor pasó de100 µH a 110 µH y el condensador de almacenamiento de energía pasó de un voluminosocondensador de 47 µF/160V a uno de tamaño más reducido y efectivo de 330 µF/63V. Elnuevo diseño muestra una gran mejora en todos los aspectos. Una eficiencia del 89 %, FPde 0.96 y DAT del 16 %. Además, el rizado de salida del nuevo diseño se redujo a la mitaden comparación con el diseño previo. Adicionalmente, se consiguió una reducción en elnúmero de componentes gracias a la eliminación de uno de los diodos que no conduciráen ningún momento. Finalmente, el análisis de pérdidas y procedimiento de mejora es decarácter general y puede ser empleado en la mejora de otros tipos de drivers LED integrados.

En este trabajo se ha desarrollado y estudiado una nueva topología que permite mejorarel FP y la DAT para conseguir valores muy por debajo de las limitaciones especificadasen la norma IEC-61000-3-2. Esta topología se ha obtenido por medio de la inserción deun condensador entrelazado entre el rectificador y el convertidor, donde el convertidor

202 Conclusions

empleado como driver LED es el IBFC. La tensión del condensador entrelazado es fijadapor un tercer devanando añadido al transformador flyback. Además, el convertidor asídesarrollado, denominado IIBFC, reduce el rizado de salida en un factor de 5 veces, lo quepermite una reducción muy significativa del condensador de almacenamiento de energía.Adicionalmente, la técnica propuesta evita la necesidad de complejas circuiterías o de otrossensores adicionales aparte de aquellos usados en el convertidor original de partida IBFC yaque la técnica de control empleada sigue siendo la misma. En relación a los componentesde potencia, la topología propuesta ofrece estas características añadiendo únicamente undevanado extra en el transformador flyback, un condensador de 2.2 µF y un diodo adicional.Así, la técnica propuesta asegura que un diodo del convertidor convencional IBFC noconducirá en ningún momento y puede ser eliminado. Finalmente, se ha desarrollado unprototipo trabajando desde tensión de red de 110 V/60 Hz, con una tensión de salida de37 V que alimenta una lámpara LED de 25 W, demostrando las características comentadaspreviamente. Los resultados experimentales probaron que la DAT de la corriente de entradaera sólo del 2.5 % y el FP de 0.997 a plena potencia de salida. Además, el convertidorsatisface la normativa IEC-61000-3-2 a todos los niveles de dimming, alcanzando un nivelmínimo del 10 %. La eficiencia del convertidor es del 80 %, lo que se considera adecuadoteniendo en cuenta la simplicidad del convertidor, la baja potencia de la presente aplicación ylas buenas características ofrecidas por el convertidor.

En este trabajo se presenta también una técnica de control de flujo luminoso (dimming)que permite mejorar el funcionamiento asegurando una mejor forma de onda de corrientea través del LED. La idea se basa en el empleo de la técnica de modulación de anchurade pulso en montaje híbrido serie-paralelo (HSP-PWM), lo cual puede ser realizado pormedio de técnicas pasivas o activas. La técnica pasiva propuesta en este trabajo se basa enañadir una rama resistiva adicional. La técnica activa emplea un nuevo convertidor dobleintegrado designado como IBFBC. El convertidor así desarrollado mantiene todas la ventadasdel convertidor previo IBFC, es decir, un elevado FP y baja DAT manejados por el interruptorprincipal. El convertidor IBFBC asegura una regulación de corriente constante de salidaademás de elevado FP a cualquier relación de dimming. El convertidor es capaz de operar arelaciones de dimming tan bajas como 2.5 % y tan elevadas como el 95 %.

Adicionalmente, el convertidor muestra una característica lineal de la potencia de salidacon respecto a la relación de dimming. Así, el flujo luminoso de salida y la intensidad deluz con respecto a la relación de dimming permanecen también lineales. Finalmente, elconvertidor propuesto no precisa de ninguna circuitería compleja o sensores adicionales másallá de los empleados para el convertidor original. Únicamente son necesarios un diodoadicional, un inductor y un interruptor. La técnica propuesta fue ensayada en el convertidor

7.2 Conclusiones y Principales Contribuciones de la Tesis 203

IBFC mostrando buenos resultados, de forma que puede ser empleada en otras topologíasdiferentes. Para verificar la técnica HSP-PWM propuesta se construyó un convertidoruniversal con tensión nominal de entrada de 230 V /50 Hz, tensión de salida de 160 V y 100W de potencia de salida. Los resultados experimentales coincidieron de forma adecuada conlos estudios teóricos y análisis matemáticos. La eficiencia medida varió en un rango entre el50 % y el 86 %, correspondiente a relaciones de dimming del 5 % y 100 % respectivamente,donde la potencia de salida al 5 % fue de 4 W.

Un nuevo convertidor de alta eficiencia y alta densidad de potencia para drivers LED fuetambién desarrollado en este trabajo. Este nuevo driver asegura un elevado FP y baja DAT,muy por debajo de los límites especificados por la normativa IEC-61000-3-2 en todo el rangode dimming. El convertidor que se propone está formado por la integración de un convertidorbuck operando como corrector del factor de potencia (CFP) con un convertidor boost operandocomo fuente de corriente constante para el LED. La topología propuesta presenta la ventajade no precisar inductores acoplados ni transformadores, lo que permite evitar la generación depicos de sobretensión y minimizar las pérdidas en los devanados. Adicionalmente, la técnicapropuesta evita la necesidad de circuitería compleja adicional o sensores avanzados, apartede los normalmente empleados en convertidores CC-CC. En relación a los componentes depotencia, la topología propuesta ofrece estas ventajas empleando únicamente un interruptorcontrolado que adicionalmente maneja baja corriente ya que la corriente que circula por elmismo corresponde a la más elevada de los convertidores buck o boost pero no a la sumade ambas. No obstante, el convertidor incorpora dos diodos adicionales. Sin embargo, estosdiodos no conducen de forma continua por lo que las pérdidas no producen un detrimentoelevado en la eficiencia del convertidor. Con el objetivo de incrementar aún más la densidadde potencia del convertidor, se propone una integración magnética de los dos inductoresdel convertidor, el buck y el boost, en un solo elemento magnético. Se ha estudiado enprofundidad el principio de funcionamiento del convertidor, incluyendo un estudio magnéticode la integración de ambos inductores en un núcleo común. Finalmente, se construyerondos prototipos de laboratorio operando desde 110 V/60 Hz, con 46 V de tensión de saliday 26.5 W de potencia de salida para demostrar la técnica desarrollada y sus características.Los resultados experimentales demostraron que el contenido armónico de la corriente deentrada del FIBBC es igual al 10 %, con un FP de 0.994, de forma que el driver LEDverifica las condiciones de la norma IEC-61000-3-2 y del programa Energy Star de EE.UU.El convertidor FIBBC obtuvo una eficiencia del 92.62 %, más elevada que el valor de 90.5 %obtenido en el convertidor IBBC. Además, esta mejora del 2 % del convertidor FIBBC semantiene en todo el rango de dimming. Adicionalmente, el convertidor FIBBC muestra unareducción de tamaño de los componentes magnéticos del 28.35 % en comparación con el

204 Conclusions

convertidor IBBC que no incorpora integración de magnéticos. Así, el convertidor propuestoFIBBC muestra un tamaño de driver más compacto con una eficiencia más elevada.

Se ha registrado una patente para este convertidor en tres regiones bajo las siguientesreferencias:

• Patente China: 201811342664.0

• Patente Taiwan: 107138097

• Patente Europea: 19154150.7 - 1201

Finalmente, en este trabajo se ha desarrollado un modelo dinámico de alta precisión paradiodos LED orgánicos (OLEDs) que incluye el efecto del envejecimiento del dispositivo. Elmodelo se ha desarrollado para OLEDs con diferentes tiempos de envejecimiento, mostrandoel efecto de envejecimiento en cada parámetro del modelo. El modelo está basado en dividirla característica del OLED en tres partes. Así, el modelo presenta tres modos de operaciónque simulan el comportamiento de las características del OLED. El modelo de envejecimientoOLED propuesto puede ser empleado como una herramienta para analizar y desarrollar eldriver OLED antes de su fabricación. El modelo propuesto puede así ahorrar años de esperapara evaluar el driver antes de su comercialización porque permite simular el comportamientoconjunto del driver y su carga OLED incluyendo los efectos de envejecimiento. Además,el estudio presenta una metodología para predecir la vida útil del OLED basada en elempleo únicamente de la tensión del OLED a la corriente nominal. Finalmente, el trabajopresenta dos verificaciones experimentales diferentes del modelo propuesto para una lámparaOLED Philips GL-55. El modelo se ha verificado para cuatro periodos de envejecimiento:L100, L70, L50 y L30. La primera verificación consistió en extraer las características I-Vexperimentalmente y compararlas con las del modelo. La segunda verificación consistió enaplicar una forma de onda de corriente cuadrada sobre el OLED con diferentes ciclos detrabajo. A continuación, la tensión del OLED se comparó experimentalmente con el modelo.Adicionalmente, el estudio presenta el efecto de envejecimiento sobre cada parámetro delmodelo dinámico.

Chapter 8

Future work

Contents8.0.1 New Electrolytic Capacitor-less Off-Line LED Driver Based on

Integrated Parallel Buck-Boost and Boost Converter . . . . . . . 206

8.0.1.1 Implementation of the integrated parallel buck-boostand boost converter . . . . . . . . . . . . . . . . . . . 207

8.0.1.2 Principle of Operation of the integrated parallel buck-boost and boost converter . . . . . . . . . . . . . . . . 209

8.0.1.3 Mathematical analysis and average model of the inte-grated parallel buck-boost and boost converter . . . . . 212

8.0.1.4 Simulation results of the integrated buck-boost and boostconverter . . . . . . . . . . . . . . . . . . . . . . . . . 216

8.0.2 Complete Model of Organic Light Emitting Diodes Taking intoAccount the Aging and Temperature Effect . . . . . . . . . . . . 221

8.0.3 Control Technique for Organic Light Emitting Diodes . . . . . . 221

206 Future work

The previously illustrated contributions bring up more research lines that could be furtherinvestigated. Mainly, three clear ideas are currently under investigation:

8.0.1 New Electrolytic Capacitor-less Off-Line LED Driver Based onIntegrated Parallel Buck-Boost and Boost Converter

The proposed converter is composed of two converters as the two-stage LED drivers. However,in the two-stage driver, the two-converter are operating in cascaded mode. This means thatthe power is handled by the first stage, later the second stage, then finally goes to the LED.Concerning the proposed converter, it has the PC stage, its main duty is to deliver the power tothe output LED. Moreover, it has a Ripple-Reduction (RR) stage, its main duty is to eliminatethe output LED ripple. Thus, no need for a bulky capacitor and in return an electrolyticcapacitor-less driver can be presented.

The ripple reduction process is so simple, the output voltage is the addition of bothvoltages, the PC stage output and the RR stage input. The RR voltage will be in reversepolarity of the PC stage, thus, the ripple will be subtracted and only the average value goes tothe output.

Fig. 8.1 shows the block diagram of the proposed converter. It shows great advantagessuch as:

• No bulk capacitor needed; thus, it offers a longer lifetime, compact, and cheaper LEDdriver.

• The driver handles less power compared to conventional cascaded integrated converters;thus, higher efficiency is obtained.

• The control can be implemented by using a conventional output current controller;thus, no extra complex control is needed.

Concerning the converter drawbacks, it can be as the following:

• The high output voltage of the buck-boost converter, as it is the addition of the LEDvoltage and the voltage of the boost converter.

• There will be a circulating power in the boost converter.

207

CBo

CBB

I LED

PO

VLED

RRPRR

Vg

I in

PC

PPC

PC

I inRR

INOUT

IN OUT

Fig. 8.1 The schematic of the proposed parallel integrated converter.

8.0.1.1 Implementation of the integrated parallel buck-boost and boost converter

This proposed driver is using the buck-boost converter as a PC stage, while a boost converteris used in the RR. The buck-boost will deliver all the energy to the output including the lossesof the driver, while the boost converter will have some circulating power in it. Fig. 8.2 showsthe structure of the proposed electrolytic capacitor-less driver.

Moreover, for further improvement, a reduction in the converter component is made, byintegrating the two converters switches, and uses a single switch. Thus, the integrated parallelbuck-boost and boost converter is proposed. Fig. 8.3 shows the structure of the IntegratedParallel Buck-Boost and Boost Converter (IPB3C). The driver offers a single switch operation.Furthermore, the controller needed is straightforward; it is a simple current or voltage controltechnique, in order to control the output of the converter to a fixed value. Thus, no complexcontrol is needed.

208 Future work

D2D1

D3 D4

Vg

D BoMBoCBo

MBB

LBB

DBB

CBB

LBo

VLED

Buck-boost (PC stage)

Boost (RR stage)IAC

Fig. 8.2 The structure of the electrolytic capacitor-less buck-boost and boost converter.

D Bo CBoM I

LBB

DBB

CBB

LBo

VLED

Buck-boost (PC stage)

Boost (RR stage)

D I

D2D1

D3 D4

Vg

IAC

Fig. 8.3 The structure of the electrolytic capacitor-less integrated parallel buck-boost andboost converter.

209

8.0.1.2 Principle of Operation of the integrated parallel buck-boost and boost con-verter

Since the proposed converter is a single switch converter, there are only two main states, on-state, and off-state. However, the DCM operation of the buck-boost and boost converters splitsthe off-state into three intervals. Thus, the converter will have four intervals in total, one forthe on state and three for the off state. Fig. 8.4, and Fig. 8.5 illustrate the equivalent circuits,and the main current waveforms within a high-frequency switching period, respectively.

In the following a concise explanation for each interval:

• Interval I

During this interval, the main switch MI is in switched-on mode. While the switch ison, both converters are operating. Thus, a current iBB flows in the buck-boost turn-onloop, coming from the AC grid to energize the buck-boost inductance. Meanwhile,a current iBo flows in the boost turn-on loop, coming from the boost capacitor, andenergizing the boost inductor. The current is increasing linearly in both inductors.

• Interval II

This interval starts with the turn-off of the main switch MI . During this intervalboth inductors of buck-boost and boost converters are de-energizing. The buck-boostinductor is de-energizing sending the power to the buck-boost capacitor through thebuck-boost diode. While the boost inductor is de-energizing delivering the power tothe buck-boost capacitor.

• Interval III

Interval II ends and interval III starts when one of the two inductors current goes tozero, and its belonging inductor de-energize completely. Fig. 8.4 Interval III and Fig.8.5 right side shows the interval III for the case where the buck-boost inductor currentreaches zero, while, the boost inductor current is still conducting. While interval III, inthe case of buck-boost current is higher than the boost current, is shown in Fig. 8.5 leftside.

• Interval IV

Finally, interval IV represents the period where both inductors are fully discharged.However, concerning the current going to the LED, it is continuous due to the outputcapacitor presence.

210Future

work

DBo CBoM I

LBB

DBB

CBB

LBo

VLED

D I

(a) Interval Ⅰ : 0 < t < DTs(b) Interval Ⅱ : DTs < t < t1

(c) Interval Ⅲ : t1 < t < t2(d) Interval Ⅳ : t2 < t < Ts

D2D1

D3 D4

Vg

IAC

DBo CBoM I

LBB

DBB

CBB

LBo

VLED

D I

D2D1

D3 D4

Vg

IAC

DBo CBoM I

LBB

DBB

CBB

LBo

VLED

D I

D2D1

D3 D4

Vg

IAC

DBo CBoM I

LBB

DBB

CBB

LBo

VLED

D I

D2D1

D3 D4

Vg

IAC

Fig. 8.4 Equivalent circuits of the IPB3C operating in DCM.

211

t

t

t

iM

iBB

i

I II III IV

DTs Tst1 t2

DTvg

LBB

DTsVBo

LBo

Bo

t

t

t

iBB

i

I II III IV

DTs Tst1 t2

DTsVBo

LBo

Bo

iD I IBo

IBB

(a) i > i (b) i < iBB Bo BB Bo

s

I

+ IBoI

BB+ IBo

iM I

DTvg

LBB

s

iD I IBo

IBB

IBB

IBoIBo

Fig. 8.5 Main current waveforms of the IPB3C operating in DCM, within a high-frequencyswitching period; (a) when iBB > iBo around the peak line voltage, (b) when iBB < iBo for lowvalues of the line voltage.

This integration is an over-current integration, which means that the current of the switchwill be the addition of both converters currents. However, the voltage across the switch willnot be the addition of the voltage across each switch in the converter before integration, it willbe the higher between them. The voltage across the switch in buck-boost operating in DCMis the addition of input and output voltages in case the inductor is de-energizing, while it willbe equal to input voltage in the zero conduction region. Conversely, the voltage across theswitch in boost operating in DCM is the output voltages in case the inductor is de-energizing,while it will be equal to input voltage in the zero conduction region. Fig. 8.6 shows thevoltage across the switch in both cases, (a) where iBB > iBo, and (b) where iBB < iBo.

212 Future work

t

t

iBB

i

I II III IV

DTs Tst1 t2

DTvg

LBB

DTsVBB

LBo

Bo

t

t

iBB

i

I II III IV

DTs Tst1 t2

DTsVBB

LBo

Bo

(a) i > i (b) i > iBB Bo Bo BB

s

DTvg

LBB

s

VM IVM I

v g VBB+

v g VBB+v g

VBB

VBo

Fig. 8.6 Inductor currents waveforms of the IPB3C operating in DCM, and voltage across theswitch, within a high-frequency switching period; (a) when iBB > iBo around the peak linevoltage, (b) when iBB < iBo for low values of the line voltage.

8.0.1.3 Mathematical analysis and average model of the integrated parallel buck-boost and boost converter

In the following, the analysis of the powers in the converter is presented. The analysis showsthe important design characteristics when both stages, buck-boost and boost, operate in DCM.For the sake of simplicity, the analysis will consider an ideal converter. An ideal sinusoidalline voltage waveform will also be considered, expressed as vg (t) =Vg sin(2π flt).

As shown in Fig. 8.1 there are three main powers in the converter and can be listed as thefollowing:

• Input power

It is the power coming from the main. This power can be expressed by the power ofthe buck-boost converter operating in DCM. It is expressed as the following:

PPC =Vg

2D2

4LBB fs(8.1)

213

• RR stage power

It is the power handled by the RR stage. This represents the circulating power in theconverter, it is equal to the boost converter power operating in DCM, it is expressed bythe following:

PRR =VBo

2D2

2LBo fs

(VBB

VBB −VBo

)(8.2)

• Output loop power

The power going from the output buck-boost capacitor to the LED and also going to theboost capacitor. Considering the converter in ideal conditions, the following relationsof the output loop are found:

Pout = ILED ∗VBB

= ILED ∗VBo + ILED ∗VLED

= PRR +PPC

(8.3)

Thus, the input power and RR stage power can be expressed as the following:

PRR = ILED ∗VBo

PPC = ILED ∗VLED(8.4)

Using the power equation in (8.1), (8.2), and (8.4) a relation between the buck-boostoutput voltage, and boost input voltage is found as the following:

VBBVBo =Vg

2

2LBo

LBB(8.5)

An additional relation between the buck-boost output voltage and the boost input voltageis found from the output loop, it is expressed as the following:

VBB =VBo +VLED (8.6)

214 Future work

Using the previously stated equations the value of the buck-boost output voltage andboost input voltage in terms of the inductance ratio, is drawn as shown in Fig. 8.7 and Fig.8.8 respectively.

0.25 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 2.75 3 3.25 3.5 3.75 4200

250

300

350

400

450

500

550

600

Inductance ratio (LBO

/LBB

)

Vol

tage

(V

olts

)

Buck−boost output voltage

Fig. 8.7 Output voltage of the buck-boost PC stage in terms of the inductance ratio (buck-boostinductance over boost inductance LBo/LBB).

0.25 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 2.75 3 3.25 3.5 3.75 40

50

100

150

200

250

300

350

400


/LBB

)

Vol

tage

(V

olts

)

Boost input voltage

Fig. 8.8 Input voltage of the boost RR stage in terms of the inductors ratio (buck-boostinductance over boost inductance LBo/LBB).

215

Using the boost input voltage, the percentage of the circulating power of the RR stagein terms of the LED power can be found, as shown in Fig. 8.9. For a better illustration, anexample is given as shown in Fig. 8.9. For instance, in the case of a inductors ratio (buck-boost inductance over boost inductance LBo/LBB) equal to one, in other words, buck-boostinductance equal to boost inductance, the power circulating in the converter will be equal to70.53 % of the LED power.

0.25 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 2.75 3 3.25 3.5 3.75 420

40

60

80

100

120

140

160

180

X: 1Y: 70.53


/LBB

)

PR

R p

erce

ntag

e of

the

LE

D p

ower

(%

) Circulating power percentage of LED power

Fig. 8.9 Circulating power of the RR stage percentage of LED power in terms of the inductorsratio (buck-boost inductance over boost inductance LBo/LBB).

Fig. 8.10 shows the average model of the proposed IPB3C. In the following the value ofthe buck-boost and boost equivalent resistances are expressed as the following:

RBB =2LBB fs

D2(8.7)

RBo =2LBo fs

D2

(VBB −VBo

VBB

)(8.8)

216 Future work

CBo

CBB

ILED

Vg

RBoIBo

IBo

RBB IBB

IBB

R

Vth

dyn

Buck-boost

(PC stage)

Boost

(RR stage)

Fig. 8.10 Average model of the proposed IPB3C LED driver.

8.0.1.4 Simulation results of the integrated parallel buck-boost and boost converter

For the sake of a better illustration of the idea, a simulation has been made. Table 8.1 showsthe parameters of the simulation. As shown in Table 8.1 the used capacitors have smallcapacitance values.

Table 8.1 Parameters of the simulation of the Integrated Buck-Boost and Boost Converter.

COMPONENTS Value






Buck-boost inductance LBB = 500 µH

Boost inductance LBo = 500 µH

Output buck-boost capacitor CBB 47µF

Input boost capacitor CBo 2µF

217

Fig. 8.11 shows the three voltages of the output loop. While the ripples of the same threevoltages are shown in Fig. 8.12.

0 0.0025 0.005 0.0075 0.01 0.0125 0.015 0.0175 0.02 0.0225 0.025100

150

200

250

300

350

Time (sec)

Vol

tage

(V

olts

)

Buck−boost output voltageBoost input voltageLED voltage

Fig. 8.11 Buck-boost output voltage (blue), boost input voltage (red), and LED voltage(green).

0 0.0025 0.005 0.0075 0.01 0.0125 0.015 0.0175 0.02 0.0225 0.025−10

−8

−6

−4

−2

0

2

4

6

Times (sec)

Vol

tage

(V

olts

)

Boost input voltage rippleLED voltage rippleBuck−boost output voltage ripple

Fig. 8.12 Buck-boost output voltage ripple (blue), boost input voltage ripple (red), and LEDvoltage ripple (green).

218 Future work

The LED voltage is the buck-boost output voltage subtracted from it the boost inputvoltage. Thus, as shown in Fig. 8.12 the ripple is also subtracted and the LED voltage rippleis lower than both voltage ripple. Moreover, most of the ripple is a high-frequency ripple.The LED current instantaneous and filtered from switching frequency are shown in Fig. 8.13.As shown in Fig. 8.13 the low-frequency ripple is equal to 9 % of the rated current, whichmeans it is far below the flicker standards. Furthermore, the driver offers the low currentripple using relatively low capacitance for the two capacitors, 2 µF and 47 µF .

0 0.0025 0.005 0.0075 0.01 0.0125 0.015 0.0175 0.02 0.0225 0.0250.32

0.33

0.34

0.35

0.36

0.37

0.38

0.39

Time (sec)

Cur

rent

(A

mps

)

LED currentLED current filtered

Fig. 8.13 LED current (blue), LED current filtered from high frequency ripple (red).

Fig. 8.14 shows the AC main voltage and current. As shown in the figure the inputcurrent is a pure sinusoidal waveform, since the buck-boost operating in DCM behaves like aresistance. It is calculated from the simulation the PF is equal to 1. However, in the practicalcase the PF will be lower than the ideal simulation; nevertheless, it gives a good indicationfor the promising PF of the driver.

For a better illustration of the converter operation, the current in both buck-boost andboost inductors are illustrated in Fig. 8.15 in line frequency period range. As shown in thefigure the peak values of the currents are not so high, they are 3.25 A and 1.5 A for thebuck-boost and boost currents, respectively.

219

0 2.5 5 7.5 10 12.5 15 17.5 20 22.5 25−375

−300

−225

−150

−75

0

75

150

225

300

375

Time (sec)

Vol

tage

(V

olts

)

0 2.5 5 7.5 10 12.5 15 17.5 20 22.5 25−0.75

−0.6

−0.45

−0.3

−0.15

0

0.15

0.3

0.45

0.6

0.75

Cur

rent

(A

mps

)

AC main voltageAC main current

Fig. 8.14 AC main voltage (blue), AC main current (green).

0 0.0025 0.005 0.0075 0.01 0.0125 0.015 0.0175 0.02 0.0225 0.025−1

0

1

2

3

4

Cur

rent

(A

mps

)

0 0.0025 0.005 0.0075 0.01 0.0125 0.015 0.0175 0.02 0.0225 0.025−0.5

0

0.5

1

1.5

2

Time (sec)

Cur

rent

(A

mps

)

Boost inductor current

Buck−boost inductor current

Fig. 8.15 Buck-boost inductor current (blue), boost inductor current (red).

220 Future work

Finally, Fig. 8.16 shows the voltage across the switch, and the current through it. Fromthe figure, the maximum voltage across the switch is 650 V which is not considered highfor high input, high output voltage application. As previously mentioned, the current in theswitch is the addition of both converters currents, thus, the peak current in the switch is equalto 4.75 A.

0 0.0025 0.005 0.0075 0.01 0.0125 0.015 0.0175 0.02 0.0225 0.0250

100

200

300

400

500

600

700

Vol

tage

(V

olts

)

0 0.0025 0.005 0.0075 0.01 0.0125 0.015 0.0175 0.02 0.0225 0.0250

1

2

3

4

5

Time (sec)

Cur

rent

(A

mps

)

Current through the switch

Voltage across the switch

Fig. 8.16 Voltage across the switch (blue), current through the switch (red).

Lastly, from the simulation, the circulating power in the RR stage equals 49.35 W, whichis 70.5 % of the LED power. It is not possible at this stage to estimate the efficiency ofthe driver. However, it is possible to claim that it will have greater efficiency than normalcascaded integrated converters. For the reason that the cascaded converter is composed oftwo stages that each of them processes the full power of the LED. Thus, the proposed driverhas one stage that will process less power and in return, the driver will have better efficiencythan the conventional integrated converters.

221

8.0.2 Complete Model of Organic Light Emitting Diodes Taking intoAccount the Aging and Temperature Effect

As aforementioned, OLEDs are like inorganic LEDs and all semiconductors have their I-V characteristic. Basically, the I-V characteristic is affected by the operating time of theOLED. Moreover, it is affected by the operating condition of the OLED such as operatingtemperature, electrical stresses, UV radiation, encapsulation quality, and on-off switching.In other words, the I-V characteristic is affected by the operating time and the operationcondition of the OLED. For instance, two OLEDs with the same operating time but underdifferent temperatures will have different I-V characteristics.

The focus of the study previously illustrated in this thesis is on the aging effect of OLEDs.However, this further study aims to create a complete model of the OLED that includes bothaging and temperature effects on the OLED. The investigation will be made on nine differentsamples at different lifetimes and different temperatures as illustrated in Table 8.2.

As shown in Table 8.2, there will be three main temperatures; room temperature 23, 40,and 60. At each temperature the tests will be made at three different lifetime; brand newL100, L70, and L50.

Using the I-V characteristic of the nine samples, a complete model for the OLED will befound. Moreover, the effect of the operation temperature on each of the model parameterswill be presented.

Table 8.2 OLED Samples Conditions

Lifetime

L100 L70 L50

Tem

pera

ture 23 Sample I Sample II Sample III

40 Sample IV Sample V Sample VI

60 Sample VII Sample VIII Sample IX

8.0.3 Control Technique for Organic Light Emitting Diodes

As previously mentioned the study of the OLED model aim is to find an accurate model inorder to use it later in proposing a control technique that takes into account the real behavior

222 Future work

of the OLED. This further investigation aims to find a control technique that suits the accuratemodel of the OLED. The required control technique should feature the ability to give asmooth start-up process. Furthermore, the aging model previously illustrated can be used tofind a control technique that ensures a promising operation for the whole OLED lifetime. Anadditional feature of the control technique is to eliminate all spikes from the OLED current,to increase the driver and OLED lifetime.

References

[1] Y. Wang, J. M. Alonso and X. Ruan, "A Review of LED Drivers and Related Technolo-gies," in IEEE Transactions on Industrial Electronics, vol. 64, no. 7, pp. 5754-5765,July 2017.

[2] H. J. Round, “A note on carborundum,” Elect. World, vol. 19, pp. 309– 3010, 1907.

[3] “The road to the transistor,” [Online]. Available: http: //www.jmargolin. com.

[4] Losev, O. V. (1927). Telegrafiya i Telefoniya bez Provodov 44: 485–494.

[5] Zheludev, N. (2007). “The life and times of the LED: a 100-year history” NaturePhotonics : 189–192. doi:10.1038/nphoton.2007.34.

[6] Lee, Thomas H. (2004). The design of CMOS radio frequency integrated circuits.Cambridge University Press. p. 20. ISBN 0-521-83539-9.

[7] K. Lehovec, C. A. Accardo, AND E. Jamgochian (1951). “Injected LightEmission of Silicon Carbide Crystals” The Physical Review 83 (3): 603–607.doi:10.1103/PhysRev.83.603.

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Appendix A

Patent Statement

115480P792EP2018-01-29

1

POWER CONVERTER SYSTEM AND COUPLED TWO-STAGE INDUCTOR

TECHNICAL FIELD

[0001] The disclosure relates in general to a power converter system and a coupled

two-stage inductor.

BACKGROUND5

[0002] Along with the advance in the technology of electronics, various electronic

devices are continuously provided one after another. Since different electronic devices

may have different voltage specifications, the power converter system is provided.

However, the single-stage power converter system with a high step-down ratio makes

the duty ratio of switch decrease. The power converter system has poor performance in 10

terms of accuracy and stability, and is susceptible to noise interference, which decreases

power conversion efficiency. Furthermore, the control unit used in the power converter

system is more expensive.

SUMMARY

[0003] The disclosure relates to a power converter system and a coupled two-stage 15

inductor. Through circuit optimization integration, one common switch enables two power

converting units to perform a charging/discharging procedure with in-phase and same

time sequence, not only greatly increasing the step-down ratio and conversion efficiency

but also reducing the cost and the volume.

[0004] According to one embodiment of the disclosure, a power converter system 20

including a first power converting unit, a second power converting unit and a common

switch is provided. The first power converting unit includes a first inductor and a first

capacitor. The first inductor is electrically connected to the first capacitor. The second

power converting unit includes a second inductor and a second capacitor. The second

inductor is electrically connected to the second capacitor. The common switch is 25

electrically connected to the first power converting unit and the second power converting

unit. The first power converting unit and the second power converting unit are both

operated with the common switch. When the common switch is conducted, the first

115480P792EP2018-01-29

2

power converting unit and the second power converting unit perform a two-stage power

converting procedure with in-phase and same time sequence.

[0005] According to another embodiment of the disclosure, a coupled two-stage

inductor including a first structure, a second structure, a first coil and a second coil is

provided. The first structure includes a first cylinder, a second cylinder, and a third5

cylinder interposed between the first cylinder and the second cylinder. The second

structure includes a fourth cylinder, a fifth cylinder, and a sixth cylinder interposed

between the fourth cylinder and the fifth cylinder. The first structure and the second

structure are disposed oppositely, such that the first cylinder and the fourth cylinder are

separated by a first gap, the second cylinder and the fifth cylinder are separated by a10

second gap, and the third cylinder and the sixth cylinder are separated by a third gap.

The first coil is winded on the first cylinder and the fourth cylinder. The second coil is

winded on the second cylinder and the fifth cylinder.

[0006] According to an embodiment of the disclosure, a power converter system

including a first power converting unit, a second power converting unit and a common 15

switch is provided. The first power converting unit includes a first inductor and a first

capacitor. The first inductor is electrically connected to the first capacitor. The second

power converting unit includes a second inductor and a second capacitor. The second

inductor is electrically connected to the second capacitor. The common switch is

electrically connected to the first power converting unit and the second power converting 20

unit. The first power converting unit and the second power converting unit are both

operated with the common switch. When the common switch is conducted, the first

power converting unit and the second power converting unit perform a two-stage power

converting procedure with in-phase and same time sequence. The first inductor and the

second inductor are integrated as a coupled two-stage inductor.25

[0007] The above and other aspects of the disclosure will become better understood

with regard to the following detailed description of the preferred but non-limiting

embodiment(s). The following description is made with reference to the accompanying

drawings.

115480P792EP2018-01-29

3

BRIEF DESCRIPTION OF THE DRAWINGS

[0008] FIG. 1 is a schematic diagram of a power converter system according to an

embodiment.

[0009] FIGS. 2A to 2D are schematic diagrams of a two-stage power converting

procedure of the power converter system of FIG. 1.5

[0010] FIG. 3A is a schematic diagram of a coupled two-stage inductor according to

an embodiment.

[0011] FIG. 3B is an equivalent circuit diagram of the coupled two-stage inductor of

FIG. 3A.

[0012] FIG. 4 is a schematic diagram of the coupled two-stage inductor of FIG. 3A10

used in the power converter system of FIG. 1.

[0013] FIG. 5 is a schematic diagram of a power converter system according to

another embodiment.


procedure of the power converter system of FIG. 5.15

[0015] FIG. 7 is a schematic diagram of a power converter system according to

another embodiment.


procedure of the power converter system of FIG. 7.

[0017] FIG. 9 is a schematic diagram of a power converter system according to 20

another embodiment.


procedure of the power converter system of FIG. 9.

[0019] FIG. 11A is a current chart of the power converter system of FIG. 1.

115480P792EP2018-01-29

4

[0020] FIG. 11B is a current chart of the power converter system of FIG. 5.

[0021] In the following detailed description, for purposes of explanation, numerous

specific details are set forth in order to provide a thorough understanding of the disclosed

embodiments. It will be apparent, however, that one or more embodiments may be

practiced without these specific details. In other instances, well-known structures and 5

devices are schematically shown in order to simplify the drawing.

DETAILED DESCRIPTION

[0022] Referring to FIG. 1, a schematic diagram of a power converter system 100

according to an embodiment is shown. In an embodiment as indicated in FIG. 1, the

power converter system 100 is a buck-buck power converter system. The power 10

converter system 100 of FIG. 1 includes a first power converting unit VT11, a second

power converting unit VT12, a common switch Q1, two charging control diodes A11 and

A12 and two converting control diodes B11 and B12. The first power converting unit

VT11 is a buck unit. The first power converting unit VT11 includes a first inductor L11 and

a first capacitor C11. The first inductor L11 is electrically connected to the first capacitor 15

C11, and, after storing power, the first inductor L11is able to charge the first capacitor

C11. The second power converting unit VT12 is a buck unit. The second power

converting unit VT12 includes a second inductor L12 and a second capacitor C12. The

second inductor L12 is electrically connected to the second capacitor C12, and, after

storing power, the second inductor L12 is able to charge the second capacitor C12.20

[0023] The common switch Q1 is electrically connected to the first power converting

unit VT11 and the second power converting unit VT12. The first power converting unit

VT11 and the second power converting unit VT12 are both operated with the common

switch Q1. When the common switch Q1 is conducted, the first power converting unit

VT11 and the second power converting unit VT12 perform a two-stage power converting 25

procedure with in-phase and same time sequence.

[0024] Referring to FIGS. 2A to 2D, schematic diagrams of a two-stage power

converting procedure of the power converter system 100 of FIG. 1 are shown. As

indicated in FIG. 2A, the charging control diodes A11 and A12 are electrically connected

to two ends of the common switch Q1 respectively. When the common switch Q1 is 30

115480P792EP2018-01-29

5

conducted, the charging control diodes A11 and A12 are automatically connected but the

converting control diodes B11 and B12 are automatically disconnected to form a first

charging loop PA11 and a second charging loop PA12. The first charging loop PA11 is

configured to charge the first inductor L11 to store power. The second charging loop

PA12 is configured to charge the second inductor L12 to store power.5

[0025] As indicated in FIG. 2B, the converting control diodes B11 and B12 are

electrically connected to an input end of the first inductor L11 and an input end of the

second inductor L12 respectively. When the common switch Q1 is not conducted, the

converting control diodes B11 and B12 are automatically connected but the charging

control diodes A11 and A12 are automatically disconnected to form a first converting loop10

PB11 and a second converting loop PB12. The first converting loop PB11 enables the

first inductor L11 to charge the first capacitor C11. The second converting loop PB12

enables the second inductor L12 to charge the second capacitor C12.

[0026] As indicated in FIG. 2C, when the first inductor L11 completes the procedure

for charging the first capacitor C11, the converting control diode B11 is automatically 15

disconnected, and only the second converting loop PB12 continues to enable the second

inductor L12 to charge the second capacitor C12.

[0027] As indicated in FIG. 2D, when the second inductor L12 completes the

procedure for charging the second capacitor C12, the converting control diode B12 is

automatically disconnected to complete the two-stage power converting procedure.20

[0028] Referring to FIG. 3A, a schematic diagram of a coupled two-stage inductor LB

according to an embodiment is shown. In the above embodiments, the coupled

two-stage inductor LB can be used to filter the waves in the two loops and suitable

allocate the power storage for two times of voltage drop/voltage rise. The coupled

two-stage inductor LB includes a first structure ST1, a second structure ST2, a first coil 25

CO1 and a second coil CO2. The first structure ST1 includes a first cylinder CY1, a

second cylinder CY2, and a third cylinder CY3 interposed between the first cylinder CY1

and the second cylinder CY2. The first cylinder CY1, the second cylinder CY2 and the

third cylinder CY3 are connected by one end, such that the first structure ST1 has an

E-shaped appearance. The second structure ST2 includes a fourth cylinder CY4, a fifth 30

cylinder CY5, and a sixth cylinder CY6 interposed between the fourth cylinder CY4 and

115480P792EP2018-01-29

6

the fifth cylinder CY5. The fourth cylinder CY4, the fifth cylinder CY5 and the sixth

cylinder CY6 are connected by one end, such that the second structure ST2 has an

E-shaped appearance. The first structure ST1 and the second structure ST2 are

disposed oppositely, such that the first cylinder CY1 corresponds to the fourth cylinder

CY4, the second cylinder CY2 corresponds to the fifth cylinder CY5, and the third5

cylinder CY3 corresponds to the sixth cylinder CY6. The first cylinder CY1 and the fourth

cylinder CY4 are separated by a first gap G1. The second cylinder CY2 and the fifth

cylinder CY5 are separated by a second gap G2. The third cylinder CY3 and the sixth

cylinder CY6 are separated by a third gap G3. The first coil CO1 is winded on the first

cylinder CY1 and the fourth cylinder CY4. The second coil CO2 is winded on the second10

cylinder CY2 and the fifth cylinder CY5. The third cylinder CY3 and the sixth cylinder

CY6 are not winded by any coil.

[0029] In the present embodiment, all of the first cylinder CY1, the second cylinder

CY2, the third cylinder CY3, the fourth cylinder CY4, the fifth cylinder CY5 and the sixth

cylinder CY6 are magnetic cylinders. The first gap G1, the second gap G2 and the third15

gap G3 can be adjusted according to power distribution, therefore the dimensions of the

first gap G1, the second gap G2 and the third gap G3 can be different. Besides, the

number of windings N1 of the first coil CO1 and the number of windings N2 of the second

coil CO2 can also be adjusted according to power distribution, and therefore can be

different. 20

[0030] Referring to FIG. 3B, an equivalent circuit diagram of the coupled two-stage

inductor LB of FIG. 3A is shown. The first gap G1, the second gap G2 and the third gap

G3 respectively form a first magneto-resistance R1, a second magneto-resistance R2

and a third magneto-resistance R3. The coupled two-stage inductor LB can obtain the

inductance of the first inductor L11 and the inductance of the second inductor L12 using 25

the following equations (1) and (2).

inductanceofthefirstinductorL11 = F1(∅1,N1) + F3(∅3)……………......... (1)

inductanceofthesecondinductorL12 = F2(∅2,N2) + F3(∅3)....................... (2)

[0031] That is, the first magnetic flux ∅1, the second magnetic flux ∅2, the third

magnetic flux ∅3 can be correspondingly adjusted through the adjustment of the first 30

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gap G1, the second gap G2 and the third gap G3. Then, suitable first inductor L11 and

second inductor L12 can be designed according to the number of windings N1 and the

number of windings N2.

[0032] Referring to FIG. 4, a schematic diagram of the coupled two-stage inductor of

FIG. 3A used in the power converter system of FIG. 1 is shown. The first inductor L115

and the second inductor L12 can be integrated as a coupled two-stage inductor LB.

Based on the requirement of the power converter system, one coupled two-stage

inductor LB corresponding to the first inductor L11 and the second inductor L12 can be

designed. Since the coupled two-stage inductor LB provides the function of two inductors

(that is, the first inductor L11 and the second inductor L12), the design of the two-stage 10

power converter system can be simplified.

[0033] According to the design of the above embodiments, the first charging loop

PA11 and the second charging loop PA12 can be controlled by the same common switch

Q1. In comparison to the single-stage power converter system, the power converter

system 100 of the present embodiment can increase the step-down ratio by more than 4 15

times, and therefore can be used in the vehicle power of the power converter system

which requires a high step-down ratio. In comparison to the existing dual-stage power

converter system, the efficiency of the power converter system 100 of the present

embodiment is increased by more than 10%, and the cost and the volume are reduced

by more than 30% and more than 40%, respectively. 20

[0034] The design of the above embodiments can also be used in other embodiments.

Referring to FIG. 5, a schematic diagram of a power converter system 500 according to

another embodiment is shown is shown. In an embodiment as indicated in FIG. 5, the

power converter system 500 is a buck-boost power converter system. The power

converter system 500 of FIG. 5 includes a first power converting unit VT51, a second 25

power converting unit VT52, a common switch Q5, two charging control diodes A51 and

A52 and two converting control diodes B51 and B52. The first power converting unit

VT51 is a buck unit. The first power converting unit VT51 includes a first inductor L51

and a first capacitor C51. The first inductor L51 is electrically connected to the first

capacitor C51, and, after storing power, the first inductor L51 is able to charge the first 30

capacitor C51. The second power converting unit VT52 is a boost unit. The second

power converting unit VT52 includes a second inductor L52 and a second capacitor C52.

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The second inductor L52 is electrically connected to the second capacitor C52, and,

after storing power, the second inductor L52 is able to charge the second capacitor C52.



VT51 and the second power converting unit VT52 are both operated with the common 5


VT51 and the second power converting unit VT52 perform a two-stage power converting



converting procedure of the power converter system 500 of FIG. 5 are shown. As 10

indicated in FIG. 6A, the charging control diodes A51 and A52 are electrically connected

to two ends of the common switch Q5 respectively. When the common switch Q5 is

conducted, the charging control diodes A51 and A52 are automatically connected but the

converting control diodes B51 and B52 are automatically disconnected to form a first

charging loop PA51 and a second charging loop PA52. The first charging loop PA51 is 15

configured to charge the first inductor L51 to store power. The second charging loop

PA52 is configured to charge the second inductor L52 to store power.


electrically connected to an input end of the first inductor L51 and an output end of the

second inductor L52 respectively. When the common switch Q5 is not conducted, the 20


control diodes A51 and A52 are automatically disconnected to form a first converting

loop PB51 and a second converting loop PB52. The first converting loop PB51 enables

the first inductor L51 to charge the first capacitor C51. The second converting loop PB52

enables the second inductor L52 to charge the second capacitor C52. 25


for charging the first capacitor C51, the converting control diode B51 is automatically



[0039] As indicated in FIG. 6D, when the second inductor L52 completes the 30

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automatically disconnected to complete the two-stage power converting procedure.

[0040] It should be noted that the coupled two-stage inductor LB of FIG. 3A and FIG.

3B can also be used in the buck-boost power converter system 500 of FIG. 5. The

design parameters of the first inductor L51 and the second inductor L52 are similar to 5

that of the above design and the similarities are not repeated here.


according to another embodiment is shown. In an embodiment as indicated in FIG. 7, the

power converter system 700 is a boost-boost power converter system. The power

converter system 700 of FIG. 7 includes a first power converting unit VT71, a second 10

power converting unit VT72, a common switch Q7, a charging control diode A71 and two

converting control diodes B71 and B72. The first power converting unit VT71 is a boost

unit. The first power converting unit VT71 includes a first inductor L71 and a first

capacitor C71. The first inductor L71 is electrically connected to the first capacitor C71,

and, after storing power, the first inductor L71 is able to charge the first capacitor C71.15

The second power converting unit VT72 is a boost unit. The second power converting

unit VT72 includes a second inductor L72 and a second capacitor C72. The second

inductor L72 is electrically connected to the second capacitor C72, and, after storing

power, the second inductor L72 is able to charge the second capacitor C72.

[0042] The common switch Q7 is electrically connected to the first power converting 20





procedure with in-phase and same time sequence.25



indicated in FIG. 8A, the charging control diode A71 is electrically connected to one end

of the common switch Q7. When the common switch Q7 is conducted, the charging

control diode A71 are automatically connected but the converting control diodes B71 and30

B72 are automatically disconnected to form a first charging loop PA71 and a second

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charging loop PA72. The first charging loop PA71 is configured to charge the first

inductor L71 to store power. The second charging loop PA72 is configured to charge the

second inductor L72 to store power.


electrically connected to an output end of the first inductor L71 and an output end of the 5



control diode A71 are automatically disconnected to form a first converting loop PB71

and a second converting loop PB72. The first converting loop PB71 enables the first

inductor L71 to charge the first capacitor C71. The second converting loop PB72 enables10

the second inductor L72 to charge the second capacitor C72.




inductor L72 to charge the second capacitor C72. 15



automatically disconnected to complete the two-stage power converting procedure.


3B can also be used in the boost-boost power converter system 700 of FIG. 7. The 20

design parameters of the first inductor L71 and the second inductor L72. The design

parameters of the first inductor L51 and the second inductor L52 are similar to that of the

above design and the similarities are not repeated here.


according to another embodiment is shown. In an embodiment as indicated in FIG. 9, the 25

power converter system 900 is a boost-buck power converter system. The power

converter system 900 of FIG. 9 includes a first power converting unit VT91, a second

power converting unit VT92, a common switch Q9, a charging control diode A91 and two

converting control diodes B91 and B92. The first power converting unit VT91 is a boost

unit. The first power converting unit VT91 includes a first inductor L91 and a first 30

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capacitor C91. The first inductor L91 is electrically connected to the first capacitor C91,

and, after storing power, the first inductor L91 is able to charge the first capacitor C91.

The second power converting unit VT92 is a buck unit. The second power converting unit

VT92 includes a second inductor L92 and a second capacitor C92. The second inductor

L92 is electrically connected to the second capacitor C92, and, after storing power, the 5

second inductor L92 is able to charge the second capacitor C92.




switch Q9. When the common switch Q9 is conducted, the first power converting unit 10





indicated in FIG. 10A, the charging control diode A91 is electrically connected to one end 15

of the common switch Q9. When the common switch Q9 is conducted, the charging

control diode A91 are automatically connected but the converting control diodes B91 and

B92 are automatically disconnected to form a first charging loop PA91 and a second

charging loop PA92. The first charging loop PA91 is configured to charge the first

inductor L91 to store power, the second charging loop PA92 is configured to charge the 20

second inductor L92 to store power.


electrically connected to an output end of the first inductor L91 and an input end of the


converting control diodes B91 and B92 are automatically connected but the charging 25

control diode A91 are automatically disconnected to form a first converting loop PB91

and a second converting loop PB92. The first converting loop PB91 enables the first

inductor L91 to charge the first capacitor C91. The second converting loop PB92 enables

the second inductor L92 to charge the second capacitor C92.

[0052] As indicated in FIG. 10C, when the first inductor L91 completes the procedure 30


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automatically disconnected to complete the two-stage power converting procedure.5


3B can also be used in the boost-buck power converter system 900 of FIG. 9. The

design parameters of the first inductor L91 and the second inductor L92 are similar to

that of the above design and are not repeated here.

[0055] In the power converter systems 100, 500, 700 and 900 of the above 10

embodiments, through circuit optimization and integration, the source of the common

switches Q1, Q5, Q7 and Q9 shares the ground with the input voltage, such that the

drive signal does not need to be isolated and the circuit cost can be reduced.

[0056] Besides, the power converter systems 100, 500, 700 and 900 further use the

charging control diodes A11 and A12, A51, A52, A71 and A91 to form the first charging 15

loops PA11, PA51, PA71 and PA91 and the second charging loop PA12, PA52, PA72 and

PA92. The power converter systems 100, 500, 700 and 900 further use the converting

control diodes B11 and B12, B51, B52, B71, B72, B91 and B92 to form the first

converting loops PB11, PB51, PB71 and PB91 and the second converting loop PB12,

PB52, PB72 and PB92. Thus, the first power converting units VT11, VT51, VT71 and20

VT91 and the second power converting units VT12, VT52, VT72 and VT92 can

concurrently perform a charging/discharging procedure with in-phase and same time

sequence.

[0057] Referring to FIG. 11A, a current chart of the power converter system 100 of

FIG. 1 is shown. In the power converter system 100, the first power converting unit VT1125

and the second power converting unit VT12 are both operated with the same common

switch Q1, and therefore have only one time sequence. Also, in the power converter

system 100, the first power converting unit VT11 and the second power converting unit

VT12 are both operated with the same common switch Q1, therefore the first inductor

L11 and the second inductor L12 can be charged at the same time. When the common 30

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switch Q1 is conducted, the current curve IQ1(1) of the common switch Q1 shows that

there are electric currents passing through the common switch Q1. A comparison of

current curves IL11 and IL12 shows that the two inductors have the same current, such

that the first power converting unit VT11 and the second power converting unit VT12 can

perform a charging/discharging procedure with in-phase and same time sequence.5

[0058] Referring to FIG. 11B, a current chart of the power converter system 500 of

FIG. 5 is shown. In the power converter system 500, the first power converting unit VT51

and the second power converting unit VT52 are both operated with the same common

switch Q1, and therefore have only one time sequence. Moreover, in the power

converter system 500, the first power converting unit VT51 and the second power 10

converting unit VT52 are both operated with the same common switch Q1, therefore the

first inductor L51 and the second inductor L52 can be charged at the same time. When

the common switch Q1 is conducted, the current curve IQ1(5) of the common switch Q1

shows that there are electric currents passing through the current curve IQ1(5). A

comparison of the current curves IL51 and IL52 shows that the two inductors have the 15

same current, such that the first power converting unit VT51 and the second power

converting unit VT522 can perform a charging/discharging procedure with in-phase and

same time sequence.

[0059] The current charts of the power converter systems 700 and 900 are similar to

the current chart of the power converter system 500. The power converter systems 700 20

and 900 both have the feature of in-phase and same time sequence, and the similarities

are not repeated here.

[0060] It will be apparent to those skilled in the art that various modifications and

variations can be made to the disclosed embodiments. It is intended that the

specification and examples be considered as exemplary only, with a true scope of the 25

disclosure being indicated by the following claims and their equivalents.

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CLAIMS

1. A power converter system (100), wherein the power converter system comprises:

a first power converting unit (VT11), comprising a first inductor (L11) and a first

capacitor (C11), wherein the first inductor (L11) is electrically connected to the first

capacitor (C11);5

a second power converting unit (VT12), comprising a second inductor (L12)

and a second capacitor (C12), wherein the second inductor (L12) is electrically

connected to the second capacitor (C12); and

a common switch (Q1) electrically connected to the first power converting unit

(VT11) and the second power converting unit (VT12), wherein the first power 10

converting unit (VT11) and the second power converting unit (VT12) are both

operated with the common switch (Q1), and when the common switch (Q1) is

conducted, the first power converting unit (VT11) and the second power converting

unit (VT12) perform a two-stage power converting procedure with in-phase and

same time sequence.15

2. The power converter system according to claim 1, further comprising:

at least one charging control diode electrically connected to the common switch,

wherein when the common switch is conducted, the at least one charging control

diode is connected to form a first charging loop and a second charging loop, the first

charging loop charges the first inductor, and the second charging loop charges the 20

second inductor.

3. The power converter system according to claim 2, wherein the first power converting

unit is a buck unit, the second power converting unit is a buck unit, the quantity of the

at least one charging control diode is two, and the two charging control diodes are

electrically connected to two ends of the common switch respectively.25


unit is a buck unit, the second power converting unit is a boost unit, the quantity of

the at least one charging control diode is two, and the two charging control diodes

are electrically connected to two ends of the common switch respectively.

5. The power converter system according to claim 2, wherein the first power converting 30

unit is a boost unit, the second power converting unit is a boost unit, the quantity of

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the at least one charging control diode is one, and the charging control diode is

electrically connected to one end of the common switch.


unit is a boost unit, the second power converting unit is a buck unit, the quantity of

the at least one charging control diode is one, and the charging control diode is 5

electrically connected to one end of the common switch.

7. The power converter system according to anyone of the claims 1 to 6, further

comprising:

at least one converting control diode electrically connected to the first power

converting unit or the second power converting unit, wherein when the common 10

switch is not conducted, the at least one converting control diode is connected to

form a first converting loop and a second converting loop, the first converting loop

enables the first inductor to charge the first capacitor, and the second converting

loop enables the second inductor to charge the second capacitor.


unit is a buck unit, the second power converting unit is a buck unit, the quantity of the

at least one converting control diode is two, and the two converting control diodes

are electrically connected to an input end of the first inductor and an input end of the

second inductor respectively.


unit is a buck unit, the second power converting unit is a boost unit, the quantity of

the at least one converting control diode is two, and the two converting control

diodes are electrically connected to an input end of the first inductor and an output

end of the second inductor respectively.


unit is a boost unit, the second power converting unit is a boost unit, the quantity of


diodes are electrically connected to an output end of the first inductor and an output



unit is a boost unit, the second power converting unit is a buck unit, the quantity of

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diodes are electrically connected to an output end of the first inductor and an input


12. The power converter system according to anyone of the claims 1 to 11, wherein the

first inductor and the second inductor are integrated as a coupled two-stage inductor, 5

and the coupled two-stage inductor comprises:

a first structure, comprising:

a first cylinder;

a second cylinder; and

a third cylinder interposed between the first cylinder and the second cylinder;10

a second structure, comprising:

a fourth cylinder;

a fifth cylinder; and

a sixth cylinder interposed between the fourth cylinder and the fifth cylinder,

wherein the first structure and the second structure are disposed oppositely, such 15

that the first cylinder and the fourth cylinder are separated by a first gap, the second

cylinder and the fifth cylinder are separated by a second gap, and the third cylinder

and the sixth cylinder are separated by a third gap;

a first coil winded on the first cylinder and the fourth cylinder; and

a second coil winded on the second cylinder and the fifth cylinder.20

13. The power converter system according to claim 12, wherein all of the first cylinder,

the second cylinder, the third cylinder, the fourth cylinder, the fifth cylinder and the

sixth cylinder are magnetic cylinders.

14. The power converter system according to claim 12 or 13, wherein the number of

windings of the first coil and the number of windings of the second coil can be 25

different.

15. The power converter system according to anyone of the claims 12 to 14, wherein the

dimensions of the first gap, the second gap and the third gap can be different.

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ABSTRACT

A power converter system and a coupled two-stage inductor are provided. The

power converter system includes a first power converting unit, a second power

converting unit and a common switch. The first power converting unit includes a first

inductor and a first capacitor. The first inductor is electrically connected to the first 5

capacitor. The second power converting unit includes a second inductor and a second

capacitor. The second inductor is electrically connected to the second capacitor. The

common switch is electrically connected to the first power converting unit and the second

power converting unit. The first power converting unit and the second power converting

unit are both operated with the common switch. When the common switch is conducted,10

the first power converting unit and the second power converting unit perform a two-stage

power converting procedure with in-phase and same time sequence.

(Fig. 1)

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