University of Notre Dame Lecture 19 - Intro to MQCA Nanomagnetic Logic Devices.

University of Notre Dame

Lecture 19 - Intro to MQCA

Nanomagnetic Logic Devices



Technology BackgroundSchematic

Device

Wire

Gate

Inverter

Experimental

i1

i3

i2

Inverted output

0 1

i o

i o

0

1

R. Cowburn, M. Welland, “Room temperature magnetic quantum cellular automata,” Science 287, 1466, 2000A. Imre, “Experimental Study of Nanomagnets for Magnetic QCA Logic Applications,” U. of Notre Dame, Ph.D. Dissertation.

M

A

C

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B MM

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B

A. Imre, et. al. “Magnetic Logic Devices Based on Field-Coupled Nanomagnets,” NanoGiga 2007.

A. Imre, et. al., “Majority logic gate for Magnetic Quantum-Dot Cellular Automata,” Science, vol. 311, No. 5758, pp. 205–208, January, 13, 2006.

A. Imre, et. al., “Majority logic gate for Magnetic Quantum-Dot Cellular Automata,” Science, vol. 311, No. 5758, pp. 205–208, January, 13, 2006.



Proposed Drive CircuitryIdea:

ProposedImplementation:

Hclock = 0 Hclock >> Hclock0

Can also changematerial aroundmagnets to increasepermeability

4



The Task at HandShow that MQCA can better state-of-the-art in

CMOS for systems-level, application-level tasks.

Suitable Architectures

Technology comparison only meaningful at systems-level(architecture important

consideration)

Aggregate system energy

1. Hysteresis loss in magnets

2. Cu wire resistance, parasitics3. Clock generation circuitry

Niemier, ISLPED, 2007

More complex circuits

Niemier, ICCD, 2008

Electrical/Magnetic Interface

DL Program Line

Free Tri-Layer

Tunnel Barrier

Pinning LayerProgram Line 1

Program Line 2

Free Tri-Layer

Tunnel Barrier

Pinning Layer

Ferromagnetic layerCoupling LayerFerromagnetic layer

Can an MQCA device provide this

functionality? Niemier, ICCD, 2008

Scalability

How small can devices be reliably made?

Fabrication Variation

What if we get this instead of

this?Niemier, DFTS, 2008

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Energy (from the magnets)• Until small feature sizes & minimum switching times, energy from magnets dwarfed by clock.

G. Csaba et. al., “Power Dissipation in Nanomagnetic Logic Devices,” 2004 4th IEEE Conference on Nanotechnology, p. 346-8

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Experimental Progress

Cu wire cladded on 3 sides w/permalloy

Nanomagnets of 4 different sizes have been placed on top

Fabrication

-108 mT

-78 mT

-64 mT

OOMMF

ModelingMaxw

ell

~ -70 mT

~ 100 mT

for J=107 A/cm2

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Logic with realistic fabrication constraints

What if:•New input applied to line in logically correct, AF ordered state?•Need correct switching with non-uniform, discontinuous fields

Newinput

Logically correct, AF ordered state

iii

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Integration with CMOS:

CMOS Logic

Nanomagnet logic

MQCAWhat goes here??

Kung, “Why Systolic Architectures,” IEEE Computer,

p. 36-47, Jan. 1982.

Map well to convolution, DFT, matrix multiply, sorting,

pattern matching...

Logic for Systolic Architectures

Data flows from memory in rhythmic fashion; passes through many PEs before returning to memory

Checkpointing Logic

Kogge, et. al. DARPA IPTO in the ExaScale Computing Study

Motivation: Device resiliency scaling:• Hard failures, SEUs, variability.Can recover via checkpoints•Copy application state to alternative storage medium to allow application to be stopped, restarted from medium (rollback)MQCA can provide dense, non-volatile shift registers (instead of flash?)

x2

y1

w3

w2

x1

w1

yin

xin

wi

xou

t

yout

yout = yin + wxinxout = xin

Device is both logic and memory!

University of Notre Dame Lecture 19 - Intro to MQCA Nanomagnetic Logic Devices.

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