University of Geneva 32-channel DRS4 Acquisition Board 01...

60
5 5 4 4 3 3 2 2 1 1 D D C C B B A A TOP FRONT PANEL FRONT PANEL FRONT PANEL REAR REAR REAR 02_01A DEBIEUX TCA modified : inversion of 100 MHz signal (U160), low-pass RC added at XTAL output AFE modified : 100 Ohms termination added at TCAL ends DRS1_OUT+ DRS1_OUT- DRS2_OUT+ DRS2_OUT- DRS3_OUT+ DRS3_OUT- DRS4_OUT+ DRS4_OUT- DAC_SCK DAC_SDI TCAE IN[1..32] IN1 IN2 IN3 IN4 IN5 IN6 IN7 IN8 IN9 IN10 IN11 IN12 IN13 IN14 IN15 IN17 IN18 IN19 IN20 IN21 IN22 IN23 IN24 IN25 IN26 IN27 IN28 IN29 IN30 IN31 IN16 IN32 TRIG[1..4] DDL_DATIN DDL_CLKIN DDL_DATOUT DDL_CLKOUT DDL_EN DRS1OUT[1..3] DRS2OUT[1..3] DRS3OUT[1..3] DRS4OUT[1..3] TS_SDO TS_SDI TS_SCK TS1CS TS2CS TS3CS TS4CS RESET ADC_CSB ADC_SCLK ADC_SDIO ADC_CLK+ ADC_CLK- ADC_FCO+ ADC_FCO- ADC_DCO+ ADC_DCO- ADC_OUT1+ ADC_OUT1- ADC_OUT2+ ADC_OUT2- ADC_OUT3+ ADC_OUT3- ADC_OUT4+ ADC_OUT4- DAC_CS VCALDIS SEL_CAL SEL_IN SEL_TC CXOE TCK TMS TDI TDO DRSIN[1..10] EXT_TCAL EXT_CLK- EXT_CLK+ UTXEN URXEN UTX[0..7] URX[0..7] FLAGA FLAGB DQ[31..0] A[1..0] PKTENDn SLWRn SLRDn SLOEn SLCSn CLK_USB UC_UART_RTSn UC_UART_CTSn UC_UART_RX UC_UART_TX CTL6 CTL8 CTL9 CTL10 GPIO50 GPIO51 UC_RESETn INTn TRIGIN_N_FP BUSY_N_FP TRIGIN_FP BUSY_FP TRIGIN[1..4] STAT[1..4] Size DWG NO Rev PCB Sheet of Rev PCBA CH-1211 GENEVE 4 02A University of Geneva DPNC342 Friday, October 14, 2016 1 60 A3 . DPNC 24 quai Ernest-Ansermet 32-channel DRS4 Acquisition Board Size DWG NO Rev PCB Sheet of Rev PCBA CH-1211 GENEVE 4 02A University of Geneva DPNC342 Friday, October 14, 2016 1 60 A3 . DPNC 24 quai Ernest-Ansermet 32-channel DRS4 Acquisition Board Size DWG NO Rev PCB Sheet of Rev PCBA CH-1211 GENEVE 4 02A University of Geneva DPNC342 Friday, October 14, 2016 1 60 A3 . DPNC 24 quai Ernest-Ansermet 32-channel DRS4 Acquisition Board Revisions Designer Description Initial revision 01_01A DEBIEUX Revisions Designer Description Initial revision 01_01A DEBIEUX Revisions Designer Description Initial revision 01_01A DEBIEUX J2 HE10 M/RA P2.54 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 35 36 J1 HE10 M/RA P2.54 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 35 36 R1 56 1% TP1 TP RND1.0 SMD 1 DDL_1 DDL_LINK DATA_IN CLK_IN DATA_OUT CLK_OUT ENABLE D1 5V PWR_1 POWER NTL_1 NIM_TO_LVTTL IN OUT FPGA_1 FPGA RESETOUT SLRDn SLWRn FLAGA FLAGB SLOEn PKTENDn SLCSn ADC_DCO+ ADC_DCO- ADC_FCO+ ADC_FCO- ADC_OUT1+ ADC_OUT2+ ADC_OUT3+ ADC_OUT4+ ADC_OUT1- ADC_OUT2- ADC_OUT3- ADC_OUT4- TS_SDO TS_SDI TS_SCK TS1CS DAC_SCK DAC_SDI ADC_CSB ADC_SCLK ADC_SDIO ADC_CLK+ ADC_CLK- TCAE TS2CS TS3CS TS4CS TRIG[1..4] DAC_CS DDL_EN DDL_CLKOUT DDL_DATOUT DDL_CLKIN DDL_DATIN DRS1OUT[1..3] DRS2OUT[1..3] DRS3OUT[1..3] DRS4OUT[1..3] VCALDIS SEL_CAL SEL_IN SEL_TC CXOE TCK TMS TDI TDO DRSIN[1..10] URXEN UTXEN URX[0..7] UTX[0..7] DQ[31..0] A[1..0] CLK_USB UC_UART_RTSn UC_UART_CTSn UC_UART_TX UC_UART_RX CTL6 CTL8 CTL9 CTL10 GPIO50 GPIO51 UC_RESETn INTn TRIGIN_FP BUSY_FP STAT[1..4] TRIGIN[1..4] USRIO_1 USRIO UTX[0..7] URX[0..7] UTXEN URXEN J3 LEMO F/RA 50R 2 1 ADC_1 ADC IN1+ IN1- IN2+ IN2- IN3+ IN3- IN4+ IN4- OUT1+ OUT1- OUT2+ OUT2- OUT3+ OUT3- OUT4+ OUT4- DCO+ DCO- FCO+ FCO- CLK+ CLK- CSB SCLK SDIO LTN_1 LVTTL_TO_NIM IN OUT J4 LEMO F/RA 50R 3 1 2 DRS4X32CH_1 DRS4X32CH OUTM1+ OUTM2+ OUTM3+ OUTM4+ OUTM1- OUTM2- OUTM3- OUTM4- EXT_CLK+ DRS1OUT[1..3] DRS2OUT[1..3] DRS3OUT[1..3] DRS4OUT[1..3] IN[1..32] TRIG[1..4] RESET TS_SDO TS_SDI TS_SCK TS4CS TS3CS TS2CS TS1CS DAC_CS DAC_SCK DAC_SDI EXT_TCAL TCAE VCALDIS EXT_CLK- SEL_IN SEL_CAL CXOE SEL_TC DRSIN[1..10] MICRO_1 MICROCONTROLLER FLAGA FLAGB DQ[31..0] A[1..0] PKTENDn SLWRn SLRDn SLOEn SLCSn CLK UART_RTSn UART_CTSn UART_RX UART_TX CTL6 CTL8 CTL9 CTL10 GPIO50 GPIO51 RESETn INTn VMECON_1 VMECON EXT_CLK+ EXT_CLK- TCK TMS TDI TDO TRIGIN[1..4] STAT[1..4]

Transcript of University of Geneva 32-channel DRS4 Acquisition Board 01...

Page 1: University of Geneva 32-channel DRS4 Acquisition Board 01 ...dpnc.unige.ch/~bravar/DRSSS/DPNC342_02_01A_A60.pdf · CH-1211 GENEVE 4 02A University of Geneva DPNC342 Friday, October

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

TOP

FRONT PANEL

FRONT PANEL

FRONT PANEL

REAR

REAR

REAR

02_01A DEBIEUX TCA modified : inversion of 100 MHz signal (U160), low-pass RC added at XTAL outputAFE modified : 100 Ohms termination added at TCAL ends

DRS1_OUT+DRS1_OUT-

DRS2_OUT+DRS2_OUT-

DRS3_OUT+DRS3_OUT-

DRS4_OUT+DRS4_OUT-

DAC_SCKDAC_SDI

TCAE

IN[1..32]

IN1IN2IN3IN4IN5IN6IN7IN8IN9IN10IN11IN12IN13IN14IN15

IN17IN18IN19IN20IN21IN22IN23IN24IN25IN26IN27IN28IN29IN30IN31

IN16

IN32

TRIG[1..4]

DDL_DATINDDL_CLKIN

DDL_DATOUTDDL_CLKOUT

DDL_EN

DRS1OUT[1..3]

DRS2OUT[1..3]

DRS3OUT[1..3]

DRS4OUT[1..3]

TS_SDOTS_SDITS_SCK

TS1CSTS2CSTS3CSTS4CS

RESET

ADC_CSBADC_SCLKADC_SDIO

ADC_CLK+ADC_CLK-

ADC_FCO+ADC_FCO-ADC_DCO+ADC_DCO-

ADC_OUT1+ADC_OUT1-ADC_OUT2+ADC_OUT2-ADC_OUT3+ADC_OUT3-ADC_OUT4+ADC_OUT4-

DAC_CS

VCALDIS

SEL_CALSEL_INSEL_TC

CXOE

TCKTMSTDITDO

DRSIN[1..10]

EXT_TCAL

EXT_CLK-EXT_CLK+

UTXEN

URXENUTX[0..7]

URX[0..7]

FLAGAFLAGB

DQ[31..0]A[1..0]

PKTENDnSLWRnSLRDnSLOEnSLCSn

CLK_USB

UC_UART_RTSnUC_UART_CTSn

UC_UART_RXUC_UART_TX

CTL6CTL8CTL9CTL10GPIO50GPIO51

UC_RESETn

INTn

TRIGIN_N_FP

BUSY_N_FP

TRIGIN_FP

BUSY_FP

TRIGIN[1..4]STAT[1..4]

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH-1211 GENEVE 4

02A

University of Geneva

DPNC342

Friday, October 14, 20161 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition Board

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH-1211 GENEVE 4

02A

University of Geneva

DPNC342

Friday, October 14, 20161 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition Board

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH-1211 GENEVE 4

02A

University of Geneva

DPNC342

Friday, October 14, 20161 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardRevisions Designer DescriptionInitial revision01_01A DEBIEUX

Revisions Designer DescriptionInitial revision01_01A DEBIEUX

Revisions Designer DescriptionInitial revision01_01A DEBIEUX

J2

HE10M/RAP2.54

13579

111315171921232527293133

246810121416182022242628303234

3536

J1

HE10M/RAP2.54

13579

111315171921232527293133

246810121416182022242628303234

3536

R1561%

TP1TPRND1.0SMD1

DDL_1

DDL_LINK

DATA_INCLK_IN

DATA_OUTCLK_OUT

ENABLE

D15V

PWR_1

POWER

NTL_1

NIM_TO_LVTTL

INOUT

FPGA_1

FPGA

RESETOUT

SLRDnSLWRn

FLAGAFLAGB

SLOEn

PKTENDn

SLCSn

ADC_DCO+ADC_DCO-

ADC_FCO+ADC_FCO-

ADC_OUT1+

ADC_OUT2+

ADC_OUT3+

ADC_OUT4+

ADC_OUT1-

ADC_OUT2-

ADC_OUT3-

ADC_OUT4-

TS_SDOTS_SDITS_SCK

TS1CS

DAC_SCKDAC_SDI

ADC_CSBADC_SCLKADC_SDIO

ADC_CLK+ADC_CLK-

TC

AE

TS2CSTS3CSTS4CS

TR

IG[1

..4]

DAC_CS

DDL_EN

DDL_CLKOUTDDL_DATOUT

DDL_CLKINDDL_DATIN

DRS1OUT[1..3]

DRS2OUT[1..3]

DRS3OUT[1..3]

DRS4OUT[1..3]

VC

ALD

IS

SE

L_C

AL

SE

L_IN

SE

L_T

CC

XO

E

TC

KT

MS

TD

IT

DO

DRSIN[1..10]

UR

XE

N

UT

XE

N

UR

X[0

..7]

UT

X[0

..7]

DQ[31..0]A[1..0]

CLK_USB

UC_UART_RTSnUC_UART_CTSn

UC_UART_TXUC_UART_RX

CTL6CTL8CTL9

CTL10GPIO50GPIO51

UC_RESETn

INTn

TR

IGIN

_FP

BU

SY

_FP

ST

AT

[1..4

]T

RIG

IN[1

..4]

USRIO_1

USRIO

UTX[0..7]

URX[0..7]

UTXEN

URXEN

J3

LEMOF/RA50R

21

ADC_1

ADC

IN1+IN1-

IN2+IN2-

IN3+IN3-

IN4+IN4-

OUT1+OUT1-OUT2+OUT2-OUT3+OUT3-OUT4+OUT4-

DCO+DCO-

FCO+FCO-

CLK+CLK-

CSBSCLKSDIO

LTN_1

LVTTL_TO_NIM

IN OUT

J4

LEMOF/RA50R

3

1

2

DRS4X32CH_1

DRS4X32CH

OUTM1+

OUTM2+

OUTM3+

OUTM4+

OUTM1-

OUTM2-

OUTM3-

OUTM4-

EXT_CLK+

DRS1OUT[1..3]

DRS2OUT[1..3]

DRS3OUT[1..3]

DRS4OUT[1..3]IN[1..32]

TRIG[1..4] RESET

TS_SDOTS_SDI

TS_SCKTS4CSTS3CSTS2CSTS1CS

DAC_CSDAC_SCKDAC_SDI

EXT_TCAL

TCAEVCALDIS

EXT_CLK-

SEL_INSEL_CAL

CXOESEL_TC

DRSIN[1..10]

MICRO_1

MICROCONTROLLER

FLAGAFLAGB

DQ[31..0]A[1..0]

PKTENDnSLWRnSLRDnSLOEnSLCSn

CLK

UART_RTSnUART_CTSn

UART_RXUART_TX

CTL6CTL8CTL9CTL10GPIO50GPIO51

RESETn

INTn

VMECON_1

VMECON

EXT_CLK+EXT_CLK-

TCKTMSTDI

TDO

TRIGIN[1..4]STAT[1..4]

Page 2: University of Geneva 32-channel DRS4 Acquisition Board 01 ...dpnc.unige.ch/~bravar/DRSSS/DPNC342_02_01A_A60.pdf · CH-1211 GENEVE 4 02A University of Geneva DPNC342 Friday, October

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

ADC

IMPORTANT:low ESR capacitorsrequired

WARNING:1.8V LOGIC LEVELFOR SPI BUS

WARNING:LVDS, MAX 1.8V

NCVIN

IN1+

IN1-

IN2+

IN2-

IN3+

IN3-

IN4+

IN4-

OUT1+OUT1-

OUT2+OUT2-

OUT3+OUT3-

OUT4+OUT4-

DCO+DCO-

FCO+FCO-

CLK+

CLK-

CSB

SCLK

SDIO

+1.8V_A +1.8V

+1.8V_A

+1.8V

+1.8V

+1.8V_A

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Thursday, September 29, 20162 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardSchematic Path = /ADC_1

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Thursday, September 29, 20162 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardSchematic Path = /ADC_1

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Thursday, September 29, 20162 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardSchematic Path = /ADC_1

R524

C1100nF10V

C14100nF10V

R121005%

R924

R1410K1%

C221uF10V

C4100nF10V

C12100nF10V

R624

C6100nF10V

C1933pF

R424

C15100nF10V

C20

100nF 10V

R824

R310K1%

C2100nF10V

C1733pF

C7100nF10V

C9100nF10V

C13100nF10V

R1510K1%

C1633pF

C1833pF

C8100nF10V

R1124

C10100nF10V

C21

100nF 10VR13

10K 1%

R210K1%

C24100nF10V

U3

AD963712-bits

40MSPS

VIN-C50

VIN+A43

VIN-A44

AG

ND

/EP

65

D+A34

D-A33

D+B32

D-B31

D+C30

D-C29

D+D28

D-D27

D+E22

D-E21

D+F20

D-F19

VIN+B47

VIN-B46

VIN+C49

VIN+D53

VIN-D52

VIN+E60

VIN+F64

VIN+G2

VIN+H6

VIN-E61

VIN-F63

VIN-G3

VIN-H5

D+G18

D+H16

D-G17

D-H15

AV

DD

1

AV

DD

4

AV

DD

7

AV

DD

8

AV

DD

11

AV

DD

12

AV

DD

37

AV

DD

42

AV

DD

45

AV

DD

48

AV

DD

51

AV

DD

59

AV

DD

62

DR

VD

D14

DR

VD

D35

CLK+10

CLK-9 DCO+

24

DCO-23

FCO+26

FCO-25SCLK/DTP

38

SDIO/DFS39

CSB40

PD

WN

41

RB

IAS

54

VCM57

SYNC58

SENSE55 VREF56

C23100nF10V

R724

C3100nF10V

C11100nF10V

C5100nF10V

R1024

Page 3: University of Geneva 32-channel DRS4 Acquisition Board 01 ...dpnc.unige.ch/~bravar/DRSSS/DPNC342_02_01A_A60.pdf · CH-1211 GENEVE 4 02A University of Geneva DPNC342 Friday, October

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

ANALOG FRONT-END STAGE

SEL_IN SEL_CAL

00

0

X

1

1 Input Signal (SiPM)

Voltage Calibration

Timing Calibration

Output/Function

SELECTION TABLE

Inversion to allow a -0.9V to +0.1Vinput rangeThis is a constraint from the DRS4readout buffer that cannot handledifferential input below -0.55V.

V+ V-

V+

V-

V+ V-

V+

V+

V- V-

TRIG

OUTP

OUTN

IN

VOCM

VCALTCAL

SEL_IN

SEL_CAL

V-

V+

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Monday, October 03, 20163 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardSchematic Path = /DRS4X32CH_1/DRS4X8CH_1/AFE_1

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Monday, October 03, 20163 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardSchematic Path = /DRS4X32CH_1/DRS4X8CH_1/AFE_1

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Monday, October 03, 20163 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardSchematic Path = /DRS4X32CH_1/DRS4X8CH_1/AFE_1

C33100nF10V

C291nF50V

R19751%

R4001005%

C30100nF10V

G=1

U8

ADV3219

IN01

V+

4

SEL8

IN13

V-

5

GN

D2

OUT6

EN7 R16

33 1%

C34100nF10V

C32100nF10V

R20

33 1%R18751%

C261nF50V

C28100nF10V

-

+

PD

VOCM

V+

V- EPAD

U9

ADA4950-1750MHz

2

3

11

513

10

9

12

1

4

17

D25V

G=1

U10

ADV3219

IN01

V+

4

SEL8

IN13

V-

5

GN

D2

OUT6

EN7

C31100nF10V

R17

75 1%

C27100nF10V

C25100nF10V

Page 4: University of Geneva 32-channel DRS4 Acquisition Board 01 ...dpnc.unige.ch/~bravar/DRSSS/DPNC342_02_01A_A60.pdf · CH-1211 GENEVE 4 02A University of Geneva DPNC342 Friday, October

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

ANALOG FRONT-END STAGE

SEL_IN SEL_CAL

00

0

X

1

1 Input Signal (SiPM)

Voltage Calibration

Timing Calibration

Output/Function

SELECTION TABLE

Inversion to allow a -0.9V to +0.1Vinput rangeThis is a constraint from the DRS4readout buffer that cannot handledifferential input below -0.55V.

V+ V-

V+

V-

V+ V-

V+

V+

V- V-

TRIG

OUTP

OUTN

IN

VOCM

VCALTCAL

SEL_IN

SEL_CAL

V-

V+

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Monday, October 03, 20164 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardSchematic Path = /DRS4X32CH_1/DRS4X8CH_1/AFE_2

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Monday, October 03, 20164 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardSchematic Path = /DRS4X32CH_1/DRS4X8CH_1/AFE_2

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Monday, October 03, 20164 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardSchematic Path = /DRS4X32CH_1/DRS4X8CH_1/AFE_2

C43100nF10V

C391nF50V

R24751%

R4011005%

C40100nF10V

G=1

U11

ADV3219

IN01

V+

4

SEL8

IN13

V-

5

GN

D2

OUT6

EN7 R21

33 1%

C44100nF10V

C42100nF10V

R25

33 1%R23751%

C361nF50V

C38100nF10V

-

+

PD

VOCM

V+

V- EPAD

U12

ADA4950-1750MHz

2

3

11

513

10

9

12

1

4

17

D35V

G=1

U13

ADV3219

IN01

V+

4

SEL8

IN13

V-

5

GN

D2

OUT6

EN7

C41100nF10V

R22

75 1%

C37100nF10V

C35100nF10V

Page 5: University of Geneva 32-channel DRS4 Acquisition Board 01 ...dpnc.unige.ch/~bravar/DRSSS/DPNC342_02_01A_A60.pdf · CH-1211 GENEVE 4 02A University of Geneva DPNC342 Friday, October

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

ANALOG FRONT-END STAGE

SEL_IN SEL_CAL

00

0

X

1

1 Input Signal (SiPM)

Voltage Calibration

Timing Calibration

Output/Function

SELECTION TABLE

Inversion to allow a -0.9V to +0.1Vinput rangeThis is a constraint from the DRS4readout buffer that cannot handledifferential input below -0.55V.

V+ V-

V+

V-

V+ V-

V+

V+

V- V-

TRIG

OUTP

OUTN

IN

VOCM

VCALTCAL

SEL_IN

SEL_CAL

V-

V+

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Monday, October 03, 20165 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardSchematic Path = /DRS4X32CH_1/DRS4X8CH_1/AFE_3

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Monday, October 03, 20165 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardSchematic Path = /DRS4X32CH_1/DRS4X8CH_1/AFE_3

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Monday, October 03, 20165 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardSchematic Path = /DRS4X32CH_1/DRS4X8CH_1/AFE_3

C53100nF10V

C491nF50V

R29751%

R4021005%

C50100nF10V

G=1

U14

ADV3219

IN01

V+

4

SEL8

IN13

V-

5

GN

D2

OUT6

EN7 R26

33 1%

C54100nF10V

C52100nF10V

R30

33 1%R28751%

C461nF50V

C48100nF10V

-

+

PD

VOCM

V+

V- EPAD

U15

ADA4950-1750MHz

2

3

11

513

10

9

12

1

4

17

D45V

G=1

U16

ADV3219

IN01

V+

4

SEL8

IN13

V-

5

GN

D2

OUT6

EN7

C51100nF10V

R27

75 1%

C47100nF10V

C45100nF10V

Page 6: University of Geneva 32-channel DRS4 Acquisition Board 01 ...dpnc.unige.ch/~bravar/DRSSS/DPNC342_02_01A_A60.pdf · CH-1211 GENEVE 4 02A University of Geneva DPNC342 Friday, October

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

ANALOG FRONT-END STAGE

SEL_IN SEL_CAL

00

0

X

1

1 Input Signal (SiPM)

Voltage Calibration

Timing Calibration

Output/Function

SELECTION TABLE

Inversion to allow a -0.9V to +0.1Vinput rangeThis is a constraint from the DRS4readout buffer that cannot handledifferential input below -0.55V.

V+ V-

V+

V-

V+ V-

V+

V+

V- V-

TRIG

OUTP

OUTN

IN

VOCM

VCALTCAL

SEL_IN

SEL_CAL

V-

V+

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Monday, October 03, 20166 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardSchematic Path = /DRS4X32CH_1/DRS4X8CH_1/AFE_4

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Monday, October 03, 20166 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardSchematic Path = /DRS4X32CH_1/DRS4X8CH_1/AFE_4

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Monday, October 03, 20166 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardSchematic Path = /DRS4X32CH_1/DRS4X8CH_1/AFE_4

C63100nF10V

C591nF50V

R34751%

R4031005%

C60100nF10V

G=1

U17

ADV3219

IN01

V+

4

SEL8

IN13

V-

5

GN

D2

OUT6

EN7 R31

33 1%

C64100nF10V

C62100nF10V

R35

33 1%R33751%

C561nF50V

C58100nF10V

-

+

PD

VOCM

V+

V- EPAD

U18

ADA4950-1750MHz

2

3

11

513

10

9

12

1

4

17

D55V

G=1

U19

ADV3219

IN01

V+

4

SEL8

IN13

V-

5

GN

D2

OUT6

EN7

C61100nF10V

R32

75 1%

C57100nF10V

C55100nF10V

Page 7: University of Geneva 32-channel DRS4 Acquisition Board 01 ...dpnc.unige.ch/~bravar/DRSSS/DPNC342_02_01A_A60.pdf · CH-1211 GENEVE 4 02A University of Geneva DPNC342 Friday, October

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

ANALOG FRONT-END STAGE

SEL_IN SEL_CAL

00

0

X

1

1 Input Signal (SiPM)

Voltage Calibration

Timing Calibration

Output/Function

SELECTION TABLE

Inversion to allow a -0.9V to +0.1Vinput rangeThis is a constraint from the DRS4readout buffer that cannot handledifferential input below -0.55V.

V+ V-

V+

V-

V+ V-

V+

V+

V- V-

TRIG

OUTP

OUTN

IN

VOCM

VCALTCAL

SEL_IN

SEL_CAL

V-

V+

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Monday, October 03, 20167 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardSchematic Path = /DRS4X32CH_1/DRS4X8CH_1/AFE_5

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Monday, October 03, 20167 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardSchematic Path = /DRS4X32CH_1/DRS4X8CH_1/AFE_5

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Monday, October 03, 20167 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardSchematic Path = /DRS4X32CH_1/DRS4X8CH_1/AFE_5

C73100nF10V

C691nF50V

R39751%

R4041005%

C70100nF10V

G=1

U20

ADV3219

IN01

V+

4

SEL8

IN13

V-

5

GN

D2

OUT6

EN7 R36

33 1%

C74100nF10V

C72100nF10V

R40

33 1%R38751%

C661nF50V

C68100nF10V

-

+

PD

VOCM

V+

V- EPAD

U21

ADA4950-1750MHz

2

3

11

513

10

9

12

1

4

17

D65V

G=1

U22

ADV3219

IN01

V+

4

SEL8

IN13

V-

5

GN

D2

OUT6

EN7

C71100nF10V

R37

75 1%

C67100nF10V

C65100nF10V

Page 8: University of Geneva 32-channel DRS4 Acquisition Board 01 ...dpnc.unige.ch/~bravar/DRSSS/DPNC342_02_01A_A60.pdf · CH-1211 GENEVE 4 02A University of Geneva DPNC342 Friday, October

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

ANALOG FRONT-END STAGE

SEL_IN SEL_CAL

00

0

X

1

1 Input Signal (SiPM)

Voltage Calibration

Timing Calibration

Output/Function

SELECTION TABLE

Inversion to allow a -0.9V to +0.1Vinput rangeThis is a constraint from the DRS4readout buffer that cannot handledifferential input below -0.55V.

V+ V-

V+

V-

V+ V-

V+

V+

V- V-

TRIG

OUTP

OUTN

IN

VOCM

VCALTCAL

SEL_IN

SEL_CAL

V-

V+

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Monday, October 03, 20168 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardSchematic Path = /DRS4X32CH_1/DRS4X8CH_1/AFE_6

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Monday, October 03, 20168 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardSchematic Path = /DRS4X32CH_1/DRS4X8CH_1/AFE_6

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Monday, October 03, 20168 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardSchematic Path = /DRS4X32CH_1/DRS4X8CH_1/AFE_6

C83100nF10V

C791nF50V

R44751%

R4051005%

C80100nF10V

G=1

U23

ADV3219

IN01

V+

4

SEL8

IN13

V-

5

GN

D2

OUT6

EN7 R41

33 1%

C84100nF10V

C82100nF10V

R45

33 1%R43751%

C761nF50V

C78100nF10V

-

+

PD

VOCM

V+

V- EPAD

U24

ADA4950-1750MHz

2

3

11

513

10

9

12

1

4

17

D75V

G=1

U25

ADV3219

IN01

V+

4

SEL8

IN13

V-

5

GN

D2

OUT6

EN7

C81100nF10V

R42

75 1%

C77100nF10V

C75100nF10V

Page 9: University of Geneva 32-channel DRS4 Acquisition Board 01 ...dpnc.unige.ch/~bravar/DRSSS/DPNC342_02_01A_A60.pdf · CH-1211 GENEVE 4 02A University of Geneva DPNC342 Friday, October

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

ANALOG FRONT-END STAGE

SEL_IN SEL_CAL

00

0

X

1

1 Input Signal (SiPM)

Voltage Calibration

Timing Calibration

Output/Function

SELECTION TABLE

Inversion to allow a -0.9V to +0.1Vinput rangeThis is a constraint from the DRS4readout buffer that cannot handledifferential input below -0.55V.

V+ V-

V+

V-

V+ V-

V+

V+

V- V-

TRIG

OUTP

OUTN

IN

VOCM

VCALTCAL

SEL_IN

SEL_CAL

V-

V+

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Monday, October 03, 20169 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardSchematic Path = /DRS4X32CH_1/DRS4X8CH_1/AFE_7

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Monday, October 03, 20169 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardSchematic Path = /DRS4X32CH_1/DRS4X8CH_1/AFE_7

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Monday, October 03, 20169 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardSchematic Path = /DRS4X32CH_1/DRS4X8CH_1/AFE_7

C93100nF10V

C891nF50V

R49751%

R4061005%

C90100nF10V

G=1

U26

ADV3219

IN01

V+

4

SEL8

IN13

V-

5

GN

D2

OUT6

EN7 R46

33 1%

C94100nF10V

C92100nF10V

R50

33 1%R48751%

C861nF50V

C88100nF10V

-

+

PD

VOCM

V+

V- EPAD

U27

ADA4950-1750MHz

2

3

11

513

10

9

12

1

4

17

D85V

G=1

U28

ADV3219

IN01

V+

4

SEL8

IN13

V-

5

GN

D2

OUT6

EN7

C91100nF10V

R47

75 1%

C87100nF10V

C85100nF10V

Page 10: University of Geneva 32-channel DRS4 Acquisition Board 01 ...dpnc.unige.ch/~bravar/DRSSS/DPNC342_02_01A_A60.pdf · CH-1211 GENEVE 4 02A University of Geneva DPNC342 Friday, October

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

ANALOG FRONT-END STAGE

SEL_IN SEL_CAL

00

0

X

1

1 Input Signal (SiPM)

Voltage Calibration

Timing Calibration

Output/Function

SELECTION TABLE

Inversion to allow a -0.9V to +0.1Vinput rangeThis is a constraint from the DRS4readout buffer that cannot handledifferential input below -0.55V.

V+ V-

V+

V-

V+ V-

V+

V+

V- V-

TRIG

OUTP

OUTN

IN

VOCM

VCALTCAL

SEL_IN

SEL_CAL

V-

V+

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Monday, October 03, 201610 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardSchematic Path = /DRS4X32CH_1/DRS4X8CH_1/AFE_8

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Monday, October 03, 201610 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardSchematic Path = /DRS4X32CH_1/DRS4X8CH_1/AFE_8

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Monday, October 03, 201610 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardSchematic Path = /DRS4X32CH_1/DRS4X8CH_1/AFE_8

C103100nF10V

C991nF50V

R54751%

R4071005%

C100100nF10V

G=1

U29

ADV3219

IN01

V+

4

SEL8

IN13

V-

5

GN

D2

OUT6

EN7 R51

33 1%

C104100nF10V

C102100nF10V

R55

33 1%R53751%

C961nF50V

C98100nF10V

-

+

PD

VOCM

V+

V- EPAD

U30

ADA4950-1750MHz

2

3

11

513

10

9

12

1

4

17

D95V

G=1

U31

ADV3219

IN01

V+

4

SEL8

IN13

V-

5

GN

D2

OUT6

EN7

C101100nF10V

R52

75 1%

C97100nF10V

C95100nF10V

Page 11: University of Geneva 32-channel DRS4 Acquisition Board 01 ...dpnc.unige.ch/~bravar/DRSSS/DPNC342_02_01A_A60.pdf · CH-1211 GENEVE 4 02A University of Geneva DPNC342 Friday, October

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

ANALOG FRONT-END STAGE

SEL_IN SEL_CAL

00

0

X

1

1 Input Signal (SiPM)

Voltage Calibration

Timing Calibration

Output/Function

SELECTION TABLE

Inversion to allow a -0.9V to +0.1Vinput rangeThis is a constraint from the DRS4readout buffer that cannot handledifferential input below -0.55V.

V+ V-

V+

V-

V+ V-

V+

V+

V- V-

TRIG

OUTP

OUTN

IN

VOCM

VCALTCAL

SEL_IN

SEL_CAL

V-

V+

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Monday, October 03, 201611 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardSchematic Path = /DRS4X32CH_1/DRS4X8CH_2/AFE_1

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Monday, October 03, 201611 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardSchematic Path = /DRS4X32CH_1/DRS4X8CH_2/AFE_1

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Monday, October 03, 201611 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardSchematic Path = /DRS4X32CH_1/DRS4X8CH_2/AFE_1

C113100nF10V

C1091nF50V

R59751%

R4081005%

C110100nF10V

G=1

U32

ADV3219

IN01

V+

4

SEL8

IN13

V-

5

GN

D2

OUT6

EN7 R56

33 1%

C114100nF10V

C112100nF10V

R60

33 1%R58751%

C1061nF50V

C108100nF10V

-

+

PD

VOCM

V+

V- EPAD

U33

ADA4950-1750MHz

2

3

11

513

10

9

12

1

4

17

D105V

G=1

U34

ADV3219

IN01

V+

4

SEL8

IN13

V-

5

GN

D2

OUT6

EN7

C111100nF10V

R57

75 1%

C107100nF10V

C105100nF10V

Page 12: University of Geneva 32-channel DRS4 Acquisition Board 01 ...dpnc.unige.ch/~bravar/DRSSS/DPNC342_02_01A_A60.pdf · CH-1211 GENEVE 4 02A University of Geneva DPNC342 Friday, October

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

ANALOG FRONT-END STAGE

SEL_IN SEL_CAL

00

0

X

1

1 Input Signal (SiPM)

Voltage Calibration

Timing Calibration

Output/Function

SELECTION TABLE

Inversion to allow a -0.9V to +0.1Vinput rangeThis is a constraint from the DRS4readout buffer that cannot handledifferential input below -0.55V.

V+ V-

V+

V-

V+ V-

V+

V+

V- V-

TRIG

OUTP

OUTN

IN

VOCM

VCALTCAL

SEL_IN

SEL_CAL

V-

V+

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Monday, October 03, 201612 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardSchematic Path = /DRS4X32CH_1/DRS4X8CH_2/AFE_2

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Monday, October 03, 201612 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardSchematic Path = /DRS4X32CH_1/DRS4X8CH_2/AFE_2

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Monday, October 03, 201612 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardSchematic Path = /DRS4X32CH_1/DRS4X8CH_2/AFE_2

C123100nF10V

C1191nF50V

R64751%

R4091005%

C120100nF10V

G=1

U35

ADV3219

IN01

V+

4

SEL8

IN13

V-

5

GN

D2

OUT6

EN7 R61

33 1%

C124100nF10V

C122100nF10V

R65

33 1%R63751%

C1161nF50V

C118100nF10V

-

+

PD

VOCM

V+

V- EPAD

U36

ADA4950-1750MHz

2

3

11

513

10

9

12

1

4

17

D115V

G=1

U37

ADV3219

IN01

V+

4

SEL8

IN13

V-

5

GN

D2

OUT6

EN7

C121100nF10V

R62

75 1%

C117100nF10V

C115100nF10V

Page 13: University of Geneva 32-channel DRS4 Acquisition Board 01 ...dpnc.unige.ch/~bravar/DRSSS/DPNC342_02_01A_A60.pdf · CH-1211 GENEVE 4 02A University of Geneva DPNC342 Friday, October

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

ANALOG FRONT-END STAGE

SEL_IN SEL_CAL

00

0

X

1

1 Input Signal (SiPM)

Voltage Calibration

Timing Calibration

Output/Function

SELECTION TABLE

Inversion to allow a -0.9V to +0.1Vinput rangeThis is a constraint from the DRS4readout buffer that cannot handledifferential input below -0.55V.

V+ V-

V+

V-

V+ V-

V+

V+

V- V-

TRIG

OUTP

OUTN

IN

VOCM

VCALTCAL

SEL_IN

SEL_CAL

V-

V+

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Monday, October 03, 201613 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardSchematic Path = /DRS4X32CH_1/DRS4X8CH_2/AFE_3

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Monday, October 03, 201613 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardSchematic Path = /DRS4X32CH_1/DRS4X8CH_2/AFE_3

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Monday, October 03, 201613 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardSchematic Path = /DRS4X32CH_1/DRS4X8CH_2/AFE_3

C133100nF10V

C1291nF50V

R69751%

R4101005%

C130100nF10V

G=1

U38

ADV3219

IN01

V+

4

SEL8

IN13

V-

5

GN

D2

OUT6

EN7 R66

33 1%

C134100nF10V

C132100nF10V

R70

33 1%R68751%

C1261nF50V

C128100nF10V

-

+

PD

VOCM

V+

V- EPAD

U39

ADA4950-1750MHz

2

3

11

513

10

9

12

1

4

17

D125V

G=1

U40

ADV3219

IN01

V+

4

SEL8

IN13

V-

5

GN

D2

OUT6

EN7

C131100nF10V

R67

75 1%

C127100nF10V

C125100nF10V

Page 14: University of Geneva 32-channel DRS4 Acquisition Board 01 ...dpnc.unige.ch/~bravar/DRSSS/DPNC342_02_01A_A60.pdf · CH-1211 GENEVE 4 02A University of Geneva DPNC342 Friday, October

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

ANALOG FRONT-END STAGE

SEL_IN SEL_CAL

00

0

X

1

1 Input Signal (SiPM)

Voltage Calibration

Timing Calibration

Output/Function

SELECTION TABLE

Inversion to allow a -0.9V to +0.1Vinput rangeThis is a constraint from the DRS4readout buffer that cannot handledifferential input below -0.55V.

V+ V-

V+

V-

V+ V-

V+

V+

V- V-

TRIG

OUTP

OUTN

IN

VOCM

VCALTCAL

SEL_IN

SEL_CAL

V-

V+

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Monday, October 03, 201614 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardSchematic Path = /DRS4X32CH_1/DRS4X8CH_2/AFE_4

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Monday, October 03, 201614 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardSchematic Path = /DRS4X32CH_1/DRS4X8CH_2/AFE_4

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Monday, October 03, 201614 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardSchematic Path = /DRS4X32CH_1/DRS4X8CH_2/AFE_4

C143100nF10V

C1391nF50V

R74751%

R4111005%

C140100nF10V

G=1

U41

ADV3219

IN01

V+

4

SEL8

IN13

V-

5

GN

D2

OUT6

EN7 R71

33 1%

C144100nF10V

C142100nF10V

R75

33 1%R73751%

C1361nF50V

C138100nF10V

-

+

PD

VOCM

V+

V- EPAD

U42

ADA4950-1750MHz

2

3

11

513

10

9

12

1

4

17

D135V

G=1

U43

ADV3219

IN01

V+

4

SEL8

IN13

V-

5

GN

D2

OUT6

EN7

C141100nF10V

R72

75 1%

C137100nF10V

C135100nF10V

Page 15: University of Geneva 32-channel DRS4 Acquisition Board 01 ...dpnc.unige.ch/~bravar/DRSSS/DPNC342_02_01A_A60.pdf · CH-1211 GENEVE 4 02A University of Geneva DPNC342 Friday, October

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

ANALOG FRONT-END STAGE

SEL_IN SEL_CAL

00

0

X

1

1 Input Signal (SiPM)

Voltage Calibration

Timing Calibration

Output/Function

SELECTION TABLE

Inversion to allow a -0.9V to +0.1Vinput rangeThis is a constraint from the DRS4readout buffer that cannot handledifferential input below -0.55V.

V+ V-

V+

V-

V+ V-

V+

V+

V- V-

TRIG

OUTP

OUTN

IN

VOCM

VCALTCAL

SEL_IN

SEL_CAL

V-

V+

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Monday, October 03, 201615 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardSchematic Path = /DRS4X32CH_1/DRS4X8CH_2/AFE_5

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Monday, October 03, 201615 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardSchematic Path = /DRS4X32CH_1/DRS4X8CH_2/AFE_5

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Monday, October 03, 201615 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardSchematic Path = /DRS4X32CH_1/DRS4X8CH_2/AFE_5

C153100nF10V

C1491nF50V

R79751%

R4121005%

C150100nF10V

G=1

U44

ADV3219

IN01

V+

4

SEL8

IN13

V-

5

GN

D2

OUT6

EN7 R76

33 1%

C154100nF10V

C152100nF10V

R80

33 1%R78751%

C1461nF50V

C148100nF10V

-

+

PD

VOCM

V+

V- EPAD

U45

ADA4950-1750MHz

2

3

11

513

10

9

12

1

4

17

D145V

G=1

U46

ADV3219

IN01

V+

4

SEL8

IN13

V-

5

GN

D2

OUT6

EN7

C151100nF10V

R77

75 1%

C147100nF10V

C145100nF10V

Page 16: University of Geneva 32-channel DRS4 Acquisition Board 01 ...dpnc.unige.ch/~bravar/DRSSS/DPNC342_02_01A_A60.pdf · CH-1211 GENEVE 4 02A University of Geneva DPNC342 Friday, October

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

ANALOG FRONT-END STAGE

SEL_IN SEL_CAL

00

0

X

1

1 Input Signal (SiPM)

Voltage Calibration

Timing Calibration

Output/Function

SELECTION TABLE

Inversion to allow a -0.9V to +0.1Vinput rangeThis is a constraint from the DRS4readout buffer that cannot handledifferential input below -0.55V.

V+ V-

V+

V-

V+ V-

V+

V+

V- V-

TRIG

OUTP

OUTN

IN

VOCM

VCALTCAL

SEL_IN

SEL_CAL

V-

V+

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Monday, October 03, 201616 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardSchematic Path = /DRS4X32CH_1/DRS4X8CH_2/AFE_6

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Monday, October 03, 201616 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardSchematic Path = /DRS4X32CH_1/DRS4X8CH_2/AFE_6

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Monday, October 03, 201616 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardSchematic Path = /DRS4X32CH_1/DRS4X8CH_2/AFE_6

C163100nF10V

C1591nF50V

R84751%

R4131005%

C160100nF10V

G=1

U47

ADV3219

IN01

V+

4

SEL8

IN13

V-

5

GN

D2

OUT6

EN7 R81

33 1%

C164100nF10V

C162100nF10V

R85

33 1%R83751%

C1561nF50V

C158100nF10V

-

+

PD

VOCM

V+

V- EPAD

U48

ADA4950-1750MHz

2

3

11

513

10

9

12

1

4

17

D155V

G=1

U49

ADV3219

IN01

V+

4

SEL8

IN13

V-

5

GN

D2

OUT6

EN7

C161100nF10V

R82

75 1%

C157100nF10V

C155100nF10V

Page 17: University of Geneva 32-channel DRS4 Acquisition Board 01 ...dpnc.unige.ch/~bravar/DRSSS/DPNC342_02_01A_A60.pdf · CH-1211 GENEVE 4 02A University of Geneva DPNC342 Friday, October

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

ANALOG FRONT-END STAGE

SEL_IN SEL_CAL

00

0

X

1

1 Input Signal (SiPM)

Voltage Calibration

Timing Calibration

Output/Function

SELECTION TABLE

Inversion to allow a -0.9V to +0.1Vinput rangeThis is a constraint from the DRS4readout buffer that cannot handledifferential input below -0.55V.

V+ V-

V+

V-

V+ V-

V+

V+

V- V-

TRIG

OUTP

OUTN

IN

VOCM

VCALTCAL

SEL_IN

SEL_CAL

V-

V+

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Monday, October 03, 201617 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardSchematic Path = /DRS4X32CH_1/DRS4X8CH_2/AFE_7

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Monday, October 03, 201617 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardSchematic Path = /DRS4X32CH_1/DRS4X8CH_2/AFE_7

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Monday, October 03, 201617 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardSchematic Path = /DRS4X32CH_1/DRS4X8CH_2/AFE_7

C173100nF10V

C1691nF50V

R89751%

R4141005%

C170100nF10V

G=1

U50

ADV3219

IN01

V+

4

SEL8

IN13

V-

5

GN

D2

OUT6

EN7 R86

33 1%

C174100nF10V

C172100nF10V

R90

33 1%R88751%

C1661nF50V

C168100nF10V

-

+

PD

VOCM

V+

V- EPAD

U51

ADA4950-1750MHz

2

3

11

513

10

9

12

1

4

17

D165V

G=1

U52

ADV3219

IN01

V+

4

SEL8

IN13

V-

5

GN

D2

OUT6

EN7

C171100nF10V

R87

75 1%

C167100nF10V

C165100nF10V

Page 18: University of Geneva 32-channel DRS4 Acquisition Board 01 ...dpnc.unige.ch/~bravar/DRSSS/DPNC342_02_01A_A60.pdf · CH-1211 GENEVE 4 02A University of Geneva DPNC342 Friday, October

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

ANALOG FRONT-END STAGE

SEL_IN SEL_CAL

00

0

X

1

1 Input Signal (SiPM)

Voltage Calibration

Timing Calibration

Output/Function

SELECTION TABLE

Inversion to allow a -0.9V to +0.1Vinput rangeThis is a constraint from the DRS4readout buffer that cannot handledifferential input below -0.55V.

V+ V-

V+

V-

V+ V-

V+

V+

V- V-

TRIG

OUTP

OUTN

IN

VOCM

VCALTCAL

SEL_IN

SEL_CAL

V-

V+

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Monday, October 03, 201618 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardSchematic Path = /DRS4X32CH_1/DRS4X8CH_2/AFE_8

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Monday, October 03, 201618 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardSchematic Path = /DRS4X32CH_1/DRS4X8CH_2/AFE_8

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Monday, October 03, 201618 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardSchematic Path = /DRS4X32CH_1/DRS4X8CH_2/AFE_8

C183100nF10V

C1791nF50V

R94751%

R4151005%

C180100nF10V

G=1

U53

ADV3219

IN01

V+

4

SEL8

IN13

V-

5

GN

D2

OUT6

EN7 R91

33 1%

C184100nF10V

C182100nF10V

R95

33 1%R93751%

C1761nF50V

C178100nF10V

-

+

PD

VOCM

V+

V- EPAD

U54

ADA4950-1750MHz

2

3

11

513

10

9

12

1

4

17

D175V

G=1

U55

ADV3219

IN01

V+

4

SEL8

IN13

V-

5

GN

D2

OUT6

EN7

C181100nF10V

R92

75 1%

C177100nF10V

C175100nF10V

Page 19: University of Geneva 32-channel DRS4 Acquisition Board 01 ...dpnc.unige.ch/~bravar/DRSSS/DPNC342_02_01A_A60.pdf · CH-1211 GENEVE 4 02A University of Geneva DPNC342 Friday, October

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

ANALOG FRONT-END STAGE

SEL_IN SEL_CAL

00

0

X

1

1 Input Signal (SiPM)

Voltage Calibration

Timing Calibration

Output/Function

SELECTION TABLE

Inversion to allow a -0.9V to +0.1Vinput rangeThis is a constraint from the DRS4readout buffer that cannot handledifferential input below -0.55V.

V+ V-

V+

V-

V+ V-

V+

V+

V- V-

TRIG

OUTP

OUTN

IN

VOCM

VCALTCAL

SEL_IN

SEL_CAL

V-

V+

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Monday, October 03, 201619 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardSchematic Path = /DRS4X32CH_1/DRS4X8CH_3/AFE_1

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Monday, October 03, 201619 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardSchematic Path = /DRS4X32CH_1/DRS4X8CH_3/AFE_1

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Monday, October 03, 201619 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardSchematic Path = /DRS4X32CH_1/DRS4X8CH_3/AFE_1

C193100nF10V

C1891nF50V

R99751%

R4161005%

C190100nF10V

G=1

U56

ADV3219

IN01

V+

4

SEL8

IN13

V-

5

GN

D2

OUT6

EN7 R96

33 1%

C194100nF10V

C192100nF10V

R100

33 1%R98751%

C1861nF50V

C188100nF10V

-

+

PD

VOCM

V+

V- EPAD

U57

ADA4950-1750MHz

2

3

11

513

10

9

12

1

4

17

D185V

G=1

U58

ADV3219

IN01

V+

4

SEL8

IN13

V-

5

GN

D2

OUT6

EN7

C191100nF10V

R97

75 1%

C187100nF10V

C185100nF10V

Page 20: University of Geneva 32-channel DRS4 Acquisition Board 01 ...dpnc.unige.ch/~bravar/DRSSS/DPNC342_02_01A_A60.pdf · CH-1211 GENEVE 4 02A University of Geneva DPNC342 Friday, October

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

ANALOG FRONT-END STAGE

SEL_IN SEL_CAL

00

0

X

1

1 Input Signal (SiPM)

Voltage Calibration

Timing Calibration

Output/Function

SELECTION TABLE

Inversion to allow a -0.9V to +0.1Vinput rangeThis is a constraint from the DRS4readout buffer that cannot handledifferential input below -0.55V.

V+ V-

V+

V-

V+ V-

V+

V+

V- V-

TRIG

OUTP

OUTN

IN

VOCM

VCALTCAL

SEL_IN

SEL_CAL

V-

V+

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Monday, October 03, 201620 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardSchematic Path = /DRS4X32CH_1/DRS4X8CH_3/AFE_2

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Monday, October 03, 201620 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardSchematic Path = /DRS4X32CH_1/DRS4X8CH_3/AFE_2

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Monday, October 03, 201620 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardSchematic Path = /DRS4X32CH_1/DRS4X8CH_3/AFE_2

C203100nF10V

C1991nF50V

R104751%

R4171005%

C200100nF10V

G=1

U59

ADV3219

IN01

V+

4

SEL8

IN13

V-

5

GN

D2

OUT6

EN7 R101

33 1%

C204100nF10V

C202100nF10V

R105

33 1%R103751%

C1961nF50V

C198100nF10V

-

+

PD

VOCM

V+

V- EPAD

U60

ADA4950-1750MHz

2

3

11

513

10

9

12

1

4

17

D195V

G=1

U61

ADV3219

IN01

V+

4

SEL8

IN13

V-

5

GN

D2

OUT6

EN7

C201100nF10V

R102

75 1%

C197100nF10V

C195100nF10V

Page 21: University of Geneva 32-channel DRS4 Acquisition Board 01 ...dpnc.unige.ch/~bravar/DRSSS/DPNC342_02_01A_A60.pdf · CH-1211 GENEVE 4 02A University of Geneva DPNC342 Friday, October

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

ANALOG FRONT-END STAGE

SEL_IN SEL_CAL

00

0

X

1

1 Input Signal (SiPM)

Voltage Calibration

Timing Calibration

Output/Function

SELECTION TABLE

Inversion to allow a -0.9V to +0.1Vinput rangeThis is a constraint from the DRS4readout buffer that cannot handledifferential input below -0.55V.

V+ V-

V+

V-

V+ V-

V+

V+

V- V-

TRIG

OUTP

OUTN

IN

VOCM

VCALTCAL

SEL_IN

SEL_CAL

V-

V+

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Monday, October 03, 201621 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardSchematic Path = /DRS4X32CH_1/DRS4X8CH_3/AFE_3

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Monday, October 03, 201621 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardSchematic Path = /DRS4X32CH_1/DRS4X8CH_3/AFE_3

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Monday, October 03, 201621 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardSchematic Path = /DRS4X32CH_1/DRS4X8CH_3/AFE_3

C213100nF10V

C2091nF50V

R109751%

R4181005%

C210100nF10V

G=1

U62

ADV3219

IN01

V+

4

SEL8

IN13

V-

5

GN

D2

OUT6

EN7 R106

33 1%

C214100nF10V

C212100nF10V

R110

33 1%R108751%

C2061nF50V

C208100nF10V

-

+

PD

VOCM

V+

V- EPAD

U63

ADA4950-1750MHz

2

3

11

513

10

9

12

1

4

17

D205V

G=1

U64

ADV3219

IN01

V+

4

SEL8

IN13

V-

5

GN

D2

OUT6

EN7

C211100nF10V

R107

75 1%

C207100nF10V

C205100nF10V

Page 22: University of Geneva 32-channel DRS4 Acquisition Board 01 ...dpnc.unige.ch/~bravar/DRSSS/DPNC342_02_01A_A60.pdf · CH-1211 GENEVE 4 02A University of Geneva DPNC342 Friday, October

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

ANALOG FRONT-END STAGE

SEL_IN SEL_CAL

00

0

X

1

1 Input Signal (SiPM)

Voltage Calibration

Timing Calibration

Output/Function

SELECTION TABLE

Inversion to allow a -0.9V to +0.1Vinput rangeThis is a constraint from the DRS4readout buffer that cannot handledifferential input below -0.55V.

V+ V-

V+

V-

V+ V-

V+

V+

V- V-

TRIG

OUTP

OUTN

IN

VOCM

VCALTCAL

SEL_IN

SEL_CAL

V-

V+

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Monday, October 03, 201622 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardSchematic Path = /DRS4X32CH_1/DRS4X8CH_3/AFE_4

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Monday, October 03, 201622 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardSchematic Path = /DRS4X32CH_1/DRS4X8CH_3/AFE_4

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Monday, October 03, 201622 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardSchematic Path = /DRS4X32CH_1/DRS4X8CH_3/AFE_4

C223100nF10V

C2191nF50V

R114751%

R4191005%

C220100nF10V

G=1

U65

ADV3219

IN01

V+

4

SEL8

IN13

V-

5

GN

D2

OUT6

EN7 R111

33 1%

C224100nF10V

C222100nF10V

R115

33 1%R113751%

C2161nF50V

C218100nF10V

-

+

PD

VOCM

V+

V- EPAD

U66

ADA4950-1750MHz

2

3

11

513

10

9

12

1

4

17

D215V

G=1

U67

ADV3219

IN01

V+

4

SEL8

IN13

V-

5

GN

D2

OUT6

EN7

C221100nF10V

R112

75 1%

C217100nF10V

C215100nF10V

Page 23: University of Geneva 32-channel DRS4 Acquisition Board 01 ...dpnc.unige.ch/~bravar/DRSSS/DPNC342_02_01A_A60.pdf · CH-1211 GENEVE 4 02A University of Geneva DPNC342 Friday, October

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

ANALOG FRONT-END STAGE

SEL_IN SEL_CAL

00

0

X

1

1 Input Signal (SiPM)

Voltage Calibration

Timing Calibration

Output/Function

SELECTION TABLE

Inversion to allow a -0.9V to +0.1Vinput rangeThis is a constraint from the DRS4readout buffer that cannot handledifferential input below -0.55V.

V+ V-

V+

V-

V+ V-

V+

V+

V- V-

TRIG

OUTP

OUTN

IN

VOCM

VCALTCAL

SEL_IN

SEL_CAL

V-

V+

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Monday, October 03, 201623 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardSchematic Path = /DRS4X32CH_1/DRS4X8CH_3/AFE_5

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Monday, October 03, 201623 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardSchematic Path = /DRS4X32CH_1/DRS4X8CH_3/AFE_5

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Monday, October 03, 201623 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardSchematic Path = /DRS4X32CH_1/DRS4X8CH_3/AFE_5

C233100nF10V

C2291nF50V

R119751%

R4201005%

C230100nF10V

G=1

U68

ADV3219

IN01

V+

4

SEL8

IN13

V-

5

GN

D2

OUT6

EN7 R116

33 1%

C234100nF10V

C232100nF10V

R120

33 1%R118751%

C2261nF50V

C228100nF10V

-

+

PD

VOCM

V+

V- EPAD

U69

ADA4950-1750MHz

2

3

11

513

10

9

12

1

4

17

D225V

G=1

U70

ADV3219

IN01

V+

4

SEL8

IN13

V-

5

GN

D2

OUT6

EN7

C231100nF10V

R117

75 1%

C227100nF10V

C225100nF10V

Page 24: University of Geneva 32-channel DRS4 Acquisition Board 01 ...dpnc.unige.ch/~bravar/DRSSS/DPNC342_02_01A_A60.pdf · CH-1211 GENEVE 4 02A University of Geneva DPNC342 Friday, October

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

ANALOG FRONT-END STAGE

SEL_IN SEL_CAL

00

0

X

1

1 Input Signal (SiPM)

Voltage Calibration

Timing Calibration

Output/Function

SELECTION TABLE

Inversion to allow a -0.9V to +0.1Vinput rangeThis is a constraint from the DRS4readout buffer that cannot handledifferential input below -0.55V.

V+ V-

V+

V-

V+ V-

V+

V+

V- V-

TRIG

OUTP

OUTN

IN

VOCM

VCALTCAL

SEL_IN

SEL_CAL

V-

V+

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Monday, October 03, 201624 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardSchematic Path = /DRS4X32CH_1/DRS4X8CH_3/AFE_6

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Monday, October 03, 201624 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardSchematic Path = /DRS4X32CH_1/DRS4X8CH_3/AFE_6

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Monday, October 03, 201624 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardSchematic Path = /DRS4X32CH_1/DRS4X8CH_3/AFE_6

C243100nF10V

C2391nF50V

R124751%

R4211005%

C240100nF10V

G=1

U71

ADV3219

IN01

V+

4

SEL8

IN13

V-

5

GN

D2

OUT6

EN7 R121

33 1%

C244100nF10V

C242100nF10V

R125

33 1%R123751%

C2361nF50V

C238100nF10V

-

+

PD

VOCM

V+

V- EPAD

U72

ADA4950-1750MHz

2

3

11

513

10

9

12

1

4

17

D235V

G=1

U73

ADV3219

IN01

V+

4

SEL8

IN13

V-

5

GN

D2

OUT6

EN7

C241100nF10V

R122

75 1%

C237100nF10V

C235100nF10V

Page 25: University of Geneva 32-channel DRS4 Acquisition Board 01 ...dpnc.unige.ch/~bravar/DRSSS/DPNC342_02_01A_A60.pdf · CH-1211 GENEVE 4 02A University of Geneva DPNC342 Friday, October

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

ANALOG FRONT-END STAGE

SEL_IN SEL_CAL

00

0

X

1

1 Input Signal (SiPM)

Voltage Calibration

Timing Calibration

Output/Function

SELECTION TABLE

Inversion to allow a -0.9V to +0.1Vinput rangeThis is a constraint from the DRS4readout buffer that cannot handledifferential input below -0.55V.

V+ V-

V+

V-

V+ V-

V+

V+

V- V-

TRIG

OUTP

OUTN

IN

VOCM

VCALTCAL

SEL_IN

SEL_CAL

V-

V+

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Monday, October 03, 201625 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardSchematic Path = /DRS4X32CH_1/DRS4X8CH_3/AFE_7

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Monday, October 03, 201625 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardSchematic Path = /DRS4X32CH_1/DRS4X8CH_3/AFE_7

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Monday, October 03, 201625 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardSchematic Path = /DRS4X32CH_1/DRS4X8CH_3/AFE_7

C253100nF10V

C2491nF50V

R129751%

R4221005%

C250100nF10V

G=1

U74

ADV3219

IN01

V+

4

SEL8

IN13

V-

5

GN

D2

OUT6

EN7 R126

33 1%

C254100nF10V

C252100nF10V

R130

33 1%R128751%

C2461nF50V

C248100nF10V

-

+

PD

VOCM

V+

V- EPAD

U75

ADA4950-1750MHz

2

3

11

513

10

9

12

1

4

17

D245V

G=1

U76

ADV3219

IN01

V+

4

SEL8

IN13

V-

5

GN

D2

OUT6

EN7

C251100nF10V

R127

75 1%

C247100nF10V

C245100nF10V

Page 26: University of Geneva 32-channel DRS4 Acquisition Board 01 ...dpnc.unige.ch/~bravar/DRSSS/DPNC342_02_01A_A60.pdf · CH-1211 GENEVE 4 02A University of Geneva DPNC342 Friday, October

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

ANALOG FRONT-END STAGE

SEL_IN SEL_CAL

00

0

X

1

1 Input Signal (SiPM)

Voltage Calibration

Timing Calibration

Output/Function

SELECTION TABLE

Inversion to allow a -0.9V to +0.1Vinput rangeThis is a constraint from the DRS4readout buffer that cannot handledifferential input below -0.55V.

V+ V-

V+

V-

V+ V-

V+

V+

V- V-

TRIG

OUTP

OUTN

IN

VOCM

VCALTCAL

SEL_IN

SEL_CAL

V-

V+

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Monday, October 03, 201626 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardSchematic Path = /DRS4X32CH_1/DRS4X8CH_3/AFE_8

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Monday, October 03, 201626 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardSchematic Path = /DRS4X32CH_1/DRS4X8CH_3/AFE_8

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Monday, October 03, 201626 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardSchematic Path = /DRS4X32CH_1/DRS4X8CH_3/AFE_8

C263100nF10V

C2591nF50V

R134751%

R4231005%

C260100nF10V

G=1

U77

ADV3219

IN01

V+

4

SEL8

IN13

V-

5

GN

D2

OUT6

EN7 R131

33 1%

C264100nF10V

C262100nF10V

R135

33 1%R133751%

C2561nF50V

C258100nF10V

-

+

PD

VOCM

V+

V- EPAD

U78

ADA4950-1750MHz

2

3

11

513

10

9

12

1

4

17

D255V

G=1

U79

ADV3219

IN01

V+

4

SEL8

IN13

V-

5

GN

D2

OUT6

EN7

C261100nF10V

R132

75 1%

C257100nF10V

C255100nF10V

Page 27: University of Geneva 32-channel DRS4 Acquisition Board 01 ...dpnc.unige.ch/~bravar/DRSSS/DPNC342_02_01A_A60.pdf · CH-1211 GENEVE 4 02A University of Geneva DPNC342 Friday, October

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

ANALOG FRONT-END STAGE

SEL_IN SEL_CAL

00

0

X

1

1 Input Signal (SiPM)

Voltage Calibration

Timing Calibration

Output/Function

SELECTION TABLE

Inversion to allow a -0.9V to +0.1Vinput rangeThis is a constraint from the DRS4readout buffer that cannot handledifferential input below -0.55V.

V+ V-

V+

V-

V+ V-

V+

V+

V- V-

TRIG

OUTP

OUTN

IN

VOCM

VCALTCAL

SEL_IN

SEL_CAL

V-

V+

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Monday, October 03, 201627 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardSchematic Path = /DRS4X32CH_1/DRS4X8CH_4/AFE_1

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Monday, October 03, 201627 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardSchematic Path = /DRS4X32CH_1/DRS4X8CH_4/AFE_1

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Monday, October 03, 201627 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardSchematic Path = /DRS4X32CH_1/DRS4X8CH_4/AFE_1

C273100nF10V

C2691nF50V

R139751%

R4241005%

C270100nF10V

G=1

U80

ADV3219

IN01

V+

4

SEL8

IN13

V-

5

GN

D2

OUT6

EN7 R136

33 1%

C274100nF10V

C272100nF10V

R140

33 1%R138751%

C2661nF50V

C268100nF10V

-

+

PD

VOCM

V+

V- EPAD

U81

ADA4950-1750MHz

2

3

11

513

10

9

12

1

4

17

D265V

G=1

U82

ADV3219

IN01

V+

4

SEL8

IN13

V-

5

GN

D2

OUT6

EN7

C271100nF10V

R137

75 1%

C267100nF10V

C265100nF10V

Page 28: University of Geneva 32-channel DRS4 Acquisition Board 01 ...dpnc.unige.ch/~bravar/DRSSS/DPNC342_02_01A_A60.pdf · CH-1211 GENEVE 4 02A University of Geneva DPNC342 Friday, October

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

ANALOG FRONT-END STAGE

SEL_IN SEL_CAL

00

0

X

1

1 Input Signal (SiPM)

Voltage Calibration

Timing Calibration

Output/Function

SELECTION TABLE

Inversion to allow a -0.9V to +0.1Vinput rangeThis is a constraint from the DRS4readout buffer that cannot handledifferential input below -0.55V.

V+ V-

V+

V-

V+ V-

V+

V+

V- V-

TRIG

OUTP

OUTN

IN

VOCM

VCALTCAL

SEL_IN

SEL_CAL

V-

V+

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Monday, October 03, 201628 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardSchematic Path = /DRS4X32CH_1/DRS4X8CH_4/AFE_2

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Monday, October 03, 201628 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardSchematic Path = /DRS4X32CH_1/DRS4X8CH_4/AFE_2

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Monday, October 03, 201628 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardSchematic Path = /DRS4X32CH_1/DRS4X8CH_4/AFE_2

C283100nF10V

C2791nF50V

R144751%

R4251005%

C280100nF10V

G=1

U83

ADV3219

IN01

V+

4

SEL8

IN13

V-

5

GN

D2

OUT6

EN7 R141

33 1%

C284100nF10V

C282100nF10V

R145

33 1%R143751%

C2761nF50V

C278100nF10V

-

+

PD

VOCM

V+

V- EPAD

U84

ADA4950-1750MHz

2

3

11

513

10

9

12

1

4

17

D275V

G=1

U85

ADV3219

IN01

V+

4

SEL8

IN13

V-

5

GN

D2

OUT6

EN7

C281100nF10V

R142

75 1%

C277100nF10V

C275100nF10V

Page 29: University of Geneva 32-channel DRS4 Acquisition Board 01 ...dpnc.unige.ch/~bravar/DRSSS/DPNC342_02_01A_A60.pdf · CH-1211 GENEVE 4 02A University of Geneva DPNC342 Friday, October

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

ANALOG FRONT-END STAGE

SEL_IN SEL_CAL

00

0

X

1

1 Input Signal (SiPM)

Voltage Calibration

Timing Calibration

Output/Function

SELECTION TABLE

Inversion to allow a -0.9V to +0.1Vinput rangeThis is a constraint from the DRS4readout buffer that cannot handledifferential input below -0.55V.

V+ V-

V+

V-

V+ V-

V+

V+

V- V-

TRIG

OUTP

OUTN

IN

VOCM

VCALTCAL

SEL_IN

SEL_CAL

V-

V+

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Monday, October 03, 201629 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardSchematic Path = /DRS4X32CH_1/DRS4X8CH_4/AFE_3

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Monday, October 03, 201629 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardSchematic Path = /DRS4X32CH_1/DRS4X8CH_4/AFE_3

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Monday, October 03, 201629 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardSchematic Path = /DRS4X32CH_1/DRS4X8CH_4/AFE_3

C293100nF10V

C2891nF50V

R149751%

R4261005%

C290100nF10V

G=1

U86

ADV3219

IN01

V+

4

SEL8

IN13

V-

5

GN

D2

OUT6

EN7 R146

33 1%

C294100nF10V

C292100nF10V

R150

33 1%R148751%

C2861nF50V

C288100nF10V

-

+

PD

VOCM

V+

V- EPAD

U87

ADA4950-1750MHz

2

3

11

513

10

9

12

1

4

17

D285V

G=1

U88

ADV3219

IN01

V+

4

SEL8

IN13

V-

5

GN

D2

OUT6

EN7

C291100nF10V

R147

75 1%

C287100nF10V

C285100nF10V

Page 30: University of Geneva 32-channel DRS4 Acquisition Board 01 ...dpnc.unige.ch/~bravar/DRSSS/DPNC342_02_01A_A60.pdf · CH-1211 GENEVE 4 02A University of Geneva DPNC342 Friday, October

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

ANALOG FRONT-END STAGE

SEL_IN SEL_CAL

00

0

X

1

1 Input Signal (SiPM)

Voltage Calibration

Timing Calibration

Output/Function

SELECTION TABLE

Inversion to allow a -0.9V to +0.1Vinput rangeThis is a constraint from the DRS4readout buffer that cannot handledifferential input below -0.55V.

V+ V-

V+

V-

V+ V-

V+

V+

V- V-

TRIG

OUTP

OUTN

IN

VOCM

VCALTCAL

SEL_IN

SEL_CAL

V-

V+

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Monday, October 03, 201630 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardSchematic Path = /DRS4X32CH_1/DRS4X8CH_4/AFE_4

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Monday, October 03, 201630 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardSchematic Path = /DRS4X32CH_1/DRS4X8CH_4/AFE_4

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Monday, October 03, 201630 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardSchematic Path = /DRS4X32CH_1/DRS4X8CH_4/AFE_4

C303100nF10V

C2991nF50V

R154751%

R4271005%

C300100nF10V

G=1

U89

ADV3219

IN01

V+

4

SEL8

IN13

V-

5

GN

D2

OUT6

EN7 R151

33 1%

C304100nF10V

C302100nF10V

R155

33 1%R153751%

C2961nF50V

C298100nF10V

-

+

PD

VOCM

V+

V- EPAD

U90

ADA4950-1750MHz

2

3

11

513

10

9

12

1

4

17

D295V

G=1

U91

ADV3219

IN01

V+

4

SEL8

IN13

V-

5

GN

D2

OUT6

EN7

C301100nF10V

R152

75 1%

C297100nF10V

C295100nF10V

Page 31: University of Geneva 32-channel DRS4 Acquisition Board 01 ...dpnc.unige.ch/~bravar/DRSSS/DPNC342_02_01A_A60.pdf · CH-1211 GENEVE 4 02A University of Geneva DPNC342 Friday, October

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

ANALOG FRONT-END STAGE

SEL_IN SEL_CAL

00

0

X

1

1 Input Signal (SiPM)

Voltage Calibration

Timing Calibration

Output/Function

SELECTION TABLE

Inversion to allow a -0.9V to +0.1Vinput rangeThis is a constraint from the DRS4readout buffer that cannot handledifferential input below -0.55V.

V+ V-

V+

V-

V+ V-

V+

V+

V- V-

TRIG

OUTP

OUTN

IN

VOCM

VCALTCAL

SEL_IN

SEL_CAL

V-

V+

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Monday, October 03, 201631 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardSchematic Path = /DRS4X32CH_1/DRS4X8CH_4/AFE_5

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Monday, October 03, 201631 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardSchematic Path = /DRS4X32CH_1/DRS4X8CH_4/AFE_5

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Monday, October 03, 201631 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardSchematic Path = /DRS4X32CH_1/DRS4X8CH_4/AFE_5

C313100nF10V

C3091nF50V

R159751%

R4281005%

C310100nF10V

G=1

U92

ADV3219

IN01

V+

4

SEL8

IN13

V-

5

GN

D2

OUT6

EN7 R156

33 1%

C314100nF10V

C312100nF10V

R160

33 1%R158751%

C3061nF50V

C308100nF10V

-

+

PD

VOCM

V+

V- EPAD

U93

ADA4950-1750MHz

2

3

11

513

10

9

12

1

4

17

D305V

G=1

U94

ADV3219

IN01

V+

4

SEL8

IN13

V-

5

GN

D2

OUT6

EN7

C311100nF10V

R157

75 1%

C307100nF10V

C305100nF10V

Page 32: University of Geneva 32-channel DRS4 Acquisition Board 01 ...dpnc.unige.ch/~bravar/DRSSS/DPNC342_02_01A_A60.pdf · CH-1211 GENEVE 4 02A University of Geneva DPNC342 Friday, October

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

ANALOG FRONT-END STAGE

SEL_IN SEL_CAL

00

0

X

1

1 Input Signal (SiPM)

Voltage Calibration

Timing Calibration

Output/Function

SELECTION TABLE

Inversion to allow a -0.9V to +0.1Vinput rangeThis is a constraint from the DRS4readout buffer that cannot handledifferential input below -0.55V.

V+ V-

V+

V-

V+ V-

V+

V+

V- V-

TRIG

OUTP

OUTN

IN

VOCM

VCALTCAL

SEL_IN

SEL_CAL

V-

V+

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Monday, October 03, 201632 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardSchematic Path = /DRS4X32CH_1/DRS4X8CH_4/AFE_6

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Monday, October 03, 201632 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardSchematic Path = /DRS4X32CH_1/DRS4X8CH_4/AFE_6

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Monday, October 03, 201632 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardSchematic Path = /DRS4X32CH_1/DRS4X8CH_4/AFE_6

C323100nF10V

C3191nF50V

R164751%

R4291005%

C320100nF10V

G=1

U95

ADV3219

IN01

V+

4

SEL8

IN13

V-

5

GN

D2

OUT6

EN7 R161

33 1%

C324100nF10V

C322100nF10V

R165

33 1%R163751%

C3161nF50V

C318100nF10V

-

+

PD

VOCM

V+

V- EPAD

U96

ADA4950-1750MHz

2

3

11

513

10

9

12

1

4

17

D315V

G=1

U97

ADV3219

IN01

V+

4

SEL8

IN13

V-

5

GN

D2

OUT6

EN7

C321100nF10V

R162

75 1%

C317100nF10V

C315100nF10V

Page 33: University of Geneva 32-channel DRS4 Acquisition Board 01 ...dpnc.unige.ch/~bravar/DRSSS/DPNC342_02_01A_A60.pdf · CH-1211 GENEVE 4 02A University of Geneva DPNC342 Friday, October

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

ANALOG FRONT-END STAGE

SEL_IN SEL_CAL

00

0

X

1

1 Input Signal (SiPM)

Voltage Calibration

Timing Calibration

Output/Function

SELECTION TABLE

Inversion to allow a -0.9V to +0.1Vinput rangeThis is a constraint from the DRS4readout buffer that cannot handledifferential input below -0.55V.

V+ V-

V+

V-

V+ V-

V+

V+

V- V-

TRIG

OUTP

OUTN

IN

VOCM

VCALTCAL

SEL_IN

SEL_CAL

V-

V+

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Monday, October 03, 201633 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardSchematic Path = /DRS4X32CH_1/DRS4X8CH_4/AFE_7

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Monday, October 03, 201633 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardSchematic Path = /DRS4X32CH_1/DRS4X8CH_4/AFE_7

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Monday, October 03, 201633 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardSchematic Path = /DRS4X32CH_1/DRS4X8CH_4/AFE_7

C333100nF10V

C3291nF50V

R169751%

R4301005%

C330100nF10V

G=1

U98

ADV3219

IN01

V+

4

SEL8

IN13

V-

5

GN

D2

OUT6

EN7 R166

33 1%

C334100nF10V

C332100nF10V

R170

33 1%R168751%

C3261nF50V

C328100nF10V

-

+

PD

VOCM

V+

V- EPAD

U99

ADA4950-1750MHz

2

3

11

513

10

9

12

1

4

17

D325V

G=1

U100

ADV3219

IN01

V+

4

SEL8

IN13

V-

5

GN

D2

OUT6

EN7

C331100nF10V

R167

75 1%

C327100nF10V

C325100nF10V

Page 34: University of Geneva 32-channel DRS4 Acquisition Board 01 ...dpnc.unige.ch/~bravar/DRSSS/DPNC342_02_01A_A60.pdf · CH-1211 GENEVE 4 02A University of Geneva DPNC342 Friday, October

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

ANALOG FRONT-END STAGE

SEL_IN SEL_CAL

00

0

X

1

1 Input Signal (SiPM)

Voltage Calibration

Timing Calibration

Output/Function

SELECTION TABLE

Inversion to allow a -0.9V to +0.1Vinput rangeThis is a constraint from the DRS4readout buffer that cannot handledifferential input below -0.55V.

V+ V-

V+

V-

V+ V-

V+

V+

V- V-

TRIG

OUTP

OUTN

IN

VOCM

VCALTCAL

SEL_IN

SEL_CAL

V-

V+

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Monday, October 03, 201634 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardSchematic Path = /DRS4X32CH_1/DRS4X8CH_4/AFE_8

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Monday, October 03, 201634 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardSchematic Path = /DRS4X32CH_1/DRS4X8CH_4/AFE_8

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Monday, October 03, 201634 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardSchematic Path = /DRS4X32CH_1/DRS4X8CH_4/AFE_8

C343100nF10V

C3391nF50V

R174751%

R4311005%

C340100nF10V

G=1

U101

ADV3219

IN01

V+

4

SEL8

IN13

V-

5

GN

D2

OUT6

EN7 R171

33 1%

C344100nF10V

C342100nF10V

R175

33 1%R173751%

C3361nF50V

C338100nF10V

-

+

PD

VOCM

V+

V- EPAD

U102

ADA4950-1750MHz

2

3

11

513

10

9

12

1

4

17

D335V

G=1

U103

ADV3219

IN01

V+

4

SEL8

IN13

V-

5

GN

D2

OUT6

EN7

C341100nF10V

R172

75 1%

C337100nF10V

C335100nF10V

Page 35: University of Geneva 32-channel DRS4 Acquisition Board 01 ...dpnc.unige.ch/~bravar/DRSSS/DPNC342_02_01A_A60.pdf · CH-1211 GENEVE 4 02A University of Geneva DPNC342 Friday, October

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

CLOCK MUX/BUFFER

No jumper: external clockJumper: on-board clock

No jumper: rear connectorJumper: front-panel connector

FRONT-PANELCONNECTOR

CLK2M4576

FP_CLK+

FP_CLK-

EX_CLK+EX_CLK-

CLK0+CLK0-

CLK1+CLK1-

CLK2+CLK2-

CLK3+CLK3-

EXT_CLK+

EXT_CLK-

+3.3V

+3.3V

+3.3V

+3.3V

+3.3V

+3.3V +3.3V

+3.3V

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Thursday, September 29, 201635 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardSchematic Path = /DRS4X32CH_1/CLK_1

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Thursday, September 29, 201635 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardSchematic Path = /DRS4X32CH_1/CLK_1

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Thursday, September 29, 201635 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardSchematic Path = /DRS4X32CH_1/CLK_1

C345100nF16V

R1771005%

U105

8SLVD1204-332GHz

GN

D1

VD

D5

SEL2

VREF8

PCLK06

nPCLK07

PCLK13

nPCLK14

Q09

Q111

Q213

Q315

nQ010

nQ112

nQ214

nQ316

U104

ICS854S01I2.5GHZ

9

GND

8

VDD

6

SEL

PCLK01

nPCLK02

PCLK13

nPCLK14

Q11

nQ10 L1

600R/100MHz

0.2A

R1811K5%

R180

22 5%

R1761005%

C346100nF16V

C347100nF16V

J7

HE10M/STP2.54

1 2

C351100nF16V

C3481uF10V

Y1

2.4576MHz50PPM

VCC4

OUT3

GND2

EN1

C35010nF16V

J8

HE10M/STP2.54

1 2

J6

LEMOF/RA50R

3

12

R1791005%

C34910uF10V

R1781K5%

Page 36: University of Geneva 32-channel DRS4 Acquisition Board 01 ...dpnc.unige.ch/~bravar/DRSSS/DPNC342_02_01A_A60.pdf · CH-1211 GENEVE 4 02A University of Geneva DPNC342 Friday, October

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

VREF2V

DISVCAL

CSSCK

SDI

DIS

TLEVEL1TLEVEL2TLEVEL3TLEVEL4

VCAL

+2.5V_A

+2.5V_A

+2.5V_A +5V_A

+5V_A -5V_A

-5V_A

+2.5V_A

-5V_A

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Thursday, September 29, 201636 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardDAC8 Schematic Path = /DRS4X32CH_1/DAC8_1

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Thursday, September 29, 201636 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardDAC8 Schematic Path = /DRS4X32CH_1/DAC8_1

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Thursday, September 29, 201636 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardDAC8 Schematic Path = /DRS4X32CH_1/DAC8_1

U107

LTC262012-bits

VOUTA2

VOUTB3

VOUTC4

VOUTD5

VOUTH15VOUTG14VOUTF13VOUTE12

SDI9

SDO10

SCK8

CS/LD7

GN

D1

VC

C16

REF6

CLR11

-

+

U108

AD8027190MHz

31

62

4

5

TP2TP

RND1.0SMD1

R184

1K 1%

C352100nF16V

TP3TP

1

R1856.20K5%

C35310uF10%10V

TP4TP

1

C356100nF16V

C357100nF16V

C355100nF16V

R182

499 1%

TP5TP

1

C3541uF10%10V

R183

1K 1%

TP7TP

RND1.0SMD1

TP6TP

1

Q1NTR1P02

0.75A20V

U106

LM41402.048V+/-0.1%

GN

D1

GN

D4

GN

D7

GN

D8

VIN2

EN3 VREF

6

Page 37: University of Geneva 32-channel DRS4 Acquisition Board 01 ...dpnc.unige.ch/~bravar/DRSSS/DPNC342_02_01A_A60.pdf · CH-1211 GENEVE 4 02A University of Geneva DPNC342 Friday, October

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

4 LVDS PAIRS TO CONNECT TO DDL LINK CONCENTRATORDDL LINK: 2 Gbps32 BOARDS PER DDL LINK-> 62.5 Mbps/board

REAR

DIN-DIN+

CLKIN+

CLKOUT-CLKOUT+

DOUT+DOUT-

CLKIN-

CLKIN_C+

CLKIN_C-

DIN_C-

DIN_C+

DATA_IN

CLK_IN

DATA_OUT

CLK_OUT

ENABLE

+3.3V +3.3V

+1.2V +1.2V

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Thursday, September 29, 201637 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardCONNECTION TO DDL LINK CONCENTRATOR Schematic Path = /DDL_1

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Thursday, September 29, 201637 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardCONNECTION TO DDL LINK CONCENTRATOR Schematic Path = /DDL_1

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Thursday, September 29, 201637 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardCONNECTION TO DDL LINK CONCENTRATOR Schematic Path = /DDL_1

TP10TPRND1.0SMD1

TP9TPRND1.0SMD1

R188515%

TP11TPRND1.0SMD1

C363

10nF

C361

10nF J9

RJ45F/RATHD SH

12345678

910

R189515%

R187515%

C364100nF10%16V

C358100nF10%16V

C359100nF10%16V

J10

HE10M/STP2.54

1 2

U109

DS90LV049400MBPS

VDD=+3.3V

ROUT115

ROUT214

DIN211

DIN110

RIN1-1

RIN2-4

DOUT2-5

DOUT1-8

RIN1+2

RIN2+3

DOUT2+6

DOUT1+7

EN16

EN9

C362

10nF

R186515%

TP8TPRND1.0SMD1

C3651nF10%25V

C360

10nF

Page 38: University of Geneva 32-channel DRS4 Acquisition Board 01 ...dpnc.unige.ch/~bravar/DRSSS/DPNC342_02_01A_A60.pdf · CH-1211 GENEVE 4 02A University of Geneva DPNC342 Friday, October

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

DRS4

1.15V1.29VO-OFSROFS

DTAP

IN1+IN1-IN2+IN2-IN3+IN3-IN4+IN4-

DRS_A0DRS_A1DRS_A2DRS_A3

DRS_RSRLOADDRS_SRCLKDRS_SRINDRS_SROUTDRS_WSROUT

DRS_DWRITEDRS_DENABLE

DRS_WSRIN

RESET

IN5+IN5-

REFCLK+REFCLK-

PLLLCK

IN6+IN6-IN7+IN7-IN8+IN8-

OUTM+OUTM-

V+

+2.5V_A

+2.5V_A

+2.5V_A

+2.5V_A

+2.5V

+2.5V

+2.5V

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Thursday, September 29, 201638 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardSchematic Path = /DRS4X32CH_1/DRS4X8CH_1/DRS4_1

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Thursday, September 29, 201638 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardSchematic Path = /DRS4X32CH_1/DRS4X8CH_1/DRS4_1

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Thursday, September 29, 201638 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardSchematic Path = /DRS4X32CH_1/DRS4X8CH_1/DRS4_1

U4

DRS49 chan.

IN0+3

IN0-4

IN1+5

IN1-6

IN2+7

IN2-8

IN3+9

IN3-10

IN4+11

IN4-12

IN5+13

IN5-14

IN6+15

IN6-16

IN7+17

IN7-18

IN8+20

IN8-21 OUT8+

37

OUT8-38

OUT7+40

OUT7-41

OUT6-42OUT6+43

OUT5+45

OUT5-46

OUT4-47OUT4+48

OUT3+49

OUT3-50

OUT2-51OUT2+52

OUT1+54

OUT1-55

OUT0-56OUT0+57

AG

ND

1

AG

ND

2

AG

ND

58

AG

ND

64

AG

ND

70

DG

ND

19

DG

ND

22

DG

ND

39

DG

ND

44

DG

ND

53

AV

DD

59

AV

DD

65

AV

DD

71

AV

DD

76

DV

DD

23

DV

DD

24

DV

DD

33

DV

DD

34

REFCLK+66

REFCLK-67

DTAP62

PLLLCK63

PLLOUT68

DSPEED69

DWRITE73

DENABLE74

WSRIN75

BIAS72

O-OFS36

ROFS30

RESET35

A361

A260

A132

A031

RSRLOAD29

SRCLK28

SRIN27

SROUT26

WSROUT25

TH

PA

D77

R1991.1K0.1%

C3751uF

10%10V

C368100nF10V

C38827nF50V

C387100nF16V

R19

7

100

5%

R19

4

100

5%

R19

3

100

5%

C384100nF16V

C377100pF50V

R206

4.7 5%

C40010uF

10%10V

C379100pF50V

R19

0

100

5%

C37010uF10V

R19

5

100

5%

C366100nF10V

TP14TP

RND1.0SMD1

C3862.2nF50V

C390100nF16V

C380100pF50V

C3854.7nF25V

R19

2

100

5%

C369100uF6.3V

C389100nF16V

C378100pF50V

R198

100 5%

R19

6

100

5%

C37210uF10V

TP13TP

RND1.0SMD1

-

+U111

AD8027

31

62

4

5

C367100nF10V

C373100nF10V

R2032205%

R2001.15K0.1%

TP12TP

RND1.0SMD1

C371100uF6.3V

U110

LM41402.048V+/-0.1%

GN

D1

GN

D4

GN

D7

GN

D8

VIN2

EN3VREF

6

R2021.47K0.1%

C376100pF50V

R19

1

100

5%

C374100nF10V

R2011.87K0.1%

Page 39: University of Geneva 32-channel DRS4 Acquisition Board 01 ...dpnc.unige.ch/~bravar/DRSSS/DPNC342_02_01A_A60.pdf · CH-1211 GENEVE 4 02A University of Geneva DPNC342 Friday, October

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

DRS4

1.15V1.29VO-OFSROFS

DTAP

IN1+IN1-IN2+IN2-IN3+IN3-IN4+IN4-

DRS_A0DRS_A1DRS_A2DRS_A3

DRS_RSRLOADDRS_SRCLKDRS_SRINDRS_SROUTDRS_WSROUT

DRS_DWRITEDRS_DENABLE

DRS_WSRIN

RESET

IN5+IN5-

REFCLK+REFCLK-

PLLLCK

IN6+IN6-IN7+IN7-IN8+IN8-

OUTM+OUTM-

V+

+2.5V_A

+2.5V_A

+2.5V_A

+2.5V_A

+2.5V

+2.5V

+2.5V

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Thursday, September 29, 201639 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardSchematic Path = /DRS4X32CH_1/DRS4X8CH_2/DRS4_1

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Thursday, September 29, 201639 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardSchematic Path = /DRS4X32CH_1/DRS4X8CH_2/DRS4_1

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Thursday, September 29, 201639 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardSchematic Path = /DRS4X32CH_1/DRS4X8CH_2/DRS4_1

U5

DRS49 chan.

IN0+3

IN0-4

IN1+5

IN1-6

IN2+7

IN2-8

IN3+9

IN3-10

IN4+11

IN4-12

IN5+13

IN5-14

IN6+15

IN6-16

IN7+17

IN7-18

IN8+20

IN8-21 OUT8+

37

OUT8-38

OUT7+40

OUT7-41

OUT6-42OUT6+43

OUT5+45

OUT5-46

OUT4-47OUT4+48

OUT3+49

OUT3-50

OUT2-51OUT2+52

OUT1+54

OUT1-55

OUT0-56OUT0+57

AG

ND

1

AG

ND

2

AG

ND

58

AG

ND

64

AG

ND

70

DG

ND

19

DG

ND

22

DG

ND

39

DG

ND

44

DG

ND

53

AV

DD

59

AV

DD

65

AV

DD

71

AV

DD

76

DV

DD

23

DV

DD

24

DV

DD

33

DV

DD

34

REFCLK+66

REFCLK-67

DTAP62

PLLLCK63

PLLOUT68

DSPEED69

DWRITE73

DENABLE74

WSRIN75

BIAS72

O-OFS36

ROFS30

RESET35

A361

A260

A132

A031

RSRLOAD29

SRCLK28

SRIN27

SROUT26

WSROUT25

TH

PA

D77

R2161.1K0.1%

C3811uF

10%10V

C393100nF10V

C41327nF50V

C412100nF16V

R21

4

100

5%

R21

1

100

5%

R21

0

100

5%

C409100nF16V

C402100pF50V

R223

4.7 5%

C40610uF

10%10V

C404100pF50V

R20

7

100

5%

C39510uF10V

R21

2

100

5%

C391100nF10V

TP17TP

RND1.0SMD1

C4112.2nF50V

C415100nF16V

C405100pF50V

C4104.7nF25V

R20

9

100

5%

C394100uF6.3V

C414100nF16V

C403100pF50V

R215

100 5%

R21

3

100

5%

C39710uF10V

TP16TP

RND1.0SMD1

-

+U113

AD8027

31

62

4

5

C392100nF10V

C398100nF10V

R2202205%

R2171.15K0.1%

TP15TP

RND1.0SMD1

C396100uF6.3V

U112

LM41402.048V+/-0.1%

GN

D1

GN

D4

GN

D7

GN

D8

VIN2

EN3VREF

6

R2191.47K0.1%

C401100pF50V

R20

8

100

5%

C399100nF10V

R2181.87K0.1%

Page 40: University of Geneva 32-channel DRS4 Acquisition Board 01 ...dpnc.unige.ch/~bravar/DRSSS/DPNC342_02_01A_A60.pdf · CH-1211 GENEVE 4 02A University of Geneva DPNC342 Friday, October

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

DRS4

1.15V1.29VO-OFSROFS

DTAP

IN1+IN1-IN2+IN2-IN3+IN3-IN4+IN4-

DRS_A0DRS_A1DRS_A2DRS_A3

DRS_RSRLOADDRS_SRCLKDRS_SRINDRS_SROUTDRS_WSROUT

DRS_DWRITEDRS_DENABLE

DRS_WSRIN

RESET

IN5+IN5-

REFCLK+REFCLK-

PLLLCK

IN6+IN6-IN7+IN7-IN8+IN8-

OUTM+OUTM-

V+

+2.5V_A

+2.5V_A

+2.5V_A

+2.5V_A

+2.5V

+2.5V

+2.5V

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Thursday, September 29, 201640 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardSchematic Path = /DRS4X32CH_1/DRS4X8CH_3/DRS4_1

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Thursday, September 29, 201640 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardSchematic Path = /DRS4X32CH_1/DRS4X8CH_3/DRS4_1

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Thursday, September 29, 201640 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardSchematic Path = /DRS4X32CH_1/DRS4X8CH_3/DRS4_1

U6

DRS49 chan.

IN0+3

IN0-4

IN1+5

IN1-6

IN2+7

IN2-8

IN3+9

IN3-10

IN4+11

IN4-12

IN5+13

IN5-14

IN6+15

IN6-16

IN7+17

IN7-18

IN8+20

IN8-21 OUT8+

37

OUT8-38

OUT7+40

OUT7-41

OUT6-42OUT6+43

OUT5+45

OUT5-46

OUT4-47OUT4+48

OUT3+49

OUT3-50

OUT2-51OUT2+52

OUT1+54

OUT1-55

OUT0-56OUT0+57

AG

ND

1

AG

ND

2

AG

ND

58

AG

ND

64

AG

ND

70

DG

ND

19

DG

ND

22

DG

ND

39

DG

ND

44

DG

ND

53

AV

DD

59

AV

DD

65

AV

DD

71

AV

DD

76

DV

DD

23

DV

DD

24

DV

DD

33

DV

DD

34

REFCLK+66

REFCLK-67

DTAP62

PLLLCK63

PLLOUT68

DSPEED69

DWRITE73

DENABLE74

WSRIN75

BIAS72

O-OFS36

ROFS30

RESET35

A361

A260

A132

A031

RSRLOAD29

SRCLK28

SRIN27

SROUT26

WSROUT25

TH

PA

D77

R2331.1K0.1%

C3821uF

10%10V

C418100nF10V

C43827nF50V

C437100nF16V

R23

1

100

5%

R22

8

100

5%

R22

7

100

5%

C434100nF16V

C427100pF50V

R240

4.7 5%

C40710uF

10%10V

C429100pF50V

R22

4

100

5%

C42010uF10V

R22

9

100

5%

C416100nF10V

TP20TP

RND1.0SMD1

C4362.2nF50V

C440100nF16V

C430100pF50V

C4354.7nF25V

R22

6

100

5%

C419100uF6.3V

C439100nF16V

C428100pF50V

R232

100 5%

R23

0

100

5%

C42210uF10V

TP19TP

RND1.0SMD1

-

+U115

AD8027

31

62

4

5

C417100nF10V

C423100nF10V

R2372205%

R2341.15K0.1%

TP18TP

RND1.0SMD1

C421100uF6.3V

U114

LM41402.048V+/-0.1%

GN

D1

GN

D4

GN

D7

GN

D8

VIN2

EN3VREF

6

R2361.47K0.1%

C426100pF50V

R22

5

100

5%

C424100nF10V

R2351.87K0.1%

Page 41: University of Geneva 32-channel DRS4 Acquisition Board 01 ...dpnc.unige.ch/~bravar/DRSSS/DPNC342_02_01A_A60.pdf · CH-1211 GENEVE 4 02A University of Geneva DPNC342 Friday, October

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

DRS4

1.15V1.29VO-OFSROFS

DTAP

IN1+IN1-IN2+IN2-IN3+IN3-IN4+IN4-

DRS_A0DRS_A1DRS_A2DRS_A3

DRS_RSRLOADDRS_SRCLKDRS_SRINDRS_SROUTDRS_WSROUT

DRS_DWRITEDRS_DENABLE

DRS_WSRIN

RESET

IN5+IN5-

REFCLK+REFCLK-

PLLLCK

IN6+IN6-IN7+IN7-IN8+IN8-

OUTM+OUTM-

V+

+2.5V_A

+2.5V_A

+2.5V_A

+2.5V_A

+2.5V

+2.5V

+2.5V

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Thursday, September 29, 201641 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardSchematic Path = /DRS4X32CH_1/DRS4X8CH_4/DRS4_1

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Thursday, September 29, 201641 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardSchematic Path = /DRS4X32CH_1/DRS4X8CH_4/DRS4_1

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Thursday, September 29, 201641 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardSchematic Path = /DRS4X32CH_1/DRS4X8CH_4/DRS4_1

U7

DRS49 chan.

IN0+3

IN0-4

IN1+5

IN1-6

IN2+7

IN2-8

IN3+9

IN3-10

IN4+11

IN4-12

IN5+13

IN5-14

IN6+15

IN6-16

IN7+17

IN7-18

IN8+20

IN8-21 OUT8+

37

OUT8-38

OUT7+40

OUT7-41

OUT6-42OUT6+43

OUT5+45

OUT5-46

OUT4-47OUT4+48

OUT3+49

OUT3-50

OUT2-51OUT2+52

OUT1+54

OUT1-55

OUT0-56OUT0+57

AG

ND

1

AG

ND

2

AG

ND

58

AG

ND

64

AG

ND

70

DG

ND

19

DG

ND

22

DG

ND

39

DG

ND

44

DG

ND

53

AV

DD

59

AV

DD

65

AV

DD

71

AV

DD

76

DV

DD

23

DV

DD

24

DV

DD

33

DV

DD

34

REFCLK+66

REFCLK-67

DTAP62

PLLLCK63

PLLOUT68

DSPEED69

DWRITE73

DENABLE74

WSRIN75

BIAS72

O-OFS36

ROFS30

RESET35

A361

A260

A132

A031

RSRLOAD29

SRCLK28

SRIN27

SROUT26

WSROUT25

TH

PA

D77

R2501.1K0.1%

C3831uF

10%10V

C443100nF10V

C46327nF50V

C462100nF16V

R24

8

100

5%

R24

5

100

5%

R24

4

100

5%

C459100nF16V

C452100pF50V

R257

4.7 5%

C40810uF

10%10V

C454100pF50V

R24

1

100

5%

C44510uF10V

R24

6

100

5%

C441100nF10V

TP23TP

RND1.0SMD1

C4612.2nF50V

C465100nF16V

C455100pF50V

C4604.7nF25V

R24

3

100

5%

C444100uF6.3V

C464100nF16V

C453100pF50V

R249

100 5%

R24

7

100

5%

C44710uF10V

TP22TP

RND1.0SMD1

-

+U117

AD8027

31

62

4

5

C442100nF10V

C448100nF10V

R2542205%

R2511.15K0.1%

TP21TP

RND1.0SMD1

C446100uF6.3V

U116

LM41402.048V+/-0.1%

GN

D1

GN

D4

GN

D7

GN

D8

VIN2

EN3VREF

6

R2531.47K0.1%

C451100pF50V

R24

2

100

5%

C449100nF10V

R2521.87K0.1%

Page 42: University of Geneva 32-channel DRS4 Acquisition Board 01 ...dpnc.unige.ch/~bravar/DRSSS/DPNC342_02_01A_A60.pdf · CH-1211 GENEVE 4 02A University of Geneva DPNC342 Friday, October

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

REFCLK1+REFCLK1-

REFCLK2+REFCLK2-

REFCLK3+REFCLK3-

REFCLK4+REFCLK4-

VOCM

IN1IN2IN3IN4IN5IN6IN7IN8

IN9IN10IN11IN12IN13IN14IN15IN16

IN17IN18IN19IN20IN21IN22IN23IN24

IN25IN26IN27IN28IN29IN30IN31IN32

TRIG4

TRIG3

TRIG2

TRIG1

DRSIN1DRSIN2DRSIN3DRSIN4DRSIN5DRSIN6DRSIN7

DRSIN8DRSIN9DRSIN10

TCAL1

TCAL2

TCAL3

TCAL4

TLEVEL1TLEVEL2TLEVEL3TLEVEL4

VCAL

DRSIN1DRSIN2DRSIN3DRSIN4DRSIN5DRSIN6DRSIN7

DRSIN8DRSIN9DRSIN10

DRSIN1DRSIN2DRSIN3DRSIN4DRSIN5DRSIN6DRSIN7

DRSIN8DRSIN9DRSIN10

DRSIN1DRSIN2DRSIN3DRSIN4DRSIN5DRSIN6DRSIN7

DRSIN8DRSIN9DRSIN10

DRS1OUT1DRS1OUT2

DRS1OUT3

DRS2OUT1DRS2OUT2

DRS2OUT3

DRS3OUT1DRS3OUT2

DRS3OUT3

DRS4OUT1DRS4OUT2

DRS4OUT3

DRSIN9DRSIN8

OUTM1+

OUTM2+

OUTM3+

OUTM4+

OUTM1-

OUTM2-

OUTM3-

OUTM4-

IN[1..32]

RESET

TS4CS

TS3CS

TS2CS

TS1CS

TS_SDOTS_SDITS_SCK

DAC_SCKDAC_SDI

EXT_TCAL

TCAE

VCALDIS

EXT_CLK+EXT_CLK-

SEL_INSEL_CAL

TRIG[1..4]

DAC_CS

CXOESEL_TC

DRS1OUT[1..3]

DRS2OUT[1..3]

DRS3OUT[1..3]

DRS4OUT[1..3]

DRSIN[1..10]

+5V_A1

+5V_A2-5V_A2

-5V_A1

-5V_A1+5V_A1

-5V_A2+5V_A2

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Thursday, September 29, 201642 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardDRS4 X4

Schematic Path = /DRS4X32CH_1

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Thursday, September 29, 201642 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardDRS4 X4

Schematic Path = /DRS4X32CH_1

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Thursday, September 29, 201642 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardDRS4 X4

Schematic Path = /DRS4X32CH_1

R2041K

DRS4X8CH_3

DRS4X8CH

IN1IN2IN3IN4IN5IN6IN7IN8

OUTM+OUTM-

REFCLK+REFCLK-

VOCMVCALTCAL

TRIGOUT

DRS_A0DRS_A1DRS_A2DRS_A3

DRS_RSRLOADDRS_SRCLK

DRS_SRINDRS_SROUT

DRS_WSROUTDRS_DWRITE

DRS_DENABLEDRS_WSRIN

PLLLCK

TS_CSTS_SCKTS_SDI

TS_SDO

RESET

SEL_CALSEL_IN

TLEVEL

V+V-

R2051K

TCA_1

TCA

TCAE

ETCAL

TCAL1

TCAL2

TCAL3

TCAL4SELCXOE

DRS4X8CH_2

DRS4X8CH

IN1IN2IN3IN4IN5IN6IN7IN8

OUTM+OUTM-

REFCLK+REFCLK-

VOCMVCALTCAL

TRIGOUT

DRS_A0DRS_A1DRS_A2DRS_A3

DRS_RSRLOADDRS_SRCLK

DRS_SRINDRS_SROUT

DRS_WSROUTDRS_DWRITE

DRS_DENABLEDRS_WSRIN

PLLLCK

TS_CSTS_SCKTS_SDI

TS_SDO

RESET

SEL_CALSEL_IN

TLEVEL

V+V-

CLK_1

CLOCK

EXT_CLK+

CLK0+CLK0-

CLK1+CLK1-

CLK2+CLK2-

CLK3+CLK3-

EXT_CLK-

DAC8_1

DAC8

CSSCKSDI

TLEVEL1TLEVEL2TLEVEL3TLEVEL4

VCALDIS

VREF_1

VREF0V7

OUT

DRS4X8CH_1

DRS4X8CH

IN1IN2IN3IN4IN5IN6IN7IN8

OUTM+OUTM-

REFCLK+REFCLK-

VOCMVCALTCAL

TRIGOUT

DRS_A0DRS_A1DRS_A2DRS_A3

DRS_RSRLOADDRS_SRCLK

DRS_SRINDRS_SROUT

DRS_WSROUTDRS_DWRITE

DRS_DENABLEDRS_WSRIN

PLLLCK

TS_CSTS_SCKTS_SDI

TS_SDO

RESET

SEL_CALSEL_IN

TLEVEL

V+V-

DRS4X8CH_4

DRS4X8CH

IN1IN2IN3IN4IN5IN6IN7IN8

OUTM+OUTM-

REFCLK+REFCLK-

VOCMVCALTCAL

TRIGOUT

DRS_A0DRS_A1DRS_A2DRS_A3

DRS_RSRLOADDRS_SRCLK

DRS_SRINDRS_SROUT

DRS_WSROUTDRS_DWRITE

DRS_DENABLEDRS_WSRIN

PLLLCK

TS_CSTS_SCKTS_SDI

TS_SDO

RESET

SEL_CALSEL_IN

TLEVEL

V+V-

Page 43: University of Geneva 32-channel DRS4 Acquisition Board 01 ...dpnc.unige.ch/~bravar/DRSSS/DPNC342_02_01A_A60.pdf · CH-1211 GENEVE 4 02A University of Geneva DPNC342 Friday, October

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

TEMPERATURE SENSORTO BE LOCATED NEAR DRS4

FOR ca. 25mVHYSTERESIS

DRS4_IN1+DRS4_IN1-

DRS4_IN2+DRS4_IN2-

DRS4_IN3+DRS4_IN3-

DRS4_IN4+DRS4_IN4-

DRS4_IN6+DRS4_IN6-

DRS4_IN7+DRS4_IN7-

DRS4_IN8+DRS4_IN8-

DRS4_IN5+DRS4_IN5-

V+

V-

V+ V-

V+

V-

V+ V-

V+

IN1

IN2

IN3

IN4

IN5

IN6

IN7

IN8

OUTM+OUTM-

REFCLK+REFCLK-

VOCMVCAL

DRS_A0DRS_A1DRS_A2DRS_A3

DRS_RSRLOADDRS_SRCLKDRS_SRIN

DRS_SROUTDRS_WSROUT

DRS_DWRITEDRS_DENABLEDRS_WSRIN

PLLLCK

RESET

TS_CSTS_SCKTS_SDI

TS_SDO

TCAL

SEL_CALSEL_IN

TRIGOUT

TLEVEL

V+V-

+3.3V

+3.3V

+2.5V

+2.5V

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Tuesday, October 04, 201643 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition Board8-Analog Front-End + DRS4 Schematic Path = /DRS4X32CH_1/DRS4X8CH_1

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Tuesday, October 04, 201643 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition Board8-Analog Front-End + DRS4 Schematic Path = /DRS4X32CH_1/DRS4X8CH_1

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Tuesday, October 04, 201643 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition Board8-Analog Front-End + DRS4 Schematic Path = /DRS4X32CH_1/DRS4X8CH_1

R268

36 5%

C472100nF16V

C466100nF10V

DRS4_1

DRS4

IN1+IN1-

IN2+IN2-

IN3+IN3-

IN4+IN4-

DRS_A0DRS_A1DRS_A2DRS_A3

DRS_RSRLOADDRS_SRCLK

DRS_SRINDRS_SROUT

DRS_WSROUT

DRS_DWRITEDRS_DENABLE

DRS_WSRIN

RESET

IN5+IN5-

REFCLK+REFCLK-

PLLLCK

IN8+

IN7+

IN8-

IN6+

IN7-

IN6-

OUTM+OUTM-

V+

R271

36 5%

R259

249 0.1%

AFE_6

AFE

TRIG

OUTPOUTN

IN

VOCMVCALTCAL

SEL_INSEL_CAL

V-V+

R260565%

+

-LE

U120

ADCMP601

1

2

3

4

56

-

+U118

LMH6609900MHz

31

52

4

R266

36 5%

C471100nF10V

C469100nF16V

AFE_5

AFE

TRIG

OUTPOUTN

IN

VOCMVCALTCAL

SEL_INSEL_CAL

V-V+

R269

36 5%

C468100nF16V

R262

24 1%

R263

499 1%

AFE_4

AFE

TRIG

OUTPOUTN

IN

VOCMVCALTCAL

SEL_INSEL_CAL

V-V+

°C

U121

ADT730113-bits

GN

D1

VD

D3

DIN2

SCLK4

CS5 DOUT

6

-

+U119

LMH6609900MHz

31

52

4

R264240K

R267

36 5%

AFE_1

AFE

TRIG

OUTPOUTN

IN

VOCMVCALTCAL

SEL_INSEL_CAL

V-V+

AFE_8

AFE

TRIG

OUTPOUTN

IN

VOCMVCALTCAL

SEL_INSEL_CAL

V-V+

R270

36 5%

AFE_3

AFE

TRIG

OUTPOUTN

IN

VOCMVCALTCAL

SEL_INSEL_CAL

V-V+

R261

499 1%

R258

36 5%

C470100nF16V

R265

36 5%

C467100nF16V

AFE_7

AFE

TRIG

OUTPOUTN

IN

VOCMVCALTCAL

SEL_INSEL_CAL

V-V+

AFE_2

AFE

TRIG

OUTPOUTN

IN

VOCMVCALTCAL

SEL_INSEL_CAL

V-V+

Page 44: University of Geneva 32-channel DRS4 Acquisition Board 01 ...dpnc.unige.ch/~bravar/DRSSS/DPNC342_02_01A_A60.pdf · CH-1211 GENEVE 4 02A University of Geneva DPNC342 Friday, October

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

TEMPERATURE SENSORTO BE LOCATED NEAR DRS4

FOR ca. 25mVHYSTERESIS

DRS4_IN1+DRS4_IN1-

DRS4_IN2+DRS4_IN2-

DRS4_IN3+DRS4_IN3-

DRS4_IN4+DRS4_IN4-

DRS4_IN6+DRS4_IN6-

DRS4_IN7+DRS4_IN7-

DRS4_IN8+DRS4_IN8-

DRS4_IN5+DRS4_IN5-

V+

V-

V+ V-

V+

V-

V+ V-

V+

IN1

IN2

IN3

IN4

IN5

IN6

IN7

IN8

OUTM+OUTM-

REFCLK+REFCLK-

VOCMVCAL

DRS_A0DRS_A1DRS_A2DRS_A3

DRS_RSRLOADDRS_SRCLKDRS_SRIN

DRS_SROUTDRS_WSROUT

DRS_DWRITEDRS_DENABLEDRS_WSRIN

PLLLCK

RESET

TS_CSTS_SCKTS_SDI

TS_SDO

TCAL

SEL_CALSEL_IN

TRIGOUT

TLEVEL

V+V-

+3.3V

+3.3V

+2.5V

+2.5V

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Tuesday, October 04, 201644 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition Board8-Analog Front-End + DRS4 Schematic Path = /DRS4X32CH_1/DRS4X8CH_2

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Tuesday, October 04, 201644 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition Board8-Analog Front-End + DRS4 Schematic Path = /DRS4X32CH_1/DRS4X8CH_2

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Tuesday, October 04, 201644 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition Board8-Analog Front-End + DRS4 Schematic Path = /DRS4X32CH_1/DRS4X8CH_2

R282

36 5%

C479100nF16V

C473100nF10V

DRS4_1

DRS4

IN1+IN1-

IN2+IN2-

IN3+IN3-

IN4+IN4-

DRS_A0DRS_A1DRS_A2DRS_A3

DRS_RSRLOADDRS_SRCLK

DRS_SRINDRS_SROUT

DRS_WSROUT

DRS_DWRITEDRS_DENABLE

DRS_WSRIN

RESET

IN5+IN5-

REFCLK+REFCLK-

PLLLCK

IN8+

IN7+

IN8-

IN6+

IN7-

IN6-

OUTM+OUTM-

V+

R285

36 5%

R273

249 0.1%

AFE_6

AFE

TRIG

OUTPOUTN

IN

VOCMVCALTCAL

SEL_INSEL_CAL

V-V+

R274565%

+

-LE

U124

ADCMP601

1

2

3

4

56

-

+U122

LMH6609900MHz

31

52

4

R280

36 5%

C478100nF10V

C476100nF16V

AFE_5

AFE

TRIG

OUTPOUTN

IN

VOCMVCALTCAL

SEL_INSEL_CAL

V-V+

R283

36 5%

C475100nF16V

R276

24 1%

R277

499 1%

AFE_4

AFE

TRIG

OUTPOUTN

IN

VOCMVCALTCAL

SEL_INSEL_CAL

V-V+

°C

U125

ADT730113-bits

GN

D1

VD

D3

DIN2

SCLK4

CS5 DOUT

6

-

+U123

LMH6609900MHz

31

52

4

R278240K

R281

36 5%

AFE_1

AFE

TRIG

OUTPOUTN

IN

VOCMVCALTCAL

SEL_INSEL_CAL

V-V+

AFE_8

AFE

TRIG

OUTPOUTN

IN

VOCMVCALTCAL

SEL_INSEL_CAL

V-V+

R284

36 5%

AFE_3

AFE

TRIG

OUTPOUTN

IN

VOCMVCALTCAL

SEL_INSEL_CAL

V-V+

R275

499 1%

R272

36 5%

C477100nF16V

R279

36 5%

C474100nF16V

AFE_7

AFE

TRIG

OUTPOUTN

IN

VOCMVCALTCAL

SEL_INSEL_CAL

V-V+

AFE_2

AFE

TRIG

OUTPOUTN

IN

VOCMVCALTCAL

SEL_INSEL_CAL

V-V+

Page 45: University of Geneva 32-channel DRS4 Acquisition Board 01 ...dpnc.unige.ch/~bravar/DRSSS/DPNC342_02_01A_A60.pdf · CH-1211 GENEVE 4 02A University of Geneva DPNC342 Friday, October

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

TEMPERATURE SENSORTO BE LOCATED NEAR DRS4

FOR ca. 25mVHYSTERESIS

DRS4_IN1+DRS4_IN1-

DRS4_IN2+DRS4_IN2-

DRS4_IN3+DRS4_IN3-

DRS4_IN4+DRS4_IN4-

DRS4_IN6+DRS4_IN6-

DRS4_IN7+DRS4_IN7-

DRS4_IN8+DRS4_IN8-

DRS4_IN5+DRS4_IN5-

V+

V-

V+ V-

V+

V-

V+ V-

V+

IN1

IN2

IN3

IN4

IN5

IN6

IN7

IN8

OUTM+OUTM-

REFCLK+REFCLK-

VOCMVCAL

DRS_A0DRS_A1DRS_A2DRS_A3

DRS_RSRLOADDRS_SRCLKDRS_SRIN

DRS_SROUTDRS_WSROUT

DRS_DWRITEDRS_DENABLEDRS_WSRIN

PLLLCK

RESET

TS_CSTS_SCKTS_SDI

TS_SDO

TCAL

SEL_CALSEL_IN

TRIGOUT

TLEVEL

V+V-

+3.3V

+3.3V

+2.5V

+2.5V

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Tuesday, October 04, 201645 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition Board8-Analog Front-End + DRS4 Schematic Path = /DRS4X32CH_1/DRS4X8CH_3

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Tuesday, October 04, 201645 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition Board8-Analog Front-End + DRS4 Schematic Path = /DRS4X32CH_1/DRS4X8CH_3

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Tuesday, October 04, 201645 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition Board8-Analog Front-End + DRS4 Schematic Path = /DRS4X32CH_1/DRS4X8CH_3

R296

36 5%

C486100nF16V

C480100nF10V

DRS4_1

DRS4

IN1+IN1-

IN2+IN2-

IN3+IN3-

IN4+IN4-

DRS_A0DRS_A1DRS_A2DRS_A3

DRS_RSRLOADDRS_SRCLK

DRS_SRINDRS_SROUT

DRS_WSROUT

DRS_DWRITEDRS_DENABLE

DRS_WSRIN

RESET

IN5+IN5-

REFCLK+REFCLK-

PLLLCK

IN8+

IN7+

IN8-

IN6+

IN7-

IN6-

OUTM+OUTM-

V+

R299

36 5%

R287

249 0.1%

AFE_6

AFE

TRIG

OUTPOUTN

IN

VOCMVCALTCAL

SEL_INSEL_CAL

V-V+

R288565%

+

-LE

U128

ADCMP601

1

2

3

4

56

-

+U126

LMH6609900MHz

31

52

4

R294

36 5%

C485100nF10V

C483100nF16V

AFE_5

AFE

TRIG

OUTPOUTN

IN

VOCMVCALTCAL

SEL_INSEL_CAL

V-V+

R297

36 5%

C482100nF16V

R290

24 1%

R291

499 1%

AFE_4

AFE

TRIG

OUTPOUTN

IN

VOCMVCALTCAL

SEL_INSEL_CAL

V-V+

°C

U129

ADT730113-bits

GN

D1

VD

D3

DIN2

SCLK4

CS5 DOUT

6

-

+U127

LMH6609900MHz

31

52

4

R292240K

R295

36 5%

AFE_1

AFE

TRIG

OUTPOUTN

IN

VOCMVCALTCAL

SEL_INSEL_CAL

V-V+

AFE_8

AFE

TRIG

OUTPOUTN

IN

VOCMVCALTCAL

SEL_INSEL_CAL

V-V+

R298

36 5%

AFE_3

AFE

TRIG

OUTPOUTN

IN

VOCMVCALTCAL

SEL_INSEL_CAL

V-V+

R289

499 1%

R286

36 5%

C484100nF16V

R293

36 5%

C481100nF16V

AFE_7

AFE

TRIG

OUTPOUTN

IN

VOCMVCALTCAL

SEL_INSEL_CAL

V-V+

AFE_2

AFE

TRIG

OUTPOUTN

IN

VOCMVCALTCAL

SEL_INSEL_CAL

V-V+

Page 46: University of Geneva 32-channel DRS4 Acquisition Board 01 ...dpnc.unige.ch/~bravar/DRSSS/DPNC342_02_01A_A60.pdf · CH-1211 GENEVE 4 02A University of Geneva DPNC342 Friday, October

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

TEMPERATURE SENSORTO BE LOCATED NEAR DRS4

FOR ca. 25mVHYSTERESIS

DRS4_IN1+DRS4_IN1-

DRS4_IN2+DRS4_IN2-

DRS4_IN3+DRS4_IN3-

DRS4_IN4+DRS4_IN4-

DRS4_IN6+DRS4_IN6-

DRS4_IN7+DRS4_IN7-

DRS4_IN8+DRS4_IN8-

DRS4_IN5+DRS4_IN5-

V+

V-

V+ V-

V+

V-

V+ V-

V+

IN1

IN2

IN3

IN4

IN5

IN6

IN7

IN8

OUTM+OUTM-

REFCLK+REFCLK-

VOCMVCAL

DRS_A0DRS_A1DRS_A2DRS_A3

DRS_RSRLOADDRS_SRCLKDRS_SRIN

DRS_SROUTDRS_WSROUT

DRS_DWRITEDRS_DENABLEDRS_WSRIN

PLLLCK

RESET

TS_CSTS_SCKTS_SDI

TS_SDO

TCAL

SEL_CALSEL_IN

TRIGOUT

TLEVEL

V+V-

+3.3V

+3.3V

+2.5V

+2.5V

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Tuesday, October 04, 201646 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition Board8-Analog Front-End + DRS4 Schematic Path = /DRS4X32CH_1/DRS4X8CH_4

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Tuesday, October 04, 201646 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition Board8-Analog Front-End + DRS4 Schematic Path = /DRS4X32CH_1/DRS4X8CH_4

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Tuesday, October 04, 201646 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition Board8-Analog Front-End + DRS4 Schematic Path = /DRS4X32CH_1/DRS4X8CH_4

R310

36 5%

C493100nF16V

C487100nF10V

DRS4_1

DRS4

IN1+IN1-

IN2+IN2-

IN3+IN3-

IN4+IN4-

DRS_A0DRS_A1DRS_A2DRS_A3

DRS_RSRLOADDRS_SRCLK

DRS_SRINDRS_SROUT

DRS_WSROUT

DRS_DWRITEDRS_DENABLE

DRS_WSRIN

RESET

IN5+IN5-

REFCLK+REFCLK-

PLLLCK

IN8+

IN7+

IN8-

IN6+

IN7-

IN6-

OUTM+OUTM-

V+

R313

36 5%

R301

249 0.1%

AFE_6

AFE

TRIG

OUTPOUTN

IN

VOCMVCALTCAL

SEL_INSEL_CAL

V-V+

R302565%

+

-LE

U132

ADCMP601

1

2

3

4

56

-

+U130

LMH6609900MHz

31

52

4

R308

36 5%

C492100nF10V

C490100nF16V

AFE_5

AFE

TRIG

OUTPOUTN

IN

VOCMVCALTCAL

SEL_INSEL_CAL

V-V+

R311

36 5%

C489100nF16V

R304

24 1%

R305

499 1%

AFE_4

AFE

TRIG

OUTPOUTN

IN

VOCMVCALTCAL

SEL_INSEL_CAL

V-V+

°C

U133

ADT730113-bits

GN

D1

VD

D3

DIN2

SCLK4

CS5 DOUT

6

-

+U131

LMH6609900MHz

31

52

4

R306240K

R309

36 5%

AFE_1

AFE

TRIG

OUTPOUTN

IN

VOCMVCALTCAL

SEL_INSEL_CAL

V-V+

AFE_8

AFE

TRIG

OUTPOUTN

IN

VOCMVCALTCAL

SEL_INSEL_CAL

V-V+

R312

36 5%

AFE_3

AFE

TRIG

OUTPOUTN

IN

VOCMVCALTCAL

SEL_INSEL_CAL

V-V+

R303

499 1%

R300

36 5%

C491100nF16V

R307

36 5%

C488100nF16V

AFE_7

AFE

TRIG

OUTPOUTN

IN

VOCMVCALTCAL

SEL_INSEL_CAL

V-V+

AFE_2

AFE

TRIG

OUTPOUTN

IN

VOCMVCALTCAL

SEL_INSEL_CAL

V-V+

Page 47: University of Geneva 32-channel DRS4 Acquisition Board 01 ...dpnc.unige.ch/~bravar/DRSSS/DPNC342_02_01A_A60.pdf · CH-1211 GENEVE 4 02A University of Geneva DPNC342 Friday, October

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

FPGA - DRS4 + TRIG + ADC (1/4)

DRSIN1DRSIN2DRSIN3DRSIN4DRSIN5DRSIN6DRSIN7DRSIN8DRSIN9

DRSxOUT1DRSIN10

DRSxOUT2DRSxOUT3

A3A2A1A0RSRLOADSRCLKSRINDWRITEDENABLE

SROUTWSRIN

WSROUTPLLLCK

DRS1OUT1

DRS1OUT3

DRS1OUT2

DRS2OUT3

DRS2OUT1

DRS2OUT2

DRS3OUT2

DRS3OUT1

DRS3OUT3

DRS4OUT1

DRS4OUT3DRS4OUT2

DRSIN4

DRSIN3

DRSIN2

DRSIN1

DRSIN5

DRSIN6DRSIN7

DRSIN8

DRSIN9

DRSIN10

TRIG1

TRIG2

TRIG3

TRIG4

TESTIO0TESTIO2TESTIO4TESTIO6TESTIO8

TESTIO10TESTIO12TESTIO14

TESTIO1

TESTIO9TESTIO11TESTIO13TESTIO15

TESTIO4TESTIO3

TESTIO6

TESTIO8

TESTIO1TESTIO9

TESTIO12

TESTIO14

TESTIO2

TESTIO10

TESTIO11

TESTIO13

TESTIO0

TESTIO15

TESTIO3

ADC_OUT1+

ADC_OUT2+

ADC_OUT3+

ADC_OUT4+

ADC_OUT1-

ADC_OUT2-

ADC_OUT3-

ADC_OUT4-

ADC_CLK+ADC_CLK-

DRS1OUT[1..3]

DRS2OUT[1..3]

DRS3OUT[1..3]

DRS4OUT[1..3]

DRSIN[1..10]

VCALDIS

TRIG[1..4]

DAC_CS

DAC_SCK

DAC_SDI

RESETOUT

TS1CS

+2.5V+2.5V

TESTIO7TESTIO5

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Thursday, September 29, 201647 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardSchematic Path = /FPGA_1

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Thursday, September 29, 201647 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardSchematic Path = /FPGA_1

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Thursday, September 29, 201647 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardSchematic Path = /FPGA_1

TP291

TP351

TP25 1

Cyclone V 5CEBA7F23VERSION : 1.1PAGE : 3 of 10DATE : JUN_ 2012

U1-3

5CEBA7F23149.5K LEC8

IO_4A_V13/DIFFIO_RX_B42N/DQ4BV13

IO_4A_AB12/DIFFIO_TX_B41P/DQ4BAB12

IO_4A_U13/DIFFIO_RX_B42P/DQ4BU13

IO_4A_T12/DIFFIO_RX_B43N/DQSN4BT12

IO_4A_AA14/DIFFIO_TX_B44N/DQ4BAA14

IO_4A_T13/DIFFIO_RX_B43P/DQS4BT13

IO_4A_AA13/DIFFIO_TX_B44PAA13

IO_4A_AB15/DIFFIO_TX_B45N/DQ4BAB15

IO_4A_Y14/DIFFIO_RX_B46N/DQ4BY14

IO_4A_AA15/DIFFIO_TX_B45P/DQ4BAA15

IO_4A_Y15/DIFFIO_RX_B46P/DQ4BY15

IO_4A_AB17/DIFFIO_TX_B48N/DQ4BAB17

IO_4A_AB18/DIFFIO_TX_B48P/DQ4BAB18

IO_4A_AB20/DIFFIO_TX_B49NAB20

IO_4A_Y16/DIFFIO_RX_B50N/DQ5BY16

IO_4A_AB21/DIFFIO_TX_B49P/DQ5BAB21

IO_4A_Y17/DIFFIO_RX_B50P/DQ5BY17

IO_4A_T14/DIFFIO_RX_B51N/DQSN5BT14

IO_4A_AA17/DIFFIO_TX_B52N/DQ5BAA17

IO_4A_U15/DIFFIO_RX_B51P/DQS5BU15

IO_4A_AA18/DIFFIO_TX_B52PAA18

IO_4A_AA19/DIFFIO_TX_B53N/DQ5BAA19

IO_4A_V20/DIFFIO_RX_B54N/DQ5BV20

IO_4A_AA20/DIFFIO_TX_B53P/DQ5BAA20

IO_4A_W19/DIFFIO_RX_B54P/DQ5BW19

IO_4A_AB22/DIFFIO_TX_B56N/DQ5BAB22

IO_4A_AA22/DIFFIO_TX_B56P/DQ5BAA22

IO_4A_Y22/DIFFIO_TX_B57NY22

IO_4A_Y20/DIFFIO_RX_B58N/DQ6BY20

IO_4A_W22/DIFFIO_TX_B57P/DQ6BW22

IO_4A_Y19/DIFFIO_RX_B58P/DQ6BY19

IO_4A_P14/DIFFIO_RX_B59N/DQSN6BP14

IO_4A_Y21/DIFFIO_TX_B60N/DQ6BY21

IO_4A_R14/DIFFIO_RX_B59P/DQS6BR14

IO_4A_W21/DIFFIO_TX_B60PW21

IO_4A_U22/DIFFIO_TX_B61N/DQ6BU22

IO_4A_V19/DIFFIO_RX_B62N/DQ6BV19

IO_4A_V21/DIFFIO_TX_B61P/DQ6BV21

IO_4A_V18/DIFFIO_RX_B62P/DQ6BV18

IO_4A_U16/DIFFIO_RX_B63NU16

IO_4A_U21/DIFFIO_TX_B64N/DQ6BU21

IO_4A_U17/DIFFIO_RX_B63PU17

IO_4A_U20/DIFFIO_TX_B64P/DQ6BU20

Cyclone V 5CEBA7F23VERSION : 1.1PAGE : 2 of 10DATE : JUN_ 2012

U1-2

5CEBA7F23149.5K LEC8

IO_3B_M8/CLK0N,FPLL_BL_FBN/DIFFIO_RX_B31NM8

IO_3B_M9/CLK0P,FPLL_BL_FBP/DIFFIO_RX_B31PM9

IO_3B_AB10/FPLL_BL_CLKOUT1,FPLL_BL_CLKOUTN/DIFFIO_TX_B37N/DQ3BAB10

IO_3B_AB11/FPLL_BL_CLKOUT0,FPLL_BL_CLKOUTP,FPLL_BL_FB/DIFFIO_TX_B37P/DQ3BAB11

IO_3A_P7/DIFFIO_TX_B8P/DQ1BP7

IO_3B_AB6/DIFFIO_TX_B25NAB6

IO_3B_V9/DIFFIO_RX_B26N/DQ2BV9

IO_3B_AB5/DIFFIO_TX_B25P/DQ2BAB5

IO_3B_V10/DIFFIO_RX_B26P/DQ2BV10

IO_3B_P8/DIFFIO_RX_B27N/DQSN2BP8

IO_3B_AA7/DIFFIO_TX_B28N/DQ2BAA7

IO_3B_N8/DIFFIO_RX_B27P/DQS2BN8

IO_3B_AB7/DIFFIO_TX_B28PAB7

IO_3B_AA8/DIFFIO_TX_B29N/DQ2BAA8

IO_3B_T9/DIFFIO_RX_B30N/DQ2BT9

IO_3B_AB8/DIFFIO_TX_B29P/DQ2BAB8

IO_3B_U10/DIFFIO_RX_B30P/DQ2BU10

IO_3B_AA10/DIFFIO_TX_B32N/DQ2BAA10

IO_3B_AA9/DIFFIO_TX_B32P/DQ2BAA9

IO_3B_Y10/DIFFIO_TX_B33NY10

IO_3B_T10/DIFFIO_RX_B34N/DQ3BT10

IO_3B_Y9/DIFFIO_TX_B33P/DQ3BY9

IO_3B_R9/DIFFIO_RX_B34P/DQ3BR9

IO_3B_U11/DIFFIO_RX_B35N/DQSN3BU11

IO_3B_R12/DIFFIO_TX_B36N/DQ3BR12

IO_3B_U12/DIFFIO_RX_B35P/DQS3BU12

IO_3B_P12/DIFFIO_TX_B36PP12

IO_3B_R10/DIFFIO_RX_B38N/DQ3BR10

IO_3B_R11/DIFFIO_RX_B38P/DQ3BR11

IO_3B_Y11/DIFFIO_TX_B40N/DQ3BY11

IO_3B_AA12/DIFFIO_TX_B40P/DQ3BAA12

TP261

J11

HE10M/STP2.54

135791113151719

2468

101214161820 TP391

TP32 1

TP271TP30 1

TP36 1

TP28 1

TP34 1

TP331

TP24 1

TP38 1

TP311

TP371

Page 48: University of Geneva 32-channel DRS4 Acquisition Board 01 ...dpnc.unige.ch/~bravar/DRSSS/DPNC342_02_01A_A60.pdf · CH-1211 GENEVE 4 02A University of Geneva DPNC342 Friday, October

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

FPGA - MCU + CLOCKS (2/4)

** NO CONNECT BECAUSE OF DEVICE MIGRATION **

FRONT PANEL

TRIG IN

DATA TRANSFER

TIMING CAL

FW UPDATE

CLK40M

GPIO50_RGPIO51_R

UC_UART_RX_R

SLOEn_R

SLCSn_RUC_UART_CTSn_R

CTL10_RDQ31_RSLWRn_RPKTENDn_RDQ29_RSLRDn_RDQ20_RDQ17_RCTL9_RDQ26_RCTL8_RDQ27_RDQ21_RDQ22_RDQ18_RDQ24_RDQ25_RDQ28_RDQ30_RCTL6_R

DQ15_R

DQ8_R

DQ12_RDQ1_RDQ13_RDQ6_RDQ19_RDQ0_RDQ2_RDQ3_RDQ4_R

DQ9_RDQ10_RDQ14_R

DQ5_RDQ7_RDQ16_RDQ23_R

DQ11_R

A1_R

A0_R

LED4

LED5

LED6

LED7

LED5

LED6

LED7

LED4

STAT4STAT3

STAT2

DQ0DQ1DQ2DQ3

DQ0_RDQ1_RDQ2_RDQ3_R

DQ4DQ5DQ6DQ7

DQ4_RDQ5_RDQ6_RDQ7_R

DQ8DQ9DQ10DQ11

DQ8_RDQ9_RDQ10_RDQ11_R

DQ12DQ13DQ14DQ15

DQ12_RDQ13_RDQ14_RDQ15_R

DQ16DQ17DQ18DQ19

DQ16_RDQ17_RDQ18_RDQ19_R

DQ20DQ21DQ22DQ23

DQ20_RDQ21_RDQ22_RDQ23_R

DQ24DQ25DQ26DQ27

DQ24_RDQ25_RDQ26_RDQ27_R

DQ28DQ29DQ30DQ31

DQ28_RDQ29_RDQ30_RDQ31_R

A0A1

FLAGA

FLAGB

ADC_FCO+ADC_FCO-

ADC_DCO+ADC_DCO-

SLRDnSLWRn

SLOEn

PKTENDn

SLCSn

A[1..0]

CLK_USB

UC_UART_CTSnUC_UART_RX

UC_RESETn

INTn

DQ[31..0]

UC_UART_RTSn

UC_UART_TX

CTL6CTL8CTL9

CTL10

GPIO50GPIO51

TRIGIN_FP

STAT[1..4]

BUSY_FP

+3.3V

+3.3V

BOARDID1

BOARDID2BOARDID0

BOARDID8

TESTIO5TESTIO7

TRIGIN3

BOARDID9BOARDID5

BOARDID3

STAT1

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Thursday, September 29, 201648 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardSchematic Path = /FPGA_1

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Thursday, September 29, 201648 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardSchematic Path = /FPGA_1

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Thursday, September 29, 201648 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardSchematic Path = /FPGA_1

1 2

D34

G1/G2

1 3

2 4

RN19 22

1234

8765

RN17 22

1234

8765

RN13 22

1234

8765

R3182005%

RN21 22

1234

8765

R314

22 5%

1 2

D35

G1/G2

1 3

2 4

R3162005%

RN15 22

1234

8765

Cyclone V 5CEBA7F23VERSION : 1.1PAGE : 4 of 10DATE : JUN_ 2012

U1-4

5CEBA7F23149.5K LEC8

IO_5B_M22/FPLL_BR_CLKOUT0,FPLL_BR_CLKOUTP,FPLL_BR_FB/DIFFIO_TX_R36P/DQ2RM22

IO_5B_L22/FPLL_BR_CLKOUT1,FPLL_BR_CLKOUTN/DIFFIO_TX_R36N/DQ2RL22

IO_5A_T15/DIFFIO_RX_R4P/DQ1RT15

IO_5A_R15/DIFFIO_RX_R4N/DQ1RR15

IO_5A_P19/DIFFIO_TX_R7P/DQ1RP19

IO_5A_P16/DIFFIO_RX_R8P/DQ1RP16

IO_5A_P18/DIFFIO_TX_R7NP18

IO_5A_P17/DIFFIO_RX_R8N/DQ1RP17

IO_5B_N20/DIFFIO_TX_R34P/DQ2RN20

IO_5B_N21/DIFFIO_TX_R34N/DQ2RN21

IO_5B_N19/DIFFIO_RX_R35P/DQ2RN19

IO_5B_M18/DIFFIO_RX_R35N/DQ2RM18

IO_5B_K17/DIFFIO_RX_R37P/DQS2RK17

IO_5B_M20/DIFFIO_TX_R38PM20

IO_5B_L17/DIFFIO_RX_R37N/DQSN2RL17

IO_5B_M21/DIFFIO_TX_R38N/DQ2RM21

IO_5B_L19/DIFFIO_RX_R39P/DQ2RL19

IO_5B_K21/DIFFIO_TX_R40P/DQ2RK21

IO_5B_L18/DIFFIO_RX_R39N/DQ2RL18

IO_5B_K22/DIFFIO_TX_R40NK22

R3172005%

RN23 22

1234

8765

RN18 22

1234

8765

RN16 22

1234

8765

RN20 22

1234

8765

RN14 22

1234

8765

RN8 22

1234

8765

Y2

40MHz25PPM

VCC4

OUT3

GND2

EN1

RN22 22

1234

8765

R399

22 5%

Cyclone V 5CEBA7F23VERSION : 1.1PAGE : 7 of 10DATE : JUN_ 2012

U1-7

5CEBA7F23149.5K LEC8

CLK1N_P9/DIFFIO_RX_B39NP9

CLK1P_N9/DIFFIO_RX_B39PN9

CLK2N_V14/DIFFIO_RX_B47NV14

CLK2P_V15/DIFFIO_RX_B47PV15

CLK3N_V16/DIFFIO_RX_B55NV16

CLK3P_W16/DIFFIO_RX_B55PW16

CLK6P_N16/DIFFIO_RX_R33PN16

CLK6N_M16/DIFFIO_RX_R33NM16

CLK11P_H16/DIFFIO_RX_T25PH16

CLK11N_H15/DIFFIO_RX_T25NH15

CLK10P_H13/DIFFIO_RX_T33PH13

CLK10N_G13/DIFFIO_RX_T33NG13

CLK9P_G10/DIFFIO_RX_T41PG10

CLK9N_F10/DIFFIO_RX_T41NF10

RZQ_0_AB13/DIFFIO_TX_B41NAB13

RZQ_1_T19/DIFFIO_TX_R1P/DQ1RT19

RZQ_2_B11/DIFFIO_TX_T40NB11

VREFB3AN0Y7

VREFB3BN0Y12

VREFB4AN0AB16

VREFB5AN0R20

VREFB5BN0L20

VREFB7AN0C14

VREFB8AN0B8

R3152005%

Cyclone V 5CEBA7F23VERSION : 1.1PAGE : 5 of 10DATE : JUN_ 2012

U1-5

5CEBA7F23149.5K LEC8

IO_7A_H21/DIFFIO_RX_T1PH21

IO_7A_E21/DIFFIO_TX_T2P/DQ1TE21

IO_7A_G21/DIFFIO_RX_T1NG21

IO_7A_D21/DIFFIO_TX_T2N/DQ1TD21

IO_7A_E19/DIFFIO_RX_T3P/DQ1TE19

IO_7A_C20/DIFFIO_TX_T4P/DQ1TC20

IO_7A_D19/DIFFIO_RX_T3N/DQ1TD19

IO_7A_B20/DIFFIO_TX_T4N/DQ1TB20

IO_7A_J21/DIFFIO_RX_T5P/DQS1TJ21

IO_7A_B18/DIFFIO_TX_T6PB18

IO_7A_J22/DIFFIO_RX_T5N/DQSN1TJ22

IO_7A_B17/DIFFIO_TX_T6N/DQ1TB17

IO_7A_C21/DIFFIO_RX_T7P/DQ1TC21

IO_7A_G22/DIFFIO_TX_T8P/DQ1TG22

IO_7A_B21/DIFFIO_RX_T7N/DQ1TB21

IO_7A_F22/DIFFIO_TX_T8NF22

IO_7A_G20/DIFFIO_RX_T9PG20

IO_7A_E22/DIFFIO_TX_T10P/DQ2TE22

IO_7A_H20/DIFFIO_RX_T9NH20

IO_7A_D22/DIFFIO_TX_T10N/DQ2TD22

IO_7A_C19/DIFFIO_RX_T11P/DQ2TC19

IO_7A_B22/DIFFIO_TX_T12P/DQ2TB22

IO_7A_C18/DIFFIO_RX_T11N/DQ2TC18

IO_7A_A22/DIFFIO_TX_T12N/DQ2TA22

IO_7A_F19/DIFFIO_RX_T13P/DQS2TF19

IO_7A_E20/DIFFIO_TX_T14PE20

IO_7A_F18/DIFFIO_RX_T13N/DQSN2TF18

IO_7A_F20/DIFFIO_TX_T14N/DQ2TF20

IO_7A_A18/DIFFIO_RX_T15P/DQ2TA18

IO_7A_A20/DIFFIO_TX_T16P/DQ2TA20

IO_7A_A17/DIFFIO_RX_T15N/DQ2TA17

IO_7A_A19/DIFFIO_TX_T16NA19

IO_7A_K20/DIFFIO_RX_T17PK20

IO_7A_B16/DIFFIO_TX_T18P/DQ3TB16

IO_7A_K19/DIFFIO_RX_T17NK19

IO_7A_C16/DIFFIO_TX_T18N/DQ3TC16

IO_7A_D17/DIFFIO_RX_T19P/DQ3TD17

IO_7A_G17/DIFFIO_TX_T20P/DQ3TG17

IO_7A_E16/DIFFIO_RX_T19N/DQ3TE16

IO_7A_G16/DIFFIO_TX_T20N/DQ3TG16

IO_7A_G18/DIFFIO_RX_T21P/DQS3TG18

IO_7A_J19/DIFFIO_TX_T22PJ19

IO_7A_H18/DIFFIO_RX_T21N/DQSN3TH18

IO_7A_J18/DIFFIO_TX_T22N/DQ3TJ18

IO_7A_E15/DIFFIO_RX_T23P/DQ3TE15

IO_7A_A15/DIFFIO_TX_T24P/DQ3TA15

IO_7A_F15/DIFFIO_RX_T23N/DQ3TF15

IO_7A_A14/DIFFIO_TX_T24NA14

IO_7A_J17/DIFFIO_TX_T26P/DQ4TJ17

IO_7A_K16/DIFFIO_TX_T26N/DQ4TK16

IO_7A_C15/DIFFIO_RX_T27P/DQ4TC15

IO_7A_G15/DIFFIO_TX_T28P/DQ4TG15

IO_7A_B15/DIFFIO_RX_T27N/DQ4TB15

IO_7A_F14/DIFFIO_TX_T28N/DQ4TF14

IO_7A_H14/DIFFIO_RX_T29P/DQS4TH14

IO_7A_B13/DIFFIO_TX_T30PB13

IO_7A_J13/DIFFIO_RX_T29N/DQSN4TJ13

IO_7A_A13/DIFFIO_TX_T30N/DQ4TA13

IO_7A_E14/DIFFIO_RX_T31P/DQ4TE14

IO_7A_J11/DIFFIO_TX_T32P/DQ4TJ11

IO_7A_F13/DIFFIO_RX_T31N/DQ4TF13

IO_7A_H10/DIFFIO_TX_T32NH10

IO_7A_G11/DIFFIO_TX_T34P/DQ5TG11

IO_7A_F12/DIFFIO_TX_T34N/DQ5TF12

IO_7A_D13/DIFFIO_RX_T35P/DQ5TD13

IO_7A_B12/DIFFIO_TX_T36P/DQ5TB12

IO_7A_C13/DIFFIO_RX_T35N/DQ5TC13

IO_7A_A12/DIFFIO_TX_T36N/DQ5TA12

IO_7A_H11/DIFFIO_RX_T37P/DQS5TH11

IO_7A_L8/DIFFIO_TX_T38PL8

IO_7A_G12/DIFFIO_RX_T37N/DQSN5TG12

IO_7A_K9/DIFFIO_TX_T38N/DQ5TK9

IO_7A_D12/DIFFIO_RX_T39P/DQ5TD12

IO_7A_C11/DIFFIO_TX_T40P/DQ5TC11

IO_7A_E12/DIFFIO_RX_T39N/DQ5TE12

C49410nF10%16V

Page 49: University of Geneva 32-channel DRS4 Acquisition Board 01 ...dpnc.unige.ch/~bravar/DRSSS/DPNC342_02_01A_A60.pdf · CH-1211 GENEVE 4 02A University of Geneva DPNC342 Friday, October

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

FPGA - DDL + USER IO + EEPROM + CONFIG

AS x4 ModeStandard PORDelay

USB-Blaster10-pin Male Header(AS Mode)

INIT_DONE OUTPUTOPTION MUST BEENABLED IN QUARTUS

FPGA I/O NEED TO BE CONFIGURED WITH PULL-UP ANDBOARDID BE INVERTED TO REFLECT CORRECT ENCODING

ACTIVE-HIGHRESET OUTPUT

FLASH MEMORYTO STORE BOARD S/NAND CALIB DATA

BOARDID + RESET + LEDS (3/4)FRONT PANEL

READY

ACQUIRE

BUSY

ERROR

AS_DATA0AS_DATA1AS_DATA2AS_DATA3NCSO

NCENSTATUS

NCONFIG

CONF_DONEDCLK

INIT_DONE

BOARDID6

BOARDID11

BOARDID4

BOARDID10

BOARDID6

BOARDID4

BOARDID7

LED1

LED3

LED2

LED1

LED2

LED3

LED0

EECS

INIT_DONE

RESETIN

LED0

UTX3

UTX5

UTX6URX1UTX2URX0URX4URX7UTX1URX5URX6

UTX7URX2UTX4UTX0

TS_SCK

TS_SDI TS_SDO

EECS

RESETIN

TRIGIN4

TRIGIN1TRIGIN2

BOARDID7

BOARDID10BOARDID11

URX3

TCKTMS

TDI

TDO

TCAE

SEL_TC

CXOE

SEL_CALSEL_IN

TS2CS

TS3CS

TS4CS

TS_SDO

TS_SCK

ADC_CSBADC_SCLK

ADC_SDIO

DDL_EN

DDL_CLKOUTDDL_DATOUT

DDL_DATIN

DDL_CLKIN

URXEN

UTXEN

URX[0..7]

UTX[0..7]

TS_SDI

TRIGIN[1..4]

+3.3V

+3.3V

+3.3V

+3.3V

+3.3V+3.3V

+3.3V

+3.3V

+3.3V

+3.3V+3.3V

+3.3V

BOARDID5

BOARDID3

BOARDID9

BOARDID1

TRIGIN3

BOARDID8

BOARDID0

BOARDID2

STAT1

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Thursday, September 29, 201649 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardSchematic Path = /FPGA_1

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Thursday, September 29, 201649 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardSchematic Path = /FPGA_1

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Thursday, September 29, 201649 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardSchematic Path = /FPGA_1

R32510K

R32710K

U135

MAX6839SXD070us

RESET_IN1

VC

C2

GN

D3

RESET4

SW2

SW ROTARYSTHEX

1248

C1C2

1 2

D37

G1/G2

1 3

2 4

R3261K

SW1

SW ROTARYSTHEX

1248

C1C2

R32310K

J13

HE10M/STP2.54

246810

13579

R32010K

R3312005%

R3292005%

U136

S25FL116K16MbVCC=+3.3V

HOLD7

SO2

WP3

SI5

SCLK6

CS1

J12

HE10M/STP2.54

1 2

C497100nF

R3302005%

R32410K

R3211K

Cyclone V 5CEBA7F23VERSION : 1.1PAGE : 8 of 10DATE : JUN_ 2012

U1-8

5CEBA7F23149.5K LEC8

NCSO_3A_R4/DATA4R4

AS_DATA3_3A_T4/DATA3T4

AS_DATA2_3A_AA5/DATA2AA5

AS_DATA1_3A_AB3/DATA1AB3

AS_DATA0,ASDO_3A_AB4/DATA0AB4

IO_3A_R6/DATA6/DIFFIO_RX_B1N/DQ1BR6

IO_3A_U7/DATA5/DIFFIO_TX_B2NU7

IO_3A_R5/DATA8/DIFFIO_RX_B1P/DQ1BR5

IO_3A_U8/DATA7/DIFFIO_TX_B2P/DQ1BU8

IO_3A_P6/DATA10/DIFFIO_RX_B3N/DQSN1BP6

IO_3A_W8/DATA9/DIFFIO_TX_B4N/DQ1BW8

IO_3A_N6/DATA12/DIFFIO_RX_B3P/DQS1BN6

IO_3A_W9/DATA11/DIFFIO_TX_B4PW9

IO_3A_T7/DATA14/DIFFIO_RX_B5N/DQ1BT7

IO_3A_U6/DATA13/DIFFIO_TX_B6N/DQ1BU6

IO_3A_V6/DATA15/DIFFIO_TX_B6P/DQ1BV6

IO_3A_T8/CLKUSR/DIFFIO_RX_B5P/DQ1BT8

IO_3A_M6/PR_DONE/DIFFIO_RX_B7NM6

IO_3A_R7/PR_READY/DIFFIO_TX_B8N/DQ1BR7

IO_3A_M7/PR_ERROR/DIFFIO_RX_B7PM7

IO_5A_T18/INIT_DONE/DIFFIO_RX_R2PT18

IO_5A_T20/PR_REQUEST/DIFFIO_TX_R1N/DQ1RT20

IO_5A_T17/CRC_ERROR/DIFFIO_RX_R2NT17

IO_5A_T22/NCEO/DIFFIO_TX_R3P/DQ1RT22

IO_5A_R22/CVP_CONFDONE/DIFFIO_TX_R3N/DQ1RR22

IO_5A_R21/DEV_OE/DIFFIO_TX_R5PR21

IO_5A_R16/NPERSTL0/DIFFIO_RX_R6P/DQS1RR16

IO_5A_P22/DEV_CLRN/DIFFIO_TX_R5N/DQ1RP22

IO_5A_R17/NPERSTL1/DIFFIO_RX_R6N/DQSN1RR17

MSEL0L6

MSEL1J6

MSEL2A2

MSEL3E5

MSEL4F3

TDOM5

TMSP5

TCKV5

TDIW5

DCLKV3

CONF_DONEK6

NSTATUSH5

NCEG5

NCONFIGA4

Cyclone V 5CEBA7F23VERSION : 1.1PAGE : 6 of 10DATE : JUN_ 2012

U1-6

5CEBA7F23149.5K LEC8

IO_8A_H8/FPLL_TL_CLKOUT0,FPLL_TL_CLKOUTP,FPLL_TL_FB/DIFFIO_TX_T44P/DQ6TH8

IO_8A_G8/FPLL_TL_CLKOUT1,FPLL_TL_CLKOUTN/DIFFIO_TX_T44N/DQ6TG8

IO_8A_E10/CLK8P,FPLL_TL_FBP/DIFFIO_RX_T49PE10

IO_8A_F9/CLK8N,FPLL_TL_FBN/DIFFIO_RX_T49NF9

IO_8A_L7/DIFFIO_TX_T42P/DQ6TL7

IO_8A_K7/DIFFIO_TX_T42N/DQ6TK7

IO_8A_J7/DIFFIO_RX_T43P/DQ6TJ7

IO_8A_J8/DIFFIO_RX_T43N/DQ6TJ8

IO_8A_J9/DIFFIO_RX_T45P/DQS6TJ9

IO_8A_A10/DIFFIO_TX_T46PA10

IO_8A_H9/DIFFIO_RX_T45N/DQSN6TH9

IO_8A_A9/DIFFIO_TX_T46N/DQ6TA9

IO_8A_B10/DIFFIO_RX_T47P/DQ6TB10

IO_8A_A5/DIFFIO_TX_T48P/DQ6TA5

IO_8A_C9/DIFFIO_RX_T47N/DQ6TC9

IO_8A_B5/DIFFIO_TX_T48NB5

IO_8A_B6/DIFFIO_TX_T50P/DQ7TB6

IO_8A_B7/DIFFIO_TX_T50N/DQ7TB7

IO_8A_A8/DIFFIO_RX_T51P/DQ7TA8

IO_8A_C6/DIFFIO_TX_T52P/DQ7TC6

IO_8A_A7/DIFFIO_RX_T51N/DQ7TA7

IO_8A_D6/DIFFIO_TX_T52N/DQ7TD6

IO_8A_E9/DIFFIO_RX_T53P/DQS7TE9

IO_8A_D7/DIFFIO_TX_T54PD7

IO_8A_D9/DIFFIO_RX_T53N/DQSN7TD9

IO_8A_C8/DIFFIO_TX_T54N/DQ7TC8

IO_8A_G6/DIFFIO_RX_T55P/DQ7TG6

IO_8A_F7/DIFFIO_TX_T56P/DQ7TF7

IO_8A_H6/DIFFIO_RX_T55N/DQ7TH6

IO_8A_E7/DIFFIO_TX_T56NE7

C496100nF16V

R31910K

U134

EPCQ64SI16N64Mb

DATA015

DATA18

DATA29

DATA31

DCLK16

nCS7

VCC2

GND10

SW4

SW ROTARYSTHEX

1248

C1C2

1 2

D36

G1/G2

1 3

2 4

C495100nF

R32210K

R3282005%

Page 50: University of Geneva 32-channel DRS4 Acquisition Board 01 ...dpnc.unige.ch/~bravar/DRSSS/DPNC342_02_01A_A60.pdf · CH-1211 GENEVE 4 02A University of Geneva DPNC342 Friday, October

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

FPGA - POWER SUPPLY + NC/DNU (4/4)

+1.1V

+2.5V

+2.5V

+3.3V

+2.5V

+2.5V

+3.3V

+1.1V

+3.3V

+2.5V +1.8V

+3.3V

+2.5V

+2.5V

+1.1V

+2.5V

+3.3V

+3.3V

+1.8V

+3.3V

+3.3V

+3.3V

+3.3V

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Thursday, September 29, 201650 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardSchematic Path = /FPGA_1

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Thursday, September 29, 201650 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardSchematic Path = /FPGA_1

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Thursday, September 29, 201650 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardSchematic Path = /FPGA_1

C503100nF10V

C511100nF10V

C543100nF10V

C513100nF10V

C539100nF10V

C528100nF10V

L2

600R/100MHz0.2A

C49810uF10V

C524100nF10V

C520100nF10V

C4991uF10V

C533100nF10V

C544100nF10V

C501100nF10V

C506100nF10V

C51810uF10V

C514100nF10V

C540100nF10V

C508100nF10V

C529100nF10V

Cyclone V 5CEBA7F23VERSION : 1.1PAGE : 9 of 10DATE : JUN_ 2012

U1-9

5CEBA7F23149.5K LEC8

NC1AA1

NC2AA2

NC3C1

NC4C2

NC5D3

NC6D4

NC7E1

NC8E2

NC9G1

NC10G2

NC11J1

NC12J2

NC13L1

NC14L2

NC15N1

NC16N2

NC17R1

NC18R2

NC19U1

NC20U2

NC21W1

NC22W2

NC23Y3

NC24Y4

DNU1B3

DNU2B4

DNU3E17

DNU4L9

DNU5V11

DNU6Y6

RREF_TLA1

C525100nF10V

C504100nF10V

C521100nF10V

Cyclone V 5CEBA7F23VERSION : 1.1PAGE : 10 of 10DATE : JUN_ 2012

U1-10

5CEBA7F23149.5K LEC8

GNDA11

GNDA21

GNDAA11

GNDAA3

GNDAA4

GNDAA6

GNDAB1

GNDAB14

GNDAB19

GNDAB2

GNDAB9

GNDB1

GNDB14

GNDB2

GNDB9

GNDC17

GNDC3

GNDC4

GNDC5

GNDD1

GNDD10

GNDD2

GNDD20

GNDD5

GNDE13

GNDE3

GNDE4

GNDF1

GNDF16

GNDF17

GNDF2

GNDF5

GNDF6

GNDG19

GNDG3

GNDG4

GNDG9

GNDH1

GNDH12

GNDH2

GNDH22

GNDH3

GNDH4

GNDH7

GNDJ15

GNDJ20

GNDJ3

GNDJ5

GNDK1

GNDK10

GNDK12

GNDK14

GNDK2

GNDK4

GNDK8

GNDL11

GNDL13

GNDL15

GNDL21

GNDL3

GNDL5

GNDM1

GNDM10

GNDM12

GNDM14

GNDM2

GNDM4

GNDN11

GNDN13

GNDN15

GNDN17

GNDN22

GNDN3

GNDN5

GNDN7

GNDP1

GNDP10

GNDP2

GNDP4

GNDR13

GNDR3

GNDT1

GNDT16

GNDT2

GNDT21

GNDU3

GNDU4

GNDU5

GNDU9

GNDV1

GNDV12

GNDV17

GNDV2

GNDV22

GNDV4

GNDV7

GNDW3

GNDW4

GNDY1

GNDY18

GNDY2

GNDY5

C547100nF10V

C54510uF10V

C530100nF10V

C53410uF10V

C507100nF10V

C515100nF10V

C509100nF10V

R3322K1%

C541100nF10V

C536100nF10V

C526100nF10V

Cyclone V 5CEBA7F23VERSION : 1.1PAGE : 1 of 10DATE : JUN_ 2012

U1-1

5CEBA7F23149.5K LEC8

VCCJ10

VCCP15

VCCP13

VCCP11

VCCN14

VCCN12

VCCN10

VCCM15

VCCM13

VCCM11

VCCL16

VCCL14

VCCL12

VCCL10

VCCK15

VCCK13

VCCK11

VCCJ16

VCCJ14

VCCJ12

VCCK3

VCCP3

VCCJ4

VCCN4

VCCL4

VCCK5

VCCPGMV8

VCCPGMR19

VCCPGMF8

VCCBATA3

VCCPD3AW6

VCCPD3B4AW11

VCCPD3B4AW17

VCCPD3B4AW14

VCCPD3B4AW12

VCCPD5AP21

VCCPD5BN18

VCCPD5BM17

VCCPD7A8AD8

VCCPD7A8AE11

VCCPD7A8AD16

VCCPD7A8AD14

VCCPD7A8AC10

VCCIO3AT6

VCCIO3AY8

VCCIO3BR8

VCCIO3BY13

VCCIO3BW10

VCCIO3BT11

VCCIO4AU14

VCCIO4AAA21

VCCIO4AAA16

VCCIO4AW20

VCCIO4AW15

VCCIO4AU19

VCCIO5AR18

VCCIO5AP20

VCCIO5BK18

VCCIO5BM19

VCCIO7AA16

VCCIO7AH17

VCCIO7AG14

VCCIO7AF21

VCCIO7AF11

VCCIO7AE18

VCCIO7AD15

VCCIO7AC22

VCCIO7AC12

VCCIO7AB19

VCCIO8AA6

VCCIO8AG7

VCCIO8AE8

VCCIO8AC7

VCCA_FPLLT5

VCCA_FPLLF4

VCCA_FPLLU18

VCCA_FPLLH19

VCCA_FPLLT3

VCCA_FPLLM3

VCC_AUXE6

VCC_AUXD11

VCC_AUXD18

VCC_AUXW18

VCC_AUXW13

VCC_AUXW7

C502100nF10V

C522100nF10V

C548100nF10V

C531100nF10V

C505100nF10V

C542100nF10V

C510100nF10V

C537100nF10V

C512100nF10V

C538100nF10V

C527100nF10V

C54610uF10V

C53510uF10V

C500100nF10V

C523100nF10V

C516100nF10V

C51710uF10V

C519100nF10V

C532100nF10V

Page 51: University of Geneva 32-channel DRS4 Acquisition Board 01 ...dpnc.unige.ch/~bravar/DRSSS/DPNC342_02_01A_A60.pdf · CH-1211 GENEVE 4 02A University of Geneva DPNC342 Friday, October

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

MICROCONTROLLER (1/2)

VIO1

VIO2

VIO3

VIO4

VIO5

CVDDQ

VBAT

DECOUPLING CAPS

JTAG & I2C

DQ0-15 + CTL + PMODE + RESET

DQ16-27

DQ28-31 + I2S

UART+SPI

CLOCK

POWER SUPPLIES

VBUS overvoltage protectionwhen using charger (VBUS up to 9V)

SSRXP is inverted with SSRXMfor layout purposes.No problem since polarity is recovered byUSB PHY interface

USB

SW OFF in order to boot µC from USB (Cypress VID)SW ON for EEPROM Boot

Write protected when on VCC (ON)Write allowed when on GND (OFF)

JTAG/EEPROM

VIO5

VIO5

JTAG ICE CONNECTOR

FRONT PANEL

* OTG_ID pin can be left unconnected if FX3is used as a USB device only. This pin mustbe connected to ground if you are using FX3as a dual role device.

*

VDD1V2

AVDD1V2

U3TXVDDQ

U3RXVDDQ

VDD1V2

AVDD1V2

U3RXVDDQ

U3TXVDDQ

VBAT

VBAT

DM

DP

SSTXM

SSRXP

SSRXM

DMDP

SSTXP

SSTXM

SSRXMSSRXP

SSTXP_CSSTXM_C

SSTXP

OTG_IDSCLSDA

TCK

TDI

TDO

TMS

TRSTn

TCK

TDI

TDO

TMS

TRSTn

SRTn

RTCK

+3.3V

+3.3V

+3.3V +3.3V +3.3V+3.3V

+3.3V +3.3V

+3.3V

+3.3V

+3.3V

+3.3V +3.3V

+3.3V +3.3V

+3.3V +3.3V

+3.3V

+3.3V

+1.2V

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Thursday, September 29, 201651 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardSchematic Path = /MICRO_1

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Thursday, September 29, 201651 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardSchematic Path = /MICRO_1

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Thursday, September 29, 201651 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardSchematic Path = /MICRO_1

L8

220R/100MHz 2A

R34

810

K

J15

FTS-110-01-L-DVM/STP1.27

13579

1113151719

2468101214161820

C56710nF10%16V

C57310nF10%16V

R337NC

R3350

C553100nF10%10V

R353 0

C589 100nF10% 10V

C587100nF10%50V

L5

600R/100MHz

2A

R340 NC

R35

110

K

GN

D

U139

SP30100.45pF

12

345

C586100nF10%50V

SEC 4/7

U - PORT

VBUS/VBAT

VBUS/VBAT

VBUS

U2D

CYUSB3014-BZXC 512KB200MHz

DPA9

OTG_IDC9

R_USB2C8

R_USB3B3

SSRXA3 SSRXPA4

SSTXA6 SSTXPA5

VBUSE11

DMA10

C58310uF10V

R34

710

K

R341NC

C56022UF10%10V

C552100nF10%10V

C562100nF10%10V

L7220R/100MHz

2A

C55810nF10%16V

R3456.04K1%0.1W

C568100nF10%10V

C590 100nF10% 50V

L6

600R/100MHz

2A

C57510nF10%16V

C554100nF10%10V

C57910nF10%16V

C551100nF10%10V

C55710nF10%16V

C555100nF10%10V

C56910nF10%16V

C572100nF10%10V

R352 NC

R3420

R34410K

C5762.2uF10%10V

C577100nF10%10V

R3382.20K5%

C5852.2uF10%6.3V

L3

SC2A

U138

24FC10251MHz1024Kb

A01

A12

A23

VSS4

SDA5SCL6WP7VCC8

J14

USB3-B F/RATHD

VBUS1

D-2

D+3

GND14

STDB_SSTX-5

STDB_SSTX+6

GND27

STDB_SSRX-8

STDB_SSRX+9

SHIELD110

C5842.2uF10%6.3V

C55610nF10%16V

R336NC

R334 1M5% 0.1W

R35

010

K

C58210uF10V

C566100nF10%10V

R3430

C56510nF10%16V

C578100nF10%10V

C549100nF10%10V

on

SW3SMDST

C55910nF10%16V

L4

600R/100MHz

2A

R3392.20K5%

C564100nF10%10V

R255

NC

C550100nF10%10V

R34

910

K

SEC 6/7

MISC

VIO5

U2F

CYUSB3014-BZXC 512KB200MHz

I2C_SCL/GPIO58D9

I2C_SDA/GPIO59D10

O60D11

TCKF6

TDIE7

TDOC10

TMSE8

TRSTB11

U137

NCP361SN

IN1

EN3

OUT5

FLAG4

GND2

C563100nF10%10V

C588 100nF10% 10V

C58110nF10%16V

C5612.2uF10%10V

C574100nF10%10V

SEC 7/7

POWER

U2G CYUSB3014-BZXC

512KB200MHz

AVDDA7

AV

SS

B7

CVDDQB6

VDD8B10

VIO5C11

VIO4B1

VIO1_1L9

VIO1_2H11

VIO2F1

VIO3E3

VDD6L5

VDD7J11

VS

S13

B9

VS

S14

B8

U3RXVDDQA2

U3TXVDDQB5

U3V

SS

QA

1

VBATE10

VDD1H1

VDD2C3

VDD3L7

VDD4E9

VDD5F11

VS

S1

G1

VS

S2

L1

VS

S3

E2

VS

S4

L6

VS

S5

D8

VS

S6

G11

VS

S7

L11

VS

S8

K4

VS

S9

L3

VS

S10

K3

VS

S11

L2

VS

S12

A8

C580100nF10%10V

TP401

R3462001%0.0625W

C571100nF10%10V

R333NC

C5702.2uF10%10V

Page 52: University of Geneva 32-channel DRS4 Acquisition Board 01 ...dpnc.unige.ch/~bravar/DRSSS/DPNC342_02_01A_A60.pdf · CH-1211 GENEVE 4 02A University of Geneva DPNC342 Friday, October

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

3V3 on VIO1

3V3 on VIO2

3V3 on VIO3

3V3 on VIO4

FIFO INTERFACE

I2C, on failure USB

CLOCK

3V3 on CVDDQ 3V3 on VIO1

BOOT MODE

19.2MHz crystal configuration

MICROCONTROLLER (2/2)

A1

A0

PMODE0

PMODE1

PMODE2

DQ_UC0

DQ_UC1

DQ_UC2

DQ_UC3

DQ0DQ1DQ2DQ3

DQ_UC4

DQ_UC5

DQ_UC6

DQ_UC7

DQ4DQ5DQ6DQ7

DQ_UC8

DQ_UC9

DQ_UC10

DQ_UC11

DQ8DQ9DQ10DQ11

DQ_UC12

DQ_UC13

DQ_UC14

DQ_UC15

DQ12DQ13DQ14DQ15

FLAGA_UC

FLAGB_UC

CTL6_UC

CTL8_UC

CTL9_UC

CTL10_UC

DQ_UC16

DQ_UC17

DQ_UC18

DQ_UC19

DQ16DQ17DQ18DQ19

DQ_UC20

DQ_UC21

DQ_UC22

DQ_UC23

DQ20DQ21DQ22DQ23

DQ_UC24

DQ_UC25

DQ_UC26

DQ_UC27

DQ24DQ25DQ26DQ27

DQ_UC28

DQ_UC29

DQ_UC30

DQ_UC31

DQ28DQ29DQ30DQ31

PMODE1PMODE2

PMODE0

DQ[31..0]

A[1..0]

PKTENDn

SLWRn

SLRDn

SLOEn

SLCSn

CLK

UART_CTSn

UART_RX

CTL6CTL8CTL9CTL10 GPIO50

GPIO51

RESETn

INTn

FLAGAFLAGB

UART_RTSnUART_TX

+3.3V

+3.3V +3.3V +3.3V

+3.3V

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Thursday, September 29, 201652 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardSchematic Path = /MICRO_1

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Thursday, September 29, 201652 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardSchematic Path = /MICRO_1

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Thursday, September 29, 201652 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardSchematic Path = /MICRO_1

R361NC

RN11 22

1234

8765

RN4 22

1234

8765

C59212pF5%

S1 - PORT

SEC 3/7

VIO3

VIO4

U2C

CYUSB3014-BZXC 512KB200MHz

DQ28F5

DQ29E1

DQ30E5

DQ31E4

I2S-CLK/GPIO50D1

I2S-SD/GPIO51D2

I2S-WS/GPIO52D3

UART-RTS/SPI-SCK/GPIO53D4

UART-CTS/SPI-SSN/I2S_CLK/GPIO54C1

UART-TX/SPI-MISO/I2S_SD/GPIO55C2

UART-RX/SPI-MOSI/I2S_WS/GPIO56D5

I2S-MCLK/GPIO57C4

R35910K5%

RN9 22

1234

8765

R362NC

RN7 22

1234

8765

TP411

RN5 22

1234

8765

C59112pF5%

R35610K5%

D42Y5MCD

TP421

R358NC5%

XTAL / CLK

SEC 5/7

CVDDQ

U2E

CYUSB3014-BZXC 512KB200MHz

CLKIND7

CLKIN_32D6

FSLC0B2

FSLC1B4

FSLC2E6

XTALINC6

XTALOUTC7 R363

NC

Q22N70020.1A60V

RN3 22

1234

8765

R3542001%

RN12 22

1234

8765

R355100K5%

R360NC5%

SEC 1/7

P - PORT

VIO1

U2A

CYUSB3014-BZXC 512KB200MHz

INT/CTL15L8

DQ0F10

DQ1F9

DQ10K11

DQ11L10

DQ12K10

DQ13K9

DQ14J8

DQ15G8

PCLK/CLKJ6

CTL0/SLCSK8

CTL1/SLWRK7

CTL2/SLOEJ7

DQ2F7

CTL3/SLRDH7

CTL4/FLAGAG7

CTL5/FLAGBG6

CTL6/GPIOK6

CTL7/PKTENDH8

CTL8/GPIOG5

CTL9/GPIOH6

CTL10/GPIOK5

CTL11/A1J5

CTL12/A0H5

DQ3G10

PMODE0G4

PMODE1H4

PMODE2L4

DQ4G9

DQ5F8

DQ6H10

DQ7H9

DQ8J10

DQ9J9

RESETC5

RN10 22

1234

8765

RN2 22

1234

8765

R35710K

Y319M230PPM

S0 - PORTSEC 2/7

VIO2

U2B

CYUSB3014-BZXC 512KB200MHz

DQ16K2

DQ17J4

DQ18K1

DQ19J2

DQ20J3

DQ21J1

DQ22H2

DQ23H3

DQ24F4

DQ25G2

DQ26G3

DQ27F3

GPIO45F2

RN6 22

1234

8765

RN1 22

1234

8765

Page 53: University of Geneva 32-channel DRS4 Acquisition Board 01 ...dpnc.unige.ch/~bravar/DRSSS/DPNC342_02_01A_A60.pdf · CH-1211 GENEVE 4 02A University of Geneva DPNC342 Friday, October

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

NIM_TO_LVTTL

LVTTL/LVCMOS 3.3 V

-0.38V

NIM

OUTIN

+5V

-5V

+3.3V

-5V

+5V +3.3V

-5V

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Thursday, September 29, 201653 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardSchematic Path = /NTL_1

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Thursday, September 29, 201653 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardSchematic Path = /NTL_1

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Thursday, September 29, 201653 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardSchematic Path = /NTL_1

R36551

R3641801%

C59510nF10%16V

-

+

U140

LT1719S8

2

37

1 84 5 6

R3662.21K1%

C594100nF

C59310nF10%16V

C59610nF10%16V

D435V

Page 54: University of Geneva 32-channel DRS4 Acquisition Board 01 ...dpnc.unige.ch/~bravar/DRSSS/DPNC342_02_01A_A60.pdf · CH-1211 GENEVE 4 02A University of Geneva DPNC342 Friday, October

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

LVTTL_TO_NIM

LVCMOS 3.3 V>6 mA

NIM

IN

OUT

-5V

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Thursday, September 29, 201654 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardSchematic Path = /LTN_1

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Thursday, September 29, 201654 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardSchematic Path = /LTN_1

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Thursday, September 29, 201654 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardSchematic Path = /LTN_1

R22264.91%

R238

402 1%

R221

169 1%

Q4BFT92

1

2 3R239

511 1%

Q3BFR520

Page 55: University of Geneva 32-channel DRS4 Acquisition Board 01 ...dpnc.unige.ch/~bravar/DRSSS/DPNC342_02_01A_A60.pdf · CH-1211 GENEVE 4 02A University of Geneva DPNC342 Friday, October

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

POWER (1/2)

+6VGND-6V

AUXPOWER SUPPLYCONNECTOR

VOUT = 1.1VRSET = 1.74 KOHMRRT = 1 MOHMFSW = 250 KHZ

DCR=0.018 OHM

DCR=0.018 OHM

DCR=0.3 OHM

DCR=0.3 OHM

+1.1V5A

+5V0.05A

+3.3V1.7A

+2.5V1.5A

+2.5V_A0.1A

+1.8V_A0.2A

+1.8V0.2A

+1.2V0.2A

+5V_A0.3A

+5V_A10.8A

+5V_A20.8A

Pd=0.08W

Pd=0.3W

Pd=0.14W

Pd=0.26W

Pd=0.3W

Pd=0.8W

Pd=0.8W

Pd=0.05W

EFF=0.87

1.05A

0.05A 0.3A

0.8A

0.1A

0.2A

0.2A

0.2A

EFF=0.89

EFF=0.88

1.05A

0.7A

+6V4.8A

0.8A

DCR=0.05 OHM

DCR=0.05 OHM

DCR=0.05 OHM

-6V2A

PVIN

PVIN PVIN

PVIN

PVIN

PVIN

PVIN

PVIN

PH_NC

+2.5V_A

+5V

+2.5V

+1.8V_A

+1.8V

+1.1V

+3.3V

+3.3V

+6V

-6V

+3.3V

+2.5V

+2.5V +1.2V

+5V_A

+5V_A1

+5V_A2

NVIN

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Thursday, September 29, 201655 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardSchematic Path = /PWR_1

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Thursday, September 29, 201655 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardSchematic Path = /PWR_1

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Thursday, September 29, 201655 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardSchematic Path = /PWR_1

TP66TPRND1.0SMD

1

C63822nF

25V

R372

5.62K 0.1%

C64647uF10V

+C613100uF20V

C6321uF10V

R377

45.3K 1%

R3981M1%0.25W

C63647uF10V

C61010uF10V

TP53TPRND1.0SMD

1

ANY OUT SETTING

U152 TPS7A4700

1AADJ

OUT1

IN15

GN

D7

FB3

EN13

NR14

6P4V

24

6P4V

15

3P2V

6

1P6V

8

0P8V

9

0P4V

10

0P2V

11

0P1V

12

C60747uF25V

U144 LMZ31707

7AADJ

VIN3

AG

ND

2

PG

ND

20

PVIN1

VOUT34

PH

10

ISHARE25

OCP_SEL4

ILIM6

SYNC_OUT7

PWRGD8

RT/CLK22

VADJ26

SENSE+27

SS/TR28

STSEL29

INH/UVLO30

C64847uF10V

TP50TPRND1.0SMD

1

TP65TPRND1.0SMD

1

U147

TPS738011AADJ

IN1

OUT2

GN

D3

FB4

EN5

C621100uF6.3V

TP45TPRND1.0SMD

1

R3761.07K1%

+C614100uF20V

TP52TPRND1.0SMD

1

C64547uF10V

C63910uF10V

C62810uF10V

L12

600R/100MHz

1A

C6061uF10V

C64347uF10V

R3753.32K1%

+C618220uF6.3V

R3782.26K1%

C63547uF10V

TP44TPRND1.0SMD

1

R374

60.4K 1%

TP46TPRND1.0SMD

1

TP58TPRND1.0SMD

1

ANY OUT SETTING

U142 TPS7A4700

1AADJ

OUT1

IN15

GN

D7

FB3

EN13

NR14

6P4V

24

6P4V

15

3P2V

6

1P6V

8

0P8V

9

0P4V

10

0P2V

11

0P1V

12

C63010uF10V

L14

120R/100MHz

1.5A

C622100uF6.3V

C6501uF10V

C60247uF10V

TP51TPRND1.0SMD

1

VME ESD StripSTRIP1

DRL2.71

R3791.07K1%

L11

160R/100MHz

6A

TP63TPRND1.0SMD

1

U145 TLV117118

1A1V8

VIN1

GN

D2

VOUT3

L10

160R/100MHz6A

C617100nF25V

C605100nF25V

C61647uF25V

+C603100uF20V

+C619220uF6.3V

TP55TPRND1.0SMD

1

TP43TP

RND1.0SMD1

C6251uF10V

TP60TPRND1.0SMD

1

TP64TPRND1.0SMD

1

TP59TPRND1.0SMD

1R3731.8K0.1%

ANY OUT SETTING

U150 TPS7A4700

1AADJ

OUT1

IN15

GN

D7

FB3

EN13

NR14

6P4V

24

6P4V

15

3P2V

6

1P6V

8

0P8V

9

0P4V

10

0P2V

11

0P1V

12

C6231uF10V

C64047uF10V

TP61TPRND1.0SMD

1

U149 LMZ12003

3AADJ

VIN1

VOUT7

GN

D4

RON2

SS5

EN3

FB6

C6261uF10V

C62710uF10V

C6121uF10V

C60110uF10V

TP57TPRND1.0SMD

1

C64922nF

25V

C63322nF25V

L9

600R/100MHz

1A

R3701.74K0.1%

ANY OUT SETTING

U148 TPS7A4700

1AADJ

OUT1

IN15

GN

D7

FB3

EN13

NR14

6P4V

24

6P4V

15

3P2V

6

1P6V

8

0P8V

9

0P4V

10

0P2V

11

0P1V

12

C60447uF25V

U151 LMZ12003

3AADJ

VIN1

VOUT7

GN

D4

RON2

SS5

EN3

FB6

C6241uF10V

C63147uF10V

TP49TPRND1.0SMD

1

L13

120R/100MHz1.5A

C61547uF25V

L15

120R/100MHz1.5A

TP56TPRND1.0SMD

1

C64710uF10V

C63447uF10V R397

1M1%0.25W

U146 TLV117112

1A1V2

VIN1

GN

D2

VOUT3

C61147uF10VTP48

TPRND1.0SMD1

C64222nF25V

C64447uF10V

TP54TPRND1.0SMD

1

TP62TPRND1.0SMD

1

C608100nF25V

J16

SL 5.08/03/180 3.2M/STP5.08

123

TP67TPRND1.0SMD

1

C6411uF10V

+C609100uF20V

ANY OUT SETTING

U143 TPS7A4700

1AADJ

OUT1

IN15

GN

D7

FB3

EN13

NR14

6P4V

24

6P4V

15

3P2V

6

1P6V

8

0P8V

9

0P4V

10

0P2V

11

0P1V

12

R3711M1%

C620100uF6.3V

TP47TPRND1.0SMD

1

C63747uF10V

Page 56: University of Geneva 32-channel DRS4 Acquisition Board 01 ...dpnc.unige.ch/~bravar/DRSSS/DPNC342_02_01A_A60.pdf · CH-1211 GENEVE 4 02A University of Geneva DPNC342 Friday, October

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

POWER (2/2)

-5V_A0.3A

Pd=0.3W

0.3A

-5V_A10.8A

Pd=0.8W

0.8A

-5V_A20.8A

Pd=0.8W

0.8A

DCR=0.05 OHM

DCR=0.05 OHM

DCR=0.05 OHM

-5V0.05A

0.05A

Pd=0.05W

-5V_A

-5V_A2

-5V_A1

-5V

NVIN

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Thursday, September 29, 201656 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardSchematic Path = /PWR_1

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Thursday, September 29, 201656 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardSchematic Path = /PWR_1

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Thursday, September 29, 201656 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardSchematic Path = /PWR_1

R380332K0.1%

C66410uF10V

TP74TPRND1.0SMD

1

R384332K0.1%

C6581uF10V

L16

120R/100MHz

1.5A

C66047uF10V

C65510nF

U156 LT1175

0.2A-5V

VIN2

GN

D3

VOUT1

VIN24

R383102K0.1%

C65247uF10V

L18

120R/100MHz

1.5A

TP70TPRND1.0SMD

1

C66347uF10V

U155 TPS7A3301

-1AADJ

OUT1

IN15

GN

D7

FB3

EN13

NR/SS14

C65110nF

R382332K0.1%

TP69TPRND1.0SMD

1

TP73TPRND1.0SMD

1

C65647uF10V

C66147uF10V

TP68TPRND1.0SMD

1

R381102K0.1%

U154 TPS7A3301

-1AADJ

OUT1

IN15

GN

D7

FB3

EN13

NR/SS14

L17

120R/100MHz

1.5A

C6621uF10V

C6541uF10V

C65347uF10V

C65910nF

U153 TPS7A3301

-1AADJ

OUT1

IN15

GN

D7

FB3

EN13

NR/SS14

R385102K0.1%

TP71TPRND1.0SMD

1

TP75TPRND1.0SMD

1

TP72TPRND1.0SMD

1

C65747uF10V

Page 57: University of Geneva 32-channel DRS4 Acquisition Board 01 ...dpnc.unige.ch/~bravar/DRSSS/DPNC342_02_01A_A60.pdf · CH-1211 GENEVE 4 02A University of Geneva DPNC342 Friday, October

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

TIMING CALIBRATION - SOURCE

ETCAL

TCAL1

TCAL2

TCAL3

TCAL4

SEL

TCAE

CXOE

+3.3V

+3.3V

+5V_A

-5V_A

+5V_A

-5V_A

+5V_A

-5V_A

+5V_A

-5V_A

+5V_A -5V_A

+5V_A -5V_A

+5V_A -5V_A

+5V_A -5V_A

+5V_A

-5V_A

+5V_A -5V_A +5V_A -5V_A

-5V_A

+5V_A

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Thursday, October 06, 201657 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardSchematic Path = /DRS4X32CH_1/TCA_1

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Thursday, October 06, 201657 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardSchematic Path = /DRS4X32CH_1/TCA_1

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Thursday, October 06, 201657 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardSchematic Path = /DRS4X32CH_1/TCA_1

C666100nF16V

C681100nF16V

R433

220 5%

C667100nF16V

R436

22 5%

C674100nF16V

R392

22 5%

R388

51 5%

R386

22 5%-

+U157

LMH6609900MHz

31

52

4

-

+U158

LMH6609900MHz

31

52

4

L19

82nH

C677100nF16V

C67115pF

R439

22 5%

R434

120 5%-

+U160

LMH6609900MHz

31

52

4

C67310nF

-

+U162

LMH6609900MHz

31

52

4

R435

12 5%

C665100nF16V

R437

22 5%

C680100nF16V

C67215pF

C678100nF10V

L20

82nH

C668100nF16V

G=1

U159

ADV3219

IN01

V+

4

SEL8

IN13

V-

5

GN

D2

OUT6

EN7

R391365%

C675100nF16V

C690100pF50V/10GHz

R393

22 5%

R387

22 5%

Y4

100MHz25PPM

VCC4

OUT3

GND2

EN1

R432

220 5%

C679100nF10V

C676100nF16V

-

+U161

LMH6609900MHz

31

52

4

C67039pF

R438

22 5%

R389

16 5%

Page 58: University of Geneva 32-channel DRS4 Acquisition Board 01 ...dpnc.unige.ch/~bravar/DRSSS/DPNC342_02_01A_A60.pdf · CH-1211 GENEVE 4 02A University of Geneva DPNC342 Friday, October

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

REAR

URX6

URX5

URX4

URX3

URX2

URX1

URX0

UTX0

UTX1

UTX2

UTX3

UTX4

UTX5

UTX6

UTX7

URX7URX7pURX7nURX6pURX6n

URX5pURX5nURX4pURX4n

URX3pURX3nURX2pURX2n

URX1pURX1nURX0pURX0n

UTX0pUTX0nUTX1pUTX1nUTX2pUTX2nUTX3pUTX3n

UTX4pUTX4nUTX5pUTX5nUTX6pUTX6nUTX7pUTX7n

URX0nURX1nURX2nURX3nURX4nURX5nURX6nURX7n

UTX0nUTX1nUTX2nUTX3nUTX4nUTX5nUTX6nUTX7n

URX0pURX1pURX2pURX3pURX4pURX5pURX6pURX7p

UTX0pUTX1pUTX2pUTX3pUTX4pUTX5pUTX6pUTX7p

UTXENURXEN

URX[0..7] UTX[0..7]

+3.3V+3.3V

+3.3V +3.3V

+3.3V +3.3V

+3.3V

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Thursday, September 29, 201658 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardUSER LVDS I/O Schematic Path = /USRIO_1

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Thursday, September 29, 201658 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardUSER LVDS I/O Schematic Path = /USRIO_1

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Thursday, September 29, 201658 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardUSER LVDS I/O Schematic Path = /USRIO_1

C682100nF10%16V

C684100nF10%16V

U164

65LVDS389630MBPS

ENA4

A1A5

A2A6

ENB16

B1A12

B2A13

A1Y38

A1Z37

A2Y36

A2Z35

B1Y27

B1Z26

B2Y25

B2Z24

2

VCC

1

GND

B3A14

B4A15

A3A7

A4A8

A3Y34

A3Z33

A4Y32

A4Z31

B3Y23

B3Z22

B4Y2120

B4Z

C6831nF10%25V

C6851nF10%25V

U163

65LVDT388A630MBPS

A1Y35

A2Y34

B1Y32

B2Y31

C1Y27

C2Y26

D1Y24

D2Y23

A1A1

A2A3

B1A6

B2A8

C1A11

C2A13

D1A16

D2A18

A1B2

A2B4

B1B7

B2B9

C1B12

C2B14

D1B17

D2B19

ENA36

ENB33

ENC25

END22

GND20DGND28

AGND5

VCC21

DVCC29

J17

HE10 M/RAP2.54

13579111315171921232527293133

2468

10121416182022242628303234

Page 59: University of Geneva 32-channel DRS4 Acquisition Board 01 ...dpnc.unige.ch/~bravar/DRSSS/DPNC342_02_01A_A60.pdf · CH-1211 GENEVE 4 02A University of Geneva DPNC342 Friday, October

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

TRIGIN1TRIGIN2TRIGIN3TRIGIN4

STAT1STAT2STAT3STAT4

EXT_CLK+EXT_CLK-

TCKTMS

TDITDO

TRIGIN[1..4] STAT[1..4]

+6V

-6V -6V

+6V

-6V

+6V

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Thursday, September 29, 201659 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardVME P1 CONNECTOR Schematic Path = /VMECON_1

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Thursday, September 29, 201659 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardVME P1 CONNECTOR Schematic Path = /VMECON_1

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Thursday, September 29, 201659 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardVME P1 CONNECTOR Schematic Path = /VMECON_1

P1B

DIN 41 612M/RAP2.54

B1B2B3B4B5B6B7B8B9B10B11B12B13B14B15B16B17B18B19B20B21B22B23B24B25B26B27B28B29B30B31B32

P1A

DIN 41 612M/RAP2.54

A1A2A3A4A5A6A7A8A9A10A11A12A13A14A15A16A17A18A19A20A21A22A23A24A25A26A27A28A29A30A31A32

12

P1C

DIN 41 612M/RAP2.54

C1C2C3C4C5C6C7C8C9C10C11C12C13C14C15C16C17C18C19C20C21C22C23C24C25C26C27C28C29C30C31C32

Page 60: University of Geneva 32-channel DRS4 Acquisition Board 01 ...dpnc.unige.ch/~bravar/DRSSS/DPNC342_02_01A_A60.pdf · CH-1211 GENEVE 4 02A University of Geneva DPNC342 Friday, October

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

0.7V VOLTAGE REFERENCE

0.701V min0.704V maxILOAD=1.2mA

VREF2V

VREF0V7

OUT

+2.5V_A

+5V_A

+5V_A

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Thursday, September 29, 201660 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardSchematic Path = /DRS4X32CH_1/VREF_1

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Thursday, September 29, 201660 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardSchematic Path = /DRS4X32CH_1/VREF_1

Size DWG NO Rev PCB

Sheet

of

Rev PCBA

CH1211 GENEVE 4

02A

University of Geneva

DPNC342

Thursday, September 29, 201660 60

A3

.DPNC24 quai Ernest-Ansermet

32-channel DRS4 Acquisition BoardSchematic Path = /DRS4X32CH_1/VREF_1

R3941.13K0.1%

-

+

U166

AD8027

31

62

4

5

C6871uF10%10V

C688100nF16V

C689100nF16V

R3965900.1%

C68610uF10%10V

R395

4.7 5%

U165

LM41402.048V+/-0.1%

GN

D1

GN

D4

GN

D7

GN

D8

VIN2

EN3 VREF

6

TP76TP

RND1.0SMD1