University of Cassino and southern Lazio Department of...

University of Cassino and southern Lazio

Department of Electrical and

Information Engineering

Electronic Research Group

Contact: prof. Giovanni Busatto [email protected] +39 07762993699

Laboratory of Industrial Electronics

ELECTRONICS Group STAFF

Laboratory of Industrial Electronics

Department of Electrical and Information Engineering

Full Professor: Giovanni Busatto

Associate Professors: Francesco Iannuzzo

Annunziata Sanseverino

Researchers: Francesco Velardi

Carmine Abbate

Ph.D. Student: Valentina De Luca

Laboratory Technician: Tomasino Iovini

Main Activities

Experimental (NDT) characterization of Power Devices

Overvoltage, overcurrent, high and low temperature,

short circuit stresses on power devices and modules

Cosmic Ray effects on Power Devices (Burnout & Total

dose)

2D/3D Devices FEM Simulation

Devices Modeling & Simulation – Lumped-Charge approach

High-Voltage/high-current/picoampere PCB layout design

Recent Active collaborations

ANSALDOBREDA – Naples – Italy STMicroelectronics – Catania – Italy Fairchild – Munich – Germany ECPE – European Centre for Power Electronics – Nuremberg -

Germany INFN – Italian Institute for Nuclear Physics – Rome - Italy

ECPE Competence Center

…specialized in non destructive testing of discrete and power modules

The laboratory is an…

Non-Destructive Tester NDT Facility

High voltage Area

Principle Schematic

Tester control panel

Features:

• SOA Tests • Sort circuit • Unclamped • Temperature • Aging • …

Voltage: 0 - 6500V (8000V) Current: 0 - 8000A

Applications:

High Voltage NDT

High voltage Devices: 1700V ≤ Vcc ≤ 6500V Ls = 110 nH Cs = 5nF

High current Devices: Ic ≤ 8000A Vcc ≤ 1700V Ls < 50 nH Cs = 12nF

High Current NDT

Very Low Inductance NDT

Very Fast Devices:

Vcc ≤ 1700V, Ls < 30 nH, Cs < 300pF

Detail of busbar

Temperature Characterization

-50°C +200°C Special Fluid

Railway inverter under test

Static Characterization

Curve Tracer 576 1.7kV, 20A pulsed

Agilent B1500A w/ 2 SMUs: • High current and voltage – junction BV • High precision (pA) – oxides percolation

Ad hoc set-ups: high voltage and current, high precision (e.g. 3kV 1nA)

Keithley Measurement System w/2 SMUs: • High current and voltage 2410

• High precision (pA) 2601

Post Failure Analysis

NISENE decapsulation system

Inspection microscope

Development of high voltage, high performances switch Marx modulator

High voltage bridge leg For railway applications

Cosmic Ray effects on Power Devices

Single Event Burnout: Experiment

3-µm resolution Ion Impact Mapping

Operations of power devices in highly stressing electrical

conditions

C. Abbate, G. Busatto, F.Iannuzzo

DIEI – Università di Cassino e del Lazio Meridionale Via G. di Biasio, 43, Cassino, Italy

e-mail: [email protected]

Outline Introduction Failure mechanisms under extreme electrical stresses:

In the device linear operating region During the device switching In avalanche conditions External causes (eg. cosmic rays impacts)

Non destructive techniques for electrical testing of power devices The basics of ND techniques taken from the literature The approach to ND SOA characterization of power module Typical problems related with the use of Non Destructive tester The “precursors” of the instabilities

Cosmic rays impact Conclusions

Switch On Switch Off

A power device in a switching circuit

Buck converter Test circuit

Switching Waveforms

Collector Voltage

Col

lect

or V

olta

ge

SOA

Electrical limits of a power semiconductor switch

Trench Gate Structure

Double Diffused Planar Structure

Elementary cells of a Power MOSFET

Power MOSFET parasitic BJT

Drain

P +

N +

P _

GateSource

N_

Body

N+

Collector

Emitter

Base

RP+ A possible cause of failure!

IGBT (Insulated Gate Bipolar Transistor)

Trench Gate Structure Planar Structure

IGBT parasitic thyristor

A further possible cause

of failure!

Failure mechanisms under extreme electrical stresses In the device linear operating region

Short circuit operations (or overload conditions) Instable DC operations (second breakdown)

During the device switching At the turn-off Reverse recovery of internal diode

In avalanche conditions UIS – Unclamped Inductive Switch

Short circuit of a Power Switch: Definitions Type 1: Short circuit takes place when the device is in

the off-state so it is turned on in short circuit

Type 1

Type 2

Type 2: Short circuit takes place when the device is in the on-state

Type 1 short circuit

Vgs

Commercial devices can sustain S.C. for 10 ms at the TJMAX and with VGS=16V

The failure of a Power MOSFET after a short circuit

Fresh Device After a short circuit Failure

Type 1 short circuit: First failure mechanism

A.Ammous, K.Ammous, H.Morel, B.Allard, D. Bergogne, F. Sellami, J.P.Chante “Electrothermal Modeling of IGBT’s: Application to Short-Circuit Conditions,” IEEE Trans. Power Electronics, Vol. 15, No. 4, JULY 2000

Device avalanching due to stray inductance

Type 1 short circuit: Second failure mechanism

Device avalanching due to stray inductance can cause device failure

H.G.Eckel, L.Sack, “Experimental Investigation on the Behaviour of IGBT at Short-Ciruit during the On-State,” Proc. IEEE PESC, 1995

Type 2 short circuit

S.C.

Avalanche limit

Failure of Power Devices in the active region

DC Safe Operating Area

Second Breakdown

DC electro-thermal instability of a low voltage Power MOSFET

Evolution of the temperature in the hot-spot

P.Spirito, G.Breglio, V.d'Alessandro, N.Rinaldi, “Analytical Model for Thermal Instability of Low Voltage Power MOS and S.O.A. in Pulse Operation,” Proc. ISPSD 2002

Basic mechanism in thermal run-away

Regenerative Thermo-electric Effect

Generated Power vs. Temperature

ID

ID

aT<0

Stable Unstable aT>0

Trans-characteristics of a low voltage Power MOSFET

P.Spirito, G.Breglio, V.d’Alessandro, “Modeling the Onset of Thermal Instability in Low Voltage Power MOS: an Experimental Validation,” Proc. ISPSD 2005

VGS=Const 0

TID

Ta

Possible thermal run-away

Experimental evidence of hot-spot formation

P.Spirito, G.Breglio, V.d’Alessandro, “Modeling the Onset of Thermal Instability in Low Voltage Power MOS: an Experimental Validation,” Proc. ISPSD 2005

Radiometric temperature detection for 55V Power MOSFET operated under pulsed bias conditions

Second Breakdown in a BJT

3D structure of a Power BJT

Typical top layout of a power BJT

Sketch of the 3D structure of

a power BJT

Crowding of emitter current

B.A.Betty, S. Krishna, M.S.Adler, “Second Breakdown in Power Transistors Due to Avalanche Injection” Trans. Electron Devices, Vol.ED-23, No.8, 1976

Reverse Base Bias: central current crowding

Second Breakdown in a BJT Avalanche injection

Impact ionizzation

At increasing Drain current

Second Breakdown in IGBT

Vcc=1800V,

Ic=4000A

RON=ROFF=0.35Ω

Lload=100µH

T=145°C

IGBT Modules rated at 3300V-1200A

Second breakdown along the voltage rise

Internal structure of a power IGBT module

IG1

IC1

Reverse Recovery of Power MOSFET internal diode

Test circuito Experimental waveforms

Second Breakdown

Parassitic BJT Activation

Drain

P +

N +

P _

GateSource

N_

Body

N+

Collector

Emitter

Base

RP+

Supplemental Charge

The role of gate capacitance in the activation of parasitic BJT

Displacement current

Phenomenon insight

53

Displacement current

UIS Typical waveforms

Safe Unclamped Inductive Switch

Test circuit Typical waveforms

Failure of Power MOSFET in Unclamped Inductive Switch

UIS – Failure Waveforms

The gate is Off

The current Is still

flowing

The voltage suddenly falls down

A. Icaza-Deckelmann, G. Wachutka, J. Krumrey, F. Hirler, “Failure Mechanism of Power DMOS Transistors under UIS Stress Conditions,” ASDAM 2002 - EDSSC ‘03


Electric Field

Avalanche multiplication

Low Drain Current

Ih

Ie

Ih

Ie


Maximum temperature in the device and currents at the source contact vs. time

(I=1mA)

Ih

Ie


Ih

Ie

Avalanche multiplication

Electric Field

Kirk Effect

High Drain Current

Experimental evidence of instability in UIS



Non destructive techniques for electrical testing of power devices Motivation of ND techniques The basics of ND techniques taken from the literature The approach to ND SOA characterization of power module Typical problems related with the use of Non Destructive tester The “precursors” of the instabilities


ND techniques for electrical testing of power devices Motivation of ND techniques

The basics of ND techniques taken from the literature

The approach to ND SOA characterization of power module

Typical problems related with the use of Non Destructive tester

The “precursors” of the instabilities

Collector Voltage

Col

lect

or V

olta

ge

RBSOA

How a Non-Destructive tester can help in robustness validation tests?

Gate Resistance

Failu

re V

olta

ge

How a Non-Destructive tester can help in robustness validation tests?

The first non destructive tester proposed in the literature

D.W. Berning: “Semiconductor Measurement Technology: A programmable Reverse Bias Safe Operating Area transistor tester” National Institute of Standard and Technology Special Publication 400-87, August 1990.

Basic schematic and principle of operation

The first non destructive tester proposed in the literature

Tester performances: VClamp,Max=2000V IC,Max=25,5A tCrowBar,on=30ns @ ICrowBar=40A tCrowBar,on=65ns @ ICrowBar=100A

Problems with vacuum tubes

• Current capabilities of vacuum tubes are quite poor and their use for collector currents larger than 50A is not practical

• Tubes are very expensive

A second version of ND tester

G. Carpenter, F.C.Y. Lee, D.Y. Chen: “An 1800-V 300-A N Nondestructive Tester for Bipolar Power Transistors” IEEE Transaction on Power Electronics, vol.5, n°3, pp. 314-322, 1990.

The MOSFET shunt circuit of the Carpenter non-destructive tester

Tester performances: VClamp,Max=1800V IC,Max=300A tCrowBar,d=10ns @ ICrowBar=300A tCrowBar,on=300ns @ ICrowBar=300A

Problems when using dV/dt sense to trigger the crow bar switch A delay time is observed which is sensitive to

the output current value The methods to speed up the turn on of the

power MOSFET cannot be easily extended to high power IGBTs when used as crow bar switches

The instabilities of the power devices often are not accompanied by a sudden variation of the collector voltage

Other techniques must be used for the activation of the Crow Bar switch!

Non Destructive Tester for High Power Modules

Q 1 , 1

V 0-8000V

I N

H.V. Power Supply

Series SW

Crow-Bar SW

V 100V

A U X

Q 1 , 2

Q 1 , 3

Q 2 , 1

D 2 D 3

D 1 L L

C

DUT

R 1

Q 2 , 2 Q 2 , 3

No dV/dt sense is used

Short circuit High temperature test

High voltage Unclamped tests

1Series SW state

DUT Collector Voltage

0

T2T3T4 TimeT1T0

Crow bar SW state

DUT Collector Current

DUT state

Crow bar Current

Tester Operations

VIN

Series SW

Crow-Bar SW

D2 D3

D1LL

C

DUT

Jitter of the crow bar turn-on

Stray capacitance of the crowbar switch

The effect of the stray inductance on the crow-bar turn-on time

The effect of the crow-bar Reverse Bias Voltage

Reverse Bias Voltage

Improved NDT

Other effects of stray inductances

LS=110nH 3300V – 1200A IGBT Module

600V – 300A IGBT Module

Different typologies of non-destructive set-up High voltage IGBTs

1700V ≤ Vcc ≤ 6500V Ls = 110 nH

High current IGBTs Vcc ≤ 1700V Ls < 50 nH

The stray inductance 600V – 300A IGBT Module

LS=110nH

LS=50nH

Stray capacitance of the busbar

Ls = 110 nH Ls < 50 nH

CSBB = 5nF CSBB = 12nF

Stray capacitance of the busbar

1200V – 25A IGBT

CSBB = 12nF

Reduced busbar stray capacitance

CSBB = 400pF

Reduction of the busbar stray capacitance

1200V – 25A IGBT CSBB = 12nF

CSBB = 400pF

A first conclusion about the tester characteristics

High voltage IGBT modules (1700V - 6500V)

High voltage series and CB switch High voltage dumping capacitor

Lower current capabilities Higher stray inductances

Lower crow bar stray capacitance

Lower stray inductances Higher dumping capacitors

Larger crow bar stray capacitance

High current series and CB switch High capacitance dumping capacitor

Lower voltage IGBT modules (600V - 1700V)

Discrete IGBT devices

Lower current much faster CB switch Lower voltage more performing

dumping capacitor

Lower current capabilities Much lower stray inductances

Lower stray busbar capacitance

A first conclusion about the tester characteristics

• It is not possible to have one experimental

set up good for any devices/modules

• Each phenomenon to be studied requires its specific experimental

set-up

Clamped test on 1500V-10A DAUX and VNEG=50V

VIN=1200V, Ic=19A, RGOFF =10Ω

Second breakdown

Crow Bar activation

Collector current is zeroed

80ns DUT Saved

Single chip MOS-GTO

Example of Tester Operation

UIS Failure

Unclamped test on 600V - 300A IGBT Modules by HC-UNDT

VNEG=800V, RGOFF=15Ω

Second breakdown

Crow Bar activation

Collector current is zeroed

60ns

DUT Fails

UIS Failure

Ts=25°C

ESB 0.1mJ (Very low energy after failure)

1 20ns

Unclamped Test JFET: Id=21A, Vav1800V, LL=1.5mH

tav 2.5µs Eav=51mJ

Post Failure Analysis

Very small damaged area

Melted area between gate and source

Is it possible to save DUT in UIS?

Other precursors must be identified

We cannot rely on dV/dt and dI/dt Indicators!!!!

Unclamped Turn-off: 1200V-400A Modules

Unclamped turn-off test

Vav=1300V Ic=400A ROFF=3.3Ω LLOAD=50mH

Second Breakdown

Precursor on the gate voltage

TCASE= 25°C

Vav=1300V Ic=400A ROFF=3.3Ω LLOAD=50mH



Precursor on the gate voltage TCASE= 25°C

Vav=1300V Ic=400A ROFF= 3.3 Ω 2.0 Ω LLOAD=50mH

TCASE= 25°C


Second Breakdown

ROFF=2.0W

ROFF=3.3W


OTHER USES OF PULSED POWER SUPPLY

Control of the energy in Avalanche Cycles (application to SiC JFETs)

Automatic Tester Operation

Effects of Avalanche Cycles on SiC JFETs

Failure during

avalanche (400 cycles)


Gate Leakage

Drain Leakage


Drain current Effect on drain leakage at fixed URS times (1.2us) and cycles (350).

Conclusions The Non Destructive Tester is a useful tool to test

power semiconductor devices at the edges of the SOA It is not possible to use the same NDT for testing

discrete devices and modules The NDT must be designed according to the

characteristics of the device/modules to be tested The pulsed apparatus can be used for other

applications In high current and in unclamped inductive turn-off a

precursor on the waveform can be recognized that evidence instabilities taking place inside the device and can be used to save the sample under test




Conclusions Cosmic rays impact

Cosmic rays impact

Neutron flux at sea level is 105 neutrons/cm2-year

with E>2 MeV which may cause SEE in electronics

“… semiconductor failures induced by cosmic radiation are no longer [only] an aerospace problem. Such failure mechanisms must be accounted for in automotive electronics systems design.” www.automotivedesignline.com, June 2006

Particle shower

Galactic Cosmic Ray

Neutron induced Single Event Effects (SEE) A neutron interacts with a nucleus to produce a heavily ionizing secondary that then causes an anomalous macroscopic effect in a working electronic device

IRRADIATION SPECIES

• Protons • Neutrons • Heavy ions

IRRADIATION FACILITIES

• INFN LNS Catania • Tandem (Heavy ions) • Ciclotrone (Protons)

• INFN LNL Legnaro • Tandem (Heavy ions)

• ENEA Casaccia Roma • Tapiro (Neutrons)

SEE irradiation experiments

SEB in a Power Diode

Typical test circuit

DUT

Vbias C

v(t)

i(t)

1MW

50W

50W line

Ion be am

Charge Amplification (2D Simulation)

0

100

200E-

field

[kV/

cm] 300

400

0 50 100 150 200 250 300 350 400 450Depth [ m]m

1013

1014

1015

1016

1017

1018

Ele

ctro

ns-D

ensi

ty [c

m]

-3

T=0

25ps 100ps 150ps

230ps

500ps 1ns

P+ N+ N-

4kV diode

Biasing voltage:

1800V

Impacting Ion:

12C (17MeV)

G. Soelkner et al. “Charge Carrier Avalanche Multiplication …”, IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. 47, NO. 6, DECEMBER 2000, pp. 2365 - 2372

-5

0

5

10

15

20

25

30C

urre

nt [

A]

-40 0 40 80 120 160 200 240Time [ns]

100ns

Diode Currente during a destructive impact

Biasing Voltage: 2200V

2D Simulation a SEB

0 50 100 150 200 250 300 350 400 450Depth [ m]m

25ps50ps 75ps 100ps125ps

150ps

300ps

1013

1014

1015

1016

1017

1018

E-D

ensi

ty [c

m]

-3

0

100

200

E-fi

eld[

kV/c

m] 300

400

0 50 100 150 200 250 300 350 400 450Depth [ m]m

25ps50ps 75ps 100ps 125ps

150ps

4kV diode

Biasing voltage:

2200V

Impacting Ion:

12C (17MeV)

A double injection like phenomenon

0

100

200

E-fi

eld[

kV/c

m] 300

400

0 50 100 150 200 250 300 350 400 450Depth [ m]m

1013

1014

1015

1016

1017

1018

E-D

ensi

ty [c

m]

-3

Impact ionization

High: Current density

Carriers concentration

Electric field

SEGR SEB

SEE in Power MOSFET

Test circuit

Computer for off-line statistical analysis

Oscilloscope

GPIB

Single Event Burn-out

3D finite element simulations are performed using the ATLAS TCAD simulation tool by Silvaco International.

The simulated elementary cell with its lumped elements and the parameters used to simulate the ionizing track for a bromine ion at 230MeV.

c

0c

t

tt

R

r

t

terfcπt

eeNtr,Q

2

c

0

32 cm

pairs

Rπ3.6

LETN

R 0.124mm

t0 4ps

tC 2ps

SEE in power mosfets Numerical simulation activity

The role of the parasitic BJT in the charge generation mechanism.

Vds=60V Vds=100V (SEB)

SEE in power mosfets 3D numerical simulation

The double injection phenomenon.

SEE in power mosfets 3D numerical simulation

Double injection in Power MOSFET

0 5 10 15 20 25 30 350

0.5

1

1.5

2

2.5x 10

17

Distance [ mm ]

Hole

Concentr

ation [

cm

-3 ]

Hole Concentration t=700ps x=9mm

Vds=100V

Vds=60V

Impact ionizzation

0 5 10 15 20 25 30 350

0.5

1

1.5

2

2.5x 10

5

Distance [ mm ]

Ele

ctr

ic F

ield

[ V

/cm

]

Electric Field t=700ps x=9mm

VDS=60V

VDS=100V

SEGR

SEE in gate oxide of Power MOSFET

Single Event Gate Rupture

A conceptual model for SEGR

J. R. Brews, et. Al. “A Conceptual model for SEGR in Power MOSFET’s,” IEEE TRANS. ON NUCLEAR SCIENCE, VOL. 40, NO. 6, DECEMBER 1993

Ion track

SEB in IGBTs

Collettore

N+

P +

P +

P _

GateEmettitore

N_

Collettore

N+

P +

P +

P _

GateEmettitore

N_

Anode

Kathode

Gate

RP+

SEB in IGBTs

2D simulation of SEB in IGBT

W. Kaindl, et. Al. “Cosmic Radiation-Induced Failure Mechanism of High Voltage IGBT,” Proc. of the 17th ISPSD, May 23-26, 2005, Santa Barbara, CA

Thank You for Your attention

DIEI – Università di Cassino e del Lazio Meridionale Via G. di Biasio, 43, Cassino, Italy

e-mail: [email protected]

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