UNIVERSITY OF CALIFORNIA, SAN DIEGO

CMOS Power Amplifiers for Wireless Communications

A dissertation submitted in partial satisfaction of the

requirements for the degree Doctor of Philosophy

in

Electrical Engineering (Electronic Circuits & Systems)

by

Chengzhou Wang

Committee in charge:

Professor Lawrence E. Larson, ChairProfessor Peter M. AsbeckProfessor Walter H. KuProfessor Chung-Kuan ChengProfessor Bill Hodgkiss

2003

Copyright

Chengzhou Wang, 2003

All rights reserved.

The dissertation of Chengzhou Wang is approved, and it is

acceptable in quality and form for publication on microfilm:

Chair

University of California, San Diego

2003

iii

To my parents and sisters

iv

TABLE OF CONTENTS

Signature Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii

Dedication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iv

Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v

List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . viii

List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xii

Acknowledgements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xiii

Vita, Publications, and Fields of Study . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xv

Abstract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xvi

I Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

I.1 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

I.1.1 Power Amplifiers in Wireless Communication Systems. . . . . . . . . . . 1

I.1.2 Power Amplifier Classifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

I.2 Limitations of Sub-micron CMOS Technology . . . . . . . . . . . . . . . . . . . . . . . . 4

I.2.1 Low Breakdown Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

I.2.2 Low Transconductance-to-current Ratio . . . . . . . . . . . . . . . . . . . . . . . 5

I.2.3 Low Substrate Resistivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

I.3 Dissertation Motivations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

I.4 Dissertation Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

II Class-E Power Amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

II.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

II.2 Improved Class-E Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

II.2.1 Circuit Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

II.2.2 Circuit Equations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

II.2.3 Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

II.2.4 Component Evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

II.3 A Design Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

II.4 Discussions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

v

II.4.1 Validity of Assumptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

II.4.2 Choice of Device Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

II.4.3 Relationship betweenPout andVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

II.4.4 Comparison with Previous Works . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

II.5 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

III Linear CMOS Class-AB Power Amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

III.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

III.2 Distortion Effects of the Gate-Source Capacitance . . . . . . . . . . . . . . . . . . . . . 31

III.2.1 Simplified Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

III.2.2 Capacitance Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

III.2.3 Impact on Linearity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

III.3 Compensation Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

III.3.1 Basic Idea . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

III.3.2 Volterra Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

III.4 Schematic Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

III.4.1 Output Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

III.4.2 Driver Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

III.4.3 Strategy for Ground Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

III.4.4 Final PA Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

III.5 Layout Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

III.5.1 IBM SiGe5AM Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

III.5.2 Basic Transistor Cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

III.5.3 On-chip Inductor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

III.5.4 Current Handling Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

III.5.5 Substrate Coupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

III.5.6 Final PA layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

III.6 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

III.6.1 Implementation Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

III.6.2 Test Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

III.6.3 Measurement Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

III.7 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

IV Dynamic Biasing Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

IV.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

IV.2 Dynamic biasing Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

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IV.2.1 Basic concept . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

IV.2.2 Response of Envelope Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

IV.3 Efficiency Improvement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

IV.3.1 Drain Efficiency for Single-tone Input . . . . . . . . . . . . . . . . . . . . . . . . . 117

IV.3.2 Average Efficiency for Varying-envelope Signals . . . . . . . . . . . . . . . . 120

IV.4 Distortion Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

IV.4.1 IM3 Expression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

IV.4.2 Estimation ofg2 andg3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

IV.4.3 Final IM3 Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

IV.5 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

IV.5.1 IC Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

IV.5.2 Measurement Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

IV.6 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

V Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

Bibliography . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

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LIST OF FIGURES

II.1 Schematic and improved model of CMOS class-E power amplifier. . . . . . . . 12

II.2 Comparison of the current and voltage waveforms between the calculation

and simulation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

II.3 Output power and the drain efficiency versus NMOS width. . . . . . . . . . . . . . 22

II.4 Simplified NMOS small-signal model in triode region and cut-off region. . 24

II.5 Simulated output power and drain efficiency versus NMOS width for the

design approaches developed by Ewing, Sokal, Li, and this work. . . . . . . . . 28

III.1 Simplified models of CMOS class-AB power amplifiers. . . . . . . . . . . . . . . . . 32

III.2 Plots of the simulated NMOS device capacitances as a function of gate-

source voltage, for a fixed drain-source voltage of 3.3 V. . . . . . . . . . . . . . . . . 33

III.3 Simplified schematics of class-AB amplifiers used to illustrate the impact

of the gate-source capacitance on linearity. . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

III.4 Third-order, intermodulation distortion at2ω1 − ω2 versus peak-envelope

output power, at various gate bias voltages. . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

III.5 Third-order, intermodulation distortion at2ω1 − ω2 versus peak-envelope

output power, at various gate bias voltages. . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

III.6 Plots of the device capacitances of a PMOS transistor as a function of its

gate-source voltage, with its drain-source voltage held at zero. . . . . . . . . . . . 39

III.7 Plots of simulatedCggn, Cggp, and the sumCggn+ Cggp for the NMOS and

PMOS devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

III.8 SPECTRE simulated and MATLAB fitted curves for (a)Ceff and (b)idsn

as functions of the NMOS gate-source voltage. . . . . . . . . . . . . . . . . . . . . . . . . 45

III.9 Nonlinear capacitor circuit for Volterra analysis. . . . . . . . . . . . . . . . . . . . . . . . 46

III.10 Simplified nonlinear model of the PA output stage. . . . . . . . . . . . . . . . . . . . . 49

III.11 Circuit for the Volterra calculation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

III.12 Calculated contributions to the drain IM3 from theCeff andidsn nonlinear-

ities for both the basic and linearized amplifiers. . . . . . . . . . . . . . . . . . . . . . . . 53

III.13 Simplified block diagram of designed two-stage CMOS class-AB power

amplifiers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

III.14 Schematic and simplified model of the output stage for the first-order anal-

ysis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

III.15 Load line of the output stage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

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III.16 Plots ofId versusVGS for an ideal class-B operation, and a short-channel

device biased near the threshold voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

III.17 Schematic and equivalent circuit of a high-pass, L-match network . . . . . . . . 61

III.18 Cascade of two lossy L-match networks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

III.19 Output matching networks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

III.20 Circuit and equivalent model of the interstage matching network. . . . . . . . . 67

III.21 Schematic and linear model of the two-stage CMOS class-AB power am-

plifier for illustrating ground connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

III.22 Two-stage CMOS class-AB PAs for illustrating the impact of ground con-

nections on gain. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

III.23 Power gain of the two-stage CMOS class-AB power amplifiers versus to-

tal ground bondwire inductance for the two ground configurations shown

in Fig. III.22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

III.24 Two-stage CMOS class-AB power amplifier for one-chip-ground and two-

chip-ground configurations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

III.25 Small-signal equivalent model of the two-stage CMOS class-AB power

amplifier for one-chip-ground and two-chip-ground configurations. . . . . . . . 77

III.26 Maximum stable ground bondwire inductance of the two-stage CMOS

class-AB PA for the ground configurations in Table III.2. . . . . . . . . . . . . . . . 80

III.27 Schematic of the fully matched two-stage CMOS class-AB power ampli-

fiers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

III.28 Layout of a basic transistor cell. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

III.29 Schematic modelling and sideview of device layouts regarding the effect

of substrate coupling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

III.30 Layout structure employing both large substrate guardrings and deep trench

blocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

III.31 Final Layout of the fully integrated and compensated two-stage CMOS

PA (PA2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

III.32 Die microphotograph of the fully integrated and compensated two-stage

CMOS PA (PA2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

III.33 Photograph and cross section drawing of the MLF package. . . . . . . . . . . . . . 91

III.34 Output and input off-chip matching network for PA3. . . . . . . . . . . . . . . . . . . 93

III.35 ADS schematic and simulated impedance of off-chip output matching net-

work for PA3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

III.36 Application schematic of PA3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

ix

III.37 Photograph of the PCB implementation of PA3. . . . . . . . . . . . . . . . . . . . . . . . 97

III.38 Test setup for evaluating the PAs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

III.39 Measured gain and power-added efficiency versus output power of the

three PAs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

III.40 Simulated and measured gain and power-added efficiency versus output

power for the three PAs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

III.41 Measured IM3, adjacent-channel leakage power, and alternate-channel

power versus peak-envelope output power for the three PAs. . . . . . . . . . . . . . 102

III.42 Measured WCDMA spectra of PA1 and PA2 at a carrier output power of

nearly 20 dBm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

IV.1 Conceptual block diagram and actual implementation of the dynamic bi-

asing technique. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

IV.2 Schematic and equivalent large-signal model of the envelope detection

and gate-bias-control circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

IV.3 Source-drain current ofMp as a function of time. . . . . . . . . . . . . . . . . . . . . . . 111

IV.4 SPECTRE simulated and MATLAB fitted PMOS source-drain current ver-

sus gate voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

IV.5 Schematic of the designed two-stage CMOS power amplifier. . . . . . . . . . . . 115

IV.6 Approximate time-domain waveforms of the input gate voltage, source-

drain current ofMp, and output voltage of the envelope detector for a

two-tone test signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

IV.7 Circuit for the Volterra calculation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

IV.8 IDS versusVGS for a long-channel class-A device and an ideal class-B device.126

IV.9 Ratio ofg2 andg3 to g1 for the four gate bias voltages (0.75 - 0.90 V) of

the implemented class-AB device. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

IV.10 Comparison of the calculated and simulated IM3 of the load voltage at

2ω1 − ω2 versus peak-envelope output power. . . . . . . . . . . . . . . . . . . . . . . . . . 129

IV.11 Contributions to the load-voltage IM3 from theg2, g3, andCeff nonlinearities.130

IV.12 Die microphotograph of the highly integrated and compensated two-stage

CMOS PA (PA3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

IV.13 Calculated, simulated, and measuredVenv versus output power for a single-

tone input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

IV.14 Measured gain and power-added efficiency versus output power for PA3

with the dynamic biasing technique, and PA3 when the envelope detector

is disabled and the gate is biased atVGG0 = 0.85 V, respectively. . . . . . . . . . 133

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IV.15 Measured power consumption improvement versus the PA output power. . . 134

IV.16 Measured IM3, adjacent-channel leakage power, and alternate-channel

power versus peak-envelope output power for the three PAs. . . . . . . . . . . . . . 135

IV.17 Comparison between the calculated and measured load-voltage IM3 ver-

sus output power. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

xi

LIST OF TABLES

I.1 Characteristics of digital wireless systems relevant to power amplifier per-formance in mobile station [1]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

I.2 Comparison of efficiency and linearity for different classes of power am-plifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

II.1 Comparison ofPout andPeff between theoretical prediction and HSPICEsimulation for the designed CMOS class-E power amplifier. . . . . . . . . . . . . . 20

II.2 Assumptions for the analysis by Ewing, Sokal, Li, and this work. . . . . . . . . 27

III.1 Estimated model parameters of driver and output stages. . . . . . . . . . . . . . . . . 69III.2 Ground configurations for the two-stage CMOS class-AB PAs in Fig. III.24. 78III.3 Properties of metal layers in IBM SiGe5AM technology. . . . . . . . . . . . . . . . 83III.4 Comparison between maximum allowable layout currents and correspond-

ing maximum designed currents of all critical components in PA2. . . . . . . . 86III.5 Performance comparison of recently reported linear power amplifiers for

handset applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

xii

ACKNOWLEDGEMENTS

Pursuing the doctoral degree begins with a great deal of excitement and expectations.

However, after years of endeavors, the initial love and devotions to the research topic grad-

ually become frustrations by the overwhelming obstacle and adversity, and I start to realize

that this journey would never be fulfilled without the support of many people.

First and foremost, I would like to express my sincere gratitude and appreciation to

my advisor Professor Lawrence E. Larson. Without his continuous guidance and encour-

agement, my research work towards this thesis would never be possible. I would also like

to thank Professor Peter M. Asbeck for his assistance throughout the years, as his knowl-

edge and experience were also valuable. Furthermore, I am indebted to Professor Walter

H. Ku, Professor Chung-Kuan Cheng, and Professor Bill Hodgkiss, for their patience and

efforts of being my dissertation committee.

This work has benefited from the contributions of many other individuals. Special

thanks to Mani Vaidyanathan and Liwei Sheng for their invaluable suggestions and ideas

to my research projects. I would also like to thank John Fairbanks, Matt Wetzel, Jonathan

Jensen, and Masaya Iwamoto for their assiduous assistance in solving the laboratory and

CAD problems I experienced. In addition, Xuejun Zhang, Junxiong Deng, Vincent Leung,

Don Kimball, Robert Wang and other brilliant colleagues deserve my sincere thanks for

their enthusiastic help and encouragement.

Finally, I am grateful to my family (my parents and my sisters Judy and Fang) and

my dear friends Changchun Shi, Yong Wang, Wei Lin, Jian Ma and others. Without their

xiii

continuous support, this Ph.D work would have been much more difficult.

This research was supported by the UCSD Center for Wireless Communications and

its member companies. Their supports are greatly acknowledged.

xiv

VITA

1992-1997 B.S., Electronics, Beijing University, China

1997-1999 M.S., Electrical Engineering (Electronic Circuits & Systems),University of California, San Diego, United States

1999-2003 Ph.D., Electrical Engineering (Electronic Circuits & Sys-tems), University of California, San Diego, United States

PUBLICATIONS

C. Wang and L.E. Larson, “Analysis of a Microwave CMOS Class-E Power Amplifierwith Finite Switching On-resistance,”1999 IEEE Topical Workshop on Power Amplifierfor Wireless Communications, La Jolla, CA, Sept. 1999.

C. Wang and L.E. Larson, “Highly Integrated Linear Class-AB CMOS Power Amplifierwith Nonlinear Capacitor Compensation,”1999 IEEE Topical Workshop on Power Ampli-fier for Wireless Communications, La Jolla, CA, Sept. 2000.

C. Wang, L.E. Larson, and P.M. Asbeck, “A Nonlinear Capacitance Cancellation Techniqueand its Application to a CMOS Class-AB Power Amplifier, ” presented at 2001 IEEE In-ternational Microwave Symposium (RFIC), Phoenix, AZ, May 2001.

C. Wang, L.E. Larson, and P.M. Asbeck, “Improved Design Technique of a MicrowaveClass-E Power Amplifier with Finite Switching On-Resistance, ” presented at 2002 IEEERadio and Wireless Conference, Boston, MA, Aug 2002.

C. Wang, M. Vaidyanathan and L.E. Larson, “A Capacitance-Compensation Technique forImproved Linearity in CMOS Class-AB Power Amplifiers,” submitted toIEEE Journal ofSolid-State Circuits.

C. Wang, and L.E. Larson, “A Dynamic Biasing Technique for Efficiency Improvement inCMOS Class-AB Power Amplifiers ,” in preparation toIEEE Transactions on MicrowaveTheory and Techniques.

FIELDS OF STUDY

Major Field: Electrical and Computer EngineeringStudies in Radio Frequency Integrated Circuit Design.Professor Lawrence E. Larson

xv

ABSTRACT OF THE DISSERTATION

CMOS Power Amplifiers for Wireless Communications

by

Chengzhou Wang

Doctor of Philosophy in Electrical Engineering (Electronic Circuits & Systems)

University of California, San Diego, 2003

Professor Lawrence E. Larson, Chair

Linearity and efficiency are the two most important characteristics of power ampli-

fiers (PAs) for wireless applications. In this dissertation, we investigate three topics on

CMOS power amplifiers: class-E, class-AB, and dynamic biasing technique.

Previous analytical efforts on class-E power amplifiers assumed either zero switch

resistance and/or infinite drain inductance, leading to less optimized design. In this dis-

sertation, we developed an improved design technique by accounting for both finite drain

inductance and finite “on” resistance for a CMOS device. A design example based on the

developed algorithm achieves an output power of 0.25 W and a drain efficiency of 87% for

a 3.5 mm NMOS class-E device withVDD = 2 V andfc = 1.90 GHz.

The intrinsic linearity obtained in a CMOS class-AB operation is often insufficient

to meet the stringent linearity requirement imposed by modern wireless standards. In this

dissertation, we propose a capacitance compensation technique to improve PA linearity.

xvi

Experiments show that the compensation technique can improve both the two-tone, third-

order intermodulation (IM3) and adjacent-channel leakage power (ACP) by approximately

8 dB. While meeting the 3GPP-WCDMA ACP requirements, the linearized two-stage am-

plifier is capable of delivering an output power of 24 dBm with a small-signal gain of nearly

24 dB and an overall power-added efficiency of 29 %.

The designed two-stage CMOS class-AB power amplifier suffers serious efficiency

degradation when operated at low output power levels. In this dissertation, it was demon-

strated that a dynamic biasing technique can improve the average efficiency of a CMOS

class-AB power amplifier by controlling the gate bias voltage with the envelope of input

RF signal. However, the envelope signal introduced by the dynamic biasing technique can

significantly limit the overall linearity of the CMOS class-AB PA. Both analysis and ex-

periments show that the dynamic biasing technique can significantly degrade the IM3 and

ACP performances of the designed two-stage CMOS class-AB power amplifier.

xvii

Chapter I

Introduction

I.1 Background

I.1.1 Power Amplifiers in Wireless Communication Systems

Recent years have witnessed a tremendous growth of wireless communication prod-

ucts. Consumer electronics, such as cellular phones, wireless local area networks, and

wireless computer peripherals, are just a few examples of the wireless devices that be-

come part of our everyday lives. This constantly growing market drives an intense effort

to develop improved wireless standards and transceiver architectures, as well as reduce

implementation costs by using low-cost technologies and higher integration solutions.

Current implementation of wireless communication devices, such as cellular phones,

employ several chips implemented in different semiconductor technologies in order to real-

ize high performance digital, analog, and RF circuit building blocks. Different technologies

are suited for different functions. For example, CMOS models an ideal switch very well,

thus is very suitable for digital functions and switch-capacitor circuits, but it is a poor tech-

nology for high-frequency, high performance analog functions for its low transconductance

and large parasitics; on the contrary, bipolar is well suited for high-frequency, high perfor-

1

2

mance analog functions, but not ideal for realizing digital functions and switch-capacitor

circuits due to its finite base current and other non-ideal switching characteristics.

The multi-chip solution limits the minimum cost and size of the final device. In

addition, the interface matching between different chips also adds cost, size, and time-to-

market to the final products. Thus, a single-chip solution is highly desirable.

With the advance of CMOS technology, many RF front-end functions, such as low-

noise amplifier, mixer, and voltage-controlled oscillator can be implemented in a low-cost,

high-volume CMOS technology. However, a fully integration of CMOS power amplifier

(PA) still remains a design challenge because, as described later in this section, the limita-

tions of the CMOS technology is especially severe for PA implementations.

Another reason for the reluctance of implementing PA in CMOS technology is the

high performance requirements imposed by modern wireless standards. With the growing

emphasis on channel capacity, more and more wireless communication systems employ

spectrally efficient modulation schemes, such as QPSK and QAM. These schemes results

in signals with highly time-varying envelopes, thus imposes a stringent linearity require-

ment of the power amplifiers to preserve modulation accuracy and limit spectral regrowth.

Meanwhile, to prolong battery life, a reasonable efficiency is also required for the power

amplifiers in such systems. Table 1 lists features pertinent to power amplifier design for

several digital wireless standards.

3

Table I.1: Characteristics of digital wireless systems relevant to power amplifier perfor-mance in mobile station [1].

CELLULAR CORDLESS

Standard GSM NADC IS-95 PDC PHS

Uplink frequency 890-915 825-849 825-849 940-956 1895-1907

band (MHz)

Channel BW (kHz) 200 32.81 1223 31.5 288

Multiple access TDMA TDMA CDMA TDMA TDMA

Modulation GMSK π/4-QPSK O-QPSK π/4-QPSK π/4-QPSK

Duplex mode FDD FDD FDD FDD TDD

Max. TX power (dBm) 30 27.8 27.8 30.0 19.0

Long-term mean 21.0 23.0 10.0 N/A 10.0

power (dBm)

TX duty ratio (%) 12.5 33.3 Variable 33.3 33.3

PA voltage (V) 3.5–6.0 3.5–6.0 3.5–6.0 3.5–4.8 3.1–3.6

ACPR (dBc) N/A -26 -26 -48 -50

Peak-ave. ratio (dB) 0 3.2 5.1 2.6 2.6

Typical PA quies- 20 180 200 150 100

cent current (mA)

Typical efficiency (%) > 50 > 40 > 30 > 50 > 50

I.1.2 Power Amplifier Classifications

Power amplifiers are historically categorized to: A, AB, B, C, D, E, F, and S. While

the first four classes are distinguished primarily by their bias conditions, the others are

categorized based on the signal operations of the amplifier.

With respect to linearity performance, power amplifiers can be divided into linear

(A, AB, B) and nonlinear amplifiers (C, D, E, F, S). In general, efficiency and linearity are

4

two conflicting parameters in PA design. Table 2 shows the comparison of efficiency and

linearity among these power amplifiers.

Table I.2: Comparison of efficiency and linearity for different classes of power amplifiers

Classification A AB B C D E F

Maximum Efficiency(%) 50 50-78 78 100 100 100 100

Typical Efficiency(%) 35 35-60 60 70 75 80 75

Linearity Excellent Good Good Bad Bad Bad Bad

Vpeak(V) 2VDD 2VDD 2VDD 2VDD 2VDD 3.6VDD 2VDD

I.2 Limitations of Sub-micron CMOS Technology

In order to design a CMOS PA, one must first understand the limitations of sub-

micron CMOS technology with respect to PA implementations. The major limitations are

low breakdown voltages, low transconductance-to-current ratio, and low substrate resistiv-

ity, as will be discussed successively.

I.2.1 Low Breakdown Voltages

The gate oxide breakdown occurs when the electric field in the oxide exceeds a cer-

tain value (about 0.07 V/A in silicon dioxide). This process is destructive to the transistor

because it results in a permanent short circuit between the gate and the channel. As the gate

length in a CMOS technology shrinks, so does the thickness of gate oxide to avoid short-

channel effects [2]. Thus, the maximum allowable gate voltage for a sub-micron CMOS

5

device is greatly limited.

In addition to gate oxide breakdown, the drain-substrate pn junction will conduct a

large current if the reverse bias applied to it exceeds a certain value [2]. This breakdown is

nondestructive, but limits the maximum PA voltage swing at the drain of the device.

I.2.2 Low Transconductance-to-current Ratio

When the velocity saturates, the ratio of the transconductance to the current for a

short-channel MOS device is [3]

gm

I=

1

VGS− Vt

=1

Vov. (I.1)

For a bipolar device, this ratio is1/VT , where the thermal voltageVT is 26 mV. In contrast,

the overdriveVov for MOS transistors is typically chosen as several hundred mV. Thus,

the transconductance per given current is much lower for MOS devices than for bipolar

devices.

To accommodate this small transconductance, either the input signal amplitude or

the device size of the PA output stage have to be increased. However, either approach will

increase the loading for the driving stage, thus resulting in higher power consumption of

the driver stage. Increasing the input signal amplitude can also dramatically degrade the PA

linearity because the third-order nonlinearity of the device current is directly proportional

to the cube of the input voltage amplitude. Thus, higher nonlinearity will be expected for

MOS devices than for bipolar devices.

6

I.2.3 Low Substrate Resistivity

In an integrated implementation, a PA resides on the same substrate as other circuit

blocks, some of which may be very sensitive. Since many CMOS processes use low-

resistivity substrates, PA signals can be easily conducted across long chip distance to cor-

rupt adjacent circuit blocks. Thus, substrate isolation is a crucial design issue for integrated

PA implementations.

In addition, a low-resistivity substrate has a detrimental effect on spiral inductors

built above it [4]. This is because the low resistivity allows for creation of eddy currents,

which reduce the effective magnetic field, thus the quality factor of the spiral inductor.

I.3 Dissertation Motivations

Class-E power amplifier is a promising candidate for realizing high efficiency. Pre-

vious analytical efforts on class-E power amplifiers assumed either zero switch resistance

and/or infinite drain inductance, leading to less optimized design. In this dissertation, we

attempt to achieve a more optimized design by accounting for both finite drain inductance

and finite “on” resistance for a NMOS device.

The intrinsic linearity obtained in a class-AB operation is often insufficient to meet

the stringent linearity requirement imposed by modern wireless standards. This is espe-

cially true for a MOS device due to its low transconductance. We attempt to linearize the

intrinsic linearity of a CMOS class-AB power amplifier and prove its feasibility for wireless

7

communications.

Although the designed two-stage CMOS class-AB PA exhibits good linearity and

maximum efficiency, it still suffers significant efficiency reductions when operated at low

power levels. Thus, we would like to explore the possibilities to improve the efficiency of

the CMOS class-AB PA at low output power levels.

I.4 Dissertation Organization

This dissertation consists of five chapters:

Chapter I is the introduction of power amplifiers in wireless communication systems,

the limitations of sub-micron CMOS technologies, and the motivations of this dissertation.

Chapter II presents an improved class-E analytical approach to account for both finite

drain inductance and finite “on” resistance of the NMOS device. A design example based

on the developed algorithm is described and verified by SPICE simulations. Key design

issues of this approach are highlighted in the end.

In Chapter III, we first identify the nonlinearity sources of a NMOS class-AB device.

Then a capacitance compensation technique is introduced, followed by the verification of

this technique using Volterra analysis. Key design issues regarding the schematic, layout,

and implementation of a two-stage CMOS class-AB power amplifier are described, and the

experimental results of prototype power amplifiers are presented and compared with sim-

ulations. It is shown that the capacitance compensation technique leads to a much better

linearity performance without seriously degrading the efficiency of the PA. This chapter

8

also proves the feasibility of linear CMOS class-AB PAs for wireless communication sys-

tems.

Chapter IV describes a dynamic biasing technique to improve PA efficiency at low

output power levels. The transient response of the envelope detector and the average effi-

ciency for a CMOS class-AB PA are analyzed. The impact of the technique on PA linearity

is verified using both Volterra analysis and SPECTRE simulations. Finally, the experimen-

tal results of a prototype amplifier is presented.

Chapter V concludes the whole dissertation.

Chapter II

Class-E Power Amplifiers

II.1 Introduction

The class-E amplifier was first introduced by Ewing [5] in his doctoral thesis, and

then was further elaborated by many other researchers [6]-[11]. As one of the switching-

mode amplifiers, the class-E amplifier realizes very high efficiency (theoretically 100%) by

operating the device as a switch,i.e.,

1. The device sustains zero voltage when it carries current.

2. The device carries zero current when it sustains a finite voltage.

3. There is no transition time between the “on” and “off” states of the device.

This is also referred as the “non-overlapping-current-and-voltage” condition and underlies

all switching-mode amplifiers. One unique feature, which distinguishes the class-E am-

plifier from other switching-mode amplifiers, is that it requireszeroslope of the drain (or

collector) voltage at the moment when the device turns on. This requirement substantially

lowers the sensitivity of the amplifier’s efficiency as a function of the component variations

and other non-ideal effects in practical implementations [12][13].

9

10

Ewing’s original development of the class-E amplifier assumed an infinite collector

inductance, but a finite “saturation” resistance of the transistor. In 1975, Sokal [6] de-

rived a method to analyze class-E amplifiers in optimum performance, where he assumed

both an infinite choke inductor and zero switching-on resistance. In Li’s analysis [8], a

finite choke inductor was introduced, but with an ideal switching-on condition. Recently

published class-E literatures [9]-[11] relied on the previously reported analysis and concen-

trated mostly on the implementation details. In practice, however,both the switching-on

resistance of the active deviceandthe “choke” inductance are finite. The latter is especially

true if MOS devices are used; as will be shown in this chapter, the large shunt parasitic

capacitance of MOS devices requires relatively small drain inductance to achieve the opti-

mum class-E operation at gigahertz-range frequencies. Therefore, an improved analytical

method which takes into account both the finite drain inductance and finite switching-on

resistance is necessary. In this chapter, this optimum is established under the constraint of a

givenRswitch-onCswitch-off product, which is a more realistic estimate of typical MOS devices.

This new technique expresses the circuit parameters in terms of the device width and the

design specifications, such as the output power and operating frequency. The agreement

obtained between the analytical and simulated results is outstanding, verifying the utility

of the technique.

This chapter begins with a brief class-E circuit description, followed by a detailed

presentation of the improved analytical method. Then, a design example based on the

developed algorithm is described and SPICE simulation results are compared with the the-

11

oretical calculations. Finally, key design issues, such as the validity of assumptions and the

choice of device width, are discussed and conclusions are summarized.

II.2 Improved Class-E Analysis

II.2.1 Circuit Description

The simplified schematic for a CMOS class-E amplifier is shown in Fig. II.1(a). Here,

M0 is an NMOS device,L1 is the finite drain (choke) inductor, andL2 andC2 provides the

output matching. The following assumptions were made to simplify the analysis:

• Ron, the switching-on resistance of the NMOS transistor, is constant and dominates

the total output impedance of the device during the “on” period.

• C1, the switching-off capacitance of the NMOS transistor, dominates the total output

impedance of the device during the “off” period and is independent of the switch

voltageVd(t).

• The quality factor Q of the output matching network is large enough to allow a sinu-

soidal output only.

Based on these assumptions, the transistor is considered to be a constant resistorRon when

it is switched on, and a constant capacitorC1 when it is off, as shown in Fig. II.1(b). The

output matching network,L2 andC2, can be divided into two parts: the ideal resonant

circuit at the operation frequencyfc and the excessive reactancejX. The latter is for

12

V

Vs

Vo

DD

L1

RL

L C2 2

0M

(a)

L

C R

1

L

V

resonator at ω

Ron off

1L

jX

DD

c

oi (t)

di (t)

2v (t)

ov (t)

dv (t)

i (t)

1on

2

(b)

Figure II.1: CMOS class-E power amplifier. Part (a) shows the simplified schematic, andpart (b) shows the model accounting for both finite “on” resistance and finite drain induc-tance.

13

shaping the current and voltage waveforms for the optimum class-E operation.

II.2.2 Circuit Equations

Output voltage and current

The amplifier is driven by a large, periodic square-wave voltage signal to obtain the

switching performance. Consequently, the steady-state output current is also periodic and

can be approximated as a sinusoidal waveform due to the highQ of the output matching

network. Let the signal period beT and the angular frequency beωc = 2π/T , the output

current is

io(t) = Io sin(ωct + φo) (II.1)

whereIo is the amplitude of the output current, andφo is the phase shift constant.

The voltage at node 2 is also sinusoidal but with an extra phase shift byjX:

v2(t) = V sin(ωct + φ1) (II.2)

where

V = IoRL

√(1 +

X2

R2L

)(II.3a)

φ1 = φo + tan−1

(X

RL

)(II.3b)

14

Drain inductor current and drain voltage

To evaluate the current flowing through the finite drain inductorL1, we apply KCL

at node 1:

iL(t) = id(t) + Io sin(ωct + φo). (II.4)

From the inductor characteristics,iL(t) is related to the drain voltagevd(t) by

VDD − vd(t) = L1diL(t)

dt. (II.5)

Since the device is switched between “on” and “off” states, the operation of the amplifier

can be divided into two parts:

• Off state(nT ≤ t ≤ (n + 12)T ): When the active device is off,vdoff(t) andidoff(t) are

governed by the characteristics of the capacitanceC1, i.e.,

idoff(t) = C1dvdoff(t)

dt. (II.6)

Substituting (II.6) and (II.5) into (II.4) results in the following second-order differ-

ential equation:

L1C1d2iLoff(t)

dt2+ iLoff(t) = Io sin(ωct + φo). (II.7)

Solving this equation gives

iLoff (t) = A cos(ωot) + B sin(ωot) +Io

1− β2sin(ωct + φo) (II.8)

where

ωo =1√

L1C1

(II.9a)

β = ωc/ωo (II.9b)

15

and the coefficientsA andB are two constants to be determined.

• On state((n + 12)T ≤ t ≤ (n + 1)T ): When the active device is “on”, it is modelled

as a small resistor, thus

vdon(t) = idon(t)Ron. (II.10)

Substituting (II.10) and (II.4) into (II.5) gives a first-order differential equation:

VDD − iLon(t)Ron + IoRon sin(ωct + φo) = L1diLon(t)

dt. (II.11)

Solving this equation yields

iLon(t) =Ioγ

γ2 + ω2c

[γ sin(ωct + φo)− ωc cos(ωct + φo)] +VDD

Ron+ Ce−γt (II.12)

where the coefficientC is a constant to be determined, andγ is defined as

γ =Ron

L1

. (II.13)

II.2.3 Conditions

To evaluate the constantsA,B, C, Io andφo, we need to apply the periodic, boundary,

and class-E conditions to the above circuit equations. Those conditions are:

• Periodic conditions: According to the characteristics of the inductance and capaci-

tance, the current ofL1 and the drain voltage (also the voltage ofC1) satisfy

iLon(t)∣∣t=(n+1)T = iLoff(t) |t=nT (II.14a)

vdon(t)∣∣t=(n+1)T = vdoff(t) |t=nT . (II.14b)

16

• Boundary condition: iLon(t) must be continuous,i.e.,

iLon(t)∣∣t=(n+1/2)T = iLoff (t)

∣∣t=(n+1/2)T . (II.15)

• class-E conditions: The optimum class-E conditions are:

vdoff(t)∣∣t=(n+1/2)T = 0 (II.16a)

dvdoff(t)

dt

∣∣t=(n+1/2)T = 0. (II.16b)

Substituting (II.6), (II.8), (II.10), and (II.12) into (II.14)-(II.16) gives the following equa-

tion array:

VDD

Ron+ Ce−γT +

Ioγ

(γ2 + ω2c )

(γ sin φo − ωc cos φo) = A +Io sin φo

(1− β2)(II.17a)

γ

ωc

Ce−γT − Ioγ

(γ2 + ω2c )

(γ cos φo + ωc sin φo) = −B

β− Io cos φo

(1− β2)(II.17b)

VDD

Ron+ Ce−γT/2 − Ioγ

(γ2 + ω2c )

(γ sin φo − ωc cos φo) = A cosπ

β+ B sin

π

β

− Io sin φo

(1− β2)(II.17c)

1

γ

(Aωo sin

π

β−Bωo cos

π

β+

Ioωc

(1− β2)cos φo

)= −VDD

Ron(II.17d)

Ce−γT/2 +Ioωc

(γ2 + ω2c )

(γ cos φo + ωc sin φo) = −VDD

Ron(II.17e)

Here,VDD, T , andωc are fixed by the design specifications;γ andβ are functions ofL1 and

C1; Ron andC1 are determined by the choice of device size.

17

DC Power Dissipation and Output Power

The total dc powerPdc is defined as the product of the power supply voltageVDD and

the dc currentIdc drawn from the power supply:

Pdc = VDDIdc (II.18)

where

Idc =1

T

∫ (n+1)T

nT

iL(t) dt

=1

T

(∫ (n+1/2)T

nT

iLoff (t) dt +

∫ (n+1)T

(n+1/2)T

iLon(t) dt

). (II.19)

Meanwhile,Pdc is the sum of the power consumed by the load and the power dissipated in

the active device,i.e.,

Pdc = Pout + Pd. (II.20)

During the switching-off period, only capacitive current flows into the device, imply-

ing no dc power dissipation in the device; during the switching-on period,Ron is the only

source of power consumption. Thus, the total power dissipation in the device, during one

period, is

Pd =1

T

∫ (n+1)T

(n+1/2)T

i2don(t)Ron dt. (II.21)

Substituting (II.18), (II.19), and (II.21) into (II.20), we have

VDD

T

(∫ (n+1/2)T

nT

iLoff(t) dt +

∫ (n+1)T

(n+1/2)T

iLon(t) dt

)= Pout +

1

T

∫ (n+1)T

(n+1/2)T

i2don(t)Ron dt

(II.22)

18

where iLoff(t) and iLon(t) are expressed in (II.8) and (II.12), respectively, andidon(t) is

related withiLon(t) by (II.4).

II.2.4 Component Evaluation

To evaluate the components ofL1, L2, C2, andRL, we need to first solve the major

current and voltage expressions:id(t), iL(t), io(t), andvd(t). As shown in (II.1), (II.8), and

(II.12), io(t) andiL(t) will be obtained ifA, B, C, φo, Io, β, andγ are given. OnceiL(t)

is solved,id(t) andvd(t) will be derived from (II.4) and (II.5), respectively. Therefore, our

first goal is to solve the above seven variables.

SinceVDD, ωc, andPout are fixed by the design specifications, the six independent

equations, (II.17a)-(II.17e) and (II.22), have a total of eight unknowns:A, B, C, φo, Io, γ,

β, andRon, among whichβ andγ are functions ofL1, C1, andRon, as illustrated in (II.9b)

and (II.13), respectively. If both the technology and width of the active device are chosen,

Ron andC1 will be fixed. Then, the remaining six independent unknowns –A, B, C, φo,

Io, andL1 – can be solved.

With our assumption of the sinusoidal output, the resistive loadRL is found from

Pout =I2o

2RL. (II.23)

As shown in (II.3a), V – the amplitude ofv2(t) – is a function ofIo, X, andRL; in addition,

it is also the fundamental component ofvd(t). Therefore, we have

V =2

T

∫ (n+1)T

nT

vd(t) sin(ωct + φ1) dt. (II.24)

19

Substituting (II.3a) into (II.24) results in

IoRL

√(1 +

X2

R2L

)=

2

T

∫ (n+1)T

nT

vd(t) sin(ωct + φ1) dt (II.25)

thus the excessive reactanceX is evaluated. There is no specific requirements for the

loaded Q of the output matching network, as long as it is large enough to allow a sinusoidal

output only. In practice, a Q of 5 is enough. Once Q is chosen,L2 is evaluated by

Q =ωcL2

RL

. (II.26)

andC2 is solved by

jωcL2 +1

jωcC2

= jX. (II.27)

Based on (II.23)-(II.27), the design algorithm of a CMOS class-E amplifiers in opti-

mum performance is straightforward. MATHEMATICA scripts were developed to perform

the calculations.

II.3 A Design Example

As an example of this design technique, a CMOS class-E power amplifier was ana-

lyzed with the following design specifications:

• Output powerPout: 0.25 W.

• Power supply voltageVDD: 2 V.

• Operating frequencyfc: 1.9 GHz.

20

The device parameters are those of a0.6 µm digital CMOS technology, in whichRon is

approximately3 Ω andC1 is roughly1 pF for a 1 mm device.

We first picked the NMOS width (WN ) as 3.5 mm, so the values ofRon and C1

were obtained. Following the component-evaluation procedure described in Section II.2.4,

we were able to computeL1, L2, C2, andRL, as well as the expressions ofid(t), iL(t),

io(t), andvd(t). Then, HSPICE netlists were constructed and simulated, and the results

were compared with the theoretical calculations. Table II.1 shows such comparison for the

amplifier’s output powerPout and drain efficiencyPeff; also shown are the employed com-

ponent values. As can be seen, less than 5% difference between the theoretical prediction

and simulation was achieved, verifying the utility of the technique.

The calculated and simulated current and voltage waveforms are compared in Fig. II.2.

Note that the pike invd(t) comes from the sharp transition of the input square-wave signal.

Table II.1: Comparison ofPout andPeff between theoretical prediction and HSPICE simu-lation for the designed CMOS class-E power amplifier.

WN (mm) L1(nH) L2(nH) C2(pF) RL(Ω) Pout(W) Peff(%)

Theory 3.5 1 7.1 1 17 0.248 85

Simulation 3.5 1 7.1 1 17 0.25 87

Since we have the freedom in choosing the NMOS widthWN , further calculations

and simulations were performed by sweepingWN from 2.5 mm to 5 mm. The resulting

Pout andPeff are shown in Fig. II.3.

21

7.8 7.9 8 8.1 8.2 8.3 8.4 8.5−0.3

−0.2

−0.1

0

0.1

0.2

0.3

0.4

0.5

TIME (ns)

CU

RR

EN

T (

A)

iL(t)

id(t)

CalculationSimulation

(a)

7.8 7.9 8 8.1 8.2 8.3 8.4 8.5−4

−2

0

2

4

6

8

TIME (ns)

VO

LTA

GE

(V

)

vd(t)

vo(t)

CalculationSimulation

(b)

Figure II.2: Comparison of the current and voltage waveforms between the calculation andsimulation. Part (a) shows the drain inductor currentiL(t) and the drain currentid(t); part(b) shows the drain voltagevd(t) and the load voltagevo(t).

22

2.5 3 3.5 4 4.5 5

0.05

0.1

0.15

0.2

0.25

DEVICE WIDTH (mm)O

UT

PU

T P

OW

ER

(W

)

Calculation Simulation

2.5 3 3.5 4 4.5 5

75

80

85

90

95

DEVICE WIDTH (mm)

DR

AIN

EF

FIC

IEN

CY

(%

)

Figure II.3: Output power and the drain efficiency versus NMOS width.

II.4 Discussions

II.4.1 Validity of Assumptions

As described in Section II.2.1, the following assumptions were made for our analysis:

• Ron, the switching-on resistance of the NMOS transistor, is constant and dominates

the total output impedance of the device during the “on” period.

• C1, the switching-off capacitance of the NMOS transistor, dominates the total output

impedance of the device and is independent of the switch voltageVd(t) during the

“off” period.

• The loaded quality factor (Q) of the output circuit is high enough to allow a sinusoidal

output only.

Since the third assumption can be easily met by a proper choice of Q, we will only investi-

gate the first two assumptions.

23

When the NMOS transistor turns on, it is in the triode region. Since theVDS is small,

the simplified model shown in Fig. II.4(a) is often used [14]. Here,rds corresponds toRon,

and is given by

rds =1

µnCox

(W

L

)(VGS− VTn)

. (II.28)

The gate-to-channel capacitance is evenly divided between the source and drain nodes,

Cgs = Cgd =WLCox

2. (II.29)

The channel-to-substrate capacitance is divided in half and shared between the source and

drain junctions. At the drain node, this channel capacitor, together with the junction-to-

substrate capacitance and the junction-sidewall capacitance, consists of the drain-bulk ca-

pacitance:

Cdb = Cj0(Ad +Ach

2) + Cj-sw0Pd. (II.30)

For typical CMOS processes,Cdb andCgd are in the range of 1 pF/mm. The quantityrds

depends on the gate-source voltageVGS, but has typical values of 2-4Ω/mm. At 1.90 GHz,

the impedance ofCdb andCgd are much higher than the “on” resistance, thus verifying our

utilization of the first assumption.

When the transistor turns off, the model changes dramatically. A reasonable model

is shown in Fig. II.4(b). Since the channel has disappeared,Cgs andCgd are now due to

only overlap and fringing capacitances:

Cgs = Cgd =WLovCox

2. (II.31)

24

Vg

VVs d

gsC

C

C

C

gd

dbsb

dsr

(a)

Vg

VVs d

gsC

C

Cgd

Cdbsb

Cgb

(b)

Figure II.4: Simplified NMOS small-signal model (a) in triode region and (b) in cut-offregion.

25

The capacitorCdb, which is also smaller when the channel is not present, is

Cdb =Cj0Ad√1 +

VDB

Φ0

. (II.32)

The total drain capacitance, if the input is treated as ac ground, is the sum ofCgd andCdb.

Thus, we have

C1 =WLovCox

2+

Cj0Ad√1 +

VDB

Φ0

. (II.33)

As shown in (II.33),C1 is a nonlinear function of its own voltageVDB, as opposed to the

“constant switching-off capacitance” of the second assumption. The simulations, however,

showed that this nonlinear capacitance does not introduce significant errors, as illustrated

in Fig II.2 and II.3.

II.4.2 Choice of Device Width

As shown in Fig. II.3, the drain efficiency is improved with an increase of the device

width. This can be seen in (II.21): the power dissipated in the device is proportional to the

switching-on resistanceRon, and the wider the device is, the smallerRon. Therefore, it is

not surprising that the efficiency is improved when a wider device is employed.

As the NMOS width increases, several practical issues arises. First, designing the

driving stage becomes more and more difficult because of the increase of the gate capaci-

tance. Second, the optimum drain inductance becomes very small, resulting in difficulties

in practical implementation. Therefore, trade-offs have to be made in choosing the opti-

mum NMOS width.

26

II.4.3 Relationship betweenPout and VDD

As illustrated in (II.17a)-(II.17e) and (II.22), all the variables have linear relationship

with VDD. In other words, if

V ′DD = kVDD (II.34)

and

I ′o = kIo (II.35)

A′ = kA (II.36)

B′ = kB (II.37)

C ′ = kC (II.38)

all the equations will be reduced to their original forms. Therefore, all the component

values –L1, L2, C2, andRL – are unchanged, and all the current and voltages –id(t), iL(t),

io(t), andvd(t) – arek times their original values. The output power becomes

P ′out = k2Pout. (II.39)

This implies a perfect application of class-E power amplifiers in envelope elimination and

restoration (EER) systems, where the envelope variation of the modulated signal is imposed

to the switching power amplifier through the power supply.

It is important to mention, however, that our analysis assumed the constant switching-

off capacitanceC1. For the actual devices, as described in Section II.4.1,C1 is nonlinear

and varies with the drain-voltage swing; this may introduce some errors.

27

Some papers [15][16] claimed that the nonlinear parasitic capacitor does not in-

fluence the class-E performance. This conclusion, however, is made based on the ideal

switching-on condition (Ron=0) and infinite drain inductance. In addition, the resulted op-

eration, due to the nonlinear capacitance, does not predict the linear relationship withVDD,

as opposed to our above conclusion. The details can be seen in (4.1)-(4.5) of [15].

II.4.4 Comparison with Previous Works

To show this technique leads to improved designs, simulations were performed based

on the different design approaches developed by Ewing [5], Sokal [6], Li [8], and our re-

sults, respectively. Ewing assumed an infinite drain choke inductance but a finite switching-

on resistance; Sokal assumed an infinite drain choke inductance with an ideal switching

condition,i.e., zero switching-on resistance; Li took the finite drain inductance into account

and assumed an ideal switching condition. These assumptions are shown in Table II.2.

Table II.2: Assumptions for the analysis by Ewing, Sokal, Li, and this work.

Ewing [64] Sokal [75] Li [94] This work

Switching-on resistance finite zero zero finite

Drain inductance infinite infinite finite finite

To make the comparison fair, we employed the same devices and set the same design

specifications ofPout = 0.25 W andfc = 1.9 GHz. Since both Ewing and Sokal assumed

an infinite choke inductance, their designs have one degree less freedom than Li’s and ours.

To achieve the design specifications and make the comparison possible,VDD was varied for

28

Ewing’s and Sokal’s designs and was fixed as2 V for Li’s and our designs.

Figure II.5 shows the simulated output power and drain efficiency versus the device

width by the four design approaches. As can be seen, Ewing’s approach has good output

power performance but poor drain efficiency, while both Sokal’s and Li’s works achieve

good efficiency but predict poor output power. Our design technique, however, not only

achieves the designed output powers, but also obtains the optimized drain efficiency.

2.5 3 3.5 4 4.5 50.05

0.1

0.15

0.2

0.25

0.3

DEVICE WIDTH (mm)

OU

TP

UT

PO

WE

R (

W)

Ewing [64]Sokal [75]Li [94]This work

Design goal

(a)

2.5 3 3.5 4 4.5 5

40

60

80

100

DEVICE WIDTH (mm)

DR

AIN

EF

FIC

IEN

CY

(%

)

Ewing [64]Sokal [75]Li [94]This work

(b)

Figure II.5: Simulated (a) output power and (b) drain efficiency versus NMOS width forthe design approaches developed by Ewing, Sokal, Li, and this work.

29

II.5 Conclusions

An improved design technique is developed to derive the optimum performance of a

CMOS class-E power amplifier. Compared with other theoretical approaches, this design

approach models not only the finite drain inductance, but also the switching-on resistance

of the transistor, thus it leads to a more optimized design. With this design technique,

optimum circuit parameters, as well as the voltage and current waveforms, are derived and

numerically computed.

The design algorithm we developed is applicable not only for bulk MOS devices, but

also for other active devices, such as bipolar transistors, as long as they are operated as

switches.

The disadvantage of this technique is the analytical complexity rising from the inclu-

sion of both the finite choke inductance and the finite switching-on resistance. Although

the analysis leads to more accurate and optimized designs, it does not provide intuitive and

straightforward expressions.

Chapter III

Linear CMOS Class-AB Power

Amplifiers

III.1 Introduction

As described in the first chapter, to meet the simultaneous requirements of high lin-

earity and reasonable efficiency, power amplifiers in non-constant-envelope systems are

often operated in a class-AB mode. Although more linear than a class-B or higher ampli-

fier, the intrinsic linearity obtained in class-AB operation is often still insufficient to meet

required specifications. This is especially true if a MOS device is employed because the

low transconductance associated with the MOS device requires a relatively large input volt-

age signal, and since the third-order nonlinearity (e.g., IM3) is directly proportional to the

cube of the input signal amplitude, this large signal amplitude will yield significant non-

linearity at the output. While many external linearization techniques are known [12], they

are complex and inconvenient for handset applications, and it is thus important that the

intrinsic amplifier linearity be made as high as possible. In this chapter, it is shown that the

gate-source capacitance of a MOS device is a major source of nonlinearity that can limit

the performance of a CMOS class-AB power amplifier. A simple technique to compensate

30

31

the nonlinearity is suggested, and simulations and experiments on a prototype amplifier are

used to demonstrate its effectiveness.

This chapter will begin with a description of distortion effects of the gate-source

capacitance. Then a capacitance compensation technique will be introduced, followed by

the verification of this technique using Volterra analysis. The detailed schematic and layout

designs will be presented, along with the implementation issues and experimental results

of the prototype power amplifiers. Finally, the conclusions will be summarized.

III.2 Distortion Effects of the Gate-Source Capacitance

III.2.1 Simplified Model

Figure III.1(a) shows a highly simplified model for an NMOS device working as a

class-AB amplifier. Here, the input signal current isis, the input-matching network (which

includes the source admittance) isI, the output-matching network isO, and the load re-

sistance isRL. The transistor itself is modeled using the quasi-static, drain-source signal

currentidsn(vgs, vds), which is a function of both the gate-source and drain-source signal

voltages,vgs and vds, and the following device capacitances: the gate-body capacitance

Cgbn, the gate-source capacitanceCgsn, and the gate-drain capacitanceCgdn. This model

assumes that the intrinsic source and body (substrate) are connected together, and omits a

number of elements, including the gate, drain, and source resistances, a substrate network,

and the capacitance between drain and source (although the linear parts of some of these

32

elements could be absorbed intoI andO). These simplifications are justified, since the pur-

pose of the model is merely to illustrate the main sources of nonlinearity under class-AB

operation. For accurate simulation results needed in final designs, however, it should be

noted that radio-frequency (RF) MOS models should include the omitted elements [17]–

[21].

(b)

gsngbn

gdn

idsnC C

C

s Ii LO R

iC C

C

dsp

gdp

gspgbp

gsngbn

gdn

idsnC C

C

s Ii LO R

(a)

g d

ss

g d

ss

Figure III.1: Simplified models of CMOS class-AB power amplifiers. Part (a) shows anNMOS device working alone, and part (b) shows an NMOS device along with a PMOSdevice used to provide a compensating input capacitance.

33

III.2.2 Capacitance Components

Shown in Fig. III.2 are plots of the simulated NMOS device capacitances as a func-

tion of gate-source voltage, for a fixed drain-source voltage. The variation of the capac-

itances with drain-source voltage can be neglected as long as the device remains in sat-

uration [2, Ch. 8]; this is typically ensured in power-amplifier design, since appreciable

distortion would otherwise occur when the device transits across the knee that exists in

the current-voltage characteristics between the saturation and triode regions. The device is

0 0.5 1 1.5 20

4

8

12

16

GATE−SOURCE VOLTAGE (V)

CA

PA

CIT

AN

CE

(pF

)

Cggn

(ac simulation)C

gsn+C

gbn+C

gdnC

gsnC

gbnC

gdn

Figure III.2: Plots of the simulated NMOS device capacitances as a function of gate-sourcevoltage, for a fixed drain-source voltage of 3.3 V. The device length and width are0.5 µmand3 mm, respectively, and the device threshold voltage isVTn = 0.66 V.

from IBM’s “SiGe5AM” technology, and the plots were obtained using SPECTRE circuit

simulator and the associated commercial MOS model released by IBM; the model em-

ploys BSIM3v3.2 as an intrinsic subcircuit, along with extrinsic parasitics to account for

RF effects [22, p. 53].

Figure III.2 confirms that the total capacitance seen looking into the gate, as found

34

from an ac simulation at each gate-source voltage,Cggn ≡ Im y11/ω, wherey11 is the

short-circuit, common-source input admittance andω = 2π(2 GHz) is the radian fre-

quency, is equal to the sum of the individual capacitance components mentioned earlier:

Cggn = Cgsn + Cgbn + Cgdn. This is to be expected when the device’s parasitic resistances

are negligible [19, eq. (9)], and helps to validate the simplified model of Fig. III.1(a). More

importantly, Fig. III.2 shows that whileCgdn andCgbn are relatively constant,Cgsn varies

substantially as the device transits from an “off” (below threshold) to an “on” (above thresh-

old) state. WhileCgsnas plotted includes both intrinsic and extrinsic parts, almost all of this

variation can be traced to a change in the intrinsic part [19, Fig. 3(a)]. This variation is par-

ticularly germane for class-AB operation, because the transition in the capacitance occurs

at the device’s threshold voltage, close to where it is typically biased. As will be shown,

the change in capacitance leads to substantial distortion at the gate, and can subsequently

limit overall amplifier linearity.

III.2.3 Impact on Linearity

In order to illustrate the impact of the gate-source capacitance on the linearity of a

class-AB amplifier, the simplified circuits of Fig. III.3 will be used; the circuit in Fig. III.3(a)

is a basic class-AB amplifier, and the circuit in Fig. III.3(b) includes additional circuitry to

“compensate” or “linearize” the nonlinear capacitance between the gate and source that

will be explained in Section III.3 A.

In addition to providing appropriate matches at the fundamental frequency, the input

35

(b)

(a)

LR

VDD

si Inputmatching network

V

Outputmatching network

GG

LR

VDD

si Inputmatching network

V

Outputmatching network

GG

VPP

Figure III.3: Simplified schematics of class-AB amplifiers used to illustrate the impact ofthe gate-source capacitance on linearity. The basic amplifier is in (a), and the linearized ver-sion is in (b). The NMOS and PMOS devices are the same as those in Figs. III.2 and III.6,respectively.

36

and output matching networks include short-circuit terminations at the harmonic frequen-

cies, which we found helped overall linearity1; they also helped to boost the fundamental

output power [23, p. 384]. The input network includes the source admittance, chosen in

this case to represent the output admittance of a driving class-A stage. In fact, the circuits

in Fig. III.3 are simplified versions of actual two-stage, class-AB amplifiers that were built

and tested, and which will be described in Section III.6.

Figures III.4 and III.5 show SPECTRE simulations of the third-order, intermodula-

tion distortion (IM3) at2ω1 − ω2 for a two-tone input at frequenciesω1 = 2π(1.96 GHz)

andω2 = 2π(1.94 GHz), at the gate and drain, respectively; note that the drain IM3 is

equivalent to the load IM3, sinceO andRL are linear and2ω1 − ω2 ≈ ω1.

As shown, the basic amplifier of Fig. III.3(a) incurs substantial distortion at both

the gate and drain; it will be proven in Section III.3 B that most of this distortion is due

to the change in gate-source capacitance as the device turns on and off during class-AB

operation. On the other hand, Figs. III.4 and III.5 show that much better performance can

be obtained by employing the scheme illustrated in Fig. III.3(b), where a compensating

nonlinear capacitance is added at the input.

1The details are described in the “out-of-band termination” part of Section III.4.

37

0 10 20 30

−80

−40

−20

0 10 20 30

−80

−60

−40

−20

0 10 20 30

−80

−60

−40

−20

0 10 20 30

−80

−60

−40

−20

OUTPUT POWER (dBm) OUTPUT POWER (dBm)

OUTPUT POWER (dBm) OUTPUT POWER (dBm)

GG

GG

GG

GG

V = 0.75V V = 0.80V

V = 0.90VV = 0.85V

GA

TE

−V

OLT

AG

E IM

3 (d

Bc)

GA

TE

−V

OLT

AG

E IM

3 (d

Bc)

−60

GA

TE

−V

OLT

AG

E IM

3 (d

Bc)

GA

TE

−V

OLT

AG

E IM

3 (d

Bc)

linearized

basic basic

linearized

basic

linearized

basic

linearized

SPECTRE (basic) SPECTRE (linearized) Volterra (basic) Volterra (linearized)

Figure III.4: Third-order, intermodulation distortion at2ω1 − ω2 versus peak-envelopeoutput power, at various gate bias voltages. The circuits are the basic and linearized class-AB amplifiers in Figs. III.3(a) and III.3(b), respectively. These plots are for the distortionin the gate voltage. Values from both simulation (using SPECTRE) and Volterra theory[using (III.22)–(III.28)] are shown.

38

0 10 20 30

−80

−60

−40

−20

0 10 20 30

−80

−60

−40

−20

0 10 20 30

−80

−60

−40

−20

0 10 20 30

−80

−60

−40

−20

OUTPUT POWER (dBm) OUTPUT POWER (dBm)

OUTPUT POWER (dBm) OUTPUT POWER (dBm)

GGV = 0.75V GGV = 0.80V

GGV = 0.90VGGV = 0.85V

DR

AIN

−V

OLT

AG

E IM

3 (d

Bc)

DR

AIN

−V

OLT

AG

E IM

3 (d

Bc)

DR

AIN

−V

OLT

AG

E IM

3 (d

Bc)

DR

AIN

−V

OLT

AG

E IM

3 (d

Bc)

linearized

basic basic

linearized linearized

basic basic

linearized

SPECTRE (basic) SPECTRE (linearized) Volterra (basic) Volterra (linearized)

Figure III.5: Third-order, intermodulation distortion at2ω1 − ω2 versus peak-envelopeoutput power, at various gate bias voltages. The circuits are the basic and linearized class-AB amplifiers in Figs. III.3(a) and III.3(b), respectively. These plots are for the distortionin the drain voltage. Values from both simulation (using SPECTRE) and Volterra theory[using (III.22)–(III.28)] are shown.

39

III.3 Compensation Technique

III.3.1 Basic Idea

Shown in Fig. III.6 are plots of the device capacitances of a PMOS transistor as a

function of its gate-source voltage, with the drain-source voltage held at zero.

−1 −0.5 0 0.50

4

8

12

GATE−SOURCE VOLTAGE (V)

CA

PA

CIT

AN

CE

(pF

)

Cgsp

+Cgbp

+Cgdp

Cgsp

Cgbp

Cgdp

Figure III.6: Plots of the device capacitances of a PMOS transistor as a function of its gate-source voltage, with its drain-source voltage held at zero. The device length and width are0.5 µm and2 mm, respectively, and the device threshold voltage isVTp = −0.49 V.

As can be seen, whileCgbp is relatively constant,Cgdp andCgsp change2 from a high

to a low value as the device transits from an “on” to an “off” state. This behavior is exactly

complementary to that ofCgsn in Fig. III.2. Therefore, it should be possible to “linearize”

or “compensate”Cgsn with the aid of a PMOS device. The basic idea is simply to place a

PMOS device alongside the NMOS device as illustrated in Fig. III.3(b); the model for the

situation is shown in Fig. III.1(b). When the PMOS device is properly biased and sized,

2Since the drain-source voltage is zero,Cgdp should equalCgsp; the small discrepancy occurs due to animplementation limit in BSIM3v3 [24, Ch. 4].

40

the total capacitanceCggn + Cggp seen at the NMOS gate will be a constant, which reduces

the distortion generated at the gate, and subsequently at the drain.

Since the change in the NMOS and PMOS capacitances occurs at their respective

threshold voltages, it is clear that the PMOS bias voltageVPP in Fig. III.3(b) should be

VPP = VTn − VTp. (III.1)

NeglectingCgbn andCgbp and extrinsic contributions to the capacitances, an appropriate

figure for the sizing of the PMOS device can be obtained by noting that the NMOS device

switches between weak and strong inversion, and the PMOS device works in the triode

region. Therefore [2, Sec. 8.3.2], the changes in NMOS and PMOS capacitances are ap-

proximately

∆Cggn∼ ∆Cgsn≈ 2

3WnLnCox n (III.2)

and

∆Cggp∼ ∆(Cgsp+ Cgdp) ≈ 2

[WpLpCox p

2

]= WpLpCox p (III.3)

whereWn andLn, andWp andLp, are the widths and lengths of the NMOS and PMOS de-

vices, andCox n andCox p are their oxide capacitances, respectively. Assuming the changes

in the capacitances are abrupt, we then require

∆Cggn

∆Cggp∼ 2

3

WnLn

WpLp

Cox n

Cox p∼ 1 (III.4)

which can be used as a guide to size the PMOS device.

41

0 0.5 1 1.5 20

4

8

12

16

20

NMOS GATE−SOURCE VOLTAGE (V)

CA

PA

CIT

AN

CE

(pF

)

Cggn

+Cggp

Cggn

Cggp

Figure III.7: Plots of simulatedCggn, Cggp, and the sumCggn + Cggp for the NMOS andPMOS devices of Figs. III.2 and III.6.

Figure III.7 shows plots ofCggn andCggp, found from Imy11/ω, and of the sum

Cggn + Cggp, for the NMOS and PMOS devices of Figs. III.2 and III.6. As shown, while

bothCggn andCggp vary with the NMOS gate-source voltage, the sumCggn + Cggp remains

roughly constant. The small ripple that occurs in the sum at the transition point arises

because the capacitances do not change abruptly; the slope of theCggn curve is not exactly

equal (in magnitude) to that of theCggp curve. The ripple can be minimized by adjusting

the bias and size of the PMOS device from the nominal values given by (III.1) and (III.4).

The impact of “linearizing” or “compensating” the input capacitance can be understood

with the aid of Volterra analysis.

III.3.2 Volterra Analysis

Usually, Volterra analysis assumes each nonlinear element in a circuit can be de-

scribed by a third-order, power-series expansion in which the series coefficients depend

42

only on the circuit’s bias point. Such analysis cannot be used to describe a highly nonlinear

circuit, such as a class-AB power amplifier. However, we will attempt to alleviate this prob-

lem by employing power-series expansions of order greater than three, and by allowing the

series coefficients to depend onboththe bias pointand the RF signal power.

Characterization of Ceff and ids

Defining an effective gate-source capacitanceCeff, and referring to Figs. III.1(a)

and III.1(b), the values ofCeff in the uncompensated and compensated cases are, respec-

tively, as follows:

Ceff = Cgbn + Cgsn (III.5)

and

Ceff = Cgbn + Cgsn+ Cgbp + Cgsp+ Cgdp. (III.6)

At each bias point, the RF signal power determines the range of excursion of the NMOS

gate-source voltage; for simplicity, this range can be approximated to be the peak-to-peak

excursion of the two-tone envelope (i.e., the envelope arising from the fundamental signal

components atω1 andω2, and neglecting the much smaller harmonic and intermodulation

components). With knowledge from SPECTRE of the behavior of the individual compo-

nents ofCeff versus this voltage,Ceff can then be modelled as a power series. We found that

a fifth-order power series would work well for all bias points and for all RF signal powers

43

considered,i.e., Ceff could always be written as follows:

Ceff = c1 + c2vgs + c3v2gs + c4v

3gs + c5v

4gs. (III.7)

It is important to emphasize that when the bias pointor RF signal power changes, the

coefficientsc1 throughc5 also change, such that the expansion in (III.7) always traces out

the appropriateCeff versusvgs curve.

The behavior of the large-signal, quasi-static, drain-source currentiDSN(vGS, vDS) for

the NMOS transistor as a function ofvGS andvDS can be simulated with SPECTRE, and

the results can be used to expand the corresponding signal currentidsn in Figs. III.1(a)

and III.1(b) as a power series. In performing the expansion, for simplicity, the dependence

on the drain-source voltage is first eliminated. Referring to Figs. III.3(a) and III.3(b), this

is done byapproximatingvDS to be a superposition of the dc bias and the purely linear part

of the output signal:

vDS ≈ VDD − gmvgsRO (III.8)

wheregm is the short-circuit transconductance, given bygm ≡ ∂iDSN/∂vGS with vDS ≡

VDD, andRO is the equivalent resistance (at the fundamental frequency) seen looking into

the output matching network from the NMOS drain. This approximation is usedsolely

for the purpose of simplifying the power-series expansion ofidsn; once the expansion is

established, the true nonlinear relationship between the drain and gate voltages will be

taken into account by the Volterra analysis. At each NMOS bias point(VGG, VDD), a given

RF signal power defines the range of excursion ofvgs, which is again approximated to be

the peak-to-peak excursion of the two-tone envelope, and for each such excursion, the locus

44

of points traced out byiDSN(VGG + vgs, VDD − gmvgsRO) can be used to find a power series

for idsn in terms ofvgs. In this case, we found a series of order three sufficed,i.e., idsn could

be written as follows:

idsn = g1vgs + g2v2gs + g3v

3gs (III.9)

where, as before, the coefficientsg1 throughg3 change withboththe bias pointand the RF

signal power, such that (III.9) always traces out the appropriateidsn versusvgs curve.

Figure III.8 shows the SPECTRE simulated and MATLAB fitted curves forCeff and

idsn as functions of the NMOS gate-source voltage. The fitted curves shown are for the gate

bias ofVGG = 0.8 V, and the input voltage amplitudevgs of 0.2 and 0.6 V, respectively. As

can be seen, the third-order current and fifth-order capacitance polynomials can fitidsn and

the compensatedCeff very well at all signal levels we are interested; for the uncompensated

Ceff, however, the fifth-order polynomial can fit well only at low power levels. This is not

surprising considering the strong nonlinear relationship between the uncompensatedCeff

and the NMOS gate-source voltage. It can be shown that a higher order polynomial will

yield a better fit but a much more complicated analysis. Thus, the choice of a fifth-order

polynomial fit for the capacitance is a compromise between accuracy and complexity.

Terminations at Sub- and Second Harmonics

In order to understand the impact of the matching-network impedances at the sub-

and second harmonics (∆ω and2ω) on the linearity of the amplifier, it is instructive to

derive the voltage responsevC of a nonlinear capacitor shown in Fig. III.9. From the

45

0 0.2 0.4 0.6 0.8 1 1.2 1.40

4

8

12

16

20

NMOS GATE−SOURCE VOLTAGE (V)

GA

TE

−S

OU

RC

E C

AP

AC

ITA

NC

E (

pF)

SPECTRE dataCurvefit (v

gs=0.2 V)

Curvefit (vgs

=0.6 V)

(a)

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6

0

0.2

0.4

0.6

NMOS GATE−SOURCE VOLTAGE (V)

DR

AIN

CU

RR

EN

T (

A)

SPECTRE dataCurvefit (v

gs=0.2 V)

Curvefit (vgs

=0.6 V)

(b)

Figure III.8: SPECTRE simulated and MATLAB fitted curves for (a)Ceff and (b)idsn asfunctions of the NMOS gate-source voltage. The fitted curves shown are for the gate biasof VGG = 0.8 V, and the input voltage amplitudevgs of 0.2 and 0.6 V, respectively.

46

i s Y s v C

i C

C

Figure III.9: Nonlinear capacitor circuit for Volterra analysis.

definition of capacitance,

C =dQ

dvC

=dQ

dt

dt

dvC

= iCdt

dvC

(III.10)

Substituting (III.7) into (III.10) and rearranging gives the current in the capacitor as

iC = c1dvC

dt+

c2

2

dv2C

dt+

c3

3

dv3C

dt. (III.11)

Here, for illustration purposes, only the first three terms in (III.7) were used. LetvC be

vC = H1(jωa) is + H2(jωa, jωb) i2s + H3(jωa, jωb, jωc) i3s. (III.12)

Applying KCL gives

is = vCYs + iC . (III.13)

Substituting (III.11) and (III.12) into (III.13) and equating the first-order terms gives

is = Ys(jωa)H1(jωa) is + jωac1H1(jωa) is. (III.14)

47

Rearranging (III.14) yields

H1(jωa) =1

jωac1 + Ys(jωa). (III.15)

The same procedure can be applied for the second and third order terms, and we obtain

H2(jωa, jωb) = − j(ωa + ωb)c2H1(jωa)H1(jωb)

2[j(ωa + ωb)c1 + Ys(jωa + jωb)]. (III.16)

and

H3(jωa, jωb, jωc) = − j(ωa + ωb + ωc)

3[j(ωa + ωb + ωc)c1 + Ys(jωa + jωb + jωc)]

×[c3H1(jωa)H1(jωb)H1(jωc) + 3c2H1(jωa)H2(jωb, jωc)] (III.17)

where

H1(jωa)H2(jωb, jωc) =1

3[H1(jωa)H2(jωb, jωc) + H1(jωb)H2(jωa, jωc)

+ H1(jωc)H2(jωa, jωb)]. (III.18)

The IM3 ofvC at2ω2 − ω1 is

IM 3 =3|H3(jω2, jω2,−jω1)|i2s

4|H1(jω1)| . (III.19)

Since the tone spacingω2−ω1 is generally much smaller thanω1 andω2, let∆ω = ω2−ω1

andω ≈ ω2 ≈ ω1. Then (III.17) reduces to

H3(jω2,jω2,−jω1) = − jω

3[jωc1 + Ys(jω)]

× [c3H21 (jω)H1(−jω) + c2(2H1(jω)H2(j∆ω) + H1(−jω)H2(j2ω))] (III.20)

48

where

H2(j∆ω) = − j∆ωc2|H1(jω)|22[j∆ωc1 + Ys(j∆ω)]

(III.21a)

H2(j2ω) = − j2ωc2H1(jω)2

2[j2ωc1 + Ys(j2ω)]. (III.21b)

Special attention should be paid to the terms in the second bracket of (III.20). The

first term comes from the intrinsic third-order nonlinearityc3; the second term comes

from the second-order nonlinearityc2, which yields third-order products by first gener-

ating second-order products and then mixing them with the fundamental signals. (III.21)

shows thatH2(j∆ω) andH2(j2ω) are greatly influenced by the source conductanceYs at

the sub- and second harmonic frequencies. For example,H2(j∆ω) andH2(j2ω) can be

set to zero by lettingYs(j∆ω) andYs(j2ω) be infinity, which is equivalent to shorting the

impedance at∆ω and2ω.

The same conclusions can be drawn for the simplified nonlinear model of the PA

output stage shown in Fig. III.10. Note that after compensation,Ceff can be approximated

as a linear capacitor, which has no second-order nonlinearity. However, the sub- and second

harmonics can still appear atvgs through theCgdn feedback.

The impact of out-of-band (in particular, the sub- and second-harmonic) impedances

on circuit’s linearity are also described in [25]–[27]. For weakly nonlinear circuits like

LNA, Volterra analysis can be applied to derive the output linearity as a function of the

out-of-band impedances, and it was shown that if the out-of-band terminations are properly

chosen, the circuit’s linearity can be improved dramatically [27]. However, this optimiza-

tion technique is not applicable for strong nonlinear circuits such as class-AB PAs, because

49

i dsn

C gdn

C eff Z I Z L C dsn i ds1 v gs

Figure III.10: Simplified nonlinear model of the PA output stage.

the strong nonlinearity sources associated with the class-AB operation do not generally

have constant second and third order coefficients for the entire signal range, as exempli-

fied in Fig. III.5. Optimizing the linearity at one signal level could worsen the linearity at

other signal levels. In addition, varying the input second harmonic of a strong nonlinear

source can also influence the generation of its intrinsic third-order term, thus making the

optimization untractable.

However, leaving the out-of-band impedances unattended is not a good strategy ei-

ther. Our calculations and simulations for the PA output stage show that while the sub-

harmonic impedances of the initially designed input and output matching networks have

slight effects on the load linearity, the second-harmonic impedance of the output match-

ing network can deteriorate the load IM3 4 − 5 dB for a wide signal range. Thus, on-chip

second-harmonic short circuits are included in the final amplifier.

50

IM 3 Calculation

With the power series in (III.7) and (III.9) established and the out-of-band short cir-

cuitry applied, the circuit for the Volterra calculation, based on the “method of nonlinear

currents” [23, pp. 190-207], is shown in Fig. III.11. Here,ZI represents the impedance

gdnC

Z I Ceff, g v ZO 2ω − ω 1 2 1 gs, 2ω − ω 1 2 2ω − ω 1 2gs, 2ω − ω 1 2v

+

−

c1~ ~

dsn,~ ~

Figure III.11: Circuit for the Volterra calculation.

seen looking into the input matching network from the NMOS gate, andZO represents the

impedance seen looking into the output matching network from the NMOS drain. SinceZI

presents a short circuit at even-order frequencies (see Section III.2), the distortion currents

generated byidsn andCeff have the following phasor amplitudes:

ıdsn,2ω1−ω2 =3

4g3v

2gs,ω1

v∗gs,ω2(III.22)

and

ıCeff,2ω1−ω2 = j(2ω1 − ω2)

[1

4c3v

2gs,ω1

v∗gs,ω2+

1

8c5

(2v3

gs,ω1v∗gs,ω1

v∗gs,ω2+ 3v2

gs,ω1vgs,ω2 v

∗ 2gs,ω2

)]

(III.23)

wherevgs,ω1 and vgs,ω2 are the phasor amplitudes of the gate-source voltage at the funda-

mental frequencies, and “∗” denotes complex conjugation. The distortion voltages that

51

result at the gate and drain can then be computed using the circuit of Fig. III.11:

vgs,2ω1−ω2 = −Z ′Iıdsn,2ω1−ω2 [j(2ω1 − ω2)CgdnZO] + ıCeff,2ω1−ω2 [1 + j(2ω1 − ω2)CgdnZO]

1 + j(2ω1 − ω2)Cgdn(Z ′I + ZO + g1Z ′

IZO)

(III.24)

vds,2ω1−ω2 = −ZOıdsn,2ω1−ω2 [1 + j(2ω1 − ω2)CgdnZ′I ]− ıCeff,2ω1−ω2 [g1 − j(2ω1 − ω2)Cgdn]Z

′I

1 + j(2ω1 − ω2)Cgdn(Z ′I + ZO + g1Z ′

IZO)

(III.25)

whereZ ′I ≡ ZI ‖ c1, and the impedancesZ ′

I andZO should be evaluated at the intermod-

ulation frequency2ω1 − ω2. The drain voltage at the fundamental frequency is also easily

found to be

vds,ω1 =−g1ZO + jω1CgdnZO

1 + jω1CgdnZO

vgs,ω1 (III.26)

where, in this case,ZO should be evaluated at the fundamental frequencyω1. The IM3 at

the gate and drain are then simply

IM3G = 20 log

∣∣∣∣vgs,2ω1−ω2

vgs,ω1

∣∣∣∣ (III.27)

and

IM3D = 20 log

∣∣∣∣vds,2ω1−ω2

vds,ω1

∣∣∣∣. (III.28)

IM 3 Contributions from Ceff and ids

Superimposed on the SPECTRE simulation results in Figs. III.4 and III.5 are values

for the gate and drain IM3 found from (III.22)–(III.28), withvgs,ω1 ≈ vgs,ω2 obtained from

the terminal gate-source voltage of the NMOS device in SPECTRE. As shown, the Volterra

52

expressions are able to predict the main trends in IM3 as a function of both bias and power

level. Of course, since the power-series coefficients in (III.7) and (III.9), and the values of

vgs,ω1 ≈ vgs,ω2, were all found from SPECTRE, this agreement may not be too surprising.

However, the real utility of the Volterra expressions lies in their ability to isolate the impact

of the individual nonlinearities.

Figure III.12 shows the contributions to the drain IM3 arising from theCeff andidsn

nonlinearities, as computed from (III.25), (III.26), and (III.28). The contribution fromCeff

is found by settingıdsn,2ω1−ω2 ≡ 0 in the expressions, and the contribution fromidsn is

found by settingıCeff,2ω1−ω2 ≡ 0. TheCeff contributions are shown for both the basic and

linearized amplifiers; theidsn contributions do not change, so only one curve is shown.

As illustrated, in the basic amplifier, theCeff nonlinearity limits the drain IM3 over

most power levels; only at very high power levels does theidsn nonlinearity become im-

portant, which is simply a result of increased clipping in class-AB mode. On the other

hand, in the linearized amplifier, the impact of theCeff nonlinearity is greatly reduced,

and correspondingly, except at high power levels where theidsn nonlinearity dominates, the

compensation scheme leads to the improved performance originally seen in Fig. III.5. Sim-

ilar analysis could be undertaken and comments made for the gate IM3 in Fig. III.4. (Again,

there is no improvement at very high power levels due to theidsn nonlinearity, which can

impact the gate IM3 by way of feedback throughCgdn.)

53

0 10 20 30

−80

−60

−40

−20

0 10 20 30

−80

−60

−40

−20

0 10 20 30

−80

−60

−40

−20

0 10 20 30

−80

−60

−40

−20

OUTPUT POWER (dBm) OUTPUT POWER (dBm)

OUTPUT POWER (dBm) OUTPUT POWER (dBm)

GGV = 0.75V GGV = 0.80V

GGV = 0.90VGGV = 0.85V

IM3

CO

NT

RIB

UT

ION

(dB

c)

IM3

CO

NT

RIB

UT

ION

(dB

c)IM

3 C

ON

TR

IBU

TIO

N (

dBc)

IM3

CO

NT

RIB

UT

ION

(dB

c)

dsni(basic)

effC

(linearized)effC

(linearized)effC

(basic)effC

dsni

(linearized)effC

dsni(basic)

effC

(linearized)effC

dsni(basic)effC

Figure III.12: Calculated contributions to the drain IM3 from theCeff andidsnnonlinearitiesfor both the basic and linearized amplifiers in Figs. III.3(a) and III.3(b), respectively. Thevalues are computed from the Volterra expressions (III.22)–(III.28), as described in the text.

54

III.4 Schematic Design

The PA schematic design involves many considerations and tradeoffs among cost,

ease of integration, and performances. In our design, a single-ended, two-stage configu-

ration was employed. The benefit of a single-ended topology is that it avoids the use of

baluns, thus making the PA more cost-effective and easier to integrate. Meanwhile, the

two-stage design enables us to achieve a power gain higher than 20 dB. Figure III.13 shows

the simplified block diagram of the designed two-stage CMOS class-AB power amplifiers.

V DD

M 1

RF

choke

V s

R s

Driver stage

V GG1

V DD

M 0

RF

choke

V GG0

Input

matching

network

Interstage

matching

network

Output

matching

network R 50

Output stage

M p

V PP

Figure III.13: Simplified block diagram of designed two-stage CMOS class-AB poweramplifiers.

This section will begin with the design of the output and driver stages. Then the

influence of out-of-band impedances on the amplifier linearity will be discussed, followed

by the study of the impact of ground connections on the amplifier gain and stability. Fi-

nally, the schematic of a fully matched two-stage CMOS class-AB power amplifier will be

55

presented.

III.4.1 Output Stage

Circuit Topology

A cascode topology is commonly used in analog and RF circuits since it provides

high gain and good reverse isolation. For PA applications, it also relaxes the breakdown

voltage concerns for each individual transistor. However, two disadvantages associated

with the cascode structure make it less attractive for RF linear power amplifier applica-

tions. First, the cascode structure limits the maximum drain voltage swing of the output

device, thus significantly degrading the drain efficiency. Second, due to the introduction

of another nonlinear device, the cascode power amplifier will generally exhibit worse lin-

earity than its single-transistor counterpart. It is also worth mentioning that the inclusion

of an extra transistor greatly complicates the circuit analysis at high frequencies where all

the transistor parasitics need to be taken into account. Thus, a single-transistor, common-

source configuration is chosen, as shown in Figure III.14 (a).

Choice of Load Impedance

Figure III.15 shows the load line of the output stage. For linearity considerations, the

transistor is only operated in saturation and cut-off regions. The load-line theory requires

the following equation to be met

RL =v2

ds0

2Pout(III.29)

56

v out

v g0

v d0

V DD

M 0

V GG0

Output matching

network R 50

M p

V PP

Z L

(a)

v gs0 g m0eqv R ds0

v g0

Output

matching network

R 50 C d0tot

v d0

R L

v out

C g0tot

(b)

Figure III.14: Output stage. (a) Schematic. (b) Simplified linear model for first-orderanalysis. The Miller effects ofCgd0 are included inCg0tot andCd0tot.

Saturation Region I D

V DD V d0min V DS

V GG

V g0max

Figure III.15: Load line of the output stage.

57

wherePout is the output power delivered to the load andvds0 is the amplitude of the drain-

source voltage signal.vds0 is related with the supply voltageVDD by

vds0 = VDD − Vds0min. (III.30)

Here,Vds0min is the minimum drain voltage. SinceVds0min is on the boundary between the

triode and saturation region, as shown in Fig. III.15, we have

Vds0min = Vgs0max− VTn

= VGG0− VTn + vgs0 (III.31)

whereVGG0 is the gate bias voltage andvgs0 is the amplitude of the gate voltage signal.

Substituting (III.31) and (III.30) into (III.29) gives

RL =(VDD − (VGG0− VTn)− vgs0))

2

2Pout. (III.32)

In the actual design,Vds0min is chosen to be slightly larger than (III.31) to include a

small margin voltage∆Vm. In other words,

Vds0min = VGG0− VTn + vgs0+ ∆Vm. (III.33)

Thus, the final expression forRL is

RL =(VDD − vgs0−∆V )2

2Pout(III.34)

where

∆V = VGG0− VTn + ∆Vm. (III.35)

58

Choice of Device Width

It can be shown as follows that the choice of device width,W0, is equivalent to the

choice ofvgs0. As illustrated in Fig. III.14 (b), the equivalent transconductance of the output

stage is defined as

gm0eqv =vds0

vgs0RL

. (III.36)

Here,Rds0 is much larger thanRL, thus ignored. For a general class-AB operation,gm0eqv is

a complicated function of the gate bias,VGG0, and the signal amplitude,vgs0; but for an ideal

class-B operation, as illustrated in Fig. III.16 (a),gm0eqv is one half of the transconductance

because the signal conducts exactly a half period. Thus, we have

gm0eqv =gm0

2. (III.37)

V GS

V T

0

v gs

I d

(a)

V GS 0

v gs

I d

V GG

(b)

Figure III.16: Plots ofId versusVGS for (a) an ideal class-B operation, and (b) a short-channel device biased near the threshold voltage.

59

For hand calculation purposes, the short-channel device that is biased near the thresh-

old voltage can be approximately treated as the ideal class-B case, as shown in Fig. III.16 (b).

When the gate voltage signal is large enough, the carrier velocity is saturated and the

transconductance of a short-channel MOS device is

gm0 = W0Coxvscl (III.38)

whereW0 is the device width,Cox is the oxide capacitance per unit area, andvscl is a

constant called the scattering-limited velocity [3]. Substituting (III.36) and (III.38) into

(III.37) and rearranging gives

W0 =2vds0

Coxvsclvgs0RL

. (III.39)

Substituting (III.34) into (III.39), we have

W0 =4Pout

Coxvsclvgs0(VDD − vgs0−∆V )(III.40)

Here,Cox andvscl are constants;Pout andVDD are fixed by the design specifications;∆V is

a function ofVGG0 and defined in (III.35). Thus, (III.40) shows that if the gate biasVGG0 is

fixed, W0 is only a function ofvgs0, proving our claim that the choice ofW0 is equivalent

to the choice ofvgs0.

It is worth mentioning that (III.40) is highly simplified and only for hand calculations.

The actual design should take all non-ideal effects into account and use simulations for final

verifications.

The choice ofvgs0 (or W0) involves a variety of tradeoffs. With respect to linearity,

small vgs0 is preferred because the third-order nonlinearity is proportional to the cube of

60

input signal amplitude. But as shown in (III.40), smallvgs0 corresponds to a large device

width, which causes the increase of all the device parasitics, thus making the design of the

matching networks more challenging. Largevgs0 can alleviate the parasitic problems, but

will deteriorate the linearity. In our design, we found that the choice of avgs0 of 0.6 V and

device width of 6 mm is a good compromise among all these tradeoffs.

On-chip Output Matching Network

The lack of high Q inductors is a major limitation in the design of an on-chip match-

ing network. It is illustrative to first derive the power loss of a simple L-match network

with respect to the finite inductor quality factor,QL. Figure III.17 shows the schematic and

equivalent circuit of a simple on-chip, high-pass, L-match network, whereRLs models the

parasitic resistance of the on-chip inductor. The goal of the matching network is to match

Rp to Rs.

Let Qt represent the total Q of the network, and assumingQ2t À 1, we have

Q2t =

Rp‖RLp

Rs

=1(

1

Rp

+1

QLωL

)Rs

=1(

1

Q2t0

+1

QLQt

) (III.41)

whereQt0 is the total Q of the network when the inductor is lossless,i.e.,

Qt0 = Qt|QL→∞ =

√Rp

Rs

. (III.42)

61

R s

C

L

R Ls

R p

(a)

R s

C

L R p R Lp

(b)

Figure III.17: High-pass, L-match network. (a) Schematic. (b) Equivalent circuit.

62

Rearranging and solving (III.41) gives

Qt =−Q2

t0 +√

Q4t0 + 4Q2

LQ2t0

2QL

. (III.43)

AssumingQt0 ¿ 2QL, (III.43) is then simplified to

Qt ≈ Qt0

(1− Qt0

2QL

). (III.44)

Defineηloss as the ratio of the power dissipated in the on-chip inductor to the power

delivered toRp, i.e.,

ηloss =Rp

RLp=

Rp

QLωL=

Rp

QLQtRs

=Q2

t0

QLQt

. (III.45)

Substituting (III.44) into (III.45) gives

ηloss =Qt0

QL

(1− Qt0

2QL

) ≈ Qt0

QL

(1 +

Qt0

2QL

). (III.46)

Again, we assumeQt0 ¿ 2QL. For a matching network ofQt0 = 3 andQL of 10, (III.46)

gives 0.35, which implies that the power loss in the on-chip inductor is approximately 35 %

of the power dissipated at the load. The same conclusion can be obtained for a low-pass,

L-match network as well.

Note that if two matching networks are cascaded together, as shown in Fig. III.18,

the total power loss ratio is

ηloss, cascade=PL1 + PL2

PRp≈ PL1

PRi+

PL2

PRp= ηloss, 1+ ηloss, 2 (III.47)

Here, we assume thatPRi ≈ PRp, andQ2t0,1 andQ2

t0,1 are much larger than one. The total

Qt0 for a cascade structure is

Qt0 =

√Rp

Rs

=

√Rp

Ri

√Ri

Rs

= Qt0,1Qt0,2. (III.48)

63

R s R p R i

Lossy

L-match

network

1

Lossy

L-match

network

2

Figure III.18: Cascade of two lossy L-match networks.

Substituting (III.48) into (III.47) and rearranging gives

ηloss, cascade=1

QL

(Qt0,1 +

Qt0

Qt0,1

)+

1

2Q2L

(Q2

t0,1 +Q2

t0

Q2t0,1

). (III.49)

(III.49) implies that the total power loss is minimized when

Qt0,1 = Qt0,2 =√

Qt0 (III.50)

and the resulting minimum total power loss ratio of a cascaded structure is

min(ηloss, cascade) =2√

Qt0

QL

(1 +

√Qt0

2QL

). (III.51)

The same approach can be applied to a cascade structure of more than two matching net-

works, and the same conclusion can be drawn, as long as theQ2t0 for each stage is much

larger than one. Comparing (III.51) with (III.46), we conclude that a cascade structure of

two on-chip matching networks can reduce the total inductor loss when the totalQt0 is

larger than four.

Let us return to the design of output matching network. The output impedance of

M0 is approximatelyRds0 in parallel withCd0tot, as shown in Fig. III.14 (b). The output

64

R 50 C d0tot

R L

(a)

R 50 C d0tot

R L

(b)

R L L

0

R L0s

C 0

C b0 R Lo1s L o1

R 50 C o2 C d0tot

(c)

Figure III.19: Output matching networks. (a) High-pass L-match. (b) Low-pass L-match.(c) Actual implementation.

65

matching network is required to match 50Ω to an impedance ofRL in parallel with an

inductive impedance (to cancelCd0tot). In this case,RL = 8 Ω andCd0tot = 9.6 pF, so the

load impedance to be matched isRL‖(− 1sCd0tot

), which results4.3 + 4j.

Since the totalQt0 of the output matching network is less than 4, there is no benefits

to cascade more than one L-match networks. If the on-chip inductors have a constantQL of

10, the matching topologies in Fig. III.19 (a) and (b) yield power loss ratios (with respect

to the load power) of 38 % and 56 %, respectively, which are close to the 38 % predicted

by (III.46). The final output matching network is chosen as Fig. III.19 (c), whereLo1 and

Co1 match 50Ω to 8 Ω, andL0 andC0 cancelsCd0tot. The power and efficiency loss ratio

associated with this matching network is approximately 36 %, slightly better than the 38 %

of the matching network in Fig. III.19 (a).

III.4.2 Driver Stage

Roles of Driver Stage

In a linear two-stage PA shown in Fig. III.13, the driver stage plays two roles. First,

it provides a linear voltage drive with the desired signal magnitude to the output stage.

Second, it exhibits an input impedance of 50Ω to the signal source. The first role of the

driver stage is very crucial for not only the gain but also the linearity of the power ampli-

fier. This can be seen as follows: assuming that, for some reasons (e.g., mismatch in the

interstage matching network), the driver stage can not provide enough signal to the output

stage, thenM1 has to be overdriven to reach the desired signal magnitude. Consequently,

66

this overdrive can enforceM1 into nonlinear regions and degrade the linearity of the PA.

Design of Interstage Matching Network

The input impedance exhibited by the output stage can be approximately modelled

as a small resistor in series with a large capacitor, as shown in Fig. III.20 (a), whereRg0tot

models the total parasitic gate resistance andCg0tot models the total gate capacitance, which

includes the PMOS gate capacitance and the Miller capacitance contributed byCgd0. The

output impedance of the driver stage is modelled as the channel-length-modulation resis-

tance,Rds1, in parallel with the total drain capacitance,Cd1tot. According to the maximum

power transfer theorem, the input impedance of the output stage should be matched to the

complex conjugate of the output impedance of the drive stage to achieve a maximum power

dissipation atRg0, thus the largest voltage swing atCg0tot. However, this theorem is estab-

lished based on the assumption that the matching network is lossless, which is not valid for

on-chip matching. In fact, the loss of on-chip inductors is a major limitation in designing

an on-chip interstage matching network.

Since on-chip inductors occupy a large amount of chip area3, the minimum number

of inductors is preferred; in this case, only one inductor is employed. It can be shown that

the inductor should be connected in a parallel configuration, as shown in Fig. III.20 (a),

whereCb1 is a “dc” blocking capacitor for separating the gate bias of the output stage from

the drain bias of the driver stage.

3The SiGe5AM design guide recommends a minimum distance of 80µm between any on-chip inductorsand adjacent conductors, thus a large amount of chip area is consumed.

67

R g0tot

C g0tot C d1tot R ds1 g m1 v gs1

Lossy interstage

matching network

C b1

L 1

R L1s

Output stage Driver stage

(a)

C tot R ds1 g m1 v gs1

L 1 Q C R g0tot R L1p

2

(b)

Figure III.20: Interstage matching network. (a) Circuit implementation. (b) Equivalentmodel. Here,Cd1tot is ignored, andCtot represents the total capacitance ofCb1 in series withCg0tot.

68

Our goal is to find the optimum values ofL1 andCb1 to achieve the maximum power

transfer toRg0tot under the constraint of a finiteQL of L1. Let Ctot represent the total

capacitance ofCb1 in series withCg0tot,

Ctot =

(1

Cb1+

1

Cg0tot

)−1

(III.52)

andQC be the quality factors ofCtot, i.e.,

QC =1

ωRg0totCtot. (III.53)

Assuming thatQL andQC are much larger than one andCd1tot is much smaller thanCg0tot,

thus ignored, Fig. III.20 (a) can then be simplified to (b), where

RL1p = QLωL1. (III.54)

The power transferred toRg0tot is

PRg0tot =g2

m1v2gs1∣∣∣∣

(1

Rds1+

1

QLωL1

+1

Q2CRg0tot

)+ j

(1

QCRg0tot− 1

ωL1

)∣∣∣∣2

Q2CRg0tot

. (III.55)

To minimize the denominator of (III.55), we first partially differentiate it with respect to

L1, it can be shown thatL1 should approximately satisfy

L1 ≈ QCRg0tot

ω. (III.56)

Thus, (III.55) reduces to

PRg0tot =g2

m1v2gs1∣∣∣∣

QC

Rds1+

1

QLRg0tot+

1

QCRg0tot

∣∣∣∣2

Rg0tot

. (III.57)

69

Then let the derivative of the denominator in (III.55) with respect toQC be zero, the opti-

mumQC is calculated as

QC =

√Rds1

Rg0tot. (III.58)

Note that (III.58) gives us the same conclusion as in the lossless matching case.Cb1 and

L1 can then be calculated from (III.53) and (III.56), respectively.

If Cd1tot is not ignored, it can be shown that (III.53) and (III.56) will be changed to

L1 ≈ QCRg0tot

ω(1 + QCRg0totωCd1tot)(III.59)

QC =

√√√√√1

Rg0tot

(1

Rds1+

ωCd1tot

QL

) (III.60)

The estimated model parameters of the driver and output stages are shown in Ta-

ble III.1, whereM1 is biased atVGG1 = 0.9 V and has a width of 3 mm. IfQL is 15,

(III.59) and (III.60) givesL1 = 0.26 nH andCb1 = 300 pF. Due to the parasitic inductance

of large on-chip capacitors, at 1.95 GHz, the maximum allowable on-chip capacitor (50 pF

calculated by size) exhibits the same impedance as an ideal 200 pF, thus used forCb1. L1

is implemented using a microstrip line, which does provide a Q of 15.

Driver stage Output stagegm1 (Ω−1) Rds1 (Ω) Cd1tot (pF) Rg0tot (Ω) Cg0tot (pF)

0.28 76 4.2 0.25 22.6

Table III.1: Estimated model parameters of driver and output stages.

70

III.4.3 Strategy for Ground Connections

Figure III.21 shows the simplified schematic and linear model of a two-stage CMOS

class-AB power amplifier. In the initial design phases, all the ground nodes (A, B, C, D,s1,

ands0) of the PA are assumed to be ideal ground. In practice, however, these nodes have

to be connected through bonding wires to an external ground (e.g., the bottom plane of a

two-layer printed circuit board). Although bonding wires exhibit only nanohenry induc-

tances, they can significantly influence the gain and stability of a power amplifier at radio

frequencies, as shown later in this section. Thus, a good strategy for ground connections is

crucial.

Impact on Gain

It is illustrative to examine the impact of the ground bondwire inductor on the gain of

output stage in Fig. III.21. When biased atVGG0 = 0.85 V, M0 has the estimated device pa-

rameters ofgm0 = 0.43, Rg0tot = 0.25, Cg0tot = 22.6 pF, andCd0tot = 9.6 pF. At 1.95 GHz,

the transconductance and input and output impedances ofM0 are

gm0 = 0.43 (III.61a)

zg0 = Rg0 +1

jωCg0= 0.25− 3.7 ∗ j (III.61b)

zd0 =1

jωCd0tot= −8.5 ∗ j. (III.61c)

As implied in [3], the bondwire inductorLs0 at the source node ofM0 behaves as a series-

series feedback. AssumingLs0 is 0.1 nH and ignoring the effect ofCgd0, theLs0 feedback

71

M 1

L 1

C f1

R f1

L s1

RF

choke

On-chip 2f termination

C 1

V in

C i1

L i1

s 1

A

B

R b1

V GG1

C b1

V DD

M 0

M p

R b0

On-chip

2f termination

C dc

Compensation

circuitry

V PP

RF

choke

L s0

V GG0

s 0

L 0

C 0

C b0 L o1

V out

C o1

C D

V DD

C b2

(a)

On-chip

2f termination

L 0

C 0

C b0 L o1 V out

C o1

C D

L 1

C 1

C b1

L s1

s 1

C gd1

C gs1 C ds1

L s0

s 0

C gd0

C gs0 C ds0

B

On-chip

2f termination

V in

C i1

L i1 C b2

A

R f1 C f1

R s R L

(b)

Figure III.21: Two-stage CMOS class-AB power amplifier for illustrating ground con-nections. Part (a) shows the schematic, and part (b) shows the simplified linear model.Here, the bias resistance and channel-length-modulation resistances of the transistors arenot shown.

72

transforms the transconductance and input and output impedances to

g′m0 ≈ gm0

1 + gm0 ∗ jωLs0= 0.34− 0.18 ∗ j (III.62a)

z′g0 ≈ zg0(1 + gm0 ∗ jωLs0) = 2.2− 3.5 ∗ j (III.62b)

z′d0 ≈ zd0(1 + gm0 ∗ jωLs0) = 4.5− 8.4 ∗ j. (III.62c)

Here, the prime represents the feedback operation.

Special attentions need to be paid to the increased real parts of both the input and

output impedances in (III.62). As described in the design of driver and output stages, the

real parts ofzg0 andzd0 play crucial roles in the interstage and output matching networks

and should be minimized to avoid significant gain and efficiency losses. Thus, (III.62)

implies huge losses in the matching networks even the ground bondwire inductance is as

small as 0.1 nH. The same conclusions can be drawn for the driver stage as well.

To alleviate this problem, we can connect all the critical ground nodes internally be-

fore connecting them to the external ground, as shown in Fig. III.22 (a). The benefit of this

connection is that the internal matching networks are less affected by the ground impedance

since they share the same internal “ground” node. Fig. III.23 shows the simulated power

gain of the two-stage CMOS class-AB PA versus the total ground bondwire inductance for

the two ground configurations shown in Fig. III.22 (a) and (b), respectively. As can be seen,

connecting the ground nodes internally can make the gain of the PA much more tolerant to

the ground bondwire inductance.

It is worth mentioning that 0.1 nH is a reasonable estimation for ground bondwire

inductance. Assuming 20 bonding wires are equally used for the grounding ats1 ands0 in

73

M 1

L 1

C f1

R f1

RF

choke

On-chip 2f termination

C 1

V in

C i1

L i1

R b1

V GG1

C b1

V DD

M 0

M p

R b0

On-chip

2f termination

C dc

Compensation

circuitry

V PP

RF

choke

L s0

V GG0

s 0

L 0

C 0

C b0 L o1

V out

C o1

V DD

C b2

(a)

M 1

L 1

C f1

R f1

L s1

RF

choke

On-chip 2f termination

C 1

V in

C i1

L i1

s 1

R b1

V GG1

C b1

V DD

M 0

M p

R b0

On-chip

2f termination

C dc

Compensation

circuitry

V PP

RF

choke

L s0

V GG0

s 0

L 0

C 0

C b0 L o1

V out

C o1

V DD

C b2

(b)

Figure III.22: Two-stage CMOS class-AB PAs for illustrating the impact of ground con-nections on gain. (a) Ground nodes are connected internally together. (b) Ground nodesare connected separately.

74

0 0.05 0.1 0.15 0.20

5

10

15

20

25

30

TOTAL GROUND BONDWIRE INDUCTANCE (nH)

PO

WE

R G

AIN

(dB

)

Ground configuration (a)Ground configuration (b)

Figure III.23: Power gain of the two-stage CMOS class-AB power amplifiers versus totalground bondwire inductance for the two ground configurations shown in Fig. III.22 (a)and (b), respectively.

Fig. III.21 and each bonding wire is 0.5-1 nH, if mutual inductances among the bondwire

inductors are ignored, bothLs0 andLs1 will be 0.05-0.1 nH, which is consistent with our

0.1 nH estimation.

Impact on Stability

In addition to the impact on gain, ground connections also play an important role in

power amplifier stability. Two techniques gain their popularity in stability analysis. The

first is the root-locus technique, which involves calculation of the poles and zeros of the

amplifier and of their movement in thes plane as the low-frequency, loop-gain magnitude

is changed. This technique is widely used in analog circuit designs in solving feedback-

induced stability problems. At microwave frequencies, however, it is often difficult to

identify the feedback loops that cause the circuit to become unstable. Under this circum-

75

stance, the second technique – Stern stability factorK – is usually employed.K is defined

as

K =1 + |∆|2 − |S11| − |S22|2

2|S21||S12| (III.63)

where∆ = S11S22−S12S21. If K > 1 and∆ < 1, the circuit is unconditionally stable,i.e.,

it does not oscillate with any combination of source and load impedances as long as their

real parts are positive. However, a disadvantage of usingK factor is that theS parameters

of the circuit must be calculated (or measured) for a wide frequency range to ensure that

K remains greater than unity at all frequencies. Thus, a great deal of effort is involved,

and most importantly, little insight can be obtained. It is also worth noting thatK is a

pessimistic measure of stability since it allows arbitrary source and load impedances.

In our investigation of PA stability, the following criterion [28] is examined.If the

determinant of a linear network contains any zeros in the right half plane (RHP), the

network will be unstable, otherwise the network is stable.This criterion is equivalent

to the pole analysis of a linear network [28].

The ground configurations are divided into two categories: one-chip-ground and two-

chip-ground, as shown in Fig. III.24. The first is defined as the configurations wheres1 and

s0 are joined together before connecting to the external ground; the latter is defined as those

wheres1 ands0 are connected independently to the external ground. Table III.2 lists all the

possible ground configurations.

Since oscillations start from noise, the small-signal equivalent models in Fig. III.25

were used for the one-chip-ground and two-chip-ground configurations, respectively. Nodal

76

M 1

L 1

C f1

R f1

RF

choke

On-chip 2f termination

C 1

V in

C i1

L i1

A

B

R b1

V GG1

C b1

V DD

M 0

M p

R b0

On-chip

2f termination

C dc

Compensation

circuitry

V PP

RF

choke

L s0

V GG0

s 0

L 0

C 0

C b0 L o1

V out

C o1

C D

V DD

C b2

(a)

M 1

L 1

C f1

R f1

L s1

RF

choke

On-chip 2f termination

C 1

V in

C i1

L i1

s 1

A

B

R b1

V GG1

C b1

V DD

M 0

M p

R b0

On-chip

2f termination

C dc

Compensation

circuitry

V PP

RF

choke

L s0

V GG0

s 0

L 0

C 0

C b0 L o1

V out

C o1

C D

V DD

C b2

(b)

Figure III.24: Two-stage CMOS class-AB power amplifier for (a) one-chip-ground and (b)two-chip-ground configurations.

77

On-chip

2f termination

L 0

C 0

C b0 L o1 V out

C o1

C D

L 1

C 1

C b1 C gd1

C gs1 C ds1

C gd0

C gs0 C ds0

B

On-chip

2f termination

V in

C i1

L i1 C b2

A

R f1 C f1

R s R L

L s0

s 0

(a)

On-chip

2f termination

L 0

C 0

C b0 L o1 V out

C o1

C D

L 1

C 1

C b1

L s1

s 1

C gd1

C gs1 C ds1

L s0

s 0

C gd0

C gs0 C ds0

B

On-chip

2f termination

V in

C i1

L i1 C b2

A

R f1 C f1

R s R L

(b)

Figure III.25: Small-signal equivalent model of the two-stage CMOS class-AB power am-plifier for (a) one-chip-ground and (b) two-chip-ground configurations.

78

Ground One-chip-ground Two-chip-groundconfiguration configurations configurations

index A B C D A B C D

0 0 0 0 0 0 0 0 01 0 0 0 s0 0 0 0 s0

2 0 0 s0 0 0 0 s0 03 0 0 s0 s0 0 0 s0 s0

4 0 s0 0 0 0 s1 0 05 0 s0 0 s0 0 s1 0 s0

6 0 s0 s0 0 0 s1 s0 07 0 s0 s0 s0 0 s1 s0 s0

8 s0 0 0 0 s1 0 0 09 s0 0 0 s0 s1 0 0 s0

10 s0 0 s0 0 s1 0 s0 011 s0 0 s0 s0 s1 0 s0 s0

12 s0 s0 0 0 s1 s1 0 013 s0 s0 0 s0 s1 s1 0 s0

14 s0 s0 s0 0 s1 s1 s0 015 s0 s0 s0 s0 s1 s1 s0 s0

0 represents the external ground.

Table III.2: Ground configurations for the two-stage CMOS class-AB PAs in Fig. III.24.

79

analysis [28] was employed to calculate the determinant of each ground configuration in

Table III.2, and the resulting determinant is a high-order polynomial with coefficients ex-

pressed by the circuit parameters, including the total ground bondwire inductanceLstot. It

is apparent thatLstot is equal toLs0 for one-chip-ground configurations and12Ls0 for two-

chip-ground configurations if we letLs1 = Ls0. ThenLstot was swept from zero to 4 nH4

to find its maximum that is capable of keeping all the roots of the determinant polynomial

in the left half s plane. This value, as defined by the stability criterion, sets the upper

limit of the ground bondwire inductance to avoid oscillation. Figure III.26 shows the cal-

culated maximum stable ground bondwire inductance of the two-stage CMOS class-AB

PA for the ground configurations in Table III.2. As can be seen, the stability of the two-

stage power amplifier is strongly dependent on how the ground nodes were connected: one

unappropriate connection could make a stable PA oscillate. It is also shown that, for our

case, most of one-chip-ground configurations have better stability performance than their

two-chip-ground counterparts.

To verify our analysis, transient simulations based on the schematic in Fig. III.21 (a)

were carried out using SPECTRE. Again, for each ground configuration, the total ground

bondwire inductance was swept to find the value that began to make the transient wave-

forms unstable. Then it was recorded and compared with the value predicted by the calcu-

lation. Less than 10 % difference between the calculated and simulatedLstot were obtained

for all ground configurations, proving the validity of our analysis.

4The value of 4 nH is arbitrarily chosen. In fact, any value can be chosen as long as it is much larger thanthe typical ground bondwire inductance.

80

0 5 10 150

1

2

3

4

GROUND CONFIGURATION INDEX

MA

XIM

UM

ST

AB

LE IN

DU

CT

AN

CE

(nH

)

One chip groundTwo chip grounds

Figure III.26: Maximum stable ground bondwire inductance of the two-stage CMOS class-AB PA for the ground configurations in Table III.2. The plot does not show the data pointsexceeding4 nH.

III.4.4 Final PA Schematic

In order to make the gain and stability of the power amplifier less sensitive to the

ground bondwire inductance, our analysis in the previous section suggests that the ground

configurations with index numbers of 12 and 15 in Table III.2 should be used.

For comparison purposes, three PAs were fabricated: PA1 is the uncompensated and

fully integrated version, which means that all the matching (input, interstage, and output)

is on-chip; PA2 is also fully integrated but with the compensation circuitry applied; PA3

is the same as PA2 except that its output matching was off-chip. Figure III.27 shows the

schematic of the three PAs that were designed and implemented.

81

RFChoke

On−chip2f termination

On−chip2f termination

C

Ci1

b2 i1L

C

L1

VDD

RFChoke

VDD

b1

Rb0

VRb1

V

M1

M0

Vin

Rf1

Mp

Cdc

VPP

C

L

0

0

C L

C

b0 o1

o1

C1

s0

Vout

Cf1 On−chipinput matching

s0 Compensation circuitry(PA2 and PA3 only)

On−chip interstage matching

L

On−chip output matching(PA1 and PA2 only)

Equivalentbondwire inductance

GG1

GG0

Figure III.27: Schematic of the fully matched two-stage CMOS class-AB power amplifiers.

82

III.5 Layout Design

As CMOS circuits evolves to low-voltage, high-speed, high-complexity systems, it

is well recognized that layout could heavily influence and limit the circuits’ performance.

Crosstalk, parasitics, and substrate coupling are just a few examples of such issues that arise

from the layout design. Tradeoffs are usually necessary under these circumstances. For ex-

ample, increasing the width of an interconnection metal can reduce its parasitic resistance,

but will inevitably raise its crosstalks with other signal paths.

RF power amplifiers, especially those for medium or high power applications, require

special attentions in layout designs due to their involvements with both high frequencies

and large currents. First, layout parasitics, which are usually ignored at low frequencies,

can play important roles at high frequencies and significantly influence the PA performance.

Second, the widths of metals that flow large “dc” or/and “ac” currents should be carefully

determined to avoid current overloads. Finally, due to large voltage swings and low cou-

pling impedances, an integrated PA can inject large noise currents into the substrate and

corrupt adjacent circuit blocks, thus methods for reducing substrate coupling are necessary.

In this section, the IBM SiGe5AM technology is first briefly described, followed by

the key layout issues of basic transistor cells and on-chip inductors. Then the choices of

routing metals are discussed and the current handling capability of the critical components

is examined. Finally, methods for reducing substrate coupling are discussed and our strat-

egy for the substrate connections is presented.

83

III.5.1 IBM SiGe5AM Technology

The IBM SiGe5AM is a high-performance SiGe BiCMOS process. The CMOS part

is developed based on an existing high-yield, 0.5µm digital CMOS technology5, but in-

cludes analog components such as polysilicon resistors, metal-insulator-metal (mim) ca-

pacitors, and on-chip inductors. One characteristic of SiGe5AM technology is its thick

Analog Metal (AM) layer, which significantly improves the Q of on-chip inductors by re-

ducing the associated series resistances.

Table III.3 shows the properties of all metal layers provided by the IBM’s SiGe5AM

technology (4 metal option), wheretox represents the dielectric thicknesses between metal

layers and the substrate/N-well. As can be seen, AM layer has best parasitic and current-

handling performances.

Table III.3: Properties of metal layers in IBM SiGe5AM technology.

Metal layer Thickness Rsheeta tox Idc

b Irmsb

ID (µm) (Ω/¤) (µm) (mA) (mA)

M1 0.63 0.076 2.34 0.74×W√

51.2×W × (W + 1.6)

M2 0.85 0.045 4.17 1.23×W√

41.6×W × (W + 3.6)

MT 0.85 0.045 6.22 1.23×W√

41.6×W × (W + 3.6)

AM 4.00 0.00725 10.05 6.17×W√

69.0×W × (W + 10.9)a sheet resistances at25C.b current limits at100C.

III.5.2 Basic Transistor Cell

For power amplifier applications, power transistors have to be laid out to reduce

not only their parasitic resistances but also their parasitic capacitance at both gate and

5The details are described in the SiGe5AM design guide.

84

Gate

Source

Drain

Substrate

Polysilicon

M1 & M2

AM

Contact

Diffusion

Figure III.28: Layout (not scaled) of a basic transistor cell. The fingers are 20µm long.

drain nodes. Figure III.28 shows our layout of a basic transistor cell. First, the two ends

of gate fingers were connected together to reduce the gate resistance by a factor of four.

Second, M1 and M2 were combined to connect both drain and source not only to reduce

their parasitic resistances but also to increase their current handling capabilities. Third, the

substrate were connected to the source for each transistor cell, thus keeping the substrate

voltage equally distributed in the whole transistor. To reduce the parasitic resistance and

capacitance, both the gate and drain were routed through the top metal layer AM.

III.5.3 On-chip Inductor

The SiGe5AM design guide recommends all on-chip inductors be placed at least

80µm away from substrate contacts to avoid coupling of inductor energy into the substrate.

It is shown through measurements that large substrate contacts adjacent to an inductor

85

may result in a 10-15 % degradation of the inductor’s quality factor Q. The disadvantage

associated with this design rule is an enormous waste of chip area. Therefore, it is advised

that inductors should be used as little as possible during the initial design phase.

Since an on-chip inductor has a maximum width of 25µm, it should not be used for

passing through a large amount of current. The initial design should be carried out with

this in mind.

III.5.4 Current Handling Capability

Since a large amount of current flows through a power amplifier, and each metal layer

has a different current handling capability for a certain width, it is necessary to determine

which metal(s) is to be used for routing and its (their) minimum width(s). If chip area is

not a concern, the ground buses can be made as wide as possible since they contribute no

parasitic capacitances; the width of the signal paths, on the other hand, need to be properly

chosen for tradeoffs between parasitic shunt capacitance and parasitic series resistance. In

our design, the combination of M1 and M2 was used for all the ground routings, and AM

was chosen for most crucial signal paths. Table III.4 shows the comparison between the

maximum allowable layout currents and the corresponding maximum designed currents of

all critical components in PA2. Note that since every component has more than one node,

and each node is routed through multiple metal layers, the maximum allowable layout

currents were considered for all critical metal layers.

86

Table III.4: Comparison between maximum allowable layout currents and correspondingmaximum designed currents of all critical components in PA2.

Critical Layout Designcomponents Metal ID Metal width Idc Irms Idc Irms

(µm) (A) (A) (A) (A)

M1&M2 160 0.32 2.22DAM 75 0.46 0.67

0.26 0.45M0 G AM 40 N/A 0.37 N/A 0.09

S M1&M2 160 0.32 2.22 0.26 0.45MT 40 N/A 0.22

L0 AM 20 N/A 0.21N/A 0.19

MT 40 N/A 0.22Lo1 AM 20 N/A 0.21

N/A 0.18

MT 50 N/A 0.27Co1 AM 20 N/A 0.21

N/A 0.20

III.5.5 Substrate Coupling

In integrated implementations, a PA resides on the same substrate as other circuit

blocks (some of them may be very sensitive), as shown in Fig. III.29, whereM0 represents

the PA transistor. Due to large voltage swings at the drain node,M0 will inject a large

amount of current into the substrate via the drain-bulk capacitanceCdb0, thus corrupting

the adjacent sensitive circuit blocks.

Various methods, such as differential topology, ground shielding, guardrings, and

deep trench, were developed to reduce the substrate coupling. Among these approaches,

differential topology requires an off-chip balun, which makes the PA not only less cost-

effective but also more difficult to integrate. The ground shielding method reduces substrate

noise, but increases both parasitic capacitance and layout complexity; the latter is due to the

extra routing of the shielding planes. Therefore, only the last two methods were employed

87

V DD

V DD

M 0

M 2

M 1

Distributed

Substrate

Model

C db0

L b

PA

Sensitive

Circuits

L d0

(a)

p +

L d0

n + n +

M 0

n + n +

M 1

C db0 C db1

PA

Sensitive

Circuits

p substrate -

(b)

Figure III.29: Effect of substrate coupling. (a) Schematic modelling. (b) Sideview ofdevice layouts.

88

n + n +

M 0

n + n +

M 1

C db0 C db1

PA

Sensitive

Circuits

p substrate -

p + p + p +

Deep Trench

Blocks

L s0

Small

Bondwires Large Substrate

Guardrings

Figure III.30: Layout structure employing both large substrate guardrings and deep trenchblocks.

in our design. First, large areas of substrate guardrings were used to encompass all the

power transistors since they are the primary sources of substrate noise. Second, multiple

deep trench blocks were placed at the boundary of the power amplifier to further increase

the isolation between the PA and other circuit blocks. The layout structure employing these

two methods is illustrated in Fig. III.30.

III.5.6 Final PA layout

Figure III.31 shows the final layout of PA2. To be consistent, the components are

labelled using the same names as in Fig. III.27. Due to its small value (0.26 nH),L1 is

implemented using a microstrip line and modelled as a small inductor. To minimize ground

impedance, multiple ground pads were used.

89

Figure III.31: Final Layout of the fully integrated and compensated two-stage CMOS PA(PA2). The components are labelled using the same names as in Fig. III.27.

90

III.6 Experimental Results

This section begins with a detailed description of some important PA implementation

issues such as the choice of package and the design of off-chip matching networks. Then

the test setup for evaluating the PAs is presented. Finally, the measurement results are

shown and the PA performance is summarized.

III.6.1 Implementation Details

IC Implementation

Figures III.32 shows the die microphotograph of PA2. Including bonding pads, the

chip occupies an area of2.0 × 1.6 mm2.

Figure III.32: Die microphotograph of the fully integrated and compensated two-stageCMOS PA (PA2).

91

Package Choice

The Amkor MicroLeadFrame (MLF) package was chosen primarily for its enhanced

thermal and electrical characteristics. It is a plastic encapsulated and leadless package

where electrical contact to the PCB is made by soldering the lands on the bottom surface of

the package to the PCB. The enhanced thermal and electrical properties of the MLF pack-

age is achieved by incorporating an exposed die paddle on the bottom, which efficiently

conducts heat to the PCB and provides a stable ground through down bonds and electrical

connections through conductive die attach material. Figure III.33 shows the photograph

and cross section drawing of the MLF package.

(a) (b)

Figure III.33: MLF package (a) photograph and (b) cross section drawing.

There is a variety of options in choosing the size and lead numbers of the MLF

package. In order to relax the handling and soldering issues, the final package was chosen

to have a large profile of6× 6 mm2 and a total of 20 leads (5 on each side).

92

Printed Circuit Board Choice

The PA evaluation board utilizes a two-layer RO4350 with a dielectric constant of

3.48 and a dielectric thickness of 20 mil. In addition to good dimensional stability and low

processing and assembly costs, RO4350 provides excellent high-frequency performance

due to its low dielectric loss and stable electrical properties over frequency. The low thermal

coefficient of the dielectric constant of RO4350 also makes it suitable for PA applications.

Off-chip Matching Networks

Before discussing the details of the off-chip matching networks, a note should be

made regarding the interstage matching of the two-stage CMOS PAs. As described in

Sec III.4, the total gate capacitance of the output stage of compensated PAs is approxi-

mately 22.6 pF and at 1.95 GHz, the corresponding matching inductor is roughly 0.26nH.

To achieve a high Q, this small inductor was implemented using a long microstrip line,

as shown in Fig. III.31. Due to the long routing of this inductor line, the interconnection

yields a parasitic inductance of more than 0.05 nH, which shifts the resonating frequency

of the interstage LC matching network from 1.95 GHz to approximately 1.75 GHz. In or-

der to acquire the designed gain and efficiency performance, both off-chip input and output

matching networks were employed for all three PAs and the measurements were carried

out at 1.75 GHz instead of 1.95 GHz. However, this slight modification does not impact

our conclusions or the generality of our results.

The off-chip output matching network for PA3 was implemented using L-match

93

L bw TL 1 C 1 TL 2 TL 3

R 50 L 1

Z L

(a)

L bw TL 1

C 1 TL 2 TL 3

Z s

Z in C 2

(b)

Figure III.34: Hybrid off-chip matching network for PA3. (a) Output. (b) Input.

94

topology, as shown in Fig. III.34 (a). Here,Lbw models the output bondwire inductance,

TL1, TL2, and TL3 model the transmission line effects of the connection traces. Since

ZL is very small (approximately4 + 4j), any slight imperfections in the matching network

could influence the value ofZL and consequently degrade the gain and efficiency of the

output stage. It can be shown that, for the output matching network in Fig. III.34, the imag-

inary part ofZL is most sensitive to the variations of the matching components. Thus, it

is very desirable to design the matching network to be capable of continuously tuning the

imaginary part ofZL. If TL1 and TL2 is short enough, adjusting the length of TL1 or TL2

can achieve the continuous tuning of the imaginary part ofZL, while keeping the real part

of ZL approximately unchanged. Since changing the length of TL1 involves physically

cutting the TL1 trace, tuning the length of TL2 is preferable, and this is accomplished by

designing the impedances of TL2 and TL3 as 50Ω and slidingL1 along the trace of TL2

and TL3.

The values of the matching components were first calculated in MATHEMATICA and

further verified and tuned using Agilent ADS. Figure III.35 shows the ADS schematic and

simulatedZL of the output matching network for PA3. Due to the large size of the pack-

age, the output bonding wire has a length of more than 1.5 mm and exhibits approximately

1.8 nH.

Considering the uncertainty of the bondwire inductance and the variations of the ac-

tual values of chip capacitors and inductors, it is necessary to tune the output matching

networks in conjunction with the exhibited testing phenomena. Since the output matching

95

(a)

(b)

Figure III.35: Off-chip output matching network for PA3 in ADS. (a) Schematic. (b) Sim-ulatedZL.

96

is the load-line matching instead of maximum power matching, optimizing the gain (|s21|)

does not necessarily imply optimized load matching. To still achieve the optimum load

matching, the gain and dc current for various output power levels were observed and com-

pared with the SPECTRE simulations, and corresponding adjustments were made in the

output matching network until good agreement was obtained. Since we only need to tune

the value and position ofL1, few iterations were needed before the optimum output match

was achieved.

After the output matching network was implemented, the input matching network

can be designed by first measuring the input impedance and then matching it with any

matching structure. Figure III.34 (b) shows our input matching network for PA3. Again,

Lbw models the input bondwire inductance, TL1, TL2, and TL3 model the transmission

line effects of the connection traces.

The final application schematic is shown in Fig. III.36, where the 47µF capacitors at

VDD1 andVDD0 are for bypassing the ac signals to ground. This is very important not only

for stability considerations, but also for linearity concerns. As illustrated in Section III.3.2,

the out-of-band (the sub-harmonic frequencies, in this case) impedance can dramatically

impact the PA linearity. As expected, the measurements showed that the inclusion of these

two capacitors can significantly improve both linearity and stability of the PA. Any value

can be chosen for these two capacitors as long as they provide good “ac” short at the sub-

harmonic frequencies. The photograph of the PCB implementation of PA3 is shown in

Fig. III.37.

97

Bias

circuit

47uF

10nH 10nH

47uF

1.3pF 2.0pF

1.5nH

5.6nH

1.3pF

V GG1

V GG0

V B1

V B2

V PP

V DD1

V DD0

RF in RF out

MLF

Die

Figure III.36: Application schematic of PA3.

Figure III.37: Photograph of the PCB implementation of PA3.

98

III.6.2 Test Setup

The test setup for evaluating the PAs is shown in Fig. III.38. The grounds of all the

test equipments and the PA were connected together. Since all the matching networks have

been implemented on the PC board, the input was directly connected to an Agilent E4438C

vector signal generator, and the output was directly fed to an Agilent E4440A PSA series

spectrum analyzer. The input and output signals are connected via two 50Ω SMA RF

cables, each of which has a loss of 0.3 dB. Two Agilent 6612C DC power supplies were

used forVDD1 andVDD0 to monitor the independent current consumptions by the driver

and output stages. To obtain direct access to the bias voltages, all the biases were directly

connected to power supplies.

PA

HP E3610A

Power supplies

HP E3610A

...

...

V DD1

V DD0

Agilent E4440A

Spectrum analyzer

Agilent E4438C

Signal generator

Agilent 6612C

Agilent 6612C

Power supplies

Figure III.38: Test setup for evaluating the PAs. The ground connections of the test equip-ments and the PA are not shown.

99

III.6.3 Measurement Results

The power amplifiers were operated at aVDD of 3.3 V and drew a total quiescent

current of 97 mA (46 mA for the driver stage and 51 mA for the output stage) when the

output stages were biased at 0.8 V.

Gain and Efficiency

Figure III.39 shows the measured gain and power-added efficiency (PAE) of the three

PAs. As can be seen, the uncompensated and fully integrated PA (PA1) achieves a small-

signal gain of 24.3 dB and a peak PAE of 23 % at the designed output power of 24 dBm.

PA2 achieves similar PAE performance but with a gain of 3 dB lower than PA1. PA3 has

better gain and efficiency performance than PA2 because of the low-loss, off-chip output

matching. It achieves a small-signal gain of 23.9 dB and a PAE of 29 % at the output power

of 24 dBm.

−5 0 5 10 15 20 25 300

5

10

15

20

25

30

35

OUTPUT POWER (dBm)

GA

IN (

dB)

PA1PA2PA3

−5 0 5 10 15 20 25 300

5

10

15

20

25

30

35

OUTPUT POWER (dBm)

PA

E (

%)

Figure III.39: Measured gain and power-added efficiency versus output power of the threePAs. The output stages of the PAs are all biased at0.8 V.

100

The measured results were compared with those from SPECTRE simulations and

good agreement was obtained. Figure III.40 shows the simulate and measured gain and

power-added efficiency (PAE) for for the three PAs.

Linearity

To verify their linearity performances, the PAs were tested under various bias and

power levels using both two-tone and WCDMA signals. Figures III.41 show the mea-

sured third-order intermodulation, adjacent-channel leakage power (ACP1), and alternate-

channel power (ACP2) for the three PAs. As can be seen, the compensated PAs (PA2 and

PA3) have much better linearity than the uncompensated PA (PA1) for various gate biases

and a wide range of output power; in addition, the IM3 measurements show similar trends

as those shown in Fig. III.5 of Section III.2 C.

PA3 achieves an ACP1 of -35 dBc and ACP2 of -55 dBc at a carrier output power of

24 dBm, which is compliant with the 3GPP-WCDMA ACP requirements of -33 dBc and

-43 dBc [29], respectively. Due to the loss of on-chip output matching, PA1 and PA2 can

only meet the WCDMA ACP requirements at output powers of 22 and 23 dBm, respec-

tively. Figure III.42 shows the measured WCDMA spectra of PA1 and PA2 at a carrier

output power of nearly 20 dBm.

It is worth mentioning that all the bias voltages utilized in our measurements are

almost exactly the designed values; in addition, no oscillation was observed during the

entire measurement procedure, even when both the source and load were disconnected.

101

−5 0 5 10 15 20 25 300

5

10

15

20

25

30

35

40

OUTPUT POWER (dBm)G

AIN

(dB

)

SimulationMeasurement

−5 0 5 10 15 20 25 300

5

10

15

20

25

30

35

40

OUTPUT POWER (dBm)

PA

E (

%)

(a)

−5 0 5 10 15 20 25 300

5

10

15

20

25

30

35

40

OUTPUT POWER (dBm)

GA

IN (

dB)

SimulationMeasurement

−5 0 5 10 15 20 25 300

5

10

15

20

25

30

35

40

OUTPUT POWER (dBm)P

AE

(%

)

(b)

−5 0 5 10 15 20 25 300

5

10

15

20

25

30

35

40

OUTPUT POWER (dBm)

GA

IN (

dB)

SimulationMeasurement

−5 0 5 10 15 20 25 300

5

10

15

20

25

30

35

40

OUTPUT POWER (dBm)

PA

E (

%)

(c)

Figure III.40: Simulated and measured gain and power-added efficiency versus outputpower for (a) PA1, (b) PA2, and (c) PA3. The output stages of the PAs are biased at0.8 V.

102

−5 0 5 10 15 20 25 30

−50

−40

−30

−20

OUTPUT POWER (dBm)

ME

AS

UR

ED

IM3

(dB

c)

PA1PA2PA3

(a)

−5 0 5 10 15 20 25 30

−50

−40

−30

−20

OUTPUT POWER (dBm)

ME

AS

UR

ED

AC

P1

(dB

c)

PA1PA2PA3

(b)

−5 0 5 10 15 20 25 30−70

−60

−50

−40

OUTPUT POWER (dBm)

ME

AS

UR

ED

AC

P2

(dB

c)

PA1PA2PA3

(c)

Figure III.41: Measured (a) IM3, (b) adjacent-channel leakage power, and (c) alternate-channel power versus peak-envelope output power for the three PAs. The output stages ofthe PAs are all biased at0.8 V.

103

Figure III.42: Measured WCDMA spectra of PA1 and PA2 at a carrier output power ofnearly 20 dBm. The output stages of the PAs are both biased at0.8 V.

Table III.5 compares the performance of recently reported linear power amplifiers

for handset applications. As can be seen, although a CMOS PA’s peak efficiency is gener-

ally lower than its GaAs HBT (FET) counterpart, if properly linearized, it can effectively

be used as a low-cost alternative, especially for low-supply voltage and medium-power

applications.

III.7 Summary

The nonlinear gate-source capacitance is a dominant source of distortion that may

limit the linearity of CMOS class-AB power amplifiers. Improved performance can be

obtained by using a compensating nonlinearity, provided by the gate-source capacitance of

an appropriately biased and sized PMOS device placed alongside the NMOS device that

provides the class-AB amplification. Simulations and experiments show that the method

can improve both the two-tone, third-order intermodulation and adjacent-channel leakage

104

Table III.5: Performance comparison of recently reported linear power amplifiers for hand-set applications.

Ref. Technology Pout PAE Gain [Signal] VDD Freq. Operating

(dBm) (dB) ACPR @ Pout (V) (MHz) class

Su 98 CMOS 28 33 % N/A [NADC] 3 836 AB

[30] 0.8 µm -30 dBc @ 28 dBm (linearized)

Giry 00 CMOS 23.5 35 % 24.6 [PDC] 2.5 1910 AB

[31] 0.35 µm -55 dBc @ 21.5 dBm

Yen 03 CMOS 20 28 % 11.2 [π/4 DQPSK] 2.5 2450 AB

[32] 0.25 µm -28 dBc @ 18 dBm (linearized)

This work CMOS 24 29 % 23.9 [WCDMA] 3.3 1750 AB

(PA3) 0.5 µm -35 dBc @ 24 dBm (linearized)

Vintola 01 AlGaAs/GaAs >24 >27 % >30 [WCDMA] 3.5 1950 AB

[33] HBT -36 dBc @ 26 dBm

Jager 02 InGaP/GaAs 27 38 % 22.6 [WCDMA] N/A 1950 AB

[34] HBT -37 dBc @ 27 dBm

Srirattana 03 GaAs 29.7 46 % 8.5 [WCDMA] N/A 1950 Doherty

[35] FET -38 dBc @ 28.6 dBm 3-stage

power by approximately 8 dB. While meeting the 3GPP-WCDMA ACP requirements, the

linearized two-stage amplifier is capable of delivering an output power of 24 dBm with a

small-signal gain of nearly 24 dB and a power-added efficiency of 29 %.

Chapter IV

Dynamic Biasing Technique

IV.1 Introduction

Efficient power amplifiers are highly desirable in mobile wireless communication

systems to prolong battery life. Meanwhile, spectrally efficient modulation schemes in

many wireless standards result in signals with highly time-varying envelopes, thus impos-

ing a stringent linearity requirement on the employed power amplifiers to preserve modu-

lation accuracy and limit spectral regrowth.

To achieve the linearity requirement, PAs are generally operated in class-A or class-

AB modes. Although class-A and AB power amplifiers have reasonable maximum effi-

ciencies (theoretical 50% for A and 50-78.5% for AB), they suffer significant efficiency

degradation if operated at low power levels. For example, the efficiency of a class-A am-

plifier is in proportion to the output power,Pout, and this results in a maximum of only

0.5 % whenPout is backed off20 dB. This efficiency degeneration at low power levels

deserves special attentions, if taking into account the statistical nature of power usage in

wireless communication systems. As exemplified in [36], despite the maximum of0.5 W,

the output power in a IS-95-CDMA system has the most probable value of only1 mW,

105

106

yielding an extremely low PA efficiency.

Various techniques [36]-[37] were developed to improve PA efficiency at low power

levels. The dynamic biasing technique described in [37] is most appropriate for IC imple-

mentation. This technique uses the envelope of the input signal to dynamically control the

gate “dc” bias voltage of the power amplifier, thus reducing the current consumption of the

amplifier at low power levels. Since the previously designed two-stage CMOS class-AB

power amplifier exhibits good linearity and maximum efficiency, we would like to explore

the utility of the dynamic biasing technique on our class-AB PA.

This chapter will begin with a brief description of the dynamic biasing technique.

Then it will be followed by the detailed analysis of the envelope detector circuit. The

average efficiency improvement and distortion impact of the technique will be discussed

successively. Finally, the experimental results of a prototype amplifier will be presented

and conclusions will be drawn.

IV.2 Dynamic biasing Technique

IV.2.1 Basic concept

Figure IV.1 (a) shows the block diagram of the dynamic biasing technique proposed

by Saleh [37]. The envelope of a sample of the input RF signal is first detected, and then

is used to dynamically control the gate bias voltage. This is done such that the bias voltage

is forced to be proportional to the signal envelope. To realize an IC implementation, the

107

schematic in Figure IV.1 (b) is used. Here, the envelope detector is directly connected to

the with the input of the output stage. Since the input impedance of the output stage of the

PA is much larger than that of the envelope detector (ED), the inclusion of the ED does not

influence the RF signal performance.

V DD

Directional

coupler

Envelope

detector

Gate bias

control

RF out RF in FET

(a)

Envelope

detector

RF out Output

V DD

Gate bias

control

Gate bias

control

RF in Driver

V DD

(b)

Figure IV.1: (a) Conceptual block diagram and (b) actual implementation of the dynamicbiasing technique.

108

IV.2.2 Response of Envelope Detector

The input of the envelope detector is a narrow-band RF voltage signal with a time-

varying envelope. Since the signal itself contains no envelope-frequency components, non-

linear operation is necessary to yield the envelope signal. This is accomplished by feeding

the RF signal to a nonlinear device, such as a diode. Since the output contains not only the

envelope, but also the RF components, a low-pass filter should be included at the output.

The simplified schematic of the designed envelope detector is shown in Fig. IV.2 (a).

Here,Cbp provides the “dc” block;VGGP controls the gate bias for the PMOS deviceMp;

the large capacitorC1 is used to remove the RF signals at the envelope-detector output.

The gate-bias-control circuit for the output stage consists of a voltage divider,R1 andR2,

and an isolation resistor,R3. The equivalent large-signal model of the envelope detector

is shown in Fig. IV.2 (b). Here,Cgp models the total gate capacitance ofMp; Isdp(t) is the

source-drain current ofMp, where the subscript “sdp” represents that the direction of the

PMOS current is from source to drain. The PA input can be approximately modelled as a

capacitor, as shown later in this section. The calculation procedure of the envelope-detector

response for a two-tone input signal is described as follows.

First, the voltage signal at the gate ofMp is

Vgp(t) = VGGP+ A(cos ω1t + cos ω2t)

= VGGP+ 2A cos(ωd

2t)

cos ωct (IV.1)

109

C 1

R 1

R 2

R 3

V B0 V DD

M p

R b1

C bp

V GGP

Envelope

detector

Gate bias

control PA input PA input

Z PA

V (t) in

V (t) gp

V (t) env

(a)

Low-pass filter PA input PA input

C 1

R 3

C PA R 2 R 1 C gp

C bp V (t) gp

V (t) in I (t) sdp

V (t) env

(b)

Figure IV.2: Envelope detection and gate-bias-control circuit. (a) Schematic. (b) Equiva-lent large-signal model.

110

whereωd andωc represent the angle frequencies of the envelope and carrier,i.e.,

ωd = ω1 − ω2 (IV.2)

ωc =ω1 + ω2

2(IV.3)

andA is the tone amplitude.

To obtain the transient response of the envelope detector, Fourier transform ofIsdp(t)

should be first calculated. However,Isdp as a function ofVgp depends on the current charac-

teristics ofMp. In the following calculations, we will derive the Fourier transform ofIsdp(t)

for a long-channel device and an ideal linear device, respectively. Then we will show that

the implemented device exhibits approximately long-channel current characteristics for the

gate-voltage range we are interested. In the analysis, all the devices are assumed at ideal

class-B biases.

Fourier Transform of Isdp(t)

a) Ideal long-channel device

The source-drain current as a function ofVSG for a long-channel PMOS device is

ISDP =

kp(VSG + VTp)2 VSG > −VTp

0 VSG≤ −VTp

(IV.4)

where

kp =µpCox p

2

(W

L

)

p

(IV.5)

111

and the channel-length modulation effect is ignored because only a small envelope

voltage amplitude will appear at the drain of the PMOS device.

To simplify our analysis, the envelope period (Td) is chosen as a multiple of the

carrier period (Tc), i.e., Td = (2M + 1)Tc, whereM is an integer and much larger

than one. This is shown in Fig. IV.3.

time __ 2

T d __ 2

- 0 T d

__ 2

T c

t m t m+1 ... ... t -m-1 ... ...

__ 2

T c

t -m

I (t) sdp

Figure IV.3: Source-drain current ofMp as a function of time.

Assuming an ideal class-B bias, we have

VDD − VGGP = −VTp. (IV.6)

Substituting (IV.1) and (IV.6) to (IV.4) and sinceωc is much larger thanωd, we have

the drain current for one carrier period as

Isdp(t) ≈

4kpA2 cos2

(ωd

2tm

)cos2 ωct (tm − Tc

4) ≤ t < (tm + Tc

4)

0 (tm + Tc

4) ≤ t < (tm+1 − Tc

4)

(IV.7)

112

SinceIsdp(t) is conveniently chosen as an even function with the period ofTd, it can

be expanded to the following Fourier series:

Isdp(t) =a0

2+

∞∑n=1

an cos(nwdt) (IV.8)

where

an =2

Td

∫ Td2

−Td2

Isdp(t) cos(nωdt) dt. (IV.9)

Among all the frequency components, we are only interested in those near the en-

velope frequency (including some of the envelope harmonics) because all the RF

frequency components will be removed by the low-pass filter. The calculation ofa1

is shown here:

a1 =2

Td

∫ Td2

−Td2

Isdp(t) cos(ωdt) dt

≈ 2

Td

M∑m=−M

(∫ tm+Tc4

tm−Tc4

4kpA2 cos2(

ωd

2tm) cos(ωdtm) cos2(ωct) dt

)

=2kpA

2

Td

∫ Td2

−Td2

cos2(ωd

2t) cos(ωdt) dt

=kpA

2

2. (IV.10)

a0 can be calculated as

a0 = kpA2. (IV.11)

For the rest of envelope harmonics,

an ≈ 2kpA2

Td

∫ Td2

−Td2

cos2(ωd

2t) cos(nωdt) dt = 0 (IV.12)

113

wheren = 2, 3, ..., and

nωd ¿ ωc. (IV.13)

It can be shown from (IV.10) to (IV.12) that the envelope component of the long-

channel PMOS current for a two-tone input signal is

isdp(t) =kpA

2

2(1 + cos ωdt). (IV.14)

b) Ideal Linear Device

The source-drain current for an ideal linear PMOS device is

ISD =

k′p(VSG + VTp) VSG > −VTp

0 VSG≤ −VTp

(IV.15)

wherek′p is a constant. The same approach can be applied, and it can be shown that

the current envelope component of the ideal linear PMOS device is directly propor-

tional to the input envelope signal amplitude,i.e.,

idsp(t) =2k

′pA

πcos

ωd

2t. (IV.16)

c) Actual Device

The gate length of the PMOS device for the envelope detector is chosen as 0.5µm,

thus it is possible that the device current exhibits short-channel characteristics. At

low gate-bias voltages, such as in the class-B case, a short-channel device still ex-

hibits long-channel characteristics. To verify this claim, we fitted the SPECTRE

114

simulated PMOS current data using the square function in (IV.4) and the linear func-

tion in (IV.15). The fitting was carried out for the gate voltage between 2.0 and 2.9

V. Figure IV.4 shows the SPECTRE simulated, the square-function fitted, and the

linear-function fitted curves, respectively. As can be seen, the square function can

fit the current very well in the voltage range we are interested. Thus, the employed

PMOS can be approximately modelled as a long-channel device.

1.9 2.1 2.3 2.5 2.7 2.9 3.1 3.3−2

0

2

4

6

8

10

GATE VOLTAGE (V)

ISD

(m

A)

SPECTRE DATACurvefit (square)Curvefit (linear)

Figure IV.4: SPECTRE simulated and MATLAB fitted PMOS source-drain current versusgate voltage. The two fitting functions are those in (IV.4) and (IV.15), respectively. Thefitting was carried out for the gate voltage between 2.0 and 2.9 V.

Low-pass Filter Transfer Function

To find the transfer function of the low-pass filter in Fig. IV.2 (b), we need to first

calculate the impedance exhibited by the power amplifier to the gate-bias-control circuit.

The two-stage CMOS PA design is described in the previous chapter, and the schematic is

shown in Fig. IV.5. Since the impedances ofL1 and all the RF chokes are very small at the

envelope frequency, they are equivalent to “ac” ground. Thus, the input of the two-stage

115

M 0

M p

On-chip 2f termination

C dc

Compensation

circuitry

V PP

RF

choke

V out

V DD

M 1

L 1

C f1

R f1

RF

choke

On-chip

2f termination

C 1

V in

C i1

L i1

R b1

V GG1

C b1

V DD

C b2

V GG0

PA

input

Figure IV.5: Schematic of the designed two-stage CMOS power amplifier.

PA is approximately the total gate capacitance ofM0 in parallel with the “dc” blocking

capacitorCb1, i.e.,

CPA ≈ Cgs0+ Cgb0 + Cgd0 + Cb1. (IV.17)

The transfer function of the low-pass filter is then

G(s) =Venv(s)

Isdp(s)=

R1,2

1 + sC1R1,2 + sCPA(R3 + R1,2 + sC1R3R1,2)(IV.18)

whereR1,2 represents the total resistance ofR1 in parallel withR2. Note that the low-pass

filter will introduce both magnitude distortion and phase delay. To minimize these effects,

C1, R1, R2, andR3 should be chosen as small as possible to maximize the frequency

of the dominant pole in (IV.18). However, to isolate the influence of the bias circuitry

on the PA RF path and minimize the current consumption,R1, R2, andR3 should be

116

maximized. In addition, to remove the RF frequency components at the envelope detector

output,C1 should be maximized. Therefore, tradeoffs in these regards have to be made. In

our implementation,C1 is chosen as 30 pF,R1 andR2 are chosen as 200Ω, R3 is 100Ω;

the input of the PA is approximately 76 pF. This yields the two poles of the low-pass filter

as 9.4 and 117.6 MHz, respectively.

Final Output Envelope Signal

Assuming all the RF components will be removed by the low-pass filter, the output

voltage of the envelope detector is

Venv(t) =R2

R1 + R2

VB0 +a0

2R1,2 + a1 |G(jωd)| cos(ωdt + ∠G(jωd))

+ a2 |G(j2ωd)| cos(2ωdt + ∠G(j2ωd)) + · · · (IV.19)

where∠G(jω) represents the phase delay introduced by the low-pass filter. Since the

PMOS device we used exhibits long-channel current characteristics, we can substitute

(IV.10)-(IV.12) to (IV.19). This gives

Venv(t) =R2

R1 + R2

VB0 +kpA

2

2[R1,2 + |G(jωd)| cos(ωdt + ∠G(jωd))]. (IV.20)

For envelope frequencies much less than 9.4 MHz (the dominant pole of the low-pass filter),

(IV.20) reduces to

Venv(t) ≈ R2

R1 + R2

VB0 +kpA

2

2R1,2(1 + cos ωdt). (IV.21)

Here, the first term is the initial bias voltage set by the gate-bias-control circuit, as shown

in Fig. IV.2 (b); the second term is the output envelope signal. As can be seen, the output

117

envelope signal is proportional to the square of the input envelope signal amplitude. This

is due to the square relationship between the source-drain current and the gate voltage of

the long-channel PMOS device.

For illustration purposes, Fig. IV.6 shows the approximate time-domain waveforms

of Vgp(t), Isdp(t), andVenv(t). The waveforms are not scaled.

IV.3 Efficiency Improvement

The drain-efficiency improvement of the dynamic biasing technique was derived as

a closed-form expression in [37] for an ideal class-A FET amplifier. For an amplifier oper-

ating in class-AB mode, closed-form expressions cannot be obtained due to the nonlinear

relationship of the current of the class-AB device with the input voltage. Therefore, nu-

merical calculations were employed to estimate the efficiency improvement of the dynamic

biasing technique.

IV.3.1 Drain Efficiency for Single-tone Input

The drain-source currentIDS(VGS, VDS) for a short-channel NMOS transistor as a

function ofVGS andVDS can be approximately modelled as

IDS =

k(VGS− VTn)2

1 + α(VGS− VTn)(1 + λVDS) VGS > VTn

0 VGS≤ VTn

(IV.22)

The I − V curve of the employed device can be obtained from the SPECTRE simulator

for theVGS andVDS ranges where the device will be operated. Using the MATLAB “least-

118

time

Vgp(t)

VGG0

(a)

time

Isdp(t)

(b)

time

Outputenvelope

Isdp(t)envelope

Venv(t)

(c)

Figure IV.6: Approximate time-domain waveforms of (a) input gate voltage, (b) source-drain current ofMp, and (c) output voltage of the envelope detector for a two-tone testsignal. The dashed lines in (a) and (b) are the corresponding signal envelopes. The dashedline in (c) is the envelope ofIsdp(t) for illustrating the delay of the ED output.

119

square curvefit” function, we can fit (IV.22) to the deviceI − V data with appropriate

coefficients ofk, α, andλ.

The single-tone input voltage signals for the fixed and dynamic biasing schemes are

Vgs(t) = VGG + A cos(ωct + φ) (IV.23)

and

Vgs(t) = VGG + vENV(A) + A cos(ωct + φ) (IV.24)

respectively, whereA stands for the RF signal amplitude. The corresponding drain current

is

Ids =

k(Vgs− VTn)2

1 + α(Vgs− VTn)(1 + λVds) Vgs > VTn

0 Vgs≤ VTn

(IV.25)

To simplify our calculation, theIds dependence onVds was eliminated by approximating

Vds as a superposition of the “dc” bias and the purely linear part of the output signal:

Vds = VDD − gvvgs = VDD − gvA cos(ωct + φ) (IV.26)

wheregv, the voltage gain of the amplifier at the fundamental frequency, can be estimated

from first-order simulations. Substituting (IV.23), (IV.24), and (IV.26) to (IV.25),Ids(t) can

be derived.

The “dc” and fundamental components of the drain current can be obtained by ap-

120

plying Fourier-series transforms to (IV.25)

IDD =1

T1

∫ T12

−T12

Ids(t) dt (IV.27)

io =2

T1

∫ T12

−T12

Ids(t) cos(ωct) dt. (IV.28)

The drain efficiency of the amplifier is defined as

Peff =Pout

Pdc=

1

2i2oRO

VDDIDD. (IV.29)

Substituting (IV.22)-(IV.28) to (IV.29), we are able to calculate the drain efficiency of the

amplifier.

IV.3.2 Average Efficiency for Varying-envelope Signals

To properly estimate the average PA efficiency, it is necessary to account for the

probability distribution of the long-time power usage as a function of the output power

Pout [38] [36]. Let this probability density function bep(Pout), the average efficiency is

defined as

ηavg =〈Pout〉〈Pdc〉

=

∫∞0

p(Pout)Pout dPout∫∞0

p(Pout)Pdc(Pout) dPout. (IV.30)

Here, 〈Pdc〉 is the average “dc” power consumed by the amplifier, which directly corre-

sponds with battery energy consumption.

121

IV.4 Distortion Calculation

IV.4.1 IM 3 Expression

To understand the impact of the dynamic biasing technique on the linearity of the

CMOS class-AB power amplifier, it is illustrative to analyze the two-tone, third-order in-

termodulation (IM3) of the PA using Volterra analysis. In general, Volterra analysis as-

sumes each nonlinear element in a circuit can be described by a third-order, power-series

expansion in which the series coefficients depend only on the circuit’s bias point. As dis-

cussed in the previous chapter, such analysis cannot be directly applied to describe highly

nonlinear circuits, such as a class-AB power amplifier; but we can alleviate this problem

by employing power-series expansions of order greater than three, and by allowing the se-

ries coefficients to depend onboth the bias pointand the RF signal power. As previously

demonstrated, the major sources of nonlinearity for a NMOS device working in a class-AB

mode are the effective gate-source capacitance (Ceff) and the drain-source current (idsn), in

which the first one can be linearized by applying a capacitance-compensation technique.

Both of these two nonlinearities can be expanded to power series of the input gate-source

voltagevgs, i.e.,

Ceff = c1 + c2vgs + c3v2gs + c4v

3gs + c5v

4gs (IV.31)

and

idsn = g1vgs + g2v2gs + g3v

3gs. (IV.32)

122

It is important to reemphasize that when the bias pointor RF signal power changes, the

coefficients (c1 throughc5 andg1 throughg3) also change, such that the expansions always

trace out the appropriateCeff andidsn versusvgs curve.

The voltage signal at the gate ofM0, when the dynamic biasing technique is applied,

contains both RF and envelope components. Assuming the spacing of the two tones is

much less than the dominant pole (9.4 MHz) of the low-pass filter, from (IV.21), the gate

voltage signal of the output device,M0, is

Vg0(t) = A(cos ω1t + cos ω2t) +R2

R1 + R2

VGG0 +kpA

2

2R1,2(1 + cos ωdt)

= (R2

R1 + R2

VGG0 + γA2) + [A(cos ω1t + cos ω2t) + γA2 cos ωdt] (IV.33)

where

γ =kp

2R1,2 (IV.34)

ωd = ω1 − ω2. (IV.35)

The first term in (IV.33) is the “dc” bias voltage, and the second term is the “ac” signal.

Note that this “dc” bias voltage varies with the input envelope amplitude, thus will have

impact on PA linearity. This will be discussed later in this section.

Substituting the “ac” signal in (IV.33) to (IV.32) gives

idsn = (g1A +9

4g3A

3 +3

2g3γ

2A5) cos(ω1t) +3

4g3A

3 cos((2ω2 − ω1)t)

+ g2γA3 cos((2ω2 − ω1)t) +3

4g3γ

2A5 cos((2ω2 − ω1)t) + · · ·

≈ g1A cos(ω1t) + (3

4g3 + g2γ)A3 cos((2ω2 − ω1)t) + · · · . (IV.36)

123

gdnC

Z I Ceff, g v ZO 2ω − ω 1 2 1 gs, 2ω − ω 1 2 2ω − ω 1 2gs, 2ω − ω 1 2v

+

−

c1~ ~

dsn,~ ~

Figure IV.7: Circuit for the Volterra calculation.

As can be seen, the IM3 of idsn now consists of two terms: the first,34g3A

3, comes from the

intrinsic current nonlinearityg3; the second,g2γA3, arises from the current’s second-order

nonlinearityg2. Note that the even-order terms ofCeff are greatly reduced by applying the

capacitance compensation technique, thus their influence are ignored.

Based on the “method of nonlinear currents” [23], the circuit for the Volterra calcu-

lation is shown in Fig. IV.7. Here,ZI represents the impedance seen looking into the input

matching network from the NMOS gate whenis = 0, andZO represents the impedance

seen looking into the output matching network from the NMOS drain. It is worth men-

tioning that bothZI andZO include short-circuit terminations at the second-harmonic fre-

quency, as described in the previous chapter. The distortion currents generated byCeff and

idsn have the following phasor amplitudes:

ıdsn,2ω1−ω2 = (3

4g3 + g2γ)v3

gs,ω1(IV.37)

and

ıCeff,2ω1−ω2 = j(2ω1 − ω2)

[1

4c3v

3gs,ω1

+5

8c5v

5gs,ω1

](IV.38)

where vgs,ω1 is the phasor amplitude of the gate-source voltage at the fundamental fre-

124

quency. The distortion voltages that result at the gate and drain can then be computed using

the circuit of Fig. IV.7:

vds,2ω1−ω2 = −ZOıdsn,2ω1−ω2 [1 + j(2ω1 − ω2)CgdnZ′I ]− ıCeff,2ω1−ω2 [g1 − j(2ω1 − ω2)Cgdn]Z

′I

1 + j(2ω1 − ω2)Cgdn(Z ′I + ZO + g1Z ′

IZO)

(IV.39)

whereZ ′I ≡ ZI ‖ c1, and the impedancesZ ′

I andZO should be evaluated at the intermod-

ulation frequency2ω1 − ω2. The drain voltage at the fundamental frequency is also easily

found to be

vds,ω1 =−g1ZO + jω1CgdnZO

1 + jω1CgdnZO

vgs,ω1 (IV.40)

where, in this case,ZO should be evaluated at the fundamental frequencyω1. The IM3 at

the drain are then simply

IM3D = 20 log

∣∣∣∣vds,2ω1−ω2

vds,ω1

∣∣∣∣ . (IV.41)

IV.4.2 Estimation of g2 and g3

As described in the previous chapter, with the capacitance compensation technique,

idsn becomes the dominant source of nonlinearity for the two-stage CMOS class-AB PA.

Since (IV.37) shows that bothg2 andg3 contribute to theidsn nonlinearity, it is beneficial to

first estimate these two polynomial coefficients. To be complete, we estimateg2 for three

devices: a long-channel class-A device, an ideal linear class-B device, and the implemented

class-AB device.

125

Estimation of g2

a) a long-channel class-A device

For a long-channel class-A device,g2 is in the same order ofg1, as illustrated in the

long-channel current expression:

ids(vgs) =µCox

2

(W

L

)(vgs + VGG− VT )2

=µCox

2

(W

L

)[(VGG− VT )2 + 2(VGG− VT )vgs + v2

gs]. (IV.42)

The IDS versusVGS curve for such a device is illustrated in Fig. IV.8 (a). Compar-

ing (IV.42) with (IV.32), we have

g2

g1

=1

2(VGG− VT ). (IV.43)

Typical values of(VGG−VT ) for a CMOS class-A PA is in the range of0.25− 0.5 V,

which implies thatg2 is approximately 1-2 times ofg1.

b) an ideal class-B device

For an ideal class-B device that has current characteristics shown in Fig. IV.8 (b),

g2 is also in the same order ofg1. Assuming the current can be expanded for three

terms,i.e.,

idsn = g1vgs + g2v2gs + g3v

3gs. (IV.44)

For an input signal ofcos ωt, (IV.44) gives

idsn(t) = g1 cos ωt +g2

2cos 2ωt + · · · . (IV.45)

126

0

I DS

v gs

V GG V T

V GS

(a)

V GS 0

v gs

V T

I DS

(b)

Figure IV.8: IDS versusVGS for (a) a long-channel class-A device, and (b) an ideal class-Bdevice.

In the meantime, the output current of an ideal class-B device is also

idsn(t) =

cos ωt −T4

< t ≤ T4

0 T4

< t ≤ 3T4

(IV.46)

Here, to simplify our analysis, we let the slope of theIDS versusVGS curve as unity.

Fourier expansion on (IV.46) gives

idsn(t) =1

2cos ωt +

2

3πcos 2ωt + · · · . (IV.47)

Comparing (IV.45) with (IV.47), we have

g2

g1

=8

3π. (IV.48)

Thus, for an ideal class-B device,g2 is approximately equal tog1. Note that the above

derivations are only for the first-order estimation.

127

c) the implemented class-AB device

For a general class-AB device,g2 varies with the device characteristics, bias voltages,

and signal amplitude. In such cases, numerical calculations described in the previous

chapter is necessary. The ratio ofg2 to g1 for the four gate bias voltages (0.75 -

0.90 V) of the implemented class-AB device is shown in Fig. IV.9 (a). As can be

seen, this ratio for most bias voltages and power levels are larger than one.

Estimation of g3

The estimation ofg3 for a CMOS class-AB device is not straightforward. Again,

numerical calculations are employed, and it was found thatg3 varies dramatically with

both the gate bias voltage,VGG0, and the output power,Pout, as shown in Fig. IV.9 (b).

IV.4.3 Final IM 3 Calculation

The maximum single-tone RF signal amplitude at the gate ofM0 is designed as

0.60 V. Thus, the maximum tone amplitude (Amax) for an input two-tone signal is 0.30 V. If

the gate bias voltage is designed to vary from 0.75 to 0.85 V, (IV.21) gives the peak-to-peak

value ofVenv(t) as

2γA2max = VGG0|max− VGG0|min = 0.85− 0.75. (IV.49)

Thus,γ can be calculated. The output IM3 can then be calculated from (IV.37)–(IV.41).

Figure IV.10 shows the comparison of the calculated and simulated load-voltage IM3 of

the designed CMOS class-AB PA with the dynamic biasing technique. As illustrated in

128

−10 0 10 20 300

1

2

3

4

5

OUTPUT POWER (dBm)

g 2/g1

VGG0

=0.75 VV

GG0=0.80 V

VGG0

=0.85 VV

GG0=0.90 V

(a)

−10 0 10 20 30−1

0

1

2

OUTPUT POWER (dBm)

g 3/g1

VGG0

=0.75 VV

GG0=0.80 V

VGG0

=0.85 VV

GG0=0.90 V

(b)

Figure IV.9: Ratio of (a)g2 and (b)g3 to g1 for the four gate bias voltages (0.75 - 0.90 V)of the implemented class-AB device.

129

(IV.33), the “dc” gate bias voltage ofM0 varies with the tone amplitude,A. Thus, each

sweptA corresponds to a different set of power-series coefficients ofCeff andidsn, which is

obtained by performing the interpolations among the four sets of coefficients atVGG0 from

0.75 to 0.90 V.

0 10 20 30−80

−60

−40

−20

OUTPUT POWER (dBm)

LOA

D−

VO

LTA

GE

IM3

(dB

c)

Calculation (ED)Simulation (ED)

Figure IV.10: Comparison of the calculated and simulated IM3 of the load voltage at2ω1−ω2 versus peak-envelope output power. The gate bias is designed to vary from 0.75 V to0.85 V.

Figure IV.11 shows the contributions to the load IM3 arising fromg2, g3 andCeff

nonlinearities, as computed from (IV.37)–(IV.41). The contribution from one nonlinearity

source is found by setting the other two to zero. As shown, theg2 nonlinearity limits the

load IM3 over a wide range of power levels.

130

0 10 20 30

−80

−60

−40

−20

OUTPUT POWER (dBm)

IM3

CO

NT

RIB

UT

ION

(dB

c)

g3 contribution

g2 contribution

Ceff

contribution

Figure IV.11: Contributions to the load-voltage IM3 from theg2, g3, andCeff nonlinearities.The values are computed from the Volterra expressions (IV.37)–(IV.41), as described in thetext.

IV.5 Experimental Results

IV.5.1 IC Implementation

The power amplifier employed for the dynamic biasing technique is the PA3 de-

scribed in the previous chapter (the envelope detector is disabled for the measurements at

that chapter). The implementation details, such as the off-chip matching design, can also

be found in that chapter. Figures IV.12 shows the die microphotograph of the PA3. The

“ED” block is the envelope detector circuit. Including bonding pads, the chip occupies an

area of2.0 × 1.6 mm2.

131

Figure IV.12: Die microphotograph of the highly integrated and compensated two-stageCMOS PA (PA3). The “ED” block is the envelope detector circuit.

132

IV.5.2 Measurement Results

Envelope Detector Output

The output voltage of the envelope detector,Venv, is measured using a high defini-

tion oscilloscope. The PMOS device is biased at the class-B mode and the corresponding

envelope output varies from 0.75 V, when no input signal is applied, to 0.85 V, when the

output power reaches the designed maximum: 24 dBm. Figure IV.13 shows the calculated,

simulated, and measuredVenv versus output power for a single-tone input. As can be seen,

our analysis accurately predicts the response of the envelope detector.

2 6 10 14 18 22 260.75

0.77

0.79

0.81

0.83

0.85

OUTPUT POWER (dBm)

Ven

v (V

)

CalculationSimulationMeasurement

Figure IV.13: Calculated, simulated, and measuredVenv versus output power for a single-tone input.

Gain and Efficiency

Figure IV.14 shows the measured gain and power-added efficiency (PAE) for PA3

when the dynamic biasing technique is applied, and PA3 when the dynamic biasing tech-

nique is disabled and the gate is biased atVGG0 = 0.85 V, respectively. As expected, the

133

dynamic biasing technique improves the PA’s 1-dB compress point due to the increased

gate bias. However, this does not yield better linearity, as shown later in the linearity mea-

surements.

−5 0 5 10 15 20 25 300

5

10

15

20

25

30

35

OUTPUT POWER (dBm)

GA

IN (

dB)

VGG0

=0.85 VV

GG0=dynamic

−5 0 5 10 15 20 25 300

5

10

15

20

25

30

35

OUTPUT POWER (dBm)

PA

E (

%)

Figure IV.14: Measured gain and power-added efficiency versus output power for PA3 withthe dynamic biasing technique, and PA3 when the envelope detector is disabled and the gateis biased atVGG0 = 0.85 V, respectively.

Define the power consumption improvementε as

ε =Pdc, 0.85 V− Pdc, dynamic

Pdc, 0.85 V(IV.50)

wherePdc, 0.85 V and Pdc, dynamic represent the “dc” power consumption of PA3 when the

dynamic biasing technique is applied, and PA3 when the dynamic biasing technique is

disabled and the gate is biased atVGG0 = 0.85 V, respectively. Figure IV.15 shows the

measured power consumption improvement versus the PA output power. As can be seen,

the dynamic biasing technique can improve the power consumption by nearly 50 % for the

output stage and 30 % for the total two-stage.

134

−5 0 5 10 15 20 25 300

10

20

30

40

50

60

OUTPUT POWER (dBm)

PO

WE

R C

ON

SU

MP

TIO

N IM

PR

OV

EM

EN

T (

%)

Two−stageOutput stage

Figure IV.15: Measured power consumption improvement versus the PA output power.

Linearity

To verify its linearity performance, PA3 was tested using both two-tone and WCDMA

signals. Again, the testings were carried out for both biasing schemes. Figures IV.16 show

the measured IM3, adjacent-channel leakage power (ACP1), and alternate-channel power

(ACP2). Figures IV.17 shows the comparison between the calculated and measured load-

voltage IM3 versus output power. As can be seen, a good agreement is obtained between

the calculations and the measurements, verifying our distortion analysis. The linearity

measurements also validate our claim that the dynamic biasing technique can introduce

significant nonlinearity into the CMOS class-AB PA.

Although more nonlinear, PA3 with the dynamic biasing technique can marginally

meet the 3GPP-WCDMA ACP requirements of -33 dBc and -43 dBc at the output power

of 24 dBm.

135

−5 0 5 10 15 20 25 30

−50

−40

−30

−20

OUTPUT POWER (dBm)M

EA

SU

RE

D IM

3 (d

Bc)

VGG0

=0.85 VV

GG0=dynamic

(a)

−5 0 5 10 15 20 25 30

−50

−40

−30

−20

OUTPUT POWER (dBm)

ME

AS

UR

ED

AC

P1

(dB

c)

VGG0

=0.85 VV

GG0=dynamic

(b)

−5 0 5 10 15 20 25 30−70

−60

−50

−40

OUTPUT POWER (dBm)

ME

AS

UR

ED

AC

P2

(dB

c)

VGG0

=0.85 VV

GG0=dynamic

(c)

Figure IV.16: Measured (a) IM3, (b) adjacent-channel leakage power, and (c) alternate-channel power versus peak-envelope output power of PA3 for both biasing schemes.

136

−5 0 5 10 15 20 25 30−50

−40

−30

−20

OUTPUT POWER (dBm)

LOA

D−

VO

LTA

GE

IM3

(dB

c)

CalculationMeasurement

Figure IV.17: Comparison between the calculated and measured load-voltage IM3 versusoutput power.

IV.6 Summary

The dynamic biasing technique can improve the efficiency of a CMOS class-AB

PA at low output power levels, as demonstrated by both calculations and experiments.

However, the envelope signal introduced by the dynamic biasing technique can significantly

limit the overall linearity of the CMOS class-AB PA, as verified by both Volterra analysis

and experimental results. Thus, further linearization methods are necessary to reduce this

nonlinearity.

Chapter V

Conclusions

Linearity and efficiency are the two most important characteristics of power ampli-

fiers for wireless applications. In this dissertation, we investigate three topics on CMOS

power amplifiers: class-E, class-AB, and dynamic biasing technique.

Class-E power amplifier is a promising candidate for realizing high efficiency. Pre-

vious analytical efforts on class-E power amplifiers assumed either zero switch resistance

and/or infinite drain inductance, leading to less optimized design. In this dissertation, we

developed an improved design technique by accounting for both finite drain inductance

and finite “on” resistance for a CMOS device. This design technique expresses the circuit

parameters in terms of the device width and the design specifications, such as the output

power and operating frequencyfc. A design example based on the developed algorithm

achieves an output power of 0.25 W and a drain efficiency of 87% for a 3.5 mm NMOS

class-E device withVDD = 2 V andfc = 1.90 GHz.

The intrinsic linearity obtained in a CMOS class-AB operation is often insufficient to

meet the stringent linearity requirement imposed by modern wireless standards. In this dis-

sertation, we found that the nonlinear gate-source capacitance is a dominant source of dis-

tortion that limits the linearity of CMOS class-AB power amplifiers. A simple technique is

137

138

proposed to cancel this nonlinearity by using a compensating nonlinearity, provided by the

gate-source capacitance of an appropriately biased and sized PMOS device placed along-

side the NMOS device that provides the class-AB amplification. Volterra analysis and

two-tone SPECTRE simulations were used to verify the technique. Prototype two-stage

CMOS class-AB power amplifiers were implemented. Experiments show that the ampli-

fiers employing the compensation technique can improve both the two-tone, third-order

intermodulation and adjacent-channel leakage power by approximately 8 dB. When oper-

ated atVDD = 3.3 V, the final linearized power amplifier is capable of delivering an output

power of 24 dBm with a small-signal gain of nearly 24 dB and an overall power-added

efficiency of 29 %. At the designed output power of 24 dBm, the adjacent-channel leakage

power of the linearized amplifier is -35 dBc, meeting the 3GPP-WCDMA requirements

of -32 dBc. The experimental results also prove the feasibility of linear CMOS class-AB

power amplifiers for wireless communication systems.

Although the designed two-stage CMOS class-AB power amplifier exhibits good lin-

earity and maximum efficiency, it still suffers serious efficiency degradation when operated

at low output power levels. This deserves special attentions considering the statistical na-

ture of power usage in wireless communication systems: as exemplified in [36], the most

probable output power of a IS-95-CDMA system is only1 mW, despite the maximum of

0.5 W. In this dissertation, it was demonstrated that a dynamic biasing technique can im-

prove the efficiency of a CMOS class-AB power amplifier by controlling the gate bias

voltage with the envelope of input RF signal. However, the envelope signal introduced by

139

the dynamic biasing technique can significantly limit the overall linearity of the CMOS

class-AB PA, as verified by both Volterra analysis and experimental results. The prototype

power amplifier employing the dynamic biasing technique exhibited more than 6 dB worse

in IM 3 and ACP performances than the one without the technique applied. Thus, further

linearization or compensation methods are necessary to reduce the nonlinearity introduced

by the dynamic biasing technique.

1

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