Universität Dortmund Laboratory Exercise...
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Universität Dortmund Laboratory Exercise 3 Davide Rossi DEI University of Bologna AA 2016-2017
Transcript of Universität Dortmund Laboratory Exercise...
Universität Dortmund
Laboratory Exercise 3
Davide Rossi
DEI University of Bologna
AA 2016-2017
Universität Dortmund
• Summary of finite state machines (Mealy, Moore)
• Description of FSMs in System Verilog
• Design of control blocks based on FSMs
• Exercise: semaphore
Objectives
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Moore FSM
3
Next State
Logic
FF
State Register
InputsOutputs
Output
Logic
Next StateCurrent State
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State Diagram: Moore
4
S0
S2
S1
reset = 1
a = 0 b = 0
Y=1
a = 1
b = 1
Outputs Y and Z are 0,
unless specified otherwise.
If an input isn’t listed for a
transition, we don’t care
about its value for that
transition
Z=1
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Moore Verilog – Part 1
5
module fsm_moore (input logic clk, input logic reset, input logic a, input logic b, output logic Y, output logic Z
);
always_ff@(posedge clk) beginif (reset)
state <= S0;else
state <= next_state;end
//continued on next slide
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Moore Verilog – Part 2
6
//next state & output logicalways@(state or a or b)case (state)
S0: if (a)next_state = S1;
elsenext_state = S0;
S1: Y = 1;if (b)
next_state = S2;else
next_state = S1;S2: Z = 1;
next_state = S0;default: next_state = S0;
endcaseendmodule
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Mealy FSM
7
Next State and
Output Logic
FF
State Register
Inputs Outputs
Current State
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State Diagram
8
S0
S2
S1
reset = 1
a = 0 b = 0
Y=1
a = 1/Z = 1
b = 1/ Z = 1
Outputs Y and Z are 0,
unless specified otherwise.
We don’t care about the
value of b in S0, or the
value of a in S1, or either a
or b in S2.
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Mealy Verilog – Part 1
9
module fsm_mealy (input logic clk, input logic reset, input logic a, input logic b, output logic Y, output logic Z);
enum { S0, S1, S2 } state, next_state;
always_ff@(posedge clk)beginif (reset)
state <= S0;else
state <= next_state; end
//continued on next slide
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Mealy Verilog – Part 2
10
// next state & output logic
always_comb
begin
Y = 0; Z = 0;
case (state)
S0: if (a)
begin
next_state = S1;
Z = 1;
end
else
next_state = S0;
S1: begin
Y = 1;
if (b)
begin
next_state = S2;
Z = 1;
end
else
next_state = S1;
end
S2: next_state = S0;
default: begin
next_state = S0; Y = 1’b1;
Z = 1’b1; end
endcase
endmodule
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Exercise 1Desig, using SystemVerilog hardware description language, a digital circuit implementing
the functionality of a controller for a beverage dispensing machine. The IO interface of the
digital circuit is the following:
module vending
(
input logic clk,
input logic rstn,
input logic dime,
input logic niche,
output logic out
);
endmodule
The dispensing machine only accepts 5 cents (nichel) and 10 cents (dime) coins. Once
the amount of 15 cents is reached the machine activates a signal to enable the release of
the beverage (output).
The machine does not give back change.
It is not allowed to insert more than one coin for a given clock cycle.
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Exercise 2
Traffic light:
module traffic_light(
input logic clk,input logic rstn,output logic red,output logic yellow,output logic green
);
endmodule
100 cycles
10 cycles
200 cycles
