Universidad Politécnica de Madrid - keeping an eye on digital ...Universidad Politécnica de Madrid...

1

1APEC 2006 Dallas (USA)DIE

UPM

UNIVERSIDAD POLITEacuteCNICADE MADRID (UPM) Escuela Teacutecnica Superior

de Ingenieros Industriales (ETSII)

DivisiDivisioacuteoacuten de Ingeniern de Ingenieriacuteiacutea Electra Electroacuteoacutenicanicawwwupmdieupmeswwwupmdieupmes

Universidad PolitUniversidad Politeacuteeacutecnica de Madridcnica de Madrid

JosJoseacuteeacute A Cobos Oscar GarcA Cobos Oscar Garciacuteiacutea Angel de Castro Andra Angel de Castro Andreacuteeacutes Sotos Soto


UPM

1 1 MotivationMotivation

keeping an eye on digital controlkeeping an eye on digital controland not determined to digital controland not determined to digital control

it is advantageous onlyit is advantageous onlyin a number of applicationsin a number of applications

in the field of power suppliesin the field of power supplies

(Do not get rid of analog)(Do not get rid of analog)

Read morehellipSolutions to those problems

This symbol is used when digital control ENABLES newfunctionality

This is used to alert on a specific problem that youshould be aware of

Beware

2


UPM

AnalogAnalog

μProccessor(DSP)

μProccessor(DSP)

Custom HW(FPGA ASIC)


MotivationMotivation

More More complexcomplexalgorithmsalgorithmsReprogrammabilityReprogrammabilityDesignDesign timetime

HigherHigher pricepriceNeedNeed ofof ADCADCLimitedLimited resolutionresolution((measuringmeasuring processingprocessing andanddutyduty cyclecycle))LimitedLimited bandwidthbandwidth(for (for thethe samesamealgorithmalgorithm))helliphellipbut enables faster but enables faster control strategiescontrol strategies

ConcurrencyConcurrencyProcessingProcessing speedspeed

HighHigh computationcomputation capabilitiescapabilitiesADC ADC integratedintegrated

DigitalDigital


UPM

1 1 SeminarSeminar approachapproachIllustrateIllustrate proprorsquorsquos cons conrsquorsquos and design issues through some specific applicationss and design issues through some specific applications

PowerPower Factor Factor CorrectionCorrection

IinVin

Vout

Digital charge control

Adaptive control

Sampling delayBeware

Model of the converter

VOUTIN VOUTVIN VOUTIN VOUTVINCOCIN

MultiphaseMultiphase for for automotiveautomotive (dual (dual voltagevoltage))

a) Reduce Co reduce current ripple by sequencing phasesb) High number of phases (current balance)

a) Reduce power losses at light load (activateappropriate number of phases)b) Change to ldquoforcedrdquo DCM

Get rid of current loops

Implementation of multi-output DPWM

3


UPM

1 1 SeminarSeminar approachapproach

IllustrateIllustrate proprorsquorsquos cons conrsquorsquos and design issues through some specific applicationss and design issues through some specific applications

PSU for RF PSU for RF transmittertransmitter

Resolution of DPWM

variable VS

Accurate model of thepower converter (G(z))

Current balance in multi-phase

DcDc--dcdc converterconverter for DVSfor DVS

Fast Vo changes for DVS (ultra high bandwidth)

Non linear control

Robust control

Quantization limit cycleBeware

ClockClockfrequencyfrequency

2V11V

33V


UPM

Seminar indexSeminar index

PowerPower converterconverterSignalSignal conditioningconditioningADCADC

DPWMDPWMDriversDriversRegulatorRegulatorDesignDesign flowflow

212211

Hardware issues222Motivation111

Applications333

Dc-dc converter for DVS444Conclusions and references555

MultiphaseMultiphase converterconverterPSU for RF PSU for RF amplifieramplifier

PFC PFC ConverterConverter

222222

232233

242244

252255

262266

272277

313311 323322

333333

4


UPM

2 Hardware 2 Hardware IssuesIssues indexindex

Powerconverter

PowerPowerconverterconverterDriversDriversDriversDPWMDPWMDPWMRegulatorRegulator

Vout(t)dk VGS(t)VSWkekVrefk+

-

SignalSignal conditioningconditioningVmeask

ADCADCVmeas(t)



212211

Hardware issues222

222222

232233

242244

252255

262266

272277

Digital Digital SchemeScheme


UPM

21 21 PowerPower converterconverter

H G(s)

G(z)

Hold Sampler

Vout

t

Digital controllersneed G(z)

Evaluatedevery Tsamp

Tsamp = N middot Tswitch (Nge1)

In dynamics-critical applications N = 1

Tsamp = Tswitch

Averaging amp Linearization

G(s)Valid for freqs lt fswitch and aroundone working point

Beware

Powerconv

PowerPowerconvconvDrivDrivDrivPWMPWMPWMRegRegReg

+

-

ADCADCADC Signal condSignalSignal condcond

5


UPM

21 21 PowerPower converterconverter exampleexample

Buck converter(linear converter)

1st approach L C RLOAD

2nd approach RL ESR

VindC

ESRVind C RLOAD

+

_

L

Vout

)s(ds

RLsmiddotCmiddotL

V)s(V

LOAD

inout

12 ++=

RLOAD Vout+

_

Parameter characterization through measurement(eg time response losses hellip)

L RL

( ))s(d

RESRRRsC

RESRRESRCR

RESRLsmiddotCmiddotL

VsCESRRESR

R

)s(V

LOAD

LOADL

LOAD

LOADL

LOAD

inLOAD

LOAD

out

++

+⎥⎦

⎤⎢⎣

⎡sdot

+sdot

+sdot++

+

sdot+sdotsdotsdot+

=2

1


UPM

21 21 DiscretizationDiscretization ofof G(sG(s))

HO G(s)

Zero-orderHold Sampler

G(z)

Powerconverter

PowerPowerconverterconverterPWMPWMPWM ADCADC

The zero order hold includes the effect of thePWM not considered in analog controllers

(VGS is digital (binary) in its nature)

More accuracyMore accuracyGood prediction up to fsamp = fswitch

Matlab functionC2D(G(s)TSrsquozohrsquo)

6


UPM

22 22 SignalSignal conditioningconditioning

Resistor Resistor dividerdivider

Power

converter

Basic low-pass filter

Choose RC such asffilter gtgt fdynamics and

ffilter lt fswitch (if possible)

VeryVery simplesimpleLowLow componentscomponents countcount lowlow costcost lowlow sizesizeBadBad noisenoise responseresponseIn In symmetricalsymmetrical inputinput voltagevoltage rangerange ADCsADCs ((egeg --1V 1V toto +1V) +1V) halfhalf resolutionresolution isis usedused andand worseworsenoisenoise response (response (halfhalf rangerange isis usedused))CommonCommon modemode voltagevoltage notnot controllablecontrollable

ADCBeware

Powerconv


+

-



UPM

22 22 OperationalOperational amplifieramplifier conditioningconditioning

More More componentscomponents costcost andand sizesizeBetterBetter noisenoise responseresponsePossiblePossible offsetoffset for for symmetricalsymmetrical inputinputvoltagevoltage rangerange ADCsADCsCommonCommon modemode voltagevoltage notnot controllablecontrollable

V+

V_

+_

Voffset

R1

R1

R2

R2

ADCVout

Pow

erco

nver

ter

_+

7


UPM

C

R2

22 22 DifferentialDifferential amplifiersamplifiers

Best Best noisenoise responseresponseADC can control ADC can control thethe commoncommon modemodevoltagevoltage

Circuit for SAMPLE amp HOLD compatibilityat high frequencies

V+

V_

ADC

Vref

R1

R1

Vcm

_

++_

ADC

R2

C


UPM

23 ADC (23 ADC (AnalogAnalog toto Digital Digital ConverterConverter))

TwoTwo digital digital effectseffects

DISCRETIZATIONR(z) hArr fSAMP

QUANTIZATIONN bits for each variable

Always taken into account sincelsquozrsquo transfer functions include it

Not taken into account in lsquozrsquotransfer functions Must be considered in actual digital implementations

V

t

ΔtV

t

ΔV

Beware

Powerconv


+

-


8


UPM

23 23 SlowSlow ADCsADCs ΣΣΔΔ amp SAR amp SAR ((sucessivesucessive approximationapproximation registerregister))

TSWITCH

TADC TPROCTDRIVER

If fsamp = fSWITCH we needfADC ge fSWITCH

fsamp up to 100 kSPS(kilo Samples Per Second)

However the switching cycle isdivided in more than one task

Other types of ADCabove 1MSPS

OtherOther typestypes ofof ADCADCaboveabove 1MSPS1MSPS

Therefore we needTADC lt TSWITCH

In many applications (eg dynamics-critical) other ADCs are necessary

High number of bits with low cost

Low sampling frequency


UPM

23 23 FastFast ADCsADCs flash flashpipelinedpipelined

High fADC butADC

latADC fNT 1

=

latencystages

stage perbitsstages

totalbit

NN

NN

N

=

= minusminus

latencyBeware

latency

High sampling frequency Latency

9


UPM

23 23 SpecificSpecific ADCsADCs

SuitableSuitable ifif VVrefref = = constantconstant ((mostmost DCDC--output output convertersconverters))HighHigh ADC ADC resolutionresolution aroundaround VVrefref usingusing fewfew bitsbits

25075

25050

25025

25000

24975

24950

24925

1 1 1

1 1 0

1 0 1

1 0 0

0 1 1

0 1 0

0 0 1

0 0 03-bits flash converter33--bits flash bits flash converterconverter

Eg Vref=25VComparators at levels

(25mV resolution)

3-bits ADC equivalent to a 10 bits ADC for full range

voltage

⎟⎠⎞

⎜⎝⎛ = VV 00250

25210

Saturation

High precision with lownumber of bits


UPM

23 23 AvoidingAvoiding noisenoise atat highhigh samplingsampling ratesrates (I)(I)

Stopping the ADC clockat very high fADC

Noise free sampling instant(avoiding switching)

More difficult inmultiphase converters

Best options

ADC-CLK

N

LATCHINSTANT

Time for stability amp propagation

DATA N-3 N-2 N-1 N

Allows easy synchronization between thecontroller and the ADC

10


UPM

23 23 AvoidingAvoiding noisenoise atat highhigh samplingsampling ratesrates (II)(II)

Low pass filters

Oversampling (fADC=Mmiddotfsamp typically Misin[216]) and internal digital filter suitable for FPGAs amp ASICs

s11)s(Fτ+

=T

bT

bzbb

)s(F τ=

τ+=

minus=

minus 10110

11Derivative operator (I)

Bilinear approximation (II) Tb

Tb

zbbz)s(F τ

minus=τ

+=+

+=

minus

minus 21211101

10

1

Special HW simplification when( )12middotT m minus=τ(I)

(II) ( )502middotT 1m minus=τ minus

TSWITCH

TADC TPROC

TDRIVER

TADC TADCTADC

Tfilter

Samp1

Samp2

Samp3

Samp4

1 noise-freesample

Intermediate value filters

D QD Q

lt gtAvoid greatest andlowest value

High inmunity for single wrong samples


UPM

24 DPWM24 DPWM

Counter

refgt on_off

Basic Basic synchronoussynchronous versionversion

Eg fSWITH = 500kHz and8bits DPWM resolution

For relatively high fSWITCH fCLK grows above

desirable frequencies

SWITCH

CLK

ff)DPWM(solutionRe =

fCLK = 128 MHz

Beware

Powerconv


+

-


11


UPM

24 24 AvoidingAvoiding limitlimit cyclingcycling

A Peterchev S Sanders Transactions PELS January 2003

If Resol (DPWM) lt Resol (ADC)the converter ldquoswingsrdquo at steady sate

PWM63

PWM62

PWM61

Vref

error3

error2

error1

error0

error-1

error-2

Conditions for the eliminationof limit cycles

111 Resol (DPWM) gt Resol (ADC)Resol (DPWM) gt Resol (ADC)

222 Integral Integral termterm in in R(zR(z))

333 1 + 1 + N(AN(A))middotmiddotL(jL(jωω) ) nene 00

0 lt Ki le 1(Ki gain of the integral term

of the controller)

(Nonlinearity of quantizers)


UPM

24 24 RaisingRaising DPWM DPWM resolutionresolution (I)(I)

BewareBeware ofof clockclock frontiersfrontiersUsingUsing 2 2 externalexternal clocksclocks isis notnotrecommendedrecommendedUse Use anan internalinternal clockclock multipliermultiplier

Synchronous DPWM are simple blocks that can work at high frequencies

D QgtCounterCounterCounter

(Counter amp comparator)

Using 2 different clocksA fast clock for the DPWMA slow clock for the rest

In most FPGAs there are DLL orsimilar blocks

DLL(x N)DLLDLL(x N)(x N) DPWM

Transfer function andauxiliar logic

TransferTransfer functionfunction andandauxiliar auxiliar logiclogic

CLKCLK2

Vout

VGS

dk

Raising DPWM resolution rArr raising fCLK

Beware

12


UPM

24 24 RaisingRaising DPWM DPWM resolutionresolution (II)(II)

Asynchronous DPWM N-bits DPWMM synchronous bitsL asynchronous bits

N = M + L2L phase-shifted clocks neededPhase-shifted clocks

0ordm 90ordm 180ordm 270ordm

PhasePhase--shiftedshifted clocksclocks

00ordmordm 9090ordmordm 180180ordmordm 270270ordmordm

CLK

MUX

SyncPWMSyncSyncPWMPWM

S QR

VGS

duty(1)duty(0)

end of sync duty

start switching cycle

duty(n-12)

Example(L=2)

Bewareof thedelay

Very dependent onvariable conditionsand synthesis results


UPM

24 24 MultipleMultiple outputsoutputs in DPWMin DPWM

HighHigh andand lowlow switchswitch control in control in synchronoussynchronous convertersconverters(V(VGHGH amp Vamp VGLGL withwith programmableprogrammable deaddead times)times)

MultiMulti--phasephase convertersconverters andand phasephase shiftersshifters for for interleavinginterleaving

VGHVGL

Phase-shifted outputs

Tswitch

delay

13


UPM

Delay to be taken into account fordynamic responsestability

25 25 DriversDrivers

Beware

In Z-transfer functionsIf Td=NmiddotTsamp rArr multiplying by Z-N

Adding a delay in s-transfer functions rArr multiplying by e-TdmiddotS (Td delay)

If Td=(1-m)middotTsamp rArr advanced Z-transform (also known as modifed Z-transform)(misin(01))

sum minusminus +=k

k1 Z)middotT)mk((fmiddotZ)mz(F

m=0 rArrTd=Tsamp m=1 rArr no delay

Driver examples

UC2710 rArr35nsIR2110 rArr 100ns

Current unbalance caused by differences in ton ndash toff rArrDifferences in the duty cycle of each phaseMultiphase converters

Change in effective duty cycle(compensated by the regulator in closed loop operation)Delay ON (ton) ne delay OFF (toff)

The important parameter is not the delay but the dispersion of the delayTheThe importantimportant parameterparameter isis notnot thethe delaydelay butbut thethe dispersiondispersion ofof thethe delaydelay

VSW

VGS

ton toff

Powerconv


+

-



UPM

26 26 RegulatorRegulator linear linear oror nonnon--linearlinear

Linear controlLinear controlLinear control Non-linear controlNonNon--linear controllinear control

Transfer function Any other

zbb

zaa)z(R 110

110

++++

= minus

minus

ai bi constants

Digital implementationallows multiplepossibilities

In same cases combinations of both

Examples of non-linear controls are studied in the

application examples

Advantages of non-linear controlsIncreases bandwidthTaking into account actuation limits (eg duty

isin[01])Robustness (parameter variation)Stability-bandwidht trade-off is improved

Main disadvantage complexity

EgPeak current(analog or digital)Hysteretic(analog or digital)Fuzzy logic(digital)

Powerconv


+

-


14


UPM

zoh

foh

matched

NA

tustin

Matlab C2D

26 Linear 26 Linear regulatorregulator designdesign (I)(I)

Once Once thethe continuouscontinuous regulatorregulator isis designeddesigned ((R(sR(s)) )) itit isis discretizeddiscretizedThereThere are are differentdifferent methodsmethods

Zero order hold or step invariant

First order hold

Polezero match

Backward Euler derivative operator or rectangular integration

Blinear Tustin or trapezoidal integration

Two possibilities

Analog regulator designand discretization of regulator

Discretization of power converterand digital regulator design

)z(R)s(R)s(G rArrrArr )z(R)z(G)s(G rArrrArr

The regulator is designed using the analog design methods (eg frequency response)

C2DDifferent methods(zoh foh tustin matched)

C2DUsing always ldquozohrdquo(zero order hold)

Recommendedby Duan APEC 1999


UPM

26 Linear 26 Linear regulatorregulator designdesign (II)(II)

)z(R)s(R)s(G rArrrArr

)z(R)z(G)s(G rArrrArr

RootRoot locuslocusDifferent methods

DirectDirect synthesissynthesis oror TruxalTruxal methodmethodDeadDead--beatbeat controllerscontrollers

Always better than discretization of continuous regulators

Two mains reasons

R(s) is designed but R(z) (which isonly similar to R(s)) is used

The best option is to design R(z) directly

G(s) rArrG(z) C2D(zoh) includes the effect of the PWM

R(s)rArrR(z) implies worsering of dynamic response

FrequencyFrequency responseresponse

15


UPM

26 Linear 26 Linear regulatorregulator designdesign (III)(III)

NotNot so so directdirect as in as in analoganalog desigdesig ((indirectindirect methodsmethods))


Time domain methods are preferible to frequency domain ones because

Frequency methods are suitable only for linear control of linear systems

Digital control is based on time domaindiscrete functions


UPM

26 Linear 26 Linear regulatorregulator designdesign (IV)(IV)

((oror TruxalTruxal methodmethod alsoalso knownknown as as RagazziniRagazzini methodmethod))

DirectDirect synthesissynthesis

TheThe objetive objetive isis toto choosechoose thethe closedclosed--looploop response response exactlyexactly

)z(G)z(R1)z(G)z(R

)z(X)z(Y)z(M

+==

))z(M1)(z(G)z(M)z(R

minus=

Choosing M(z) the controller for that closed-loop TF is

Causality order (den(M(z)) ndash order (num(M(z)) ge order (den(G(z)) ndash order (num(G(z)))Stability 1-M(z) has as zeros all the unstable (or near unstable) poles of G(z)

M(z) has as zeros all the unstable zeros of G(z)

Simplicity Same condition but with all the zeros (not only unstable ones)

Beware

Ideally any response is possible Some restrictions

+ Y(z)

_

E(z)X(z)R(z) G(z)

16


UPM

26 Linear 26 Linear regulatorregulator designdesign (V)(V)

DeadDead--beatbeat controllerscontrollers

The objective is to eliminate the error completely in a finite (and small) number of samplescycles

CONDITION error )z(PZmiddote)z(E 1

k

kk

minusminus == sum No denominator in the error

When the input is a step 1z11)z(Z minusminus

=

⎪⎭

⎪⎬⎫

⎪⎩

⎪⎨⎧

minusminus=

minus=minusrArr

minusminus

=minusminus

minusminus

minus )z(P)z1(1)z(M)z(P)z1()z(M1

z1)z(M1)z(E

11

11

1As rArr Now use ldquodirect synthesisrdquo

Drawbacks of direct synthesisdead-beat

Very precise G(z) characterization is necessary (very sensitive to parameter variation)

Only suitable for a single working point (eg only one load condition)

If high dynamic response is requested rArr duty cycle saturation (dtheor notin [01])

Dynamic response is limited by the L-C filter


UPM

26 Linear 26 Linear regulatorregulator designdesign (VI)(VI)

10

p1=e-σmiddotejθ

p2=p1=e-σmiddote-jθ

θ

γe-σ

(time (time domaindomain designdesign))RootRoot--locuslocus

Desirable closed-loop poles location

Settling number of samplesσπ

=sR

Overshoot peak θσπ

minus= eMp

DesirableDesirable conditionsconditionsLow settling time rArrσuarrrArrclosed-loop poles near the originLow overshoot rArrσuarr amp θdarrrArrclosed-loop polers near the real axis

((AvoidAvoid negativenegative real real partpart ofof thethe circlecircle))

17


UPM

26 26 DesignDesign exampleexample (I)(I)

xx

xx

OO

Pole zero mapMultiphase buck converter (4 phases)

Inductor Inductor resistanceresistance((perper phasephase)) 68m68mΩΩ

InputInput voltagevoltage 28V28VNo No ofof phasesphases 44SwitchingSwitching freqfreq 250kHz250kHzInductanceInductance ((perper phasephase)) 1010μμHH

CapacitorCapacitor ((perper phasephase)) 2222μμHH

ESR (ESR (perper phasephase)) 15m15mΩΩ

96730middot29412239middot6229)(

110middot826110middot22110middot3328)(

2

7211

8

+minus+

=

+++

= minusminus

minus

zzzzG

ssssG

(No load rArrworst stability

condition)

C2D(G1250e3rsquozohrsquo)


UPM

26 26 DesignDesign exampleexample (II)(II)

((fromfrom MatlabMatlab))SisotoolSisotool

P regulator R(z)=10-5

Vout

Duty

Near unstable

Steady-state error gt 99

Integral term necessary

18


UPM

26 26 DesignDesign exampleexample (III)(III)

PI PI regulatorregulator

1z110)z(R 5

minus= minus

Vout

Duty

Order (den (regulator))gt order (num (regulator))

Allows practical implementation (explained)

Stable amp no error in steady-state

Very slow (ns=10000 samples)

Branches going outside the unit circle rArrvery small gain rArr very slow


UPM

26 26 DesignDesign exampleexample (IV)(IV)

PID PID regulatorregulator

)7330z)middot(1z(730Z10middot558)z(R 4minusminus

+= minus

Vout

Duty

Locate pole amp zero trying to take the branchesinside the unit circle


Dynamics improved considerably(ns=25 samples)

19


UPM

26 26 DesignDesign exampleexample (V)(V)ImprovedImproved linear linear regulatorregulator

Vout

Duty

Digital implementation allows using more poles andzeroes even pair of complex poleszeroes

Dynamics improved even further(ns=15) and overshoot decreased atthe same time


)3820z5790z)middot(1z(z)8480z9590z(10middot35)z(R 2

23

+minusminus+minus

= minusMuch accuracy amp repetitibility in the controller (allimplementations are exactly the same)

2 2 zeroeszeroes4 4 polespoles


UPM

26 26 ImplementationImplementation ofof thethe controllercontroller

xk xk-1

hellip

xk-m

X

b0

X

b1

X

bm

hellip

+

+

hellip

+

yk yk-1

hellip

yk-n

X

a1

X

an

+

+

hellip

hellip

+

-yk

nn

22

110

mm

22

110

zazazaazbzbzbb

)z(e)z(d)z(R

minusminusminus

minusminusminus

sdot++sdot+sdot+

sdot++sdot+sdot+== nkn1k1mkm1k1k0k dadaebebebd minusminusminusminus sdotminusminussdotminussdot++sdot+sdot=

The transfer function R(z) is not implemented but its equivalent difference equation

TF Difference equation

(a(a00=1 for =1 for normalizationnormalization))

20


UPM

Z-1

a1

a2

Z-1

26 Canonical 26 Canonical formform

Z-1

bo

eK

Z-1

b1

b2

R1(z) R2(z)YK

dK

eK

R1 R2

Z-1

Z-1

a1

bo

b1

dKeK

Half memory elements

Half variables(in DSPs or μCs)

Half registers(in FPGAs or ASICs)

Higher values in theregisters (more bits)


UPM

Difference equation

26 Delta 26 Delta transformtransform (I)(I)

a1a2

e(z)

⎩⎨⎧

rarrδ

+=δminus=δ= δδ+

sUmiddotBXmiddotAXmiddot

TXXXmiddotY kkkk1k

kk

Tz1 1minusminus

=δ

k1

1k

1k Y

z1zTYXminus

minusminus

minus

sdot=δ=

δ-1 δ-1

aman

δ-1 δ-1

bm

+

bo

b1

u(z)h(z)

T Z-1

δ-1

(Integral)

+

Numerical robustness

Less bits are necessary

Digital Digital implementationimplementation

More adders

21


UPM

a1

a2

δ-1

bo

b1T

b2T2 δ-1 T2

T

26 Delta 26 Delta transformtransform (II)(II)

Tn Tn

Taking out the T multiplier of δ-1 into the coefficients

Z-1

+


bboo isis eliminatedeliminatedifif orderorder (den) gt (den) gt orderorder ((numnum))TheThe newnew coefficientscoefficients are are TTiimiddotmiddotaaii TTiimiddotmiddotbbiiaann=0 =0 ifif KKiinene0 (integral action)0 (integral action)

Adapted δ-1


UPM

26 26 Order(denOrder(den) gt ) gt Orden(numOrden(num))

Really convenient for practical implementation especially for high fSAMP

If order (den) = order (num) rArr dk = bomiddotek+hellip

DutyDuty cyclecycle mustmust be be changedchanged ((theoreticallytheoretically) ) atat thethe samesame time a time a newnewsamplesample isis receivedreceived withwith a a sampledsampled periodperiod ofof ((theoreticallytheoretically) 0 ) 0 nsns

If order (den) gt order (num) rArr dk = b1middotek-1+hellip

We have a full cycle for all the process

sampling period processing

ek-1 isrequested

ek-1 isavailable

dk isimposed

T

22


UPM

0 1 2 3 4 5 6 7 8

x 10 -4

-04

-02

0

02

04

06

08

1

12

14

16

26 Number of bits26 Number of bits

δδ--11 using 8using 8--bitsbitszz--1 1 using 8using 8--bitsbits

Ideal (floating point)Ideal (floating point)

vo

48 5 52 54 56 58

10-4

138

14

142

144

146

148

15

152

154

156

vo

Matlabfixed-point

toolbox

CoefficientsCoefficients amp variables are amp variables are implementedimplemented usingusing fixedfixed pointpoint formatformatFPGAsFPGAs ampampASICsASICs allowallow usingusing anyany numbernumber ofof bitsbitsfor for eacheach variablevariableDSPsDSPs amp amp μμCs use multiples of 8Cs use multiples of 8

FloatingFloating pointpointdemandsdemands too too manymanyresourcesresources andandprocessingprocessing timetime

Low number of bits rArr big differences between ideal model amp practical implementation

δδ--11 allows less number of bitsallows less number of bits


UPM

26 26 AdjustAdjust coefficientscoefficients toto powerspowers ofof twotwo

nkn1k1mkm1k1k0k dadaebebebd minusminusminusminus sdotminusminussdotminussdot++sdot+sdot=

00011111b0 =

1rsquos Maximumerror

Meanerror

22 143143 5252

11 333333 170170

44 3232 0606

33 6767 1717

Transf func Gates Delay

615615 105ns105ns

12481248 168ns168ns

Mp ts

Example

160160 012ms012ms

113113 011ms011ms1

124640152middot0minusminus

zz

( )1

222 353

minusminus+ minusminusminus

zz

Useful in FPGA or ASIC implementations

00101000b0 = k53

k5

k3 e)22(e2e2 sdot+=sdot+sdot minusminusminusminus

00101001b0 = k853

k8

k5

k3 e)222(e2e2e2 minusminusminusminusminusminus ++=sdot+sdot+sdot

222

333

Multiplier substituted by 1 adder

Multiplier substituted by 2 adders

00100000b0 = k3 e2 sdotminus111

Shift-operation rArr no resources(only appropriate connections)

1rsquos

23


UPM

26 26 MaximumMaximum workingworking frequencyfrequency

Two solutionsa) Setting the synthesizer

to ignore the transferfunction for time purposes

b) Using pipeline(inserting alwaysenabled registers)

D QEN

new_cycle Xek

b0

D QEN

new_cycle Xek-1

b1

+

D QEN

new_cycle Xdk-1

a1

D QEN

new_cycle Xdk-2

b2

+ D QENnew_cycle

dk

+

decreased critical path

D Q

D Q

D Q

D Q

D Q

D Q


The critical path is almost always in the transfer functionSynchronous DPWM rArr raising fCLK rArr decreasing critical path (longest combinational delay)

eeii d dii registersregisters are are enabledenabled onlyonlyonce once everyevery switchingswitching cyclecycleThereThere are are Resol(DPWMResol(DPWM) ) clockclockcyclescycles in in eacheach switchingswitching cyclecycleThisThis isis NOT NOT thethe truetrue criticalcriticalpathpath

ldquofalserdquo critical path


UPM

Fixed-point toolbox

27 27 DesignDesign flowflow (I)(I)

Design R(z) rArr MatlabsisotoolDesignDesign R(zR(z) ) rArrrArr MatlabsisotoolMatlabsisotool

Simulation of transfer functionSimulationSimulation ofof transfertransfer functionfunction

Simulation with switched modelsSimulationSimulation withwith switchedswitched modelsmodels

Simulation including bits ADCampPWMSimulationSimulation includingincluding bitsbits ADCampPWMADCampPWM

Simulation including bits internal variablesSimulationSimulation includingincluding bitsbits internalinternal variablesvariables

MatlabSimulink

Convert regulator (Matlab model) to VHDL-VerilogC-assemblerConvertConvert regulatorregulator ((MatlabMatlab modelmodel) ) toto VHDLVHDL--VerilogVerilogCC--assemblerassembler

HDLC simulation (only to verify there are no conversion errors)HDLC HDLC simulationsimulation ((onlyonly toto verifyverify therethere are no are no conversionconversion errorserrors))

24


UPM

VHDL or VHDL-AMS

27 27 DesignDesign flowflow (II)(II)



Convert regulator (R(z)) to VHDL-VerilogC-assemblerConvertConvert regulatorregulator ((R(zR(z)) )) toto VHDLVHDL--VerilogVerilogCC--assemblerassembler

HDLC simulation including all the effects (switched model amp bits)HDLC HDLC simulationsimulation includingincluding allall thethe effectseffects ((switchedswitched modelmodel amp bits)amp bits)

Simulation of transfer function rArr MatlabsimulinkSimulationSimulation ofof transfertransfer functionfunction rArrrArr MatlabsimulinkMatlabsimulink

Verilog or Verilog-AMS

C or mixed signal tool

Create power converteramp ADC modelMixed-signal simulation


UPM


Applications333


PFC PFC ConverterConverter313311

323322

333333

25


UPM

31 PFC 31 PFC ConverterConverter PowerPower StageStageFlyback converter working as Power Factor CorrectorFlyback converter working as Power Factor CorrectorFlyback converter working as Power Factor Corrector

IinVin

Vout

DCDCREGULATOR LO

AD

~

IoutIin

PFC ACDCPRE-REGULATOR

Vout

+_Vin

CONTROL

d

R1

R2

R3

R4

n1 n2LINE

LOAD

Main Switch

Vin

Iin Vout

PO=50Wf=50kHz

CCM (for testing purposes)

PO=50Wf=50kHz



UPM


Interesting in this applicationInteresting in this applicationInteresting in this application


Influence of the sampling delay

Adaptive control

Illustrate design flow (option 2)

LOA

D

~

IoutIin

PFC CONVERTERVout

+_Vin

Controlblock

Controlblock

onoff

R1

R2

R3

R4

Vout

Iin

Vin

ADCADC

ADC

26


UPM

31 Control 31 Control overviewoverview

X

Measured VINMeasured VIN

IIN-ref

Protections

Control signal goes directly to the driver (no need for PWM)

VOUT max

IIN max

ldquodrdquo max

ldquoΔdrdquo max

ON-OFF Main Switch

ON-OFF Main Switch

Fast loop controls Iinthrough Gin to attain PFC

(Iin = Vin middot Gin)



intΣIin

gt

CalculatedOn-Off

Measured IINMeasured IIN

Max

Measured VOUTMeasured VOUT

Slow loop controls Voutchanging the input

resistance (Gin = 1 Rin)



VOUT-ref

GinPI


UPM

31 31 FastFast looploop ((VVinin--IIinin) ) -- attainingattaining PFCPFC

Charge control mean Iin through integration rArr adder in digital versionCharge control Charge control mean mean IIinin through through

integration integration rArrrArr adder in digital versionadder in digital version

Desired mean Iin valueVinmiddotGin

(Gin imposed by the slow loop)



Enabled by theFPGA concurrency


VinGin

Multiplier

xVin

Gin(1Rin)

50 kHz

MOSFET on until the Iin adder reaches VinmiddotGin


Adder

+Iin

ΣIin

Comparator

gtOnOff

20 MHz

NoPWMNoPWM

Easy implementation of charge control

27


UPM

31 31 StabilityStability analysisanalysis

Variation of the plant with loadVariable delay in the voltage loop(control of the maximum)

Variation of the plant with loadVariation of the plant with loadVariable delay in the voltage loopVariable delay in the voltage loop(control of the maximum)(control of the maximum)

10 W 30 W 50 W 30 W 10 W

Vout

IinGin

StableStable

Load

InstabilityInstabilityInstability

Unstable

Unstable

Unstable

Unstable


UPM

31 31 SolvingSolving StabilityStability problemsproblems

Solution adaptive controlSolution adaptive controlSolution adaptive control

Original regulator (25 load)Original regulator (25 load) Modified-k regulator (25 load)Modified-k regulator (25 load)

Adaptive control

28


UPM

31 31 SolvingSolving stabilitystability problemsproblems

Low Load DetectionConstant Changed

Load Change

Vout

Iin

This is an important advantage of the digital controlThis is an important advantage of the digital control

Full loadFull load Sampling delay introduces a zero in the TF

Sampling delay introduces a zero in the TF

T



UPM

Vin_dc

Iin_dc

d

Vout

31 31 Experimental resultsExperimental results

OnOff

FPGAXilinx

XC4010-e

8 8 12

Vin Vout Iin

PROMXC 17512

ADC0808

ADC0808

HI 5805

FPGA fCLK = 20 MHzFPGA fCLK = 20 MHz

ADCsADCs

Power Converter

Vout Vin_acIin_ac

PF = 099PF = 099PF = 099

29


UPM

31 Complete 31 Complete simulationsimulation schemescheme

DigitalController

ControlSignals(for the

switches)Digital

SwitchingPower Converter

Measuredamp State

Variables(real type)

Analog

ADConverter

MeasuredVariables

(digital buses)

Mixed

How to simulate the complete systemHow to simulate the complete system

Closed-loop as the best way to validate the controllerClosedClosed--looploop as as thethe best best wayway toto validatevalidate thethe controllercontroller


UPM

31 31 PowerPower ConverterConverter VHDL VHDL ModelModel

M1

C Vout

D11n

+

_Vin

Iin

IL1

RL

IR

ON

L1OFF

M1

C Vout

D11n

+

_Vin

Iin

IL1

RL

IR

OFF

L1ON

Vout

n

ID1 = IL1 n

IC

Obtaining the differential equations for each circuit state (depending on the switches)Translating the differential equations to finite difference equationsCoding the finite difference equations in VHDL


1

kin1k1Lk1L

1L1in L

tVII

dtdILV

Δsdot+=rArr= minus

CtI

VVdt

dVCI kR1koutkout

outR

Δsdotminus=rArrminus= minus

1

1kout1k1Lk1L

1L1

out

LntV

IIdt

dILnV

sdotΔsdot

minus=rArr=minus minus

minus

C

tIn

I

VVdt

dVCInI kR

1k1L

1koutkoutout

R1L

Δsdot⎟⎟⎠

⎞⎜⎜⎝

⎛minus

+=rArr=minus

minus

minus

Simple model fast simulationNon-synthesizable VHDLSimple model fast simulationNon-synthesizable VHDL


30


UPM

31 VHDL 31 VHDL vsvs VHDLVHDL--AMS AMS ComparisonComparison

VHDLVHDLVHDL

VHDL-AMS

VHDLVHDL--AMSAMS

Flyback converter working as Power Factor Corrector (PFC)

Input currentInput current Output voltageOutput voltage

Models validation throughexperimental results



UPM


Control over the model (changing thetime-step or results file size)


VHDLVHDL

Available tools (VHDL std in 1987 VHDL-AMS std in 1999)


Easy model creation (schematics and no finite difference equations)


Results visualization (analog waveformsdisplayed by the simulator)


Simulation timeSimulation time

Simulationtime

SimulationSimulationtimetime

CPU time using VHDL

models

CPU time CPU time usingusing VHDL VHDL

modelsmodels

CPU time using VHDL-AMS models

CPU time CPU time usingusing VHDLVHDL--AMS AMS modelsmodels

VHDL speed VHDL-AMS

speed

VHDL VHDL speedspeed VHDL VHDL--AMS AMS

speedspeed

10 ms10 10 msms 69 s69 s69 s 446 s446 s446 s 641641641

100 ms100 100 msms 700 s700 s700 s 6912 s6912 s6912 s 987987987

1000 ms1000 1000 msms 6890 s6890 s6890 s 68443 s68443 s68443 s 993993993

VHDLVHDL--AMSAMS

31


UPM

42V 14V

CC

CC 42V 14V

1000W BI-DIRECTIONAL DCDC CONVERTER1000W BI-DIRECTIONAL DCDC CONVERTERDual batterysystem vehiclesDual battery

system vehicles

VOUTIN VOUTVIN VOUTIN VOUTVIN

Q1-1

Q2-1

Q16-1

Q16-2

Q2-2

Q1-2

L

L

L

COCIN

32 32 Multiphase converter automotive ApplicationMultiphase converter automotive Application

Multiphase buck converterMultiphase buck converterMultiphase buck converter


UPM


Q1-1

Q2-1

Q16-1

Q16-2

Q2-2

Q1-2

L

L

L

COCIN




High number of phases (no current loops)

Implementations of the multi-DPWM

Reduce current ripple due to non-idealities

Change the number of phases dynamically

3 prototypes

8 phases PO=500W 16 phases PO=1000W36 phases PO=1000W

3 prototypes


Changing the operation mode

32


UPM

32 32 Current Balance CCM operationCurrent Balance CCM operation

VoVIN

L2d2

d1L1

Equivalent circuitEquivalent circuit

Current unbalance depends onDuty cycle differencesParasitic resistances


VINd1

Battery

R1

R2

+

+ +

VINd2

1

BAT1IN1 R

VdVI minus=

2

22 R

VdVI BATIN -=


UPM

32 32 Current Balance CCM operation 16 phasesCurrent Balance CCM operation 16 phases

Duty cycle (for 15 phases) 03368

Duty cycle phase 16 03402

Average phase current (A)

DC current in phases 1-15

DC current for phase 16

446

416

03360

03528

320

2336

523Maximumaverage currents ()

Duty cycle differences

1 5

CCM ndash 1000W

824

184

Not acceptable

Analog controllers need current loopsAnalogAnalog controllerscontrollers needneed currentcurrent loopsloops

Q1-1

Q2-1

Q16-1

Q16-2

Q2-2

Q1-2

L

L

L

33


UPM

AVGLI AVGLI

32 32 Current Balance DCM operationCurrent Balance DCM operation

dT T

LVV OIN minus

LVOminus

AVGLI

dT T

LVV OIN minus

LVOminus

AVGLI

⎟⎟⎠

⎞⎜⎜⎝

⎛ minus=

O

OIN

i

2iIN

i VVV

fL2dVI

CurrentCurrent balance balance dependsdepends ononDutyDuty cyclecycle differencesdifferencesInductanceInductance tolerancestolerances((ItIt doesdoes notnot dependdepend onon parasiticparasitic resistanceresistance))

Average Average phasephase currentcurrent isis lessless sensitivesensitive

AVGLI AVGLI

DCMDCM


UPM

32 32 Current Balance DCM operation 16 phasesCurrent Balance DCM operation 16 phases

03360

03528



Average phase current (A) 446

DC current for phases 1-15 (A) 320

DC current for phase 16 (A) 2336

416

824

523Maximumaverage currents () 184


1 5

CCM ndash 1000W

0262002623

0275102649


1 5

DCM ndash 1000W

Not acceptable

445

490

446

454

110102

Very good

Unbalance in DCM is better but there are higher rms currentsUnbalanceUnbalance in DCM in DCM isis betterbetter butbut therethere are are higherhigher rms rms currentscurrents

34


UPM

32 32 Experimental results with digital control 8 phases CCM Experimental results with digital control 8 phases CCM

Inductor currents (phases 246 and 8) Inductor currents (phases 246 and 8) 421 97Phase 1

420 97

435 100

440 101

435 -

DC Current(A)

429 99

428 98

446 103

460 106

Deviation()

Phase 2

Phase 3

Phase 4

Phase 5

Phase 6

Phase 7

Phase 8

Average

CCM

Maximum current is 6 higher than the averageMaximum current is 6 higher than the average

IO=35A

Very good current unbalance with digital control in CCMVeryVery goodgood currentcurrent unbalanceunbalance withwith digital control in CCMdigital control in CCM

The high accuracy of the digital device reduces unbalance


UPM

32 32 Control blocks DCM generationControl blocks DCM generation

ADCInterface

ampfilter

Regulator8

d1

H-Pulses 16 L-Pulses12

Vout

ADCcontrol

Reset

Vin

12

MCDgenerator

12

Vout

12

Vin

Phase-shifter

8

d2

Protections

1616

Clock

16

H-Pulses L-Pulses

FreeFree--wheelingwheeling OnOn--Time Time isis calculatedcalculated fromfrom d Vd VININ andand VVOO

AccuracyAccuracy isis desirabledesirable sincesinceShorterShorter times times forceforce thethe conductionconduction ofof diodesdiodesLargerLarger times times involveinvolve negativenegative currentscurrents

Very easy to change theoperation mode

35


UPM

32 32 Experimental results with digital control 8 phases DCMExperimental results with digital control 8 phases DCM

Inductor currents (phases 135 and 7)Inductor currents (phases 135 and 7)

425 98Phase 1Phase 1

422 97

438 101

442 102

434 -

DC Current(A)

431 99

445 102

424 98

448 103

Deviation()

Phase 2Phase 2

Phase 3Phase 3

Phase 4Phase 4

Phase 5Phase 5

Phase 6Phase 6

Phase 7Phase 7

Phase 8Phase 8

AverageAverage

DCMDCM

Maximum current is ONLY 3 higher than the averageMaximum current is ONLY 3 higher than the average

IO=17A

IO=27A


UPM

32 36 32 36 phasesphases prototypeprototype

Power phase 28WSMD InductorsTransistors 2 in a SO-8No current loops


Digital control allows the use of a high number of phasesDigital control Digital control allowsallows thethe use use ofof a a highhigh numbernumber ofof phasesphases

36


UPM


-05

0

05

1

15

2

00E+00 50E-06 10E-05 15E-05 20E-05 25E-05t (s)

()

-05

0

05

1

15

2

00E+00 50E-06 10E-05 15E-05 20E-05 25E-05t (s)

()

0

20

40

60

80

100

120

140

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35

Phase number

[+6-8]

0

20

40

60

80

100

120

140

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35

Phase number

[+6-8]

Half load(500W)

CurrentCurrent waveformswaveforms DC DC currentcurrent

Full load(1000W)

0

1

2

3

4

p

0 5μs 10μs 15μs 20μs0

1

2

3

4

p

0 5μs 10μs 15μs 20μs

Very good current balance without current loops

0

20

40

60

80

100

120

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35

Phase number

+10-75

0

20

40

60

80

100

120

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35

Phase number

+10-75

Current loops can be avoidedusing digital control


UPM

Output currentDC AC

11App

70ADC

Due to tolerances in inductances ideal cancellation is not achievedDueDue to tolerances in inductances ideal cancellation is not achieveto tolerances in inductances ideal cancellation is not achievedd

is

0 01 02 03 04 05 06 07 08 09 100102030405

060708091

Duty cycle (d)

Nor

m c

urre

nt r

ippl

e Dutyvariation

2 phases

3 phases

Ripple cancellationRipple cancellation

32 32 Ripple cancellation in multiphase convertersRipple cancellation in multiphase converters

37


UPM

10

5

5

10

3T0 x

5

5

3T0 x

Ideal case

The hardware is the same for all shown casesThe solution only requires changes in the triggering sequenceApplicable in those cases with current sensing (1 or n)


32 32 Example 8 phases d=033Example 8 phases d=033

Overall current ripple asymp 2A

Current ripple per phase = 15A

10

5

5

10

3T0 x

5

5

3T0 x

Non-ideal


1 phase has 18A currentripple (20 more)

10

5

5

10

3T0 x

5

5

3T0 x

Worse case


2 consecutive phaseshave 18A current

10

5

5

10

3T0 x

5

5

3T0 x

Solution toworse case


Those phases are 180ordmdelayed


UPM

ΔIP-P= 40A (5Adiv)

1 phase

ΔIP-P= 12A (5Adiv)

2 phases

ΔIP-P= 5A (5Adiv)

4 phases

ΔIP-P= 22A (1Adiv)

8 phases

ΔIP-P= 16A (1Adiv)

16 phases

With 8 and 16 phases non-idealities are very importantThe logical order of the triggering sequence is importantWith 8 and 16 phases non-idealities are very importantThe logical order of the triggering sequence is important

32 32 MeasuredMeasured output output currentcurrent (16 (16 phasesphases prototypeprototype andand VVIN=10V)=10V)

38


UPM

(a)

30

31

22 40

37

22 33

2830

31

22 40

37

22 33

28

(a)

Center of mass

(a)

30

31

22 40

37

22 33

2830

31

22 40

37

22 33

28

(a)

Center of mass

Phase1Phase

2

Phase3

Phase4

Phase5

Phase6

Phase7

Phase8

1st

2nd

3rd 4th

6th

5th 8th

7th

(b)

1st

2nd

3rd 4th

6th

5th 8th

7th

1st

2nd

3rd 4th

6th

5th 8th

7th

(b)

40 A

37 A30 A

33 A

22 A 28 A

31 A

22 A

Prior to normal operation the digital controlFirst switches each phase individuallyStores the phase current rippleAssigns the pre-calculated order


Digital control may help to reduce output current ripple

32 32 Reduction of the impact of nonReduction of the impact of non--idealtiesidealties


UPM

18 0 18

18

18

OVERALL 67A

18 0 18

18

18

1

2

34

56

7

8

9

10

1112 13

14

15

16

MAX

MIN

18 0 18

18

18

OVERALL 05A

18 0 18

18

18

1

2

34

56

7

8

9

10

1112 13

1415

16

MAX

MIN

32 32 SwitchingSwitching starstar optimizationoptimization

16151413121110987654321

Phase number

165155177152140144148128147122154158139149142133

Current ripple (A)

39


UPM

ΔIP-P= 40A

ΔIP-P= 40A

ΔIP-P= 07A

ΔIP-P= 16A

57

ΔIP-P= 11A

ΔIP-P= 22A

50

ΔIP-P= 28A

ΔIP-P= 5A

44

ΔIP-P= 11A

ΔIP-P= 12A

9

WITHOUT OPTIMIZATIONWITHOUT OPTIMIZATION

WITH OPTIMIZATIONWITH OPTIMIZATION

RIPPLE REDUCTIONRIPPLE REDUCTION

32 32 ComparisonComparison currentcurrent rippleripple improvementimprovement

NUMBER OF PHASESNUMBER OF PHASES

1 2 4 8 16

Non-idealities are less importantBig reduction of current ripple without any change in the hardware


UPM

32 32 PhasePhase ShiftingShifting -- MultiDPWMMultiDPWM

Tswitch

delay

Load

voutvin

Interleaving techniqueInterleaving techniqueInterleaving technique

Addition andComparison Shift Register

COUNTERDUTY CYCLE

DRIVING SIGNAL

Load

voutvin

Duty cycle resolution freq(counter)freq(switching)


40


UPM

32 32 AdditionAddition andand ComparisonComparison

Phase shifted saw-tooth signals

Dri

vin

gsi

gnal

s

Counter

+ hellip +

ResolN Resolmiddot(N-1)N

Duty cycle

lt lt lthellipDrivingsignals

Phase 1 Phase 2 Phase N

Better dynamic responseSize depends on thenumber of phases


UPM

32 32 ShiftShift RegisterRegister

Dri

vin

gD

rivi

ng

sign

als

sign

als

ShiftShift RegisterRegister

PhasePhase 11 PhasePhase 22 PhasePhase 33 PhasePhase 44

ltDuty cycle

Phase 1 Phase 2 Phase 3 Phase 4

Shift Register

Dependency on the duty cycle resolution but not on the number of phases

ShorterShorter criticalcritical pathpath

Counter

Size determined by the resolution Slow dynamic response

41


UPM

32 32 ComparisonComparison betweenbetween methodsmethods

ldquodrdquo resolution FPGA

256256 8 8 phasesphases



ASIC

12 12 phasesphases

6 6 phasesphases

24 24 phasesphases

Boundary forArea(Shift Reg) lt Area(Add amp Comp)

Shift Register rArr higher frequency rArr higher duty cycle resolutionAddition and Comparison rArr higher dynamic response (duty change takes place inmediately independently of the current phase)


Synthesis for FPGA Virtex V200E XilinxSynthesis for ASIC technology cub_50V AMS

0

2000

4000

6000

8000

10000

12000

14000

16000

2 4 6 8 12 16 20 24

0

2000

4000

6000

8000

10000

12000

2 4 6 8 12 16 20 24

0

2000

4000

6000

8000

10000

12000

14000

16000

18000

2 4 6 8 12 16 20 24

Add amp Comp Shift Reg

Res

ol 1

28Res

ol 2

56Res

ol 5

12

FPGA

Equ

ival

ent

gate

s

Phases

0

200

400

600

800

1000

2 4 6 8 12 16 20 24


Res

ol 1

28Res

ol 2

56Res

ol 5

120

200

400

600

800

1000

1200

2 4 6 8 12 16 20 24

0

200

400

600

800

1000

1200

1400

2 4 6 8 12 16 20 24

ASIC

Equ

ival

ent

gate

s

Phases


UPM

Improvements in the efficiency are expected at low-loadDigital control allows changes in the number of phases easilyImprovements in the efficiency are expected at low-loadDigital control allows changes in the number of phases easily

0

10

20

30

40

50

0 20 40 60 80

Power losses with dinamicoptimization of the number of phases

Power losses for 16 phases

0

10

20

30

40

50

0 20 40 60 80



Iout

Pow

erlo

sses

(W)

80

84

88

92

96

0 10 20 30 40 50 60 70 80

6 phases

8 phases12 phases

16 phases

4 phases

Optimized efficiency(nb of phases variable)

Nb of phases for theoptimized efficiency4 6 8 12 16

Iout

Effic

ienc

y(

)

80

84

88

92

96

0 10 20 30 40 50 60 70 80

6 phases

8 phases12 phases

16 phases

4 phases



Iout

Effic

ienc

y(

)

32 32 ChangeChange thethe numbernumber thethe phasesphases dynamicallydynamically

Easily implementedwith digital control

42


UPM

Switch-off Switch-on


Phases are balanced after transientsPhasesPhases are are balancedbalanced afterafter transientstransients


UPM

33 PSU 33 PSU ofof RF RF PowerPower amplifieramplifier

RFAmp

Pow

erSt

age

Control

iRF

vs

VS

variable VS

Max Output voltage ripple= 50mV

24V

9Vfmax=35kHz

Input voltage = 28V


Resolution improvement

Current balance under transients

Adjustment of the model

43


UPM

33 RF 33 RF powerpower amplifieramplifier PowerPower stagestage

Cs

M1

L

M2

Cs

M1

L

M2

Cs

M1

L

M2

Cs

M1

L

M2

Ve Vout

CAR

GA

Multiphase synchronous buck converterMultiphase synchronous buck converterMultiphase synchronous buck converter

Power stageInterface with control


UPM

33 33 ResolutionResolution improvementimprovement

SW

CLK

ff Resolution =

Pipeline

fCLK

f = 25MHz f = 45MHz

Resolution required

WithWith thethe initialinitial 7 bits7 bits rArrrArr resolution = 0218V (28V2resolution = 0218V (28V277))

ThanksThanks toto thethe DLL DLL ofof thethe FPGA DPWM can FPGA DPWM can workwork a a twicetwice frequencyfrequency (64MHz) (64MHz) rArrrArr8 bits (64MHz250kHz)=28 bits (64MHz250kHz)=288rArrrArr resolution = 0109V (28V2resolution = 0109V (28V288))

fselected = 32MHz

Resolution is improved thanks to pipeline

44


UPM

33 33 DitherDither

SW

CLK

ff Resolution gt

d = 42

d =43

d =425

T=2TSW=8μs

Output voltage

2 solutions

V=50mV

TSW=4μs 1 solution

T=4μs

Output voltage

V=25mV

SW

CLKNVirtual

ff 2 Resolution sdot=

Resolution is improvedthanks limit cycle

Average duty cycle

It gives 1 more bit


UPM

33 33 AdjustmentAdjustment ofof thethe modelmodel parametersparametersSee the design of this regulator in section 26See the design of this regulator in section 26

Testablecim = 60micros

SimulatedSimulated

MeasuredMeasured

Simulated after adjustmentSimulated after adjustment

Correction of the modelCorrection of the model

)(

4110780250 22

ltheoreticathanhighermuch

RRIRP phaseRMSLOSS Ω=rArrsdot=rArrsdot=

Model resistance estimatedthrough power losses

45


UPM

33 33 StaticStatic performanceperformance

Vs = 24V Is = 5A Vs = 24V Is = 10AVs = 24V Is = 5A Vs = 24V Is = 10A


Current unbalance lt 17CurrentCurrent unbalanceunbalance lt 17lt 17


UPM

33 Output 33 Output voltagevoltage

f = 200Hz f = 15kHz

f = 3kHz f = 5kHz

46


UPM

33 33 DynamicDynamic equalizationequalization

Phase currents are balanced during transientsPhasePhase currentscurrents are are balancedbalanced duringduring transientstransients

Current balance in multi-phase after transient


UPM

4 Dc4 Dc--dc converter for DVSdc converter for DVS

Voltage stepsVoltage steps

2 2 micromicross

Vo

1 V

2 V

VRM for DVS5 V

Io = 20 A max

1V - 2 V

Io

02 V max02 V max

0 A

20 A

500 Amicros

Vo

Current stepsCurrent steps

20 mV max20 mV maxVo

Output voltage rippleOutput voltage ripple

47


UPM

Analysis and design of the power stageAnalysis and design of the power stage

10-1 100 101

100

L-C diagram

C2 micros

200 mV

20A

Maximum efficiency at Maximum efficiency at LLeq_maxeq_max and and ffswsw = 500 kHz = 500 kHz 4 phases required to achieve 20 mV of output voltage ripple4 phases required to achieve 20 mV of output voltage ripple

Selected point for maximum efficiency

LLeq_maxeq_max = 50 = 50 nHnH

C = 35 C = 35 μμFF

Power stage constraintsPower stage constraints


UPM

4 Converter design4 Converter design

4 x FDS7766 MOSFETs (6 mΩ Rds_on)

50 nH eq (4 x 200 nH SMD)

35 microF ceramic output cap

Driver LM2722 (20 ns delay)

fsw = 520 kHz

(125 mΩ eq Rds_on)

4 phases design4 phases design

Digital non-linear control in an FPGA

Minimum time controlFast feed-forward of load current

How to obtain a 500 kHz bandwidthif the optimum fsw= 500 kHz

48


UPM

4 Control combination linear and non4 Control combination linear and non--linearlinear

0

1

To drivers

New vref

vo dig

N-phases_tran

N-phases

New vref

vo dig

New vref

vo dig

Minimum time and load control

ic

Fastest control actionFastest control actionLinear control

NON-LINEAR CONTROL

- Minimum time for voltage steps- Minimum drop for load steps

Non linear controlNon linear control active only during the transientVo not fed back during the transient

sdot LUT for voltage stepssdot current through Co to zero for load steps


UPM

4 Linear part of the control4 Linear part of the control

vref

vo

0

1

To drivers

clk_sample

clk_sample

ADC

N-phases_tran

N-phases

vo dig

LINEAR CONTROL

Accurate closed-loop regulationIt should be as fast as possible (fsampling = fsw) to correct Vo deviations after non linear action

Digital implementation of linear control facilitates interaction offast linear and even faster non-linear controls

49


UPM

4 Linear and non4 Linear and non--linear interactionlinear interaction

vref

vo

0

1

To drivers

New vref

vo dig

clk_sample

clk_sample

ADC

N-phases_tran

N-phases

vo dig

New vref

LINEAR CONTROL

NON-LINEAR CONTROL

vo dig

New vrefvo dig


ic

Linear control is halted during the transientNominal duty cycle is updated as a function of the transientA LUT sets the nominal duty value

Interaction of fast linear and even faster non-linear controls

Beware


UPM

4 Non4 Non--linear control for voltage steps Minimum timelinear control for voltage steps Minimum time

UpUp--stepstep

ConverterFPGA

tt11

1 1 micromicross1 1 micromicross

ddnn ddn+1n+1 ddn+2n+2

DownDown--stepstep

t1 t2 t1 t2

ddnn

tt22vref

500 kHz

LUT

DIGITAL control enables implementation of minimum time strategy

05

1

15

2

25

0 02 04 06 08 1 12 14 16 18-10

0

10

20

30

40

50

ton toff

Tmin

05

1

15

2

25

0 02 04 06 08 1 12 14 16 18-10

0

10

20

30

40

50

ton toff

Tmin

i L(A

)i L

(A)

V o(V

)V o

(V)

Time (micros)Time (micros)

50


UPM

4 Minimum time and interleaving4 Minimum time and interleaving

t1 t2 t1 t2

094 096 098 1 102 104 106 108 11

x 10-4

14

16

18

2

22

24

26

28

3

32

094 096 098 1 102 104 106 108 11

x 10-4

0

1

2

3

4

5092 094 096 098 1 102 104 106 108 11 112

x 10-4

14

16

18

2

22

24

26

28

3

32

092 094 096 098 1 102 104 106 108 11 112

x 10-4

0

05

1

15

2

25

3

35

4

45

Transient

PWM is halted during the transient

Transient current unbalance

bull DC current balancebull Phase shifting for many phasesbull Current unbalance during

transients is minimized

Beware


UPM

ΔIo

iL

Io

vo

ic 0 ATrip point 1

Trip point 2

ΔIo

ic

Sw_controlSw_control

This strategy produces minimum drop

4 Non4 Non--linear control for current steps Minimum voltage droplinear control for current steps Minimum voltage drop

Counting transition time (proportional to ΔIo)hellipVoltage reference to the linear control can be changed for AVPDuty cycle for the linear control can be updated for fast recovery

51


UPM

4 Linear control design plant model4 Linear control design plant model

05358z02236z07417)(z3767G(z) 2 +sdotminus

+sdot=

B G(s)

G(z)

fsampling = fsw = 5208 kHz

Rphase = 60 mΩ(not 11 mΩ Rdc)

Lphase = 200 nHC = 35 microF

N = 4

ESR = 125 mΩ

( )CL

1sRESRL1s

CL1)1sCESR(V

)s(Gdv

L2

ino

sdot+sdot+sdot+

sdotsdot+sdotsdotsdot

==

~ VinmiddotdCo

ESR

RphaseN LphaseN

Expected by design

If controller is designed assuming

DC resistance

Actual response Incorrect plant

model

Parameters identificationby measurement

Beware


UPM

4 Design linear part (integration pole at 1)4 Design linear part (integration pole at 1)

Pole-Zero Map

Real Axis

-1 -08 -06 -04 -02 0 02 04 06 08 1-1

-08

-06

-04

-02

0

02

04

06

08

1

09

0807060504

03

02

01

26e5

234e5

208e5

182e5

156e513e5

104e5

781e4

521e4

26e4

26e5

234e5

208e5

182e5

156e513e5

104e5

781e4

521e4

26e4

x

x

x

AccuracyAccuracyNo limit cyclesNo limit cycles

SISO TOOLSISO TOOLSISO TOOL

Transient responseTransient response

Duty cycle

30 micros

Simple but slow responsefor stability

1z00372)z(Rminus

=

1zK)z(R 1

minus=

Controller delay

05358z02236z07417)(z3767G(z) 2 +sdotminus

+sdot=Converter

x

x

x Duty cycle

Output voltage

52


UPM

10 micros

4 Design linear part (addition of a zero4 Design linear part (addition of a zero--pole pair)pole pair)

xx

x

x

x

x

x

x

SISO TOOLSISO TOOLSISO TOOL Transient responseTransient response

Transition within 5 cycles (10 Transition within 5 cycles (10 micromicros) Can it be even fasters) Can it be even fasterIncreasing GainIncreasing Gain

Adding another poleAdding another pole--zerozero

00775)(z1)(z037)(z00378R(z)

minussdotminus+sdot

=

Duty cycle

Output voltage


UPM

4 Stability4 Stability--speed tradeoffspeed tradeoff

75 micros

xx

x

x

x

xx

x


Trade-off Faster than 5 cycles rArr lower damping 00775)(z1)(z037)(z00466R(z)

minussdotminus+sdot

=

53


UPM

4 Implementation in delta form4 Implementation in delta form

Duty

a1 = -0922548 b1 = 0037759b2 = 0051742a2 = 0

b1

b2

δ-1

δ-1

δ-1

a1

a2

Error

bn0

No b0

δ-1

Z-1

+

00775)(z1)(z037)(z00378R(z)

minussdotminus+sdot

=




UPM


z2d_m ( tf ([00378 0013986] [1 -10775 00775] 192e-6) )

MATLAB MMATLAB M--file to convert from z domain to file to convert from z domain to δδ

Try to convert 00775)(z1)(z

037)(z00378R(z)minussdotminus+sdot

=Tsample = Tsw

⎪⎩

⎪⎨⎧

rarrδ

+=δ δδ

s

umiddotBxmiddotAxmiddot kkk

54


UPM

4 Quantization of PWM and ADC4 Quantization of PWM and ADC

Reference

Switched model

7 bits

8 bits

Not quantizied

Check if selected PWM and ADC resolutions are OKby simulating with a non-quantizied controller (to isolate problems)Check if selected PWM and ADC resolutions are OKCheck if selected PWM and ADC resolutions are OKby simulating with a nonby simulating with a non--quantiziedquantizied controller (to isolate problems)controller (to isolate problems)

PWM

ADC

111

a) 40 mV resolution for output voltage regulation a) 40 mV resolution for output voltage regulation rArrrArr 7 bits for a 5 V (V7 bits for a 5 V (Vinin) swing in V) swing in Voo

b) b) DesignDesign rulerule toto avoidavoid limitlimit cyclingcycling Resol (DPWM) gt Resol (ADC) Resol (DPWM) gt Resol (ADC) rArrrArr 8 bits8 bits

Quantization of PWM and ADC

Check if transient response is OK(no limit cyclying and transient performance equal to the non-quantizied one)


UPM

Reference

4 Quantization of the controller4 Quantization of the controller

PWM

ADC

Switched modelQuantizied model of controller

Fixed-point interface

Simulink Fixed-point blockset

HW design of the controller (quantization effects)by simulation of a quantizied controller How to model itHW design of the controller (quantization effects)HW design of the controller (quantization effects)by simulation of a by simulation of a quantiziedquantizied controller How to model itcontroller How to model it

Fixed-point can model ANY hardware behaviorsdot Determine the number of bits of internal signalssdot Scaling factor of coefficients

hellip

222

55


UPM

4 Not 4 Not quantiziedquantizied controllercontroller

This controller is modeled using Fix Point blockset

a1 = -0922548 b1 = 0037759b2 = 0051742a2 = 0

b1

b2

δ-1

δ-1

δ-1

a1

a2

Error

bn0

No b0


UPM

4 4 QuantiziedQuantizied model of the controller (n bits)model of the controller (n bits)

0lt Duty cycle lt1

Two alternativesDecimal pointNo decimal point

Hardware adders

Hardware multipliers

coefficients should be scaled so

05lt|coef|lt1 (no left zeros or ones)

Rounders (nearest)(as a function of PWM resolution)

HW operators should detect overflows and then saturateObviously models need to be defined accordingly

Beware

56


UPM

0 1 2 30

05

1

15

2

25

4 Number of bits determination4 Number of bits determination

a) Simulation of an a) Simulation of an aggresiveaggresive transient with transient with nonnon--quantiziedquantizied valuesvalues

b) Fixedb) Fixed--point stores maximum and point stores maximum and minimum values in each internal signalminimum values in each internal signal

c) Number of bits for the integer c) Number of bits for the integer part are determined to avoid part are determined to avoid

saturationsaturation

Characterizing signals within the controller integer bitsCharacterizing signals within the controller integer bitsCharacterizing signals within the controller integer bits333


UPM

4 Sizing decimal bits4 Sizing decimal bits

No saturations Transient response OK(not quantizied equal to quantizied)

0 1 2 3

x 10-4

0

05

1

15

2

25

100 usdiv100 usdiv

Characterizing signals within the controller decimal bitsCharacterizing signals within the controller decimal bitsCharacterizing signals within the controller decimal bits444

Increase decimal bits untilIncrease decimal bits until

57


UPM

4 Experimental results System4 Experimental results System

ADC boardUser interface

Control in FPGA Converter

PROTOTYPEPROTOTYPEPROTOTYPE


UPM

4 Linear loop4 Linear loop

Voltage step responseVoltage step responseVoltage step response

As expected by design but 5 times slower than minimum time

58


UPM


13 14 15 16 17 18 19

x 10-4

12

14

16

18

2

22

08 V drop

10 microsdiv

2 V

Load step with linear control(SIMULINK simulation)

Load step with linear controlLoad step with linear control(SIMULINK simulation)(SIMULINK simulation)

Not acceptable Non-linear control needs to be included


UPM

4 Non4 Non--linear loop Minimum timelinear loop Minimum time

Currents of inductors(one phase not shown)

Vo

1 V

2 V

2 micros (1 switching period)

1 1 micromicros divs div

11 A11 A

20 mV

520 kHz


Non-linear minimum time control enables fastest voltage transition at only fsw = 500 kHz

59


UPM

4 Non4 Non--linear looplinear loop

Vo

Io

200 mV

15 A-- 400 A400 Amicromicross

400 ns div400 ns div

02 V withONLY 35 microFof output cap

Load stepLoad stepLoad step

NonNon--linear feedback of the capacitor current enables best linear feedback of the capacitor current enables best regulation under load steps at regulation under load steps at ffswsw = 500 kHz= 500 kHz


UPM

4 Combination of the loops for accuracy4 Combination of the loops for accuracy

Vo

1 V

2 V

10 10 micromicrosdivsdiv

Linear loop resumes control

Linear control provides closedLinear control provides closed--loop accuracy A digital implementation of this loop enablesloop accuracy A digital implementation of this loop enablesHighest linear bandwidth only limited by Highest linear bandwidth only limited by ffswsw

No interaction problems with the nonNo interaction problems with the non--linear looplinear loop

60


UPM

5 Conclusions5 ConclusionsMajor topics related with digital control for power supplies havMajor topics related with digital control for power supplies have been addressede been addressed

Design methodology includesDesign methodology includesDiscretizationDiscretizationRegulator designRegulator designSimulationSimulationADC amp PWM selectionADC amp PWM selection

Digital control enables or facilitatesDigital control enables or facilitatesNon linear controlNon linear controlAdaptive control and concurrencyAdaptive control and concurrencyGet rid of current loops in multiphase convertersGet rid of current loops in multiphase convertersReduce the influence of nonReduce the influence of non--idelaitiesidelaities and tolerancesand tolerancesImplement standby and light load power saving techniques Implement standby and light load power saving techniques

Limit the influence of critical points in digital controlLimit the influence of critical points in digital controlLimit cycleLimit cycleSampling delay and latencySampling delay and latencyQuantizationQuantizationResolutionResolutionhelliphellip

Beware

Some KEY APPLICATIONSSome KEY APPLICATIONSDcDc--dc converters with DVS for power savingdc converters with DVS for power savingMultiphase convertersMultiphase convertersIntegrated converters in CMOSIntegrated converters in CMOSSystems that already have digital Systems that already have digital components andor several parts to controlcomponents andor several parts to control


UPM

5 References5 References

IEEE Transactions on Power Electronics (Special Issue on DigitalIEEE Transactions on Power Electronics (Special Issue on Digital Control in Power ElectronicsControl in Power Electronics)) vol 18 n 1 part II Jan vol 18 n 1 part II Jan 20032003Y Y DuanDuan H Jin H Jin ldquoldquoDigital Controller Design for Digital Controller Design for SwitchmodeSwitchmode Power ConvertersPower Convertersrdquordquo Proc IEEE Applied Power Electronics Conf Proc IEEE Applied Power Electronics Conf Expo (APEC)Expo (APEC) vol 2 Mar 1999 Dallas TXvol 2 Mar 1999 Dallas TX--USA pp 967USA pp 967--973973A V A V PeterchevPeterchev S R Sanders S R Sanders ldquoldquoQuantization Resolution and Limit Cycling in Digitally ControlleQuantization Resolution and Limit Cycling in Digitally Controlled PWM Convertersd PWM Convertersrdquordquo IEEE IEEE Trans Power ElectronTrans Power Electron vol 18 n 1 pp 301vol 18 n 1 pp 301--308 Jan 2003308 Jan 2003A V A V PeterchevPeterchev J Xiao S R Sanders J Xiao S R Sanders ldquoldquoArchitecture and IC Implementation of a Digital VRM ControllerArchitecture and IC Implementation of a Digital VRM Controllerrdquordquo IEEEIEEE Trans Power Trans Power ElectronElectron vol 18 n 1 pp 356vol 18 n 1 pp 356--364 Jan 2003364 Jan 2003B J Patella A B J Patella A ProdicProdic A A ZirgerZirger D D MaksimovicMaksimovic ldquoldquoHighHigh--Frequency Digital Controller IC for DCFrequency Digital Controller IC for DC--DC ConvertersDC Convertersrdquordquo IEEE Trans IEEE Trans Power ElectronPower Electron vol 18 n 1 pp 438vol 18 n 1 pp 438--446 Jan 2003446 Jan 2003T D T D BurdBurd T A T A PeringPering A J A J StratakosStratakos R W R W BrodersenBrodersen ldquoldquoA dynamic voltage scaled microprocessor systemA dynamic voltage scaled microprocessor systemrdquordquo IEEE Journal IEEE Journal on Solidon Solid--State CircuitsState Circuits vol 35 n 11 pp 1571 vol 35 n 11 pp 1571--1580 Nov 20001580 Nov 2000P P MattavelliMattavelli G G SpiazziSpiazzi P P TentiTenti ldquoldquoPredictive Digital Control of Power Factor Predictive Digital Control of Power Factor PreregulatorsPreregulators With Input Voltage Estimation With Input Voltage Estimation Using Disturbance ObserversUsing Disturbance Observersrdquordquo IEEE Trans Power ElectronIEEE Trans Power Electron vol 20 n 1 pp 140 vol 20 n 1 pp 140--147 Jan 2005147 Jan 2005A de Castro P A de Castro P ZumelZumel O O GarcGarciacuteiacuteaa T T RiesgoRiesgo ldquoldquoDigital Control in MultiDigital Control in Multi--Phase DCPhase DC--DC ConvertersDC Convertersrdquordquo EPE JournalEPE Journal vol 13 n 2 vol 13 n 2 pp 21pp 21--27 May 200327 May 2003O GarcO Garciacuteiacutea P Zumel A de Castro J A Cobos a P Zumel A de Castro J A Cobos ldquoldquoHighHigh CurrentCurrent dcdc--dcdc ConverterConverter withwith SMT SMT ComponentsComponentsrdquordquo Proc Proc IEEE Applied IEEE Applied Power Electronics Conf (APECPower Electronics Conf (APEC)) vol 3 Mar 2005 Austin TX vol 3 Mar 2005 Austin TX--USA pp 1401USA pp 1401--14061406A de Castro P A de Castro P ZumelZumel O O GarcGarciacuteiacuteaa T T RiesgoRiesgo J Uceda J Uceda ldquoldquoConcurrent and Simple Digital Controller of an ACConcurrent and Simple Digital Controller of an AC--DC Converter with DC Converter with Power Factor Correction based on an FPGAPower Factor Correction based on an FPGArdquordquo IEEE Trans Power ElectronIEEE Trans Power Electron vol 18 n 1 pp 334 vol 18 n 1 pp 334--343 Jan 2003 343 Jan 2003 O Garcia A de Castro A Soto JA Oliver JA O Garcia A de Castro A Soto JA Oliver JA CobosCobos J Cez J Cezoacuteoacuten n ldquoldquoDigital control for a power supply for a RF transmitter with Digital control for a power supply for a RF transmitter with variable referencevariable referencerdquordquo IEEE Applied Power Electronics Conference (APEC)IEEE Applied Power Electronics Conference (APEC) March 2006 Dallas TX March 2006 Dallas TX--USAUSA

2


UPM

AnalogAnalog

μProccessor(DSP)

μProccessor(DSP)



MotivationMotivation

More More complexcomplexalgorithmsalgorithmsReprogrammabilityReprogrammabilityDesignDesign timetime

HigherHigher pricepriceNeedNeed ofof ADCADCLimitedLimited resolutionresolution((measuringmeasuring processingprocessing andanddutyduty cyclecycle))LimitedLimited bandwidthbandwidth(for (for thethe samesamealgorithmalgorithm))helliphellipbut enables faster but enables faster control strategiescontrol strategies

ConcurrencyConcurrencyProcessingProcessing speedspeed

HighHigh computationcomputation capabilitiescapabilitiesADC ADC integratedintegrated

DigitalDigital


UPM

1 1 SeminarSeminar approachapproachIllustrateIllustrate proprorsquorsquos cons conrsquorsquos and design issues through some specific applicationss and design issues through some specific applications

PowerPower Factor Factor CorrectionCorrection

IinVin

Vout


Adaptive control



VOUTIN VOUTVIN VOUTIN VOUTVINCOCIN

MultiphaseMultiphase for for automotiveautomotive (dual (dual voltagevoltage))

a) Reduce Co reduce current ripple by sequencing phasesb) High number of phases (current balance)

a) Reduce power losses at light load (activateappropriate number of phases)b) Change to ldquoforcedrdquo DCM

Get rid of current loops

Implementation of multi-output DPWM

3


UPM




Resolution of DPWM

variable VS





Non linear control

Robust control



2V11V

33V


UPM




212211


Applications333




222222

232233

242244

252255

262266

272277

313311 323322

333333

4


UPM


Powerconverter



-


ADCADCVmeas(t)



212211

Hardware issues222

222222

232233

242244

252255

262266

272277



UPM


H G(s)

G(z)

Hold Sampler

Vout

t





Tsamp = Tswitch



Beware

Powerconv


+

-


5


UPM




2nd approach RL ESR

VindC

ESRVind C RLOAD

+

_

L

Vout

)s(ds

RLsmiddotCmiddotL

V)s(V

LOAD

inout

12 ++=

RLOAD Vout+

_


L RL

( ))s(d

RESRRRsC

RESRRESRCR


VsCESRRESR

R

)s(V

LOAD

LOADL

LOAD

LOADL

LOAD

inLOAD

LOAD

out

++

+⎥⎦

⎤⎢⎣

⎡sdot

+sdot

+sdot++

+

sdot+sdotsdotsdot+

=2

1


UPM


HO G(s)


G(z)

Powerconverter






6


UPM



Power

converter





ADCBeware

Powerconv


+

-



UPM



V+

V_

+_

Voffset

R1

R1

R2

R2

ADCVout

Pow

erco

nver

ter

_+

7


UPM

C

R2




V+

V_

ADC

Vref

R1

R1

Vcm

_

++_

ADC

R2

C


UPM







V

t

ΔtV

t

ΔV

Beware

Powerconv


+

-


8


UPM


TSWITCH

TADC TPROCTDRIVER











UPM


High fADC butADC

latADC fNT 1

=

latencystages

stage perbitsstages

totalbit

NN

NN

N

=

= minusminus

latencyBeware

latency


9


UPM



25075

25050

25025

25000

24975

24950

24925

1 1 1

1 1 0

1 0 1

1 0 0

0 1 1

0 1 0

0 0 1



(25mV resolution)


voltage

⎟⎠⎞

⎜⎝⎛ = VV 00250

25210

Saturation



UPM





Best options

ADC-CLK

N

LATCHINSTANT


DATA N-3 N-2 N-1 N


10


UPM


Low pass filters


s11)s(Fτ+

=T

bT

bzbb

)s(F τ=

τ+=

minus=

minus 10110



Tb

zbbz)s(F τ

minus=τ

+=+

+=

minus

minus 21211101

10

1



TSWITCH

TADC TPROC

TDRIVER

TADC TADCTADC

Tfilter

Samp1

Samp2

Samp3

Samp4

1 noise-freesample


D QD Q




UPM

24 DPWM24 DPWM

Counter

refgt on_off





SWITCH

CLK


fCLK = 128 MHz

Beware

Powerconv


+

-


11


UPM




PWM63

PWM62

PWM61

Vref

error3

error2

error1

error0

error-1

error-2






of the controller)



UPM











CLKCLK2

Vout

VGS

dk


Beware

12


UPM







CLK

MUX


S QR

VGS

duty(1)duty(0)

end of sync duty


duty(n-12)

Example(L=2)

Bewareof thedelay



UPM




VGHVGL


Tswitch

delay

13


UPM



Beware




sum minusminus +=k



Driver examples





VSW

VGS

ton toff

Powerconv


+

-



UPM




zbb

zaa)z(R 110

110

++++

= minus

minus

ai bi constants









Powerconv


+

-


14


UPM

zoh

foh

matched

NA

tustin

Matlab C2D




First order hold

Polezero match



Two possibilities









UPM







Two mains reasons






15


UPM








UPM





)z(G)z(R1)z(G)z(R

)z(X)z(Y)z(M

+==

))z(M1)(z(G)z(M)z(R

minus=





Beware


+ Y(z)

_

E(z)X(z)R(z) G(z)

16


UPM





k

kk



=

⎪⎭

⎪⎬⎫

⎪⎩

⎪⎨⎧

minusminus=

minus=minusrArr

minusminus

=minusminus

minusminus


z1)z(M1)z(E

11

11








UPM


10

p1=e-σmiddotejθ


θ

γe-σ




=sR


minus= eMp



17


UPM


xx

xx

OO






96730middot29412239middot6229)(


2

7211

8

+minus+

=

+++

= minusminus

minus

zzzzG

ssssG


condition)



UPM




Vout

Duty

Near unstable



18


UPM



1z110)z(R 5

minus= minus

Vout

Duty







UPM




+= minus

Vout

Duty




19


UPM


Vout

Duty





23

+minusminus+minus




UPM


xk xk-1

hellip

xk-m

X

b0

X

b1

X

bm

hellip

+

+

hellip

+

yk yk-1

hellip

yk-n

X

a1

X

an

+

+

hellip

hellip

+

-yk

nn

22

110

mm

22

110

zazazaazbzbzbb

)z(e)z(d)z(R

minusminusminus

minusminusminus

sdot++sdot+sdot+





20


UPM

Z-1

a1

a2

Z-1


Z-1

bo

eK

Z-1

b1

b2

R1(z) R2(z)YK

dK

eK

R1 R2

Z-1

Z-1

a1

bo

b1

dKeK






UPM

Difference equation


a1a2

e(z)

⎩⎨⎧

rarrδ

+=δminus=δ= δδ+


TXXXmiddotY kkkk1k

kk

Tz1 1minusminus

=δ

k1

1k

1k Y

z1zTYXminus

minusminus

minus

sdot=δ=

δ-1 δ-1

aman

δ-1 δ-1

bm

+

bo

b1

u(z)h(z)

T Z-1

δ-1

(Integral)

+




More adders

21


UPM

a1

a2

δ-1

bo

b1T

b2T2 δ-1 T2

T


Tn Tn


Z-1

+



Adapted δ-1


UPM








ek-1 isrequested

ek-1 isavailable

dk isimposed

T

22


UPM

0 1 2 3 4 5 6 7 8

x 10 -4

-04

-02

0

02

04

06

08

1

12

14

16




vo

48 5 52 54 56 58

10-4

138

14

142

144

146

148

15

152

154

156

vo

Matlabfixed-point

toolbox






UPM



00011111b0 =


Meanerror

22 143143 5252

11 333333 170170

44 3232 0606

33 6767 1717


615615 105ns105ns

12481248 168ns168ns

Mp ts

Example

160160 012ms012ms

113113 011ms011ms1


zz

( )1

222 353


zz


00101000b0 = k53

k5


00101001b0 = k853

k8

k5


222

333



00100000b0 = k3 e2 sdotminus111


1rsquos

23


UPM





D QEN

new_cycle Xek

b0

D QEN

new_cycle Xek-1

b1

+

D QEN

new_cycle Xdk-1

a1

D QEN

new_cycle Xdk-2

b2

+ D QENnew_cycle

dk

+


D Q

D Q

D Q

D Q

D Q

D Q






UPM

Fixed-point toolbox







MatlabSimulink



24


UPM

VHDL or VHDL-AMS











UPM


Applications333



323322

333333

25


UPM


IinVin

Vout

DCDCREGULATOR LO

AD

~

IoutIin


Vout

+_Vin

CONTROL

d

R1

R2

R3

R4

n1 n2LINE

LOAD

Main Switch

Vin

Iin Vout

PO=50Wf=50kHz


PO=50Wf=50kHz



UPM





Adaptive control


LOA

D

~

IoutIin

PFC CONVERTERVout

+_Vin

Controlblock

Controlblock

onoff

R1

R2

R3

R4

Vout

Iin

Vin

ADCADC

ADC

26


UPM


X


IIN-ref

Protections


VOUT max

IIN max

ldquodrdquo max

ldquoΔdrdquo max

ON-OFF Main Switch

ON-OFF Main Switch





intΣIin

gt

CalculatedOn-Off


Max






VOUT-ref

GinPI


UPM










VinGin

Multiplier

xVin

Gin(1Rin)

50 kHz



Adder

+Iin

ΣIin

Comparator

gtOnOff

20 MHz

NoPWMNoPWM


27


UPM




10 W 30 W 50 W 30 W 10 W

Vout

IinGin

StableStable

Load


Unstable

Unstable

Unstable

Unstable


UPM




Adaptive control

28


UPM



Load Change

Vout

Iin




T



UPM

Vin_dc

Iin_dc

d

Vout


OnOff

FPGAXilinx

XC4010-e

8 8 12

Vin Vout Iin

PROMXC 17512

ADC0808

ADC0808

HI 5805


ADCsADCs

Power Converter

Vout Vin_acIin_ac

PF = 099PF = 099PF = 099

29


UPM


DigitalController


switches)Digital


Measuredamp State


Analog

ADConverter

MeasuredVariables

(digital buses)

Mixed




UPM


M1

C Vout

D11n

+

_Vin

Iin

IL1

RL

IR

ON

L1OFF

M1

C Vout

D11n

+

_Vin

Iin

IL1

RL

IR

OFF

L1ON

Vout

n

ID1 = IL1 n

IC



1

kin1k1Lk1L

1L1in L

tVII

dtdILV

Δsdot+=rArr= minus

CtI

VVdt

dVCI kR1koutkout

outR


1

1kout1k1Lk1L

1L1

out

LntV

IIdt

dILnV

sdotΔsdot


minus

C

tIn

I

VVdt

dVCInI kR

1k1L

1koutkoutout

R1L

Δsdot⎟⎟⎠

⎞⎜⎜⎝

⎛minus

+=rArr=minus

minus

minus



30


UPM


VHDLVHDLVHDL

VHDL-AMS

VHDLVHDL--AMSAMS






UPM




VHDLVHDL








Simulationtime


CPU time using VHDL

models


modelsmodels



VHDL speed VHDL-AMS

speed


speedspeed

10 ms10 10 msms 69 s69 s69 s 446 s446 s446 s 641641641

100 ms100 100 msms 700 s700 s700 s 6912 s6912 s6912 s 987987987

1000 ms1000 1000 msms 6890 s6890 s6890 s 68443 s68443 s68443 s 993993993

VHDLVHDL--AMSAMS

31


UPM

42V 14V

CC

CC 42V 14V


system vehicles


Q1-1

Q2-1

Q16-1

Q16-2

Q2-2

Q1-2

L

L

L

COCIN




UPM


Q1-1

Q2-1

Q16-1

Q16-2

Q2-2

Q1-2

L

L

L

COCIN








3 prototypes


3 prototypes



32


UPM


VoVIN

L2d2

d1L1




VINd1

Battery

R1

R2

+

+ +

VINd2

1

BAT1IN1 R

VdVI minus=

2

22 R

VdVI BATIN -=


UPM







446

416

03360

03528

320

2336



1 5

CCM ndash 1000W

824

184

Not acceptable


Q1-1

Q2-1

Q16-1

Q16-2

Q2-2

Q1-2

L

L

L

33


UPM

AVGLI AVGLI


dT T

LVV OIN minus

LVOminus

AVGLI

dT T

LVV OIN minus

LVOminus

AVGLI

⎟⎟⎠

⎞⎜⎜⎝

⎛ minus=

O

OIN

i

2iIN

i VVV

fL2dVI



AVGLI AVGLI

DCMDCM


UPM


03360

03528






416

824



1 5

CCM ndash 1000W

0262002623

0275102649


1 5

DCM ndash 1000W

Not acceptable

445

490

446

454

110102

Very good


34


UPM



420 97

435 100

440 101

435 -

DC Current(A)

429 99

428 98

446 103

460 106

Deviation()

Phase 2

Phase 3

Phase 4

Phase 5

Phase 6

Phase 7

Phase 8

Average

CCM


IO=35A




UPM


ADCInterface

ampfilter

Regulator8

d1


Vout

ADCcontrol

Reset

Vin

12

MCDgenerator

12

Vout

12

Vin

Phase-shifter

8

d2

Protections

1616

Clock

16

H-Pulses L-Pulses




35


UPM




422 97

438 101

442 102

434 -

DC Current(A)

431 99

445 102

424 98

448 103

Deviation()

Phase 2Phase 2

Phase 3Phase 3

Phase 4Phase 4

Phase 5Phase 5

Phase 6Phase 6

Phase 7Phase 7

Phase 8Phase 8

AverageAverage

DCMDCM


IO=17A

IO=27A


UPM





36


UPM


-05

0

05

1

15

2

00E+00 50E-06 10E-05 15E-05 20E-05 25E-05t (s)

()

-05

0

05

1

15

2

00E+00 50E-06 10E-05 15E-05 20E-05 25E-05t (s)

()

0

20

40

60

80

100

120

140

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35

Phase number

[+6-8]

0

20

40

60

80

100

120

140

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35

Phase number

[+6-8]

Half load(500W)


Full load(1000W)

0

1

2

3

4

p

0 5μs 10μs 15μs 20μs0

1

2

3

4

p



0

20

40

60

80

100

120

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35

Phase number

+10-75

0

20

40

60

80

100

120

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35

Phase number

+10-75



UPM

Output currentDC AC

11App

70ADC


is

0 01 02 03 04 05 06 07 08 09 100102030405

060708091

Duty cycle (d)

Nor

m c

urre

nt r

ippl

e Dutyvariation

2 phases

3 phases



37


UPM

10

5

5

10

3T0 x

5

5

3T0 x

Ideal case






10

5

5

10

3T0 x

5

5

3T0 x

Non-ideal



10

5

5

10

3T0 x

5

5

3T0 x

Worse case



10

5

5

10

3T0 x

5

5

3T0 x





UPM

ΔIP-P= 40A (5Adiv)

1 phase

ΔIP-P= 12A (5Adiv)

2 phases

ΔIP-P= 5A (5Adiv)

4 phases

ΔIP-P= 22A (1Adiv)

8 phases

ΔIP-P= 16A (1Adiv)

16 phases



38


UPM

(a)

30

31

22 40

37

22 33

2830

31

22 40

37

22 33

28

(a)

Center of mass

(a)

30

31

22 40

37

22 33

2830

31

22 40

37

22 33

28

(a)

Center of mass

Phase1Phase

2

Phase3

Phase4

Phase5

Phase6

Phase7

Phase8

1st

2nd

3rd 4th

6th

5th 8th

7th

(b)

1st

2nd

3rd 4th

6th

5th 8th

7th

1st

2nd

3rd 4th

6th

5th 8th

7th

(b)

40 A

37 A30 A

33 A

22 A 28 A

31 A

22 A






UPM

18 0 18

18

18

OVERALL 67A

18 0 18

18

18

1

2

34

56

7

8

9

10

1112 13

14

15

16

MAX

MIN

18 0 18

18

18

OVERALL 05A

18 0 18

18

18

1

2

34

56

7

8

9

10

1112 13

1415

16

MAX

MIN


16151413121110987654321

Phase number

165155177152140144148128147122154158139149142133

Current ripple (A)

39


UPM

ΔIP-P= 40A

ΔIP-P= 40A

ΔIP-P= 07A

ΔIP-P= 16A

57

ΔIP-P= 11A

ΔIP-P= 22A

50

ΔIP-P= 28A

ΔIP-P= 5A

44

ΔIP-P= 11A

ΔIP-P= 12A

9






1 2 4 8 16



UPM


Tswitch

delay

Load

voutvin



COUNTERDUTY CYCLE

DRIVING SIGNAL

Load

voutvin



40


UPM



Dri

vin

gsi

gnal

s

Counter

+ hellip +


Duty cycle





UPM


Dri

vin

gD

rivi

ng

sign

als

sign

als



ltDuty cycle


Shift Register



Counter


41


UPM






ASIC

12 12 phasesphases

6 6 phasesphases

24 24 phasesphases





0

2000

4000

6000

8000

10000

12000

14000

16000

2 4 6 8 12 16 20 24

0

2000

4000

6000

8000

10000

12000

2 4 6 8 12 16 20 24

0

2000

4000

6000

8000

10000

12000

14000

16000

18000

2 4 6 8 12 16 20 24


Res

ol 1

28Res

ol 2

56Res

ol 5

12

FPGA

Equ

ival

ent

gate

s

Phases

0

200

400

600

800

1000

2 4 6 8 12 16 20 24


Res

ol 1

28Res

ol 2

56Res

ol 5

120

200

400

600

800

1000

1200

2 4 6 8 12 16 20 24

0

200

400

600

800

1000

1200

1400

2 4 6 8 12 16 20 24

ASIC

Equ

ival

ent

gate

s

Phases


UPM


0

10

20

30

40

50

0 20 40 60 80



0

10

20

30

40

50

0 20 40 60 80



Iout

Pow

erlo

sses

(W)

80

84

88

92

96

0 10 20 30 40 50 60 70 80

6 phases

8 phases12 phases

16 phases

4 phases



Iout

Effic

ienc

y(

)

80

84

88

92

96

0 10 20 30 40 50 60 70 80

6 phases

8 phases12 phases

16 phases

4 phases



Iout

Effic

ienc

y(

)



42


UPM





UPM


RFAmp

Pow

erSt

age

Control

iRF

vs

VS

variable VS


24V

9Vfmax=35kHz

Input voltage = 28V





43


UPM


Cs

M1

L

M2

Cs

M1

L

M2

Cs

M1

L

M2

Cs

M1

L

M2

Ve Vout

CAR

GA




UPM


SW

CLK

ff Resolution =

Pipeline

fCLK

f = 25MHz f = 45MHz

Resolution required



fselected = 32MHz


44


UPM

33 33 DitherDither

SW

CLK

ff Resolution gt

d = 42

d =43

d =425

T=2TSW=8μs

Output voltage

2 solutions

V=50mV

TSW=4μs 1 solution

T=4μs

Output voltage

V=25mV

SW

CLKNVirtual



Average duty cycle

It gives 1 more bit


UPM



SimulatedSimulated

MeasuredMeasured



)(

4110780250 22




45


UPM






UPM


f = 200Hz f = 15kHz

f = 3kHz f = 5kHz

46


UPM





UPM



2 2 micromicross

Vo

1 V

2 V

VRM for DVS5 V

Io = 20 A max

1V - 2 V

Io

02 V max02 V max

0 A

20 A

500 Amicros

Vo




47


UPM


10-1 100 101

100

L-C diagram

C2 micros

200 mV

20A




C = 35 C = 35 μμFF



UPM






fsw = 520 kHz

(125 mΩ eq Rds_on)





48


UPM


0

1

To drivers

New vref

vo dig

N-phases_tran

N-phases

New vref

vo dig

New vref

vo dig


ic


NON-LINEAR CONTROL





UPM


vref

vo

0

1

To drivers

clk_sample

clk_sample

ADC

N-phases_tran

N-phases

vo dig

LINEAR CONTROL



49


UPM


vref

vo

0

1

To drivers

New vref

vo dig

clk_sample

clk_sample

ADC

N-phases_tran

N-phases

vo dig

New vref

LINEAR CONTROL

NON-LINEAR CONTROL

vo dig

New vrefvo dig


ic



Beware


UPM


UpUp--stepstep

ConverterFPGA

tt11



DownDown--stepstep

t1 t2 t1 t2

ddnn

tt22vref

500 kHz

LUT


05

1

15

2

25

0 02 04 06 08 1 12 14 16 18-10

0

10

20

30

40

50

ton toff

Tmin

05

1

15

2

25

0 02 04 06 08 1 12 14 16 18-10

0

10

20

30

40

50

ton toff

Tmin

i L(A

)i L

(A)

V o(V

)V o

(V)


50


UPM


t1 t2 t1 t2

094 096 098 1 102 104 106 108 11

x 10-4

14

16

18

2

22

24

26

28

3

32

094 096 098 1 102 104 106 108 11

x 10-4

0

1

2

3

4

5092 094 096 098 1 102 104 106 108 11 112

x 10-4

14

16

18

2

22

24

26

28

3

32

092 094 096 098 1 102 104 106 108 11 112

x 10-4

0

05

1

15

2

25

3

35

4

45

Transient





Beware


UPM

ΔIo

iL

Io

vo

ic 0 ATrip point 1

Trip point 2

ΔIo

ic





51


UPM


05358z02236z07417)(z3767G(z) 2 +sdotminus

+sdot=

B G(s)

G(z)




N = 4

ESR = 125 mΩ

( )CL

1sRESRL1s

CL1)1sCESR(V

)s(Gdv

L2

ino

sdot+sdot+sdot+


==

~ VinmiddotdCo

ESR

RphaseN LphaseN

Expected by design


DC resistance


model


Beware


UPM


Pole-Zero Map

Real Axis

-1 -08 -06 -04 -02 0 02 04 06 08 1-1

-08

-06

-04

-02

0

02

04

06

08

1

09

0807060504

03

02

01

26e5

234e5

208e5

182e5

156e513e5

104e5

781e4

521e4

26e4

26e5

234e5

208e5

182e5

156e513e5

104e5

781e4

521e4

26e4

x

x

x




Duty cycle

30 micros


1z00372)z(Rminus

=

1zK)z(R 1

minus=

Controller delay

05358z02236z07417)(z3767G(z) 2 +sdotminus

+sdot=Converter

x

x

x Duty cycle

Output voltage

52


UPM

10 micros


xx

x

x

x

x

x

x




00775)(z1)(z037)(z00378R(z)

minussdotminus+sdot

=

Duty cycle

Output voltage


UPM


75 micros

xx

x

x

x

xx

x



minussdotminus+sdot

=

53


UPM


Duty

a1 = -0922548 b1 = 0037759b2 = 0051742a2 = 0

b1

b2

δ-1

δ-1

δ-1

a1

a2

Error

bn0

No b0

δ-1

Z-1

+

00775)(z1)(z037)(z00378R(z)

minussdotminus+sdot

=




UPM


z2d_m ( tf ([00378 0013986] [1 -10775 00775] 192e-6) )




=Tsample = Tsw

⎪⎩

⎪⎨⎧

rarrδ

+=δ δδ

s


54


UPM


Reference

Switched model

7 bits

8 bits

Not quantizied


PWM

ADC

111






UPM

Reference


PWM

ADC






hellip

222

55


UPM



a1 = -0922548 b1 = 0037759b2 = 0051742a2 = 0

b1

b2

δ-1

δ-1

δ-1

a1

a2

Error

bn0

No b0


UPM


0lt Duty cycle lt1


Hardware adders






Beware

56


UPM

0 1 2 30

05

1

15

2

25








UPM



0 1 2 3

x 10-4

0

05

1

15

2

25

100 usdiv100 usdiv



57


UPM






UPM




58


UPM


13 14 15 16 17 18 19

x 10-4

12

14

16

18

2

22

08 V drop

10 microsdiv

2 V





UPM



Vo

1 V

2 V



11 A11 A

20 mV

520 kHz



59


UPM


Vo

Io

200 mV







UPM


Vo

1 V

2 V





60


UPM





Beware



UPM



3


UPM




Resolution of DPWM

variable VS





Non linear control

Robust control



2V11V

33V


UPM




212211


Applications333




222222

232233

242244

252255

262266

272277

313311 323322

333333

4


UPM


Powerconverter



-


ADCADCVmeas(t)



212211

Hardware issues222

222222

232233

242244

252255

262266

272277



UPM


H G(s)

G(z)

Hold Sampler

Vout

t





Tsamp = Tswitch



Beware

Powerconv


+

-


5


UPM




2nd approach RL ESR

VindC

ESRVind C RLOAD

+

_

L

Vout

)s(ds

RLsmiddotCmiddotL

V)s(V

LOAD

inout

12 ++=

RLOAD Vout+

_


L RL

( ))s(d

RESRRRsC

RESRRESRCR


VsCESRRESR

R

)s(V

LOAD

LOADL

LOAD

LOADL

LOAD

inLOAD

LOAD

out

++

+⎥⎦

⎤⎢⎣

⎡sdot

+sdot

+sdot++

+

sdot+sdotsdotsdot+

=2

1


UPM


HO G(s)


G(z)

Powerconverter






6


UPM



Power

converter





ADCBeware

Powerconv


+

-



UPM



V+

V_

+_

Voffset

R1

R1

R2

R2

ADCVout

Pow

erco

nver

ter

_+

7


UPM

C

R2




V+

V_

ADC

Vref

R1

R1

Vcm

_

++_

ADC

R2

C


UPM







V

t

ΔtV

t

ΔV

Beware

Powerconv


+

-


8


UPM


TSWITCH

TADC TPROCTDRIVER











UPM


High fADC butADC

latADC fNT 1

=

latencystages

stage perbitsstages

totalbit

NN

NN

N

=

= minusminus

latencyBeware

latency


9


UPM



25075

25050

25025

25000

24975

24950

24925

1 1 1

1 1 0

1 0 1

1 0 0

0 1 1

0 1 0

0 0 1



(25mV resolution)


voltage

⎟⎠⎞

⎜⎝⎛ = VV 00250

25210

Saturation



UPM





Best options

ADC-CLK

N

LATCHINSTANT


DATA N-3 N-2 N-1 N


10


UPM


Low pass filters


s11)s(Fτ+

=T

bT

bzbb

)s(F τ=

τ+=

minus=

minus 10110



Tb

zbbz)s(F τ

minus=τ

+=+

+=

minus

minus 21211101

10

1



TSWITCH

TADC TPROC

TDRIVER

TADC TADCTADC

Tfilter

Samp1

Samp2

Samp3

Samp4

1 noise-freesample


D QD Q




UPM

24 DPWM24 DPWM

Counter

refgt on_off





SWITCH

CLK


fCLK = 128 MHz

Beware

Powerconv


+

-


11


UPM




PWM63

PWM62

PWM61

Vref

error3

error2

error1

error0

error-1

error-2






of the controller)



UPM











CLKCLK2

Vout

VGS

dk


Beware

12


UPM







CLK

MUX


S QR

VGS

duty(1)duty(0)

end of sync duty


duty(n-12)

Example(L=2)

Bewareof thedelay



UPM




VGHVGL


Tswitch

delay

13


UPM



Beware




sum minusminus +=k



Driver examples





VSW

VGS

ton toff

Powerconv


+

-



UPM




zbb

zaa)z(R 110

110

++++

= minus

minus

ai bi constants









Powerconv


+

-


14


UPM

zoh

foh

matched

NA

tustin

Matlab C2D




First order hold

Polezero match



Two possibilities









UPM







Two mains reasons






15


UPM








UPM





)z(G)z(R1)z(G)z(R

)z(X)z(Y)z(M

+==

))z(M1)(z(G)z(M)z(R

minus=





Beware


+ Y(z)

_

E(z)X(z)R(z) G(z)

16


UPM





k

kk



=

⎪⎭

⎪⎬⎫

⎪⎩

⎪⎨⎧

minusminus=

minus=minusrArr

minusminus

=minusminus

minusminus


z1)z(M1)z(E

11

11








UPM


10

p1=e-σmiddotejθ


θ

γe-σ




=sR


minus= eMp



17


UPM


xx

xx

OO






96730middot29412239middot6229)(


2

7211

8

+minus+

=

+++

= minusminus

minus

zzzzG

ssssG


condition)



UPM




Vout

Duty

Near unstable



18


UPM



1z110)z(R 5

minus= minus

Vout

Duty







UPM




+= minus

Vout

Duty




19


UPM


Vout

Duty





23

+minusminus+minus




UPM


xk xk-1

hellip

xk-m

X

b0

X

b1

X

bm

hellip

+

+

hellip

+

yk yk-1

hellip

yk-n

X

a1

X

an

+

+

hellip

hellip

+

-yk

nn

22

110

mm

22

110

zazazaazbzbzbb

)z(e)z(d)z(R

minusminusminus

minusminusminus

sdot++sdot+sdot+





20


UPM

Z-1

a1

a2

Z-1


Z-1

bo

eK

Z-1

b1

b2

R1(z) R2(z)YK

dK

eK

R1 R2

Z-1

Z-1

a1

bo

b1

dKeK






UPM

Difference equation


a1a2

e(z)

⎩⎨⎧

rarrδ

+=δminus=δ= δδ+


TXXXmiddotY kkkk1k

kk

Tz1 1minusminus

=δ

k1

1k

1k Y

z1zTYXminus

minusminus

minus

sdot=δ=

δ-1 δ-1

aman

δ-1 δ-1

bm

+

bo

b1

u(z)h(z)

T Z-1

δ-1

(Integral)

+




More adders

21


UPM

a1

a2

δ-1

bo

b1T

b2T2 δ-1 T2

T


Tn Tn


Z-1

+



Adapted δ-1


UPM








ek-1 isrequested

ek-1 isavailable

dk isimposed

T

22


UPM

0 1 2 3 4 5 6 7 8

x 10 -4

-04

-02

0

02

04

06

08

1

12

14

16




vo

48 5 52 54 56 58

10-4

138

14

142

144

146

148

15

152

154

156

vo

Matlabfixed-point

toolbox






UPM



00011111b0 =


Meanerror

22 143143 5252

11 333333 170170

44 3232 0606

33 6767 1717


615615 105ns105ns

12481248 168ns168ns

Mp ts

Example

160160 012ms012ms

113113 011ms011ms1


zz

( )1

222 353


zz


00101000b0 = k53

k5


00101001b0 = k853

k8

k5


222

333



00100000b0 = k3 e2 sdotminus111


1rsquos

23


UPM





D QEN

new_cycle Xek

b0

D QEN

new_cycle Xek-1

b1

+

D QEN

new_cycle Xdk-1

a1

D QEN

new_cycle Xdk-2

b2

+ D QENnew_cycle

dk

+


D Q

D Q

D Q

D Q

D Q

D Q






UPM

Fixed-point toolbox







MatlabSimulink



24


UPM

VHDL or VHDL-AMS











UPM


Applications333



323322

333333

25


UPM


IinVin

Vout

DCDCREGULATOR LO

AD

~

IoutIin


Vout

+_Vin

CONTROL

d

R1

R2

R3

R4

n1 n2LINE

LOAD

Main Switch

Vin

Iin Vout

PO=50Wf=50kHz


PO=50Wf=50kHz



UPM





Adaptive control


LOA

D

~

IoutIin

PFC CONVERTERVout

+_Vin

Controlblock

Controlblock

onoff

R1

R2

R3

R4

Vout

Iin

Vin

ADCADC

ADC

26


UPM


X


IIN-ref

Protections


VOUT max

IIN max

ldquodrdquo max

ldquoΔdrdquo max

ON-OFF Main Switch

ON-OFF Main Switch





intΣIin

gt

CalculatedOn-Off


Max






VOUT-ref

GinPI


UPM










VinGin

Multiplier

xVin

Gin(1Rin)

50 kHz



Adder

+Iin

ΣIin

Comparator

gtOnOff

20 MHz

NoPWMNoPWM


27


UPM




10 W 30 W 50 W 30 W 10 W

Vout

IinGin

StableStable

Load


Unstable

Unstable

Unstable

Unstable


UPM




Adaptive control

28


UPM



Load Change

Vout

Iin




T



UPM

Vin_dc

Iin_dc

d

Vout


OnOff

FPGAXilinx

XC4010-e

8 8 12

Vin Vout Iin

PROMXC 17512

ADC0808

ADC0808

HI 5805


ADCsADCs

Power Converter

Vout Vin_acIin_ac

PF = 099PF = 099PF = 099

29


UPM


DigitalController


switches)Digital


Measuredamp State


Analog

ADConverter

MeasuredVariables

(digital buses)

Mixed




UPM


M1

C Vout

D11n

+

_Vin

Iin

IL1

RL

IR

ON

L1OFF

M1

C Vout

D11n

+

_Vin

Iin

IL1

RL

IR

OFF

L1ON

Vout

n

ID1 = IL1 n

IC



1

kin1k1Lk1L

1L1in L

tVII

dtdILV

Δsdot+=rArr= minus

CtI

VVdt

dVCI kR1koutkout

outR


1

1kout1k1Lk1L

1L1

out

LntV

IIdt

dILnV

sdotΔsdot


minus

C

tIn

I

VVdt

dVCInI kR

1k1L

1koutkoutout

R1L

Δsdot⎟⎟⎠

⎞⎜⎜⎝

⎛minus

+=rArr=minus

minus

minus



30


UPM


VHDLVHDLVHDL

VHDL-AMS

VHDLVHDL--AMSAMS






UPM




VHDLVHDL








Simulationtime


CPU time using VHDL

models


modelsmodels



VHDL speed VHDL-AMS

speed


speedspeed

10 ms10 10 msms 69 s69 s69 s 446 s446 s446 s 641641641

100 ms100 100 msms 700 s700 s700 s 6912 s6912 s6912 s 987987987

1000 ms1000 1000 msms 6890 s6890 s6890 s 68443 s68443 s68443 s 993993993

VHDLVHDL--AMSAMS

31


UPM

42V 14V

CC

CC 42V 14V


system vehicles


Q1-1

Q2-1

Q16-1

Q16-2

Q2-2

Q1-2

L

L

L

COCIN




UPM


Q1-1

Q2-1

Q16-1

Q16-2

Q2-2

Q1-2

L

L

L

COCIN








3 prototypes


3 prototypes



32


UPM


VoVIN

L2d2

d1L1




VINd1

Battery

R1

R2

+

+ +

VINd2

1

BAT1IN1 R

VdVI minus=

2

22 R

VdVI BATIN -=


UPM







446

416

03360

03528

320

2336



1 5

CCM ndash 1000W

824

184

Not acceptable


Q1-1

Q2-1

Q16-1

Q16-2

Q2-2

Q1-2

L

L

L

33


UPM

AVGLI AVGLI


dT T

LVV OIN minus

LVOminus

AVGLI

dT T

LVV OIN minus

LVOminus

AVGLI

⎟⎟⎠

⎞⎜⎜⎝

⎛ minus=

O

OIN

i

2iIN

i VVV

fL2dVI



AVGLI AVGLI

DCMDCM


UPM


03360

03528






416

824



1 5

CCM ndash 1000W

0262002623

0275102649


1 5

DCM ndash 1000W

Not acceptable

445

490

446

454

110102

Very good


34


UPM



420 97

435 100

440 101

435 -

DC Current(A)

429 99

428 98

446 103

460 106

Deviation()

Phase 2

Phase 3

Phase 4

Phase 5

Phase 6

Phase 7

Phase 8

Average

CCM


IO=35A




UPM


ADCInterface

ampfilter

Regulator8

d1


Vout

ADCcontrol

Reset

Vin

12

MCDgenerator

12

Vout

12

Vin

Phase-shifter

8

d2

Protections

1616

Clock

16

H-Pulses L-Pulses




35


UPM




422 97

438 101

442 102

434 -

DC Current(A)

431 99

445 102

424 98

448 103

Deviation()

Phase 2Phase 2

Phase 3Phase 3

Phase 4Phase 4

Phase 5Phase 5

Phase 6Phase 6

Phase 7Phase 7

Phase 8Phase 8

AverageAverage

DCMDCM


IO=17A

IO=27A


UPM





36


UPM


-05

0

05

1

15

2

00E+00 50E-06 10E-05 15E-05 20E-05 25E-05t (s)

()

-05

0

05

1

15

2

00E+00 50E-06 10E-05 15E-05 20E-05 25E-05t (s)

()

0

20

40

60

80

100

120

140

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35

Phase number

[+6-8]

0

20

40

60

80

100

120

140

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35

Phase number

[+6-8]

Half load(500W)


Full load(1000W)

0

1

2

3

4

p

0 5μs 10μs 15μs 20μs0

1

2

3

4

p



0

20

40

60

80

100

120

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35

Phase number

+10-75

0

20

40

60

80

100

120

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35

Phase number

+10-75



UPM

Output currentDC AC

11App

70ADC


is

0 01 02 03 04 05 06 07 08 09 100102030405

060708091

Duty cycle (d)

Nor

m c

urre

nt r

ippl

e Dutyvariation

2 phases

3 phases



37


UPM

10

5

5

10

3T0 x

5

5

3T0 x

Ideal case






10

5

5

10

3T0 x

5

5

3T0 x

Non-ideal



10

5

5

10

3T0 x

5

5

3T0 x

Worse case



10

5

5

10

3T0 x

5

5

3T0 x





UPM

ΔIP-P= 40A (5Adiv)

1 phase

ΔIP-P= 12A (5Adiv)

2 phases

ΔIP-P= 5A (5Adiv)

4 phases

ΔIP-P= 22A (1Adiv)

8 phases

ΔIP-P= 16A (1Adiv)

16 phases



38


UPM

(a)

30

31

22 40

37

22 33

2830

31

22 40

37

22 33

28

(a)

Center of mass

(a)

30

31

22 40

37

22 33

2830

31

22 40

37

22 33

28

(a)

Center of mass

Phase1Phase

2

Phase3

Phase4

Phase5

Phase6

Phase7

Phase8

1st

2nd

3rd 4th

6th

5th 8th

7th

(b)

1st

2nd

3rd 4th

6th

5th 8th

7th

1st

2nd

3rd 4th

6th

5th 8th

7th

(b)

40 A

37 A30 A

33 A

22 A 28 A

31 A

22 A






UPM

18 0 18

18

18

OVERALL 67A

18 0 18

18

18

1

2

34

56

7

8

9

10

1112 13

14

15

16

MAX

MIN

18 0 18

18

18

OVERALL 05A

18 0 18

18

18

1

2

34

56

7

8

9

10

1112 13

1415

16

MAX

MIN


16151413121110987654321

Phase number

165155177152140144148128147122154158139149142133

Current ripple (A)

39


UPM

ΔIP-P= 40A

ΔIP-P= 40A

ΔIP-P= 07A

ΔIP-P= 16A

57

ΔIP-P= 11A

ΔIP-P= 22A

50

ΔIP-P= 28A

ΔIP-P= 5A

44

ΔIP-P= 11A

ΔIP-P= 12A

9






1 2 4 8 16



UPM


Tswitch

delay

Load

voutvin



COUNTERDUTY CYCLE

DRIVING SIGNAL

Load

voutvin



40


UPM



Dri

vin

gsi

gnal

s

Counter

+ hellip +


Duty cycle





UPM


Dri

vin

gD

rivi

ng

sign

als

sign

als



ltDuty cycle


Shift Register



Counter


41


UPM






ASIC

12 12 phasesphases

6 6 phasesphases

24 24 phasesphases





0

2000

4000

6000

8000

10000

12000

14000

16000

2 4 6 8 12 16 20 24

0

2000

4000

6000

8000

10000

12000

2 4 6 8 12 16 20 24

0

2000

4000

6000

8000

10000

12000

14000

16000

18000

2 4 6 8 12 16 20 24


Res

ol 1

28Res

ol 2

56Res

ol 5

12

FPGA

Equ

ival

ent

gate

s

Phases

0

200

400

600

800

1000

2 4 6 8 12 16 20 24


Res

ol 1

28Res

ol 2

56Res

ol 5

120

200

400

600

800

1000

1200

2 4 6 8 12 16 20 24

0

200

400

600

800

1000

1200

1400

2 4 6 8 12 16 20 24

ASIC

Equ

ival

ent

gate

s

Phases


UPM


0

10

20

30

40

50

0 20 40 60 80



0

10

20

30

40

50

0 20 40 60 80



Iout

Pow

erlo

sses

(W)

80

84

88

92

96

0 10 20 30 40 50 60 70 80

6 phases

8 phases12 phases

16 phases

4 phases



Iout

Effic

ienc

y(

)

80

84

88

92

96

0 10 20 30 40 50 60 70 80

6 phases

8 phases12 phases

16 phases

4 phases



Iout

Effic

ienc

y(

)



42


UPM





UPM


RFAmp

Pow

erSt

age

Control

iRF

vs

VS

variable VS


24V

9Vfmax=35kHz

Input voltage = 28V





43


UPM


Cs

M1

L

M2

Cs

M1

L

M2

Cs

M1

L

M2

Cs

M1

L

M2

Ve Vout

CAR

GA




UPM


SW

CLK

ff Resolution =

Pipeline

fCLK

f = 25MHz f = 45MHz

Resolution required



fselected = 32MHz


44


UPM

33 33 DitherDither

SW

CLK

ff Resolution gt

d = 42

d =43

d =425

T=2TSW=8μs

Output voltage

2 solutions

V=50mV

TSW=4μs 1 solution

T=4μs

Output voltage

V=25mV

SW

CLKNVirtual



Average duty cycle

It gives 1 more bit


UPM



SimulatedSimulated

MeasuredMeasured



)(

4110780250 22




45


UPM






UPM


f = 200Hz f = 15kHz

f = 3kHz f = 5kHz

46


UPM





UPM



2 2 micromicross

Vo

1 V

2 V

VRM for DVS5 V

Io = 20 A max

1V - 2 V

Io

02 V max02 V max

0 A

20 A

500 Amicros

Vo




47


UPM


10-1 100 101

100

L-C diagram

C2 micros

200 mV

20A




C = 35 C = 35 μμFF



UPM






fsw = 520 kHz

(125 mΩ eq Rds_on)





48


UPM


0

1

To drivers

New vref

vo dig

N-phases_tran

N-phases

New vref

vo dig

New vref

vo dig


ic


NON-LINEAR CONTROL





UPM


vref

vo

0

1

To drivers

clk_sample

clk_sample

ADC

N-phases_tran

N-phases

vo dig

LINEAR CONTROL



49


UPM


vref

vo

0

1

To drivers

New vref

vo dig

clk_sample

clk_sample

ADC

N-phases_tran

N-phases

vo dig

New vref

LINEAR CONTROL

NON-LINEAR CONTROL

vo dig

New vrefvo dig


ic



Beware


UPM


UpUp--stepstep

ConverterFPGA

tt11



DownDown--stepstep

t1 t2 t1 t2

ddnn

tt22vref

500 kHz

LUT


05

1

15

2

25

0 02 04 06 08 1 12 14 16 18-10

0

10

20

30

40

50

ton toff

Tmin

05

1

15

2

25

0 02 04 06 08 1 12 14 16 18-10

0

10

20

30

40

50

ton toff

Tmin

i L(A

)i L

(A)

V o(V

)V o

(V)


50


UPM


t1 t2 t1 t2

094 096 098 1 102 104 106 108 11

x 10-4

14

16

18

2

22

24

26

28

3

32

094 096 098 1 102 104 106 108 11

x 10-4

0

1

2

3

4

5092 094 096 098 1 102 104 106 108 11 112

x 10-4

14

16

18

2

22

24

26

28

3

32

092 094 096 098 1 102 104 106 108 11 112

x 10-4

0

05

1

15

2

25

3

35

4

45

Transient





Beware


UPM

ΔIo

iL

Io

vo

ic 0 ATrip point 1

Trip point 2

ΔIo

ic





51


UPM


05358z02236z07417)(z3767G(z) 2 +sdotminus

+sdot=

B G(s)

G(z)




N = 4

ESR = 125 mΩ

( )CL

1sRESRL1s

CL1)1sCESR(V

)s(Gdv

L2

ino

sdot+sdot+sdot+


==

~ VinmiddotdCo

ESR

RphaseN LphaseN

Expected by design


DC resistance


model


Beware


UPM


Pole-Zero Map

Real Axis

-1 -08 -06 -04 -02 0 02 04 06 08 1-1

-08

-06

-04

-02

0

02

04

06

08

1

09

0807060504

03

02

01

26e5

234e5

208e5

182e5

156e513e5

104e5

781e4

521e4

26e4

26e5

234e5

208e5

182e5

156e513e5

104e5

781e4

521e4

26e4

x

x

x




Duty cycle

30 micros


1z00372)z(Rminus

=

1zK)z(R 1

minus=

Controller delay

05358z02236z07417)(z3767G(z) 2 +sdotminus

+sdot=Converter

x

x

x Duty cycle

Output voltage

52


UPM

10 micros


xx

x

x

x

x

x

x




00775)(z1)(z037)(z00378R(z)

minussdotminus+sdot

=

Duty cycle

Output voltage


UPM


75 micros

xx

x

x

x

xx

x



minussdotminus+sdot

=

53


UPM


Duty

a1 = -0922548 b1 = 0037759b2 = 0051742a2 = 0

b1

b2

δ-1

δ-1

δ-1

a1

a2

Error

bn0

No b0

δ-1

Z-1

+

00775)(z1)(z037)(z00378R(z)

minussdotminus+sdot

=




UPM


z2d_m ( tf ([00378 0013986] [1 -10775 00775] 192e-6) )




=Tsample = Tsw

⎪⎩

⎪⎨⎧

rarrδ

+=δ δδ

s


54


UPM


Reference

Switched model

7 bits

8 bits

Not quantizied


PWM

ADC

111






UPM

Reference


PWM

ADC






hellip

222

55


UPM



a1 = -0922548 b1 = 0037759b2 = 0051742a2 = 0

b1

b2

δ-1

δ-1

δ-1

a1

a2

Error

bn0

No b0


UPM


0lt Duty cycle lt1


Hardware adders






Beware

56


UPM

0 1 2 30

05

1

15

2

25








UPM



0 1 2 3

x 10-4

0

05

1

15

2

25

100 usdiv100 usdiv



57


UPM






UPM




58


UPM


13 14 15 16 17 18 19

x 10-4

12

14

16

18

2

22

08 V drop

10 microsdiv

2 V





UPM



Vo

1 V

2 V



11 A11 A

20 mV

520 kHz



59


UPM


Vo

Io

200 mV







UPM


Vo

1 V

2 V





60


UPM





Beware



UPM



4


UPM


Powerconverter



-


ADCADCVmeas(t)



212211

Hardware issues222

222222

232233

242244

252255

262266

272277



UPM


H G(s)

G(z)

Hold Sampler

Vout

t





Tsamp = Tswitch



Beware

Powerconv


+

-


5


UPM




2nd approach RL ESR

VindC

ESRVind C RLOAD

+

_

L

Vout

)s(ds

RLsmiddotCmiddotL

V)s(V

LOAD

inout

12 ++=

RLOAD Vout+

_


L RL

( ))s(d

RESRRRsC

RESRRESRCR


VsCESRRESR

R

)s(V

LOAD

LOADL

LOAD

LOADL

LOAD

inLOAD

LOAD

out

++

+⎥⎦

⎤⎢⎣

⎡sdot

+sdot

+sdot++

+

sdot+sdotsdotsdot+

=2

1


UPM


HO G(s)


G(z)

Powerconverter






6


UPM



Power

converter





ADCBeware

Powerconv


+

-



UPM



V+

V_

+_

Voffset

R1

R1

R2

R2

ADCVout

Pow

erco

nver

ter

_+

7


UPM

C

R2




V+

V_

ADC

Vref

R1

R1

Vcm

_

++_

ADC

R2

C


UPM







V

t

ΔtV

t

ΔV

Beware

Powerconv


+

-


8


UPM


TSWITCH

TADC TPROCTDRIVER











UPM


High fADC butADC

latADC fNT 1

=

latencystages

stage perbitsstages

totalbit

NN

NN

N

=

= minusminus

latencyBeware

latency


9


UPM



25075

25050

25025

25000

24975

24950

24925

1 1 1

1 1 0

1 0 1

1 0 0

0 1 1

0 1 0

0 0 1



(25mV resolution)


voltage

⎟⎠⎞

⎜⎝⎛ = VV 00250

25210

Saturation



UPM





Best options

ADC-CLK

N

LATCHINSTANT


DATA N-3 N-2 N-1 N


10


UPM


Low pass filters


s11)s(Fτ+

=T

bT

bzbb

)s(F τ=

τ+=

minus=

minus 10110



Tb

zbbz)s(F τ

minus=τ

+=+

+=

minus

minus 21211101

10

1



TSWITCH

TADC TPROC

TDRIVER

TADC TADCTADC

Tfilter

Samp1

Samp2

Samp3

Samp4

1 noise-freesample


D QD Q




UPM

24 DPWM24 DPWM

Counter

refgt on_off





SWITCH

CLK


fCLK = 128 MHz

Beware

Powerconv


+

-


11


UPM




PWM63

PWM62

PWM61

Vref

error3

error2

error1

error0

error-1

error-2






of the controller)



UPM











CLKCLK2

Vout

VGS

dk


Beware

12


UPM







CLK

MUX


S QR

VGS

duty(1)duty(0)

end of sync duty


duty(n-12)

Example(L=2)

Bewareof thedelay



UPM




VGHVGL


Tswitch

delay

13


UPM



Beware




sum minusminus +=k



Driver examples





VSW

VGS

ton toff

Powerconv


+

-



UPM




zbb

zaa)z(R 110

110

++++

= minus

minus

ai bi constants









Powerconv


+

-


14


UPM

zoh

foh

matched

NA

tustin

Matlab C2D




First order hold

Polezero match



Two possibilities









UPM







Two mains reasons






15


UPM








UPM





)z(G)z(R1)z(G)z(R

)z(X)z(Y)z(M

+==

))z(M1)(z(G)z(M)z(R

minus=





Beware


+ Y(z)

_

E(z)X(z)R(z) G(z)

16


UPM





k

kk



=

⎪⎭

⎪⎬⎫

⎪⎩

⎪⎨⎧

minusminus=

minus=minusrArr

minusminus

=minusminus

minusminus


z1)z(M1)z(E

11

11








UPM


10

p1=e-σmiddotejθ


θ

γe-σ




=sR


minus= eMp



17


UPM


xx

xx

OO






96730middot29412239middot6229)(


2

7211

8

+minus+

=

+++

= minusminus

minus

zzzzG

ssssG


condition)



UPM




Vout

Duty

Near unstable



18


UPM



1z110)z(R 5

minus= minus

Vout

Duty







UPM




+= minus

Vout

Duty




19


UPM


Vout

Duty





23

+minusminus+minus




UPM


xk xk-1

hellip

xk-m

X

b0

X

b1

X

bm

hellip

+

+

hellip

+

yk yk-1

hellip

yk-n

X

a1

X

an

+

+

hellip

hellip

+

-yk

nn

22

110

mm

22

110

zazazaazbzbzbb

)z(e)z(d)z(R

minusminusminus

minusminusminus

sdot++sdot+sdot+





20


UPM

Z-1

a1

a2

Z-1


Z-1

bo

eK

Z-1

b1

b2

R1(z) R2(z)YK

dK

eK

R1 R2

Z-1

Z-1

a1

bo

b1

dKeK






UPM

Difference equation


a1a2

e(z)

⎩⎨⎧

rarrδ

+=δminus=δ= δδ+


TXXXmiddotY kkkk1k

kk

Tz1 1minusminus

=δ

k1

1k

1k Y

z1zTYXminus

minusminus

minus

sdot=δ=

δ-1 δ-1

aman

δ-1 δ-1

bm

+

bo

b1

u(z)h(z)

T Z-1

δ-1

(Integral)

+




More adders

21


UPM

a1

a2

δ-1

bo

b1T

b2T2 δ-1 T2

T


Tn Tn


Z-1

+



Adapted δ-1


UPM








ek-1 isrequested

ek-1 isavailable

dk isimposed

T

22


UPM

0 1 2 3 4 5 6 7 8

x 10 -4

-04

-02

0

02

04

06

08

1

12

14

16




vo

48 5 52 54 56 58

10-4

138

14

142

144

146

148

15

152

154

156

vo

Matlabfixed-point

toolbox






UPM



00011111b0 =


Meanerror

22 143143 5252

11 333333 170170

44 3232 0606

33 6767 1717


615615 105ns105ns

12481248 168ns168ns

Mp ts

Example

160160 012ms012ms

113113 011ms011ms1


zz

( )1

222 353


zz


00101000b0 = k53

k5


00101001b0 = k853

k8

k5


222

333



00100000b0 = k3 e2 sdotminus111


1rsquos

23


UPM





D QEN

new_cycle Xek

b0

D QEN

new_cycle Xek-1

b1

+

D QEN

new_cycle Xdk-1

a1

D QEN

new_cycle Xdk-2

b2

+ D QENnew_cycle

dk

+


D Q

D Q

D Q

D Q

D Q

D Q






UPM

Fixed-point toolbox







MatlabSimulink



24


UPM

VHDL or VHDL-AMS











UPM


Applications333



323322

333333

25


UPM


IinVin

Vout

DCDCREGULATOR LO

AD

~

IoutIin


Vout

+_Vin

CONTROL

d

R1

R2

R3

R4

n1 n2LINE

LOAD

Main Switch

Vin

Iin Vout

PO=50Wf=50kHz


PO=50Wf=50kHz



UPM





Adaptive control


LOA

D

~

IoutIin

PFC CONVERTERVout

+_Vin

Controlblock

Controlblock

onoff

R1

R2

R3

R4

Vout

Iin

Vin

ADCADC

ADC

26


UPM


X


IIN-ref

Protections


VOUT max

IIN max

ldquodrdquo max

ldquoΔdrdquo max

ON-OFF Main Switch

ON-OFF Main Switch





intΣIin

gt

CalculatedOn-Off


Max






VOUT-ref

GinPI


UPM










VinGin

Multiplier

xVin

Gin(1Rin)

50 kHz



Adder

+Iin

ΣIin

Comparator

gtOnOff

20 MHz

NoPWMNoPWM


27


UPM




10 W 30 W 50 W 30 W 10 W

Vout

IinGin

StableStable

Load


Unstable

Unstable

Unstable

Unstable


UPM




Adaptive control

28


UPM



Load Change

Vout

Iin




T



UPM

Vin_dc

Iin_dc

d

Vout


OnOff

FPGAXilinx

XC4010-e

8 8 12

Vin Vout Iin

PROMXC 17512

ADC0808

ADC0808

HI 5805


ADCsADCs

Power Converter

Vout Vin_acIin_ac

PF = 099PF = 099PF = 099

29


UPM


DigitalController


switches)Digital


Measuredamp State


Analog

ADConverter

MeasuredVariables

(digital buses)

Mixed




UPM


M1

C Vout

D11n

+

_Vin

Iin

IL1

RL

IR

ON

L1OFF

M1

C Vout

D11n

+

_Vin

Iin

IL1

RL

IR

OFF

L1ON

Vout

n

ID1 = IL1 n

IC



1

kin1k1Lk1L

1L1in L

tVII

dtdILV

Δsdot+=rArr= minus

CtI

VVdt

dVCI kR1koutkout

outR


1

1kout1k1Lk1L

1L1

out

LntV

IIdt

dILnV

sdotΔsdot


minus

C

tIn

I

VVdt

dVCInI kR

1k1L

1koutkoutout

R1L

Δsdot⎟⎟⎠

⎞⎜⎜⎝

⎛minus

+=rArr=minus

minus

minus



30


UPM


VHDLVHDLVHDL

VHDL-AMS

VHDLVHDL--AMSAMS






UPM




VHDLVHDL








Simulationtime


CPU time using VHDL

models


modelsmodels



VHDL speed VHDL-AMS

speed


speedspeed

10 ms10 10 msms 69 s69 s69 s 446 s446 s446 s 641641641

100 ms100 100 msms 700 s700 s700 s 6912 s6912 s6912 s 987987987

1000 ms1000 1000 msms 6890 s6890 s6890 s 68443 s68443 s68443 s 993993993

VHDLVHDL--AMSAMS

31


UPM

42V 14V

CC

CC 42V 14V


system vehicles


Q1-1

Q2-1

Q16-1

Q16-2

Q2-2

Q1-2

L

L

L

COCIN




UPM


Q1-1

Q2-1

Q16-1

Q16-2

Q2-2

Q1-2

L

L

L

COCIN








3 prototypes


3 prototypes



32


UPM


VoVIN

L2d2

d1L1




VINd1

Battery

R1

R2

+

+ +

VINd2

1

BAT1IN1 R

VdVI minus=

2

22 R

VdVI BATIN -=


UPM







446

416

03360

03528

320

2336



1 5

CCM ndash 1000W

824

184

Not acceptable


Q1-1

Q2-1

Q16-1

Q16-2

Q2-2

Q1-2

L

L

L

33


UPM

AVGLI AVGLI


dT T

LVV OIN minus

LVOminus

AVGLI

dT T

LVV OIN minus

LVOminus

AVGLI

⎟⎟⎠

⎞⎜⎜⎝

⎛ minus=

O

OIN

i

2iIN

i VVV

fL2dVI



AVGLI AVGLI

DCMDCM


UPM


03360

03528






416

824



1 5

CCM ndash 1000W

0262002623

0275102649


1 5

DCM ndash 1000W

Not acceptable

445

490

446

454

110102

Very good


34


UPM



420 97

435 100

440 101

435 -

DC Current(A)

429 99

428 98

446 103

460 106

Deviation()

Phase 2

Phase 3

Phase 4

Phase 5

Phase 6

Phase 7

Phase 8

Average

CCM


IO=35A




UPM


ADCInterface

ampfilter

Regulator8

d1


Vout

ADCcontrol

Reset

Vin

12

MCDgenerator

12

Vout

12

Vin

Phase-shifter

8

d2

Protections

1616

Clock

16

H-Pulses L-Pulses




35


UPM




422 97

438 101

442 102

434 -

DC Current(A)

431 99

445 102

424 98

448 103

Deviation()

Phase 2Phase 2

Phase 3Phase 3

Phase 4Phase 4

Phase 5Phase 5

Phase 6Phase 6

Phase 7Phase 7

Phase 8Phase 8

AverageAverage

DCMDCM


IO=17A

IO=27A


UPM





36


UPM


-05

0

05

1

15

2

00E+00 50E-06 10E-05 15E-05 20E-05 25E-05t (s)

()

-05

0

05

1

15

2

00E+00 50E-06 10E-05 15E-05 20E-05 25E-05t (s)

()

0

20

40

60

80

100

120

140

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35

Phase number

[+6-8]

0

20

40

60

80

100

120

140

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35

Phase number

[+6-8]

Half load(500W)


Full load(1000W)

0

1

2

3

4

p

0 5μs 10μs 15μs 20μs0

1

2

3

4

p



0

20

40

60

80

100

120

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35

Phase number

+10-75

0

20

40

60

80

100

120

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35

Phase number

+10-75



UPM

Output currentDC AC

11App

70ADC


is

0 01 02 03 04 05 06 07 08 09 100102030405

060708091

Duty cycle (d)

Nor

m c

urre

nt r

ippl

e Dutyvariation

2 phases

3 phases



37


UPM

10

5

5

10

3T0 x

5

5

3T0 x

Ideal case






10

5

5

10

3T0 x

5

5

3T0 x

Non-ideal



10

5

5

10

3T0 x

5

5

3T0 x

Worse case



10

5

5

10

3T0 x

5

5

3T0 x





UPM

ΔIP-P= 40A (5Adiv)

1 phase

ΔIP-P= 12A (5Adiv)

2 phases

ΔIP-P= 5A (5Adiv)

4 phases

ΔIP-P= 22A (1Adiv)

8 phases

ΔIP-P= 16A (1Adiv)

16 phases



38


UPM

(a)

30

31

22 40

37

22 33

2830

31

22 40

37

22 33

28

(a)

Center of mass

(a)

30

31

22 40

37

22 33

2830

31

22 40

37

22 33

28

(a)

Center of mass

Phase1Phase

2

Phase3

Phase4

Phase5

Phase6

Phase7

Phase8

1st

2nd

3rd 4th

6th

5th 8th

7th

(b)

1st

2nd

3rd 4th

6th

5th 8th

7th

1st

2nd

3rd 4th

6th

5th 8th

7th

(b)

40 A

37 A30 A

33 A

22 A 28 A

31 A

22 A






UPM

18 0 18

18

18

OVERALL 67A

18 0 18

18

18

1

2

34

56

7

8

9

10

1112 13

14

15

16

MAX

MIN

18 0 18

18

18

OVERALL 05A

18 0 18

18

18

1

2

34

56

7

8

9

10

1112 13

1415

16

MAX

MIN


16151413121110987654321

Phase number

165155177152140144148128147122154158139149142133

Current ripple (A)

39


UPM

ΔIP-P= 40A

ΔIP-P= 40A

ΔIP-P= 07A

ΔIP-P= 16A

57

ΔIP-P= 11A

ΔIP-P= 22A

50

ΔIP-P= 28A

ΔIP-P= 5A

44

ΔIP-P= 11A

ΔIP-P= 12A

9






1 2 4 8 16



UPM


Tswitch

delay

Load

voutvin



COUNTERDUTY CYCLE

DRIVING SIGNAL

Load

voutvin



40


UPM



Dri

vin

gsi

gnal

s

Counter

+ hellip +


Duty cycle





UPM


Dri

vin

gD

rivi

ng

sign

als

sign

als



ltDuty cycle


Shift Register



Counter


41


UPM






ASIC

12 12 phasesphases

6 6 phasesphases

24 24 phasesphases





0

2000

4000

6000

8000

10000

12000

14000

16000

2 4 6 8 12 16 20 24

0

2000

4000

6000

8000

10000

12000

2 4 6 8 12 16 20 24

0

2000

4000

6000

8000

10000

12000

14000

16000

18000

2 4 6 8 12 16 20 24


Res

ol 1

28Res

ol 2

56Res

ol 5

12

FPGA

Equ

ival

ent

gate

s

Phases

0

200

400

600

800

1000

2 4 6 8 12 16 20 24


Res

ol 1

28Res

ol 2

56Res

ol 5

120

200

400

600

800

1000

1200

2 4 6 8 12 16 20 24

0

200

400

600

800

1000

1200

1400

2 4 6 8 12 16 20 24

ASIC

Equ

ival

ent

gate

s

Phases


UPM


0

10

20

30

40

50

0 20 40 60 80



0

10

20

30

40

50

0 20 40 60 80



Iout

Pow

erlo

sses

(W)

80

84

88

92

96

0 10 20 30 40 50 60 70 80

6 phases

8 phases12 phases

16 phases

4 phases



Iout

Effic

ienc

y(

)

80

84

88

92

96

0 10 20 30 40 50 60 70 80

6 phases

8 phases12 phases

16 phases

4 phases



Iout

Effic

ienc

y(

)



42


UPM





UPM


RFAmp

Pow

erSt

age

Control

iRF

vs

VS

variable VS


24V

9Vfmax=35kHz

Input voltage = 28V





43


UPM


Cs

M1

L

M2

Cs

M1

L

M2

Cs

M1

L

M2

Cs

M1

L

M2

Ve Vout

CAR

GA




UPM


SW

CLK

ff Resolution =

Pipeline

fCLK

f = 25MHz f = 45MHz

Resolution required



fselected = 32MHz


44


UPM

33 33 DitherDither

SW

CLK

ff Resolution gt

d = 42

d =43

d =425

T=2TSW=8μs

Output voltage

2 solutions

V=50mV

TSW=4μs 1 solution

T=4μs

Output voltage

V=25mV

SW

CLKNVirtual



Average duty cycle

It gives 1 more bit


UPM



SimulatedSimulated

MeasuredMeasured



)(

4110780250 22




45


UPM






UPM


f = 200Hz f = 15kHz

f = 3kHz f = 5kHz

46


UPM





UPM



2 2 micromicross

Vo

1 V

2 V

VRM for DVS5 V

Io = 20 A max

1V - 2 V

Io

02 V max02 V max

0 A

20 A

500 Amicros

Vo




47


UPM


10-1 100 101

100

L-C diagram

C2 micros

200 mV

20A




C = 35 C = 35 μμFF



UPM






fsw = 520 kHz

(125 mΩ eq Rds_on)





48


UPM


0

1

To drivers

New vref

vo dig

N-phases_tran

N-phases

New vref

vo dig

New vref

vo dig


ic


NON-LINEAR CONTROL





UPM


vref

vo

0

1

To drivers

clk_sample

clk_sample

ADC

N-phases_tran

N-phases

vo dig

LINEAR CONTROL



49


UPM


vref

vo

0

1

To drivers

New vref

vo dig

clk_sample

clk_sample

ADC

N-phases_tran

N-phases

vo dig

New vref

LINEAR CONTROL

NON-LINEAR CONTROL

vo dig

New vrefvo dig


ic



Beware


UPM


UpUp--stepstep

ConverterFPGA

tt11



DownDown--stepstep

t1 t2 t1 t2

ddnn

tt22vref

500 kHz

LUT


05

1

15

2

25

0 02 04 06 08 1 12 14 16 18-10

0

10

20

30

40

50

ton toff

Tmin

05

1

15

2

25

0 02 04 06 08 1 12 14 16 18-10

0

10

20

30

40

50

ton toff

Tmin

i L(A

)i L

(A)

V o(V

)V o

(V)


50


UPM


t1 t2 t1 t2

094 096 098 1 102 104 106 108 11

x 10-4

14

16

18

2

22

24

26

28

3

32

094 096 098 1 102 104 106 108 11

x 10-4

0

1

2

3

4

5092 094 096 098 1 102 104 106 108 11 112

x 10-4

14

16

18

2

22

24

26

28

3

32

092 094 096 098 1 102 104 106 108 11 112

x 10-4

0

05

1

15

2

25

3

35

4

45

Transient





Beware


UPM

ΔIo

iL

Io

vo

ic 0 ATrip point 1

Trip point 2

ΔIo

ic





51


UPM


05358z02236z07417)(z3767G(z) 2 +sdotminus

+sdot=

B G(s)

G(z)




N = 4

ESR = 125 mΩ

( )CL

1sRESRL1s

CL1)1sCESR(V

)s(Gdv

L2

ino

sdot+sdot+sdot+


==

~ VinmiddotdCo

ESR

RphaseN LphaseN

Expected by design


DC resistance


model


Beware


UPM


Pole-Zero Map

Real Axis

-1 -08 -06 -04 -02 0 02 04 06 08 1-1

-08

-06

-04

-02

0

02

04

06

08

1

09

0807060504

03

02

01

26e5

234e5

208e5

182e5

156e513e5

104e5

781e4

521e4

26e4

26e5

234e5

208e5

182e5

156e513e5

104e5

781e4

521e4

26e4

x

x

x




Duty cycle

30 micros


1z00372)z(Rminus

=

1zK)z(R 1

minus=

Controller delay

05358z02236z07417)(z3767G(z) 2 +sdotminus

+sdot=Converter

x

x

x Duty cycle

Output voltage

52


UPM

10 micros


xx

x

x

x

x

x

x




00775)(z1)(z037)(z00378R(z)

minussdotminus+sdot

=

Duty cycle

Output voltage


UPM


75 micros

xx

x

x

x

xx

x



minussdotminus+sdot

=

53


UPM


Duty

a1 = -0922548 b1 = 0037759b2 = 0051742a2 = 0

b1

b2

δ-1

δ-1

δ-1

a1

a2

Error

bn0

No b0

δ-1

Z-1

+

00775)(z1)(z037)(z00378R(z)

minussdotminus+sdot

=




UPM


z2d_m ( tf ([00378 0013986] [1 -10775 00775] 192e-6) )




=Tsample = Tsw

⎪⎩

⎪⎨⎧

rarrδ

+=δ δδ

s


54


UPM


Reference

Switched model

7 bits

8 bits

Not quantizied


PWM

ADC

111






UPM

Reference


PWM

ADC






hellip

222

55


UPM



a1 = -0922548 b1 = 0037759b2 = 0051742a2 = 0

b1

b2

δ-1

δ-1

δ-1

a1

a2

Error

bn0

No b0


UPM


0lt Duty cycle lt1


Hardware adders






Beware

56


UPM

0 1 2 30

05

1

15

2

25








UPM



0 1 2 3

x 10-4

0

05

1

15

2

25

100 usdiv100 usdiv



57


UPM






UPM




58


UPM


13 14 15 16 17 18 19

x 10-4

12

14

16

18

2

22

08 V drop

10 microsdiv

2 V





UPM



Vo

1 V

2 V



11 A11 A

20 mV

520 kHz



59


UPM


Vo

Io

200 mV







UPM


Vo

1 V

2 V





60


UPM





Beware



UPM



5


UPM




2nd approach RL ESR

VindC

ESRVind C RLOAD

+

_

L

Vout

)s(ds

RLsmiddotCmiddotL

V)s(V

LOAD

inout

12 ++=

RLOAD Vout+

_


L RL

( ))s(d

RESRRRsC

RESRRESRCR


VsCESRRESR

R

)s(V

LOAD

LOADL

LOAD

LOADL

LOAD

inLOAD

LOAD

out

++

+⎥⎦

⎤⎢⎣

⎡sdot

+sdot

+sdot++

+

sdot+sdotsdotsdot+

=2

1


UPM


HO G(s)


G(z)

Powerconverter






6


UPM



Power

converter





ADCBeware

Powerconv


+

-



UPM



V+

V_

+_

Voffset

R1

R1

R2

R2

ADCVout

Pow

erco

nver

ter

_+

7


UPM

C

R2




V+

V_

ADC

Vref

R1

R1

Vcm

_

++_

ADC

R2

C


UPM







V

t

ΔtV

t

ΔV

Beware

Powerconv


+

-


8


UPM


TSWITCH

TADC TPROCTDRIVER











UPM


High fADC butADC

latADC fNT 1

=

latencystages

stage perbitsstages

totalbit

NN

NN

N

=

= minusminus

latencyBeware

latency


9


UPM



25075

25050

25025

25000

24975

24950

24925

1 1 1

1 1 0

1 0 1

1 0 0

0 1 1

0 1 0

0 0 1



(25mV resolution)


voltage

⎟⎠⎞

⎜⎝⎛ = VV 00250

25210

Saturation



UPM





Best options

ADC-CLK

N

LATCHINSTANT


DATA N-3 N-2 N-1 N


10


UPM


Low pass filters


s11)s(Fτ+

=T

bT

bzbb

)s(F τ=

τ+=

minus=

minus 10110



Tb

zbbz)s(F τ

minus=τ

+=+

+=

minus

minus 21211101

10

1



TSWITCH

TADC TPROC

TDRIVER

TADC TADCTADC

Tfilter

Samp1

Samp2

Samp3

Samp4

1 noise-freesample


D QD Q




UPM

24 DPWM24 DPWM

Counter

refgt on_off





SWITCH

CLK


fCLK = 128 MHz

Beware

Powerconv


+

-


11


UPM




PWM63

PWM62

PWM61

Vref

error3

error2

error1

error0

error-1

error-2






of the controller)



UPM











CLKCLK2

Vout

VGS

dk


Beware

12


UPM







CLK

MUX


S QR

VGS

duty(1)duty(0)

end of sync duty


duty(n-12)

Example(L=2)

Bewareof thedelay



UPM




VGHVGL


Tswitch

delay

13


UPM



Beware




sum minusminus +=k



Driver examples





VSW

VGS

ton toff

Powerconv


+

-



UPM




zbb

zaa)z(R 110

110

++++

= minus

minus

ai bi constants









Powerconv


+

-


14


UPM

zoh

foh

matched

NA

tustin

Matlab C2D




First order hold

Polezero match



Two possibilities









UPM







Two mains reasons






15


UPM








UPM





)z(G)z(R1)z(G)z(R

)z(X)z(Y)z(M

+==

))z(M1)(z(G)z(M)z(R

minus=





Beware


+ Y(z)

_

E(z)X(z)R(z) G(z)

16


UPM





k

kk



=

⎪⎭

⎪⎬⎫

⎪⎩

⎪⎨⎧

minusminus=

minus=minusrArr

minusminus

=minusminus

minusminus


z1)z(M1)z(E

11

11








UPM


10

p1=e-σmiddotejθ


θ

γe-σ




=sR


minus= eMp



17


UPM


xx

xx

OO






96730middot29412239middot6229)(


2

7211

8

+minus+

=

+++

= minusminus

minus

zzzzG

ssssG


condition)



UPM




Vout

Duty

Near unstable



18


UPM



1z110)z(R 5

minus= minus

Vout

Duty







UPM




+= minus

Vout

Duty




19


UPM


Vout

Duty





23

+minusminus+minus




UPM


xk xk-1

hellip

xk-m

X

b0

X

b1

X

bm

hellip

+

+

hellip

+

yk yk-1

hellip

yk-n

X

a1

X

an

+

+

hellip

hellip

+

-yk

nn

22

110

mm

22

110

zazazaazbzbzbb

)z(e)z(d)z(R

minusminusminus

minusminusminus

sdot++sdot+sdot+





20


UPM

Z-1

a1

a2

Z-1


Z-1

bo

eK

Z-1

b1

b2

R1(z) R2(z)YK

dK

eK

R1 R2

Z-1

Z-1

a1

bo

b1

dKeK






UPM

Difference equation


a1a2

e(z)

⎩⎨⎧

rarrδ

+=δminus=δ= δδ+


TXXXmiddotY kkkk1k

kk

Tz1 1minusminus

=δ

k1

1k

1k Y

z1zTYXminus

minusminus

minus

sdot=δ=

δ-1 δ-1

aman

δ-1 δ-1

bm

+

bo

b1

u(z)h(z)

T Z-1

δ-1

(Integral)

+




More adders

21


UPM

a1

a2

δ-1

bo

b1T

b2T2 δ-1 T2

T


Tn Tn


Z-1

+



Adapted δ-1


UPM








ek-1 isrequested

ek-1 isavailable

dk isimposed

T

22


UPM

0 1 2 3 4 5 6 7 8

x 10 -4

-04

-02

0

02

04

06

08

1

12

14

16




vo

48 5 52 54 56 58

10-4

138

14

142

144

146

148

15

152

154

156

vo

Matlabfixed-point

toolbox






UPM



00011111b0 =


Meanerror

22 143143 5252

11 333333 170170

44 3232 0606

33 6767 1717


615615 105ns105ns

12481248 168ns168ns

Mp ts

Example

160160 012ms012ms

113113 011ms011ms1


zz

( )1

222 353


zz


00101000b0 = k53

k5


00101001b0 = k853

k8

k5


222

333



00100000b0 = k3 e2 sdotminus111


1rsquos

23


UPM





D QEN

new_cycle Xek

b0

D QEN

new_cycle Xek-1

b1

+

D QEN

new_cycle Xdk-1

a1

D QEN

new_cycle Xdk-2

b2

+ D QENnew_cycle

dk

+


D Q

D Q

D Q

D Q

D Q

D Q






UPM

Fixed-point toolbox







MatlabSimulink



24


UPM

VHDL or VHDL-AMS











UPM


Applications333



323322

333333

25


UPM


IinVin

Vout

DCDCREGULATOR LO

AD

~

IoutIin


Vout

+_Vin

CONTROL

d

R1

R2

R3

R4

n1 n2LINE

LOAD

Main Switch

Vin

Iin Vout

PO=50Wf=50kHz


PO=50Wf=50kHz



UPM





Adaptive control


LOA

D

~

IoutIin

PFC CONVERTERVout

+_Vin

Controlblock

Controlblock

onoff

R1

R2

R3

R4

Vout

Iin

Vin

ADCADC

ADC

26


UPM


X


IIN-ref

Protections


VOUT max

IIN max

ldquodrdquo max

ldquoΔdrdquo max

ON-OFF Main Switch

ON-OFF Main Switch





intΣIin

gt

CalculatedOn-Off


Max






VOUT-ref

GinPI


UPM










VinGin

Multiplier

xVin

Gin(1Rin)

50 kHz



Adder

+Iin

ΣIin

Comparator

gtOnOff

20 MHz

NoPWMNoPWM


27


UPM




10 W 30 W 50 W 30 W 10 W

Vout

IinGin

StableStable

Load


Unstable

Unstable

Unstable

Unstable


UPM




Adaptive control

28


UPM



Load Change

Vout

Iin




T



UPM

Vin_dc

Iin_dc

d

Vout


OnOff

FPGAXilinx

XC4010-e

8 8 12

Vin Vout Iin

PROMXC 17512

ADC0808

ADC0808

HI 5805


ADCsADCs

Power Converter

Vout Vin_acIin_ac

PF = 099PF = 099PF = 099

29


UPM


DigitalController


switches)Digital


Measuredamp State


Analog

ADConverter

MeasuredVariables

(digital buses)

Mixed




UPM


M1

C Vout

D11n

+

_Vin

Iin

IL1

RL

IR

ON

L1OFF

M1

C Vout

D11n

+

_Vin

Iin

IL1

RL

IR

OFF

L1ON

Vout

n

ID1 = IL1 n

IC



1

kin1k1Lk1L

1L1in L

tVII

dtdILV

Δsdot+=rArr= minus

CtI

VVdt

dVCI kR1koutkout

outR


1

1kout1k1Lk1L

1L1

out

LntV

IIdt

dILnV

sdotΔsdot


minus

C

tIn

I

VVdt

dVCInI kR

1k1L

1koutkoutout

R1L

Δsdot⎟⎟⎠

⎞⎜⎜⎝

⎛minus

+=rArr=minus

minus

minus



30


UPM


VHDLVHDLVHDL

VHDL-AMS

VHDLVHDL--AMSAMS






UPM




VHDLVHDL








Simulationtime


CPU time using VHDL

models


modelsmodels



VHDL speed VHDL-AMS

speed


speedspeed

10 ms10 10 msms 69 s69 s69 s 446 s446 s446 s 641641641

100 ms100 100 msms 700 s700 s700 s 6912 s6912 s6912 s 987987987

1000 ms1000 1000 msms 6890 s6890 s6890 s 68443 s68443 s68443 s 993993993

VHDLVHDL--AMSAMS

31


UPM

42V 14V

CC

CC 42V 14V


system vehicles


Q1-1

Q2-1

Q16-1

Q16-2

Q2-2

Q1-2

L

L

L

COCIN




UPM


Q1-1

Q2-1

Q16-1

Q16-2

Q2-2

Q1-2

L

L

L

COCIN








3 prototypes


3 prototypes



32


UPM


VoVIN

L2d2

d1L1




VINd1

Battery

R1

R2

+

+ +

VINd2

1

BAT1IN1 R

VdVI minus=

2

22 R

VdVI BATIN -=


UPM







446

416

03360

03528

320

2336



1 5

CCM ndash 1000W

824

184

Not acceptable


Q1-1

Q2-1

Q16-1

Q16-2

Q2-2

Q1-2

L

L

L

33


UPM

AVGLI AVGLI


dT T

LVV OIN minus

LVOminus

AVGLI

dT T

LVV OIN minus

LVOminus

AVGLI

⎟⎟⎠

⎞⎜⎜⎝

⎛ minus=

O

OIN

i

2iIN

i VVV

fL2dVI



AVGLI AVGLI

DCMDCM


UPM


03360

03528






416

824



1 5

CCM ndash 1000W

0262002623

0275102649


1 5

DCM ndash 1000W

Not acceptable

445

490

446

454

110102

Very good


34


UPM



420 97

435 100

440 101

435 -

DC Current(A)

429 99

428 98

446 103

460 106

Deviation()

Phase 2

Phase 3

Phase 4

Phase 5

Phase 6

Phase 7

Phase 8

Average

CCM


IO=35A




UPM


ADCInterface

ampfilter

Regulator8

d1


Vout

ADCcontrol

Reset

Vin

12

MCDgenerator

12

Vout

12

Vin

Phase-shifter

8

d2

Protections

1616

Clock

16

H-Pulses L-Pulses




35


UPM




422 97

438 101

442 102

434 -

DC Current(A)

431 99

445 102

424 98

448 103

Deviation()

Phase 2Phase 2

Phase 3Phase 3

Phase 4Phase 4

Phase 5Phase 5

Phase 6Phase 6

Phase 7Phase 7

Phase 8Phase 8

AverageAverage

DCMDCM


IO=17A

IO=27A


UPM





36


UPM


-05

0

05

1

15

2

00E+00 50E-06 10E-05 15E-05 20E-05 25E-05t (s)

()

-05

0

05

1

15

2

00E+00 50E-06 10E-05 15E-05 20E-05 25E-05t (s)

()

0

20

40

60

80

100

120

140

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35

Phase number

[+6-8]

0

20

40

60

80

100

120

140

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35

Phase number

[+6-8]

Half load(500W)


Full load(1000W)

0

1

2

3

4

p

0 5μs 10μs 15μs 20μs0

1

2

3

4

p



0

20

40

60

80

100

120

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35

Phase number

+10-75

0

20

40

60

80

100

120

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35

Phase number

+10-75



UPM

Output currentDC AC

11App

70ADC


is

0 01 02 03 04 05 06 07 08 09 100102030405

060708091

Duty cycle (d)

Nor

m c

urre

nt r

ippl

e Dutyvariation

2 phases

3 phases



37


UPM

10

5

5

10

3T0 x

5

5

3T0 x

Ideal case






10

5

5

10

3T0 x

5

5

3T0 x

Non-ideal



10

5

5

10

3T0 x

5

5

3T0 x

Worse case



10

5

5

10

3T0 x

5

5

3T0 x





UPM

ΔIP-P= 40A (5Adiv)

1 phase

ΔIP-P= 12A (5Adiv)

2 phases

ΔIP-P= 5A (5Adiv)

4 phases

ΔIP-P= 22A (1Adiv)

8 phases

ΔIP-P= 16A (1Adiv)

16 phases



38


UPM

(a)

30

31

22 40

37

22 33

2830

31

22 40

37

22 33

28

(a)

Center of mass

(a)

30

31

22 40

37

22 33

2830

31

22 40

37

22 33

28

(a)

Center of mass

Phase1Phase

2

Phase3

Phase4

Phase5

Phase6

Phase7

Phase8

1st

2nd

3rd 4th

6th

5th 8th

7th

(b)

1st

2nd

3rd 4th

6th

5th 8th

7th

1st

2nd

3rd 4th

6th

5th 8th

7th

(b)

40 A

37 A30 A

33 A

22 A 28 A

31 A

22 A






UPM

18 0 18

18

18

OVERALL 67A

18 0 18

18

18

1

2

34

56

7

8

9

10

1112 13

14

15

16

MAX

MIN

18 0 18

18

18

OVERALL 05A

18 0 18

18

18

1

2

34

56

7

8

9

10

1112 13

1415

16

MAX

MIN


16151413121110987654321

Phase number

165155177152140144148128147122154158139149142133

Current ripple (A)

39


UPM

ΔIP-P= 40A

ΔIP-P= 40A

ΔIP-P= 07A

ΔIP-P= 16A

57

ΔIP-P= 11A

ΔIP-P= 22A

50

ΔIP-P= 28A

ΔIP-P= 5A

44

ΔIP-P= 11A

ΔIP-P= 12A

9






1 2 4 8 16



UPM


Tswitch

delay

Load

voutvin



COUNTERDUTY CYCLE

DRIVING SIGNAL

Load

voutvin



40


UPM



Dri

vin

gsi

gnal

s

Counter

+ hellip +


Duty cycle





UPM


Dri

vin

gD

rivi

ng

sign

als

sign

als



ltDuty cycle


Shift Register



Counter


41


UPM






ASIC

12 12 phasesphases

6 6 phasesphases

24 24 phasesphases





0

2000

4000

6000

8000

10000

12000

14000

16000

2 4 6 8 12 16 20 24

0

2000

4000

6000

8000

10000

12000

2 4 6 8 12 16 20 24

0

2000

4000

6000

8000

10000

12000

14000

16000

18000

2 4 6 8 12 16 20 24


Res

ol 1

28Res

ol 2

56Res

ol 5

12

FPGA

Equ

ival

ent

gate

s

Phases

0

200

400

600

800

1000

2 4 6 8 12 16 20 24


Res

ol 1

28Res

ol 2

56Res

ol 5

120

200

400

600

800

1000

1200

2 4 6 8 12 16 20 24

0

200

400

600

800

1000

1200

1400

2 4 6 8 12 16 20 24

ASIC

Equ

ival

ent

gate

s

Phases


UPM


0

10

20

30

40

50

0 20 40 60 80



0

10

20

30

40

50

0 20 40 60 80



Iout

Pow

erlo

sses

(W)

80

84

88

92

96

0 10 20 30 40 50 60 70 80

6 phases

8 phases12 phases

16 phases

4 phases



Iout

Effic

ienc

y(

)

80

84

88

92

96

0 10 20 30 40 50 60 70 80

6 phases

8 phases12 phases

16 phases

4 phases



Iout

Effic

ienc

y(

)



42


UPM





UPM


RFAmp

Pow

erSt

age

Control

iRF

vs

VS

variable VS


24V

9Vfmax=35kHz

Input voltage = 28V





43


UPM


Cs

M1

L

M2

Cs

M1

L

M2

Cs

M1

L

M2

Cs

M1

L

M2

Ve Vout

CAR

GA




UPM


SW

CLK

ff Resolution =

Pipeline

fCLK

f = 25MHz f = 45MHz

Resolution required



fselected = 32MHz


44


UPM

33 33 DitherDither

SW

CLK

ff Resolution gt

d = 42

d =43

d =425

T=2TSW=8μs

Output voltage

2 solutions

V=50mV

TSW=4μs 1 solution

T=4μs

Output voltage

V=25mV

SW

CLKNVirtual



Average duty cycle

It gives 1 more bit


UPM



SimulatedSimulated

MeasuredMeasured



)(

4110780250 22




45


UPM






UPM


f = 200Hz f = 15kHz

f = 3kHz f = 5kHz

46


UPM





UPM



2 2 micromicross

Vo

1 V

2 V

VRM for DVS5 V

Io = 20 A max

1V - 2 V

Io

02 V max02 V max

0 A

20 A

500 Amicros

Vo




47


UPM


10-1 100 101

100

L-C diagram

C2 micros

200 mV

20A




C = 35 C = 35 μμFF



UPM






fsw = 520 kHz

(125 mΩ eq Rds_on)





48


UPM


0

1

To drivers

New vref

vo dig

N-phases_tran

N-phases

New vref

vo dig

New vref

vo dig


ic


NON-LINEAR CONTROL





UPM


vref

vo

0

1

To drivers

clk_sample

clk_sample

ADC

N-phases_tran

N-phases

vo dig

LINEAR CONTROL



49


UPM


vref

vo

0

1

To drivers

New vref

vo dig

clk_sample

clk_sample

ADC

N-phases_tran

N-phases

vo dig

New vref

LINEAR CONTROL

NON-LINEAR CONTROL

vo dig

New vrefvo dig


ic



Beware


UPM


UpUp--stepstep

ConverterFPGA

tt11



DownDown--stepstep

t1 t2 t1 t2

ddnn

tt22vref

500 kHz

LUT


05

1

15

2

25

0 02 04 06 08 1 12 14 16 18-10

0

10

20

30

40

50

ton toff

Tmin

05

1

15

2

25

0 02 04 06 08 1 12 14 16 18-10

0

10

20

30

40

50

ton toff

Tmin

i L(A

)i L

(A)

V o(V

)V o

(V)


50


UPM


t1 t2 t1 t2

094 096 098 1 102 104 106 108 11

x 10-4

14

16

18

2

22

24

26

28

3

32

094 096 098 1 102 104 106 108 11

x 10-4

0

1

2

3

4

5092 094 096 098 1 102 104 106 108 11 112

x 10-4

14

16

18

2

22

24

26

28

3

32

092 094 096 098 1 102 104 106 108 11 112

x 10-4

0

05

1

15

2

25

3

35

4

45

Transient





Beware


UPM

ΔIo

iL

Io

vo

ic 0 ATrip point 1

Trip point 2

ΔIo

ic





51


UPM


05358z02236z07417)(z3767G(z) 2 +sdotminus

+sdot=

B G(s)

G(z)




N = 4

ESR = 125 mΩ

( )CL

1sRESRL1s

CL1)1sCESR(V

)s(Gdv

L2

ino

sdot+sdot+sdot+


==

~ VinmiddotdCo

ESR

RphaseN LphaseN

Expected by design


DC resistance


model


Beware


UPM


Pole-Zero Map

Real Axis

-1 -08 -06 -04 -02 0 02 04 06 08 1-1

-08

-06

-04

-02

0

02

04

06

08

1

09

0807060504

03

02

01

26e5

234e5

208e5

182e5

156e513e5

104e5

781e4

521e4

26e4

26e5

234e5

208e5

182e5

156e513e5

104e5

781e4

521e4

26e4

x

x

x




Duty cycle

30 micros


1z00372)z(Rminus

=

1zK)z(R 1

minus=

Controller delay

05358z02236z07417)(z3767G(z) 2 +sdotminus

+sdot=Converter

x

x

x Duty cycle

Output voltage

52


UPM

10 micros


xx

x

x

x

x

x

x




00775)(z1)(z037)(z00378R(z)

minussdotminus+sdot

=

Duty cycle

Output voltage


UPM


75 micros

xx

x

x

x

xx

x



minussdotminus+sdot

=

53


UPM


Duty

a1 = -0922548 b1 = 0037759b2 = 0051742a2 = 0

b1

b2

δ-1

δ-1

δ-1

a1

a2

Error

bn0

No b0

δ-1

Z-1

+

00775)(z1)(z037)(z00378R(z)

minussdotminus+sdot

=




UPM


z2d_m ( tf ([00378 0013986] [1 -10775 00775] 192e-6) )




=Tsample = Tsw

⎪⎩

⎪⎨⎧

rarrδ

+=δ δδ

s


54


UPM


Reference

Switched model

7 bits

8 bits

Not quantizied


PWM

ADC

111






UPM

Reference


PWM

ADC






hellip

222

55


UPM



a1 = -0922548 b1 = 0037759b2 = 0051742a2 = 0

b1

b2

δ-1

δ-1

δ-1

a1

a2

Error

bn0

No b0


UPM


0lt Duty cycle lt1


Hardware adders






Beware

56


UPM

0 1 2 30

05

1

15

2

25








UPM



0 1 2 3

x 10-4

0

05

1

15

2

25

100 usdiv100 usdiv



57


UPM






UPM




58


UPM


13 14 15 16 17 18 19

x 10-4

12

14

16

18

2

22

08 V drop

10 microsdiv

2 V





UPM



Vo

1 V

2 V



11 A11 A

20 mV

520 kHz



59


UPM


Vo

Io

200 mV







UPM


Vo

1 V

2 V





60


UPM





Beware



UPM



6


UPM



Power

converter





ADCBeware

Powerconv


+

-



UPM



V+

V_

+_

Voffset

R1

R1

R2

R2

ADCVout

Pow

erco

nver

ter

_+

7


UPM

C

R2




V+

V_

ADC

Vref

R1

R1

Vcm

_

++_

ADC

R2

C


UPM







V

t

ΔtV

t

ΔV

Beware

Powerconv


+

-


8


UPM


TSWITCH

TADC TPROCTDRIVER











UPM


High fADC butADC

latADC fNT 1

=

latencystages

stage perbitsstages

totalbit

NN

NN

N

=

= minusminus

latencyBeware

latency


9


UPM



25075

25050

25025

25000

24975

24950

24925

1 1 1

1 1 0

1 0 1

1 0 0

0 1 1

0 1 0

0 0 1



(25mV resolution)


voltage

⎟⎠⎞

⎜⎝⎛ = VV 00250

25210

Saturation



UPM





Best options

ADC-CLK

N

LATCHINSTANT


DATA N-3 N-2 N-1 N


10


UPM


Low pass filters


s11)s(Fτ+

=T

bT

bzbb

)s(F τ=

τ+=

minus=

minus 10110



Tb

zbbz)s(F τ

minus=τ

+=+

+=

minus

minus 21211101

10

1



TSWITCH

TADC TPROC

TDRIVER

TADC TADCTADC

Tfilter

Samp1

Samp2

Samp3

Samp4

1 noise-freesample


D QD Q




UPM

24 DPWM24 DPWM

Counter

refgt on_off





SWITCH

CLK


fCLK = 128 MHz

Beware

Powerconv


+

-


11


UPM




PWM63

PWM62

PWM61

Vref

error3

error2

error1

error0

error-1

error-2






of the controller)



UPM











CLKCLK2

Vout

VGS

dk


Beware

12


UPM







CLK

MUX


S QR

VGS

duty(1)duty(0)

end of sync duty


duty(n-12)

Example(L=2)

Bewareof thedelay



UPM




VGHVGL


Tswitch

delay

13


UPM



Beware




sum minusminus +=k



Driver examples





VSW

VGS

ton toff

Powerconv


+

-



UPM




zbb

zaa)z(R 110

110

++++

= minus

minus

ai bi constants









Powerconv


+

-


14


UPM

zoh

foh

matched

NA

tustin

Matlab C2D




First order hold

Polezero match



Two possibilities









UPM







Two mains reasons






15


UPM








UPM





)z(G)z(R1)z(G)z(R

)z(X)z(Y)z(M

+==

))z(M1)(z(G)z(M)z(R

minus=





Beware


+ Y(z)

_

E(z)X(z)R(z) G(z)

16


UPM





k

kk



=

⎪⎭

⎪⎬⎫

⎪⎩

⎪⎨⎧

minusminus=

minus=minusrArr

minusminus

=minusminus

minusminus


z1)z(M1)z(E

11

11








UPM


10

p1=e-σmiddotejθ


θ

γe-σ




=sR


minus= eMp



17


UPM


xx

xx

OO






96730middot29412239middot6229)(


2

7211

8

+minus+

=

+++

= minusminus

minus

zzzzG

ssssG


condition)



UPM




Vout

Duty

Near unstable



18


UPM



1z110)z(R 5

minus= minus

Vout

Duty







UPM




+= minus

Vout

Duty




19


UPM


Vout

Duty





23

+minusminus+minus




UPM


xk xk-1

hellip

xk-m

X

b0

X

b1

X

bm

hellip

+

+

hellip

+

yk yk-1

hellip

yk-n

X

a1

X

an

+

+

hellip

hellip

+

-yk

nn

22

110

mm

22

110

zazazaazbzbzbb

)z(e)z(d)z(R

minusminusminus

minusminusminus

sdot++sdot+sdot+





20


UPM

Z-1

a1

a2

Z-1


Z-1

bo

eK

Z-1

b1

b2

R1(z) R2(z)YK

dK

eK

R1 R2

Z-1

Z-1

a1

bo

b1

dKeK






UPM

Difference equation


a1a2

e(z)

⎩⎨⎧

rarrδ

+=δminus=δ= δδ+


TXXXmiddotY kkkk1k

kk

Tz1 1minusminus

=δ

k1

1k

1k Y

z1zTYXminus

minusminus

minus

sdot=δ=

δ-1 δ-1

aman

δ-1 δ-1

bm

+

bo

b1

u(z)h(z)

T Z-1

δ-1

(Integral)

+




More adders

21


UPM

a1

a2

δ-1

bo

b1T

b2T2 δ-1 T2

T


Tn Tn


Z-1

+



Adapted δ-1


UPM








ek-1 isrequested

ek-1 isavailable

dk isimposed

T

22


UPM

0 1 2 3 4 5 6 7 8

x 10 -4

-04

-02

0

02

04

06

08

1

12

14

16




vo

48 5 52 54 56 58

10-4

138

14

142

144

146

148

15

152

154

156

vo

Matlabfixed-point

toolbox






UPM



00011111b0 =


Meanerror

22 143143 5252

11 333333 170170

44 3232 0606

33 6767 1717


615615 105ns105ns

12481248 168ns168ns

Mp ts

Example

160160 012ms012ms

113113 011ms011ms1


zz

( )1

222 353


zz


00101000b0 = k53

k5


00101001b0 = k853

k8

k5


222

333



00100000b0 = k3 e2 sdotminus111


1rsquos

23


UPM





D QEN

new_cycle Xek

b0

D QEN

new_cycle Xek-1

b1

+

D QEN

new_cycle Xdk-1

a1

D QEN

new_cycle Xdk-2

b2

+ D QENnew_cycle

dk

+


D Q

D Q

D Q

D Q

D Q

D Q






UPM

Fixed-point toolbox







MatlabSimulink



24


UPM

VHDL or VHDL-AMS











UPM


Applications333



323322

333333

25


UPM


IinVin

Vout

DCDCREGULATOR LO

AD

~

IoutIin


Vout

+_Vin

CONTROL

d

R1

R2

R3

R4

n1 n2LINE

LOAD

Main Switch

Vin

Iin Vout

PO=50Wf=50kHz


PO=50Wf=50kHz



UPM





Adaptive control


LOA

D

~

IoutIin

PFC CONVERTERVout

+_Vin

Controlblock

Controlblock

onoff

R1

R2

R3

R4

Vout

Iin

Vin

ADCADC

ADC

26


UPM


X


IIN-ref

Protections


VOUT max

IIN max

ldquodrdquo max

ldquoΔdrdquo max

ON-OFF Main Switch

ON-OFF Main Switch





intΣIin

gt

CalculatedOn-Off


Max






VOUT-ref

GinPI


UPM










VinGin

Multiplier

xVin

Gin(1Rin)

50 kHz



Adder

+Iin

ΣIin

Comparator

gtOnOff

20 MHz

NoPWMNoPWM


27


UPM




10 W 30 W 50 W 30 W 10 W

Vout

IinGin

StableStable

Load


Unstable

Unstable

Unstable

Unstable


UPM




Adaptive control

28


UPM



Load Change

Vout

Iin




T



UPM

Vin_dc

Iin_dc

d

Vout


OnOff

FPGAXilinx

XC4010-e

8 8 12

Vin Vout Iin

PROMXC 17512

ADC0808

ADC0808

HI 5805


ADCsADCs

Power Converter

Vout Vin_acIin_ac

PF = 099PF = 099PF = 099

29


UPM


DigitalController


switches)Digital


Measuredamp State


Analog

ADConverter

MeasuredVariables

(digital buses)

Mixed




UPM


M1

C Vout

D11n

+

_Vin

Iin

IL1

RL

IR

ON

L1OFF

M1

C Vout

D11n

+

_Vin

Iin

IL1

RL

IR

OFF

L1ON

Vout

n

ID1 = IL1 n

IC



1

kin1k1Lk1L

1L1in L

tVII

dtdILV

Δsdot+=rArr= minus

CtI

VVdt

dVCI kR1koutkout

outR


1

1kout1k1Lk1L

1L1

out

LntV

IIdt

dILnV

sdotΔsdot


minus

C

tIn

I

VVdt

dVCInI kR

1k1L

1koutkoutout

R1L

Δsdot⎟⎟⎠

⎞⎜⎜⎝

⎛minus

+=rArr=minus

minus

minus



30


UPM


VHDLVHDLVHDL

VHDL-AMS

VHDLVHDL--AMSAMS






UPM




VHDLVHDL








Simulationtime


CPU time using VHDL

models


modelsmodels



VHDL speed VHDL-AMS

speed


speedspeed

10 ms10 10 msms 69 s69 s69 s 446 s446 s446 s 641641641

100 ms100 100 msms 700 s700 s700 s 6912 s6912 s6912 s 987987987

1000 ms1000 1000 msms 6890 s6890 s6890 s 68443 s68443 s68443 s 993993993

VHDLVHDL--AMSAMS

31


UPM

42V 14V

CC

CC 42V 14V


system vehicles


Q1-1

Q2-1

Q16-1

Q16-2

Q2-2

Q1-2

L

L

L

COCIN




UPM


Q1-1

Q2-1

Q16-1

Q16-2

Q2-2

Q1-2

L

L

L

COCIN








3 prototypes


3 prototypes



32


UPM


VoVIN

L2d2

d1L1




VINd1

Battery

R1

R2

+

+ +

VINd2

1

BAT1IN1 R

VdVI minus=

2

22 R

VdVI BATIN -=


UPM







446

416

03360

03528

320

2336



1 5

CCM ndash 1000W

824

184

Not acceptable


Q1-1

Q2-1

Q16-1

Q16-2

Q2-2

Q1-2

L

L

L

33


UPM

AVGLI AVGLI


dT T

LVV OIN minus

LVOminus

AVGLI

dT T

LVV OIN minus

LVOminus

AVGLI

⎟⎟⎠

⎞⎜⎜⎝

⎛ minus=

O

OIN

i

2iIN

i VVV

fL2dVI



AVGLI AVGLI

DCMDCM


UPM


03360

03528






416

824



1 5

CCM ndash 1000W

0262002623

0275102649


1 5

DCM ndash 1000W

Not acceptable

445

490

446

454

110102

Very good


34


UPM



420 97

435 100

440 101

435 -

DC Current(A)

429 99

428 98

446 103

460 106

Deviation()

Phase 2

Phase 3

Phase 4

Phase 5

Phase 6

Phase 7

Phase 8

Average

CCM


IO=35A




UPM


ADCInterface

ampfilter

Regulator8

d1


Vout

ADCcontrol

Reset

Vin

12

MCDgenerator

12

Vout

12

Vin

Phase-shifter

8

d2

Protections

1616

Clock

16

H-Pulses L-Pulses




35


UPM




422 97

438 101

442 102

434 -

DC Current(A)

431 99

445 102

424 98

448 103

Deviation()

Phase 2Phase 2

Phase 3Phase 3

Phase 4Phase 4

Phase 5Phase 5

Phase 6Phase 6

Phase 7Phase 7

Phase 8Phase 8

AverageAverage

DCMDCM


IO=17A

IO=27A


UPM





36


UPM


-05

0

05

1

15

2

00E+00 50E-06 10E-05 15E-05 20E-05 25E-05t (s)

()

-05

0

05

1

15

2

00E+00 50E-06 10E-05 15E-05 20E-05 25E-05t (s)

()

0

20

40

60

80

100

120

140

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35

Phase number

[+6-8]

0

20

40

60

80

100

120

140

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35

Phase number

[+6-8]

Half load(500W)


Full load(1000W)

0

1

2

3

4

p

0 5μs 10μs 15μs 20μs0

1

2

3

4

p



0

20

40

60

80

100

120

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35

Phase number

+10-75

0

20

40

60

80

100

120

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35

Phase number

+10-75



UPM

Output currentDC AC

11App

70ADC


is

0 01 02 03 04 05 06 07 08 09 100102030405

060708091

Duty cycle (d)

Nor

m c

urre

nt r

ippl

e Dutyvariation

2 phases

3 phases



37


UPM

10

5

5

10

3T0 x

5

5

3T0 x

Ideal case






10

5

5

10

3T0 x

5

5

3T0 x

Non-ideal



10

5

5

10

3T0 x

5

5

3T0 x

Worse case



10

5

5

10

3T0 x

5

5

3T0 x





UPM

ΔIP-P= 40A (5Adiv)

1 phase

ΔIP-P= 12A (5Adiv)

2 phases

ΔIP-P= 5A (5Adiv)

4 phases

ΔIP-P= 22A (1Adiv)

8 phases

ΔIP-P= 16A (1Adiv)

16 phases



38


UPM

(a)

30

31

22 40

37

22 33

2830

31

22 40

37

22 33

28

(a)

Center of mass

(a)

30

31

22 40

37

22 33

2830

31

22 40

37

22 33

28

(a)

Center of mass

Phase1Phase

2

Phase3

Phase4

Phase5

Phase6

Phase7

Phase8

1st

2nd

3rd 4th

6th

5th 8th

7th

(b)

1st

2nd

3rd 4th

6th

5th 8th

7th

1st

2nd

3rd 4th

6th

5th 8th

7th

(b)

40 A

37 A30 A

33 A

22 A 28 A

31 A

22 A






UPM

18 0 18

18

18

OVERALL 67A

18 0 18

18

18

1

2

34

56

7

8

9

10

1112 13

14

15

16

MAX

MIN

18 0 18

18

18

OVERALL 05A

18 0 18

18

18

1

2

34

56

7

8

9

10

1112 13

1415

16

MAX

MIN


16151413121110987654321

Phase number

165155177152140144148128147122154158139149142133

Current ripple (A)

39


UPM

ΔIP-P= 40A

ΔIP-P= 40A

ΔIP-P= 07A

ΔIP-P= 16A

57

ΔIP-P= 11A

ΔIP-P= 22A

50

ΔIP-P= 28A

ΔIP-P= 5A

44

ΔIP-P= 11A

ΔIP-P= 12A

9






1 2 4 8 16



UPM


Tswitch

delay

Load

voutvin



COUNTERDUTY CYCLE

DRIVING SIGNAL

Load

voutvin



40


UPM



Dri

vin

gsi

gnal

s

Counter

+ hellip +


Duty cycle





UPM


Dri

vin

gD

rivi

ng

sign

als

sign

als



ltDuty cycle


Shift Register



Counter


41


UPM






ASIC

12 12 phasesphases

6 6 phasesphases

24 24 phasesphases





0

2000

4000

6000

8000

10000

12000

14000

16000

2 4 6 8 12 16 20 24

0

2000

4000

6000

8000

10000

12000

2 4 6 8 12 16 20 24

0

2000

4000

6000

8000

10000

12000

14000

16000

18000

2 4 6 8 12 16 20 24


Res

ol 1

28Res

ol 2

56Res

ol 5

12

FPGA

Equ

ival

ent

gate

s

Phases

0

200

400

600

800

1000

2 4 6 8 12 16 20 24


Res

ol 1

28Res

ol 2

56Res

ol 5

120

200

400

600

800

1000

1200

2 4 6 8 12 16 20 24

0

200

400

600

800

1000

1200

1400

2 4 6 8 12 16 20 24

ASIC

Equ

ival

ent

gate

s

Phases


UPM


0

10

20

30

40

50

0 20 40 60 80



0

10

20

30

40

50

0 20 40 60 80



Iout

Pow

erlo

sses

(W)

80

84

88

92

96

0 10 20 30 40 50 60 70 80

6 phases

8 phases12 phases

16 phases

4 phases



Iout

Effic

ienc

y(

)

80

84

88

92

96

0 10 20 30 40 50 60 70 80

6 phases

8 phases12 phases

16 phases

4 phases



Iout

Effic

ienc

y(

)



42


UPM





UPM


RFAmp

Pow

erSt

age

Control

iRF

vs

VS

variable VS


24V

9Vfmax=35kHz

Input voltage = 28V





43


UPM


Cs

M1

L

M2

Cs

M1

L

M2

Cs

M1

L

M2

Cs

M1

L

M2

Ve Vout

CAR

GA




UPM


SW

CLK

ff Resolution =

Pipeline

fCLK

f = 25MHz f = 45MHz

Resolution required



fselected = 32MHz


44


UPM

33 33 DitherDither

SW

CLK

ff Resolution gt

d = 42

d =43

d =425

T=2TSW=8μs

Output voltage

2 solutions

V=50mV

TSW=4μs 1 solution

T=4μs

Output voltage

V=25mV

SW

CLKNVirtual



Average duty cycle

It gives 1 more bit


UPM



SimulatedSimulated

MeasuredMeasured



)(

4110780250 22




45


UPM






UPM


f = 200Hz f = 15kHz

f = 3kHz f = 5kHz

46


UPM





UPM



2 2 micromicross

Vo

1 V

2 V

VRM for DVS5 V

Io = 20 A max

1V - 2 V

Io

02 V max02 V max

0 A

20 A

500 Amicros

Vo




47


UPM


10-1 100 101

100

L-C diagram

C2 micros

200 mV

20A




C = 35 C = 35 μμFF



UPM






fsw = 520 kHz

(125 mΩ eq Rds_on)





48


UPM


0

1

To drivers

New vref

vo dig

N-phases_tran

N-phases

New vref

vo dig

New vref

vo dig


ic


NON-LINEAR CONTROL





UPM


vref

vo

0

1

To drivers

clk_sample

clk_sample

ADC

N-phases_tran

N-phases

vo dig

LINEAR CONTROL



49


UPM


vref

vo

0

1

To drivers

New vref

vo dig

clk_sample

clk_sample

ADC

N-phases_tran

N-phases

vo dig

New vref

LINEAR CONTROL

NON-LINEAR CONTROL

vo dig

New vrefvo dig


ic



Beware


UPM


UpUp--stepstep

ConverterFPGA

tt11



DownDown--stepstep

t1 t2 t1 t2

ddnn

tt22vref

500 kHz

LUT


05

1

15

2

25

0 02 04 06 08 1 12 14 16 18-10

0

10

20

30

40

50

ton toff

Tmin

05

1

15

2

25

0 02 04 06 08 1 12 14 16 18-10

0

10

20

30

40

50

ton toff

Tmin

i L(A

)i L

(A)

V o(V

)V o

(V)


50


UPM


t1 t2 t1 t2

094 096 098 1 102 104 106 108 11

x 10-4

14

16

18

2

22

24

26

28

3

32

094 096 098 1 102 104 106 108 11

x 10-4

0

1

2

3

4

5092 094 096 098 1 102 104 106 108 11 112

x 10-4

14

16

18

2

22

24

26

28

3

32

092 094 096 098 1 102 104 106 108 11 112

x 10-4

0

05

1

15

2

25

3

35

4

45

Transient





Beware


UPM

ΔIo

iL

Io

vo

ic 0 ATrip point 1

Trip point 2

ΔIo

ic





51


UPM


05358z02236z07417)(z3767G(z) 2 +sdotminus

+sdot=

B G(s)

G(z)




N = 4

ESR = 125 mΩ

( )CL

1sRESRL1s

CL1)1sCESR(V

)s(Gdv

L2

ino

sdot+sdot+sdot+


==

~ VinmiddotdCo

ESR

RphaseN LphaseN

Expected by design


DC resistance


model


Beware


UPM


Pole-Zero Map

Real Axis

-1 -08 -06 -04 -02 0 02 04 06 08 1-1

-08

-06

-04

-02

0

02

04

06

08

1

09

0807060504

03

02

01

26e5

234e5

208e5

182e5

156e513e5

104e5

781e4

521e4

26e4

26e5

234e5

208e5

182e5

156e513e5

104e5

781e4

521e4

26e4

x

x

x




Duty cycle

30 micros


1z00372)z(Rminus

=

1zK)z(R 1

minus=

Controller delay

05358z02236z07417)(z3767G(z) 2 +sdotminus

+sdot=Converter

x

x

x Duty cycle

Output voltage

52


UPM

10 micros


xx

x

x

x

x

x

x




00775)(z1)(z037)(z00378R(z)

minussdotminus+sdot

=

Duty cycle

Output voltage


UPM


75 micros

xx

x

x

x

xx

x



minussdotminus+sdot

=

53


UPM


Duty

a1 = -0922548 b1 = 0037759b2 = 0051742a2 = 0

b1

b2

δ-1

δ-1

δ-1

a1

a2

Error

bn0

No b0

δ-1

Z-1

+

00775)(z1)(z037)(z00378R(z)

minussdotminus+sdot

=




UPM


z2d_m ( tf ([00378 0013986] [1 -10775 00775] 192e-6) )




=Tsample = Tsw

⎪⎩

⎪⎨⎧

rarrδ

+=δ δδ

s


54


UPM


Reference

Switched model

7 bits

8 bits

Not quantizied


PWM

ADC

111






UPM

Reference


PWM

ADC






hellip

222

55


UPM



a1 = -0922548 b1 = 0037759b2 = 0051742a2 = 0

b1

b2

δ-1

δ-1

δ-1

a1

a2

Error

bn0

No b0


UPM


0lt Duty cycle lt1


Hardware adders






Beware

56


UPM

0 1 2 30

05

1

15

2

25








UPM



0 1 2 3

x 10-4

0

05

1

15

2

25

100 usdiv100 usdiv



57


UPM






UPM




58


UPM


13 14 15 16 17 18 19

x 10-4

12

14

16

18

2

22

08 V drop

10 microsdiv

2 V





UPM



Vo

1 V

2 V



11 A11 A

20 mV

520 kHz



59


UPM


Vo

Io

200 mV







UPM


Vo

1 V

2 V





60


UPM





Beware



UPM



7


UPM

C

R2




V+

V_

ADC

Vref

R1

R1

Vcm

_

++_

ADC

R2

C


UPM







V

t

ΔtV

t

ΔV

Beware

Powerconv


+

-


8


UPM


TSWITCH

TADC TPROCTDRIVER











UPM


High fADC butADC

latADC fNT 1

=

latencystages

stage perbitsstages

totalbit

NN

NN

N

=

= minusminus

latencyBeware

latency


9


UPM



25075

25050

25025

25000

24975

24950

24925

1 1 1

1 1 0

1 0 1

1 0 0

0 1 1

0 1 0

0 0 1



(25mV resolution)


voltage

⎟⎠⎞

⎜⎝⎛ = VV 00250

25210

Saturation



UPM





Best options

ADC-CLK

N

LATCHINSTANT


DATA N-3 N-2 N-1 N


10


UPM


Low pass filters


s11)s(Fτ+

=T

bT

bzbb

)s(F τ=

τ+=

minus=

minus 10110



Tb

zbbz)s(F τ

minus=τ

+=+

+=

minus

minus 21211101

10

1



TSWITCH

TADC TPROC

TDRIVER

TADC TADCTADC

Tfilter

Samp1

Samp2

Samp3

Samp4

1 noise-freesample


D QD Q




UPM

24 DPWM24 DPWM

Counter

refgt on_off





SWITCH

CLK


fCLK = 128 MHz

Beware

Powerconv


+

-


11


UPM




PWM63

PWM62

PWM61

Vref

error3

error2

error1

error0

error-1

error-2






of the controller)



UPM











CLKCLK2

Vout

VGS

dk


Beware

12


UPM







CLK

MUX


S QR

VGS

duty(1)duty(0)

end of sync duty


duty(n-12)

Example(L=2)

Bewareof thedelay



UPM




VGHVGL


Tswitch

delay

13


UPM



Beware




sum minusminus +=k



Driver examples





VSW

VGS

ton toff

Powerconv


+

-



UPM




zbb

zaa)z(R 110

110

++++

= minus

minus

ai bi constants









Powerconv


+

-


14


UPM

zoh

foh

matched

NA

tustin

Matlab C2D




First order hold

Polezero match



Two possibilities









UPM







Two mains reasons






15


UPM








UPM





)z(G)z(R1)z(G)z(R

)z(X)z(Y)z(M

+==

))z(M1)(z(G)z(M)z(R

minus=





Beware


+ Y(z)

_

E(z)X(z)R(z) G(z)

16


UPM





k

kk



=

⎪⎭

⎪⎬⎫

⎪⎩

⎪⎨⎧

minusminus=

minus=minusrArr

minusminus

=minusminus

minusminus


z1)z(M1)z(E

11

11








UPM


10

p1=e-σmiddotejθ


θ

γe-σ




=sR


minus= eMp



17


UPM


xx

xx

OO






96730middot29412239middot6229)(


2

7211

8

+minus+

=

+++

= minusminus

minus

zzzzG

ssssG


condition)



UPM




Vout

Duty

Near unstable



18


UPM



1z110)z(R 5

minus= minus

Vout

Duty







UPM




+= minus

Vout

Duty




19


UPM


Vout

Duty





23

+minusminus+minus




UPM


xk xk-1

hellip

xk-m

X

b0

X

b1

X

bm

hellip

+

+

hellip

+

yk yk-1

hellip

yk-n

X

a1

X

an

+

+

hellip

hellip

+

-yk

nn

22

110

mm

22

110

zazazaazbzbzbb

)z(e)z(d)z(R

minusminusminus

minusminusminus

sdot++sdot+sdot+





20


UPM

Z-1

a1

a2

Z-1


Z-1

bo

eK

Z-1

b1

b2

R1(z) R2(z)YK

dK

eK

R1 R2

Z-1

Z-1

a1

bo

b1

dKeK






UPM

Difference equation


a1a2

e(z)

⎩⎨⎧

rarrδ

+=δminus=δ= δδ+


TXXXmiddotY kkkk1k

kk

Tz1 1minusminus

=δ

k1

1k

1k Y

z1zTYXminus

minusminus

minus

sdot=δ=

δ-1 δ-1

aman

δ-1 δ-1

bm

+

bo

b1

u(z)h(z)

T Z-1

δ-1

(Integral)

+




More adders

21


UPM

a1

a2

δ-1

bo

b1T

b2T2 δ-1 T2

T


Tn Tn


Z-1

+



Adapted δ-1


UPM








ek-1 isrequested

ek-1 isavailable

dk isimposed

T

22


UPM

0 1 2 3 4 5 6 7 8

x 10 -4

-04

-02

0

02

04

06

08

1

12

14

16




vo

48 5 52 54 56 58

10-4

138

14

142

144

146

148

15

152

154

156

vo

Matlabfixed-point

toolbox






UPM



00011111b0 =


Meanerror

22 143143 5252

11 333333 170170

44 3232 0606

33 6767 1717


615615 105ns105ns

12481248 168ns168ns

Mp ts

Example

160160 012ms012ms

113113 011ms011ms1


zz

( )1

222 353


zz


00101000b0 = k53

k5


00101001b0 = k853

k8

k5


222

333



00100000b0 = k3 e2 sdotminus111


1rsquos

23


UPM





D QEN

new_cycle Xek

b0

D QEN

new_cycle Xek-1

b1

+

D QEN

new_cycle Xdk-1

a1

D QEN

new_cycle Xdk-2

b2

+ D QENnew_cycle

dk

+


D Q

D Q

D Q

D Q

D Q

D Q






UPM

Fixed-point toolbox







MatlabSimulink



24


UPM

VHDL or VHDL-AMS











UPM


Applications333



323322

333333

25


UPM


IinVin

Vout

DCDCREGULATOR LO

AD

~

IoutIin


Vout

+_Vin

CONTROL

d

R1

R2

R3

R4

n1 n2LINE

LOAD

Main Switch

Vin

Iin Vout

PO=50Wf=50kHz


PO=50Wf=50kHz



UPM





Adaptive control


LOA

D

~

IoutIin

PFC CONVERTERVout

+_Vin

Controlblock

Controlblock

onoff

R1

R2

R3

R4

Vout

Iin

Vin

ADCADC

ADC

26


UPM


X


IIN-ref

Protections


VOUT max

IIN max

ldquodrdquo max

ldquoΔdrdquo max

ON-OFF Main Switch

ON-OFF Main Switch





intΣIin

gt

CalculatedOn-Off


Max






VOUT-ref

GinPI


UPM










VinGin

Multiplier

xVin

Gin(1Rin)

50 kHz



Adder

+Iin

ΣIin

Comparator

gtOnOff

20 MHz

NoPWMNoPWM


27


UPM




10 W 30 W 50 W 30 W 10 W

Vout

IinGin

StableStable

Load


Unstable

Unstable

Unstable

Unstable


UPM




Adaptive control

28


UPM



Load Change

Vout

Iin




T



UPM

Vin_dc

Iin_dc

d

Vout


OnOff

FPGAXilinx

XC4010-e

8 8 12

Vin Vout Iin

PROMXC 17512

ADC0808

ADC0808

HI 5805


ADCsADCs

Power Converter

Vout Vin_acIin_ac

PF = 099PF = 099PF = 099

29


UPM


DigitalController


switches)Digital


Measuredamp State


Analog

ADConverter

MeasuredVariables

(digital buses)

Mixed




UPM


M1

C Vout

D11n

+

_Vin

Iin

IL1

RL

IR

ON

L1OFF

M1

C Vout

D11n

+

_Vin

Iin

IL1

RL

IR

OFF

L1ON

Vout

n

ID1 = IL1 n

IC



1

kin1k1Lk1L

1L1in L

tVII

dtdILV

Δsdot+=rArr= minus

CtI

VVdt

dVCI kR1koutkout

outR


1

1kout1k1Lk1L

1L1

out

LntV

IIdt

dILnV

sdotΔsdot


minus

C

tIn

I

VVdt

dVCInI kR

1k1L

1koutkoutout

R1L

Δsdot⎟⎟⎠

⎞⎜⎜⎝

⎛minus

+=rArr=minus

minus

minus



30


UPM


VHDLVHDLVHDL

VHDL-AMS

VHDLVHDL--AMSAMS






UPM




VHDLVHDL








Simulationtime


CPU time using VHDL

models


modelsmodels



VHDL speed VHDL-AMS

speed


speedspeed

10 ms10 10 msms 69 s69 s69 s 446 s446 s446 s 641641641

100 ms100 100 msms 700 s700 s700 s 6912 s6912 s6912 s 987987987

1000 ms1000 1000 msms 6890 s6890 s6890 s 68443 s68443 s68443 s 993993993

VHDLVHDL--AMSAMS

31


UPM

42V 14V

CC

CC 42V 14V


system vehicles


Q1-1

Q2-1

Q16-1

Q16-2

Q2-2

Q1-2

L

L

L

COCIN




UPM


Q1-1

Q2-1

Q16-1

Q16-2

Q2-2

Q1-2

L

L

L

COCIN








3 prototypes


3 prototypes



32


UPM


VoVIN

L2d2

d1L1




VINd1

Battery

R1

R2

+

+ +

VINd2

1

BAT1IN1 R

VdVI minus=

2

22 R

VdVI BATIN -=


UPM







446

416

03360

03528

320

2336



1 5

CCM ndash 1000W

824

184

Not acceptable


Q1-1

Q2-1

Q16-1

Q16-2

Q2-2

Q1-2

L

L

L

33


UPM

AVGLI AVGLI


dT T

LVV OIN minus

LVOminus

AVGLI

dT T

LVV OIN minus

LVOminus

AVGLI

⎟⎟⎠

⎞⎜⎜⎝

⎛ minus=

O

OIN

i

2iIN

i VVV

fL2dVI



AVGLI AVGLI

DCMDCM


UPM


03360

03528






416

824



1 5

CCM ndash 1000W

0262002623

0275102649


1 5

DCM ndash 1000W

Not acceptable

445

490

446

454

110102

Very good


34


UPM



420 97

435 100

440 101

435 -

DC Current(A)

429 99

428 98

446 103

460 106

Deviation()

Phase 2

Phase 3

Phase 4

Phase 5

Phase 6

Phase 7

Phase 8

Average

CCM


IO=35A




UPM


ADCInterface

ampfilter

Regulator8

d1


Vout

ADCcontrol

Reset

Vin

12

MCDgenerator

12

Vout

12

Vin

Phase-shifter

8

d2

Protections

1616

Clock

16

H-Pulses L-Pulses




35


UPM




422 97

438 101

442 102

434 -

DC Current(A)

431 99

445 102

424 98

448 103

Deviation()

Phase 2Phase 2

Phase 3Phase 3

Phase 4Phase 4

Phase 5Phase 5

Phase 6Phase 6

Phase 7Phase 7

Phase 8Phase 8

AverageAverage

DCMDCM


IO=17A

IO=27A


UPM





36


UPM


-05

0

05

1

15

2

00E+00 50E-06 10E-05 15E-05 20E-05 25E-05t (s)

()

-05

0

05

1

15

2

00E+00 50E-06 10E-05 15E-05 20E-05 25E-05t (s)

()

0

20

40

60

80

100

120

140

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35

Phase number

[+6-8]

0

20

40

60

80

100

120

140

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35

Phase number

[+6-8]

Half load(500W)


Full load(1000W)

0

1

2

3

4

p

0 5μs 10μs 15μs 20μs0

1

2

3

4

p



0

20

40

60

80

100

120

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35

Phase number

+10-75

0

20

40

60

80

100

120

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35

Phase number

+10-75



UPM

Output currentDC AC

11App

70ADC


is

0 01 02 03 04 05 06 07 08 09 100102030405

060708091

Duty cycle (d)

Nor

m c

urre

nt r

ippl

e Dutyvariation

2 phases

3 phases



37


UPM

10

5

5

10

3T0 x

5

5

3T0 x

Ideal case






10

5

5

10

3T0 x

5

5

3T0 x

Non-ideal



10

5

5

10

3T0 x

5

5

3T0 x

Worse case



10

5

5

10

3T0 x

5

5

3T0 x





UPM

ΔIP-P= 40A (5Adiv)

1 phase

ΔIP-P= 12A (5Adiv)

2 phases

ΔIP-P= 5A (5Adiv)

4 phases

ΔIP-P= 22A (1Adiv)

8 phases

ΔIP-P= 16A (1Adiv)

16 phases



38


UPM

(a)

30

31

22 40

37

22 33

2830

31

22 40

37

22 33

28

(a)

Center of mass

(a)

30

31

22 40

37

22 33

2830

31

22 40

37

22 33

28

(a)

Center of mass

Phase1Phase

2

Phase3

Phase4

Phase5

Phase6

Phase7

Phase8

1st

2nd

3rd 4th

6th

5th 8th

7th

(b)

1st

2nd

3rd 4th

6th

5th 8th

7th

1st

2nd

3rd 4th

6th

5th 8th

7th

(b)

40 A

37 A30 A

33 A

22 A 28 A

31 A

22 A






UPM

18 0 18

18

18

OVERALL 67A

18 0 18

18

18

1

2

34

56

7

8

9

10

1112 13

14

15

16

MAX

MIN

18 0 18

18

18

OVERALL 05A

18 0 18

18

18

1

2

34

56

7

8

9

10

1112 13

1415

16

MAX

MIN


16151413121110987654321

Phase number

165155177152140144148128147122154158139149142133

Current ripple (A)

39


UPM

ΔIP-P= 40A

ΔIP-P= 40A

ΔIP-P= 07A

ΔIP-P= 16A

57

ΔIP-P= 11A

ΔIP-P= 22A

50

ΔIP-P= 28A

ΔIP-P= 5A

44

ΔIP-P= 11A

ΔIP-P= 12A

9






1 2 4 8 16



UPM


Tswitch

delay

Load

voutvin



COUNTERDUTY CYCLE

DRIVING SIGNAL

Load

voutvin



40


UPM



Dri

vin

gsi

gnal

s

Counter

+ hellip +


Duty cycle





UPM


Dri

vin

gD

rivi

ng

sign

als

sign

als



ltDuty cycle


Shift Register



Counter


41


UPM






ASIC

12 12 phasesphases

6 6 phasesphases

24 24 phasesphases





0

2000

4000

6000

8000

10000

12000

14000

16000

2 4 6 8 12 16 20 24

0

2000

4000

6000

8000

10000

12000

2 4 6 8 12 16 20 24

0

2000

4000

6000

8000

10000

12000

14000

16000

18000

2 4 6 8 12 16 20 24


Res

ol 1

28Res

ol 2

56Res

ol 5

12

FPGA

Equ

ival

ent

gate

s

Phases

0

200

400

600

800

1000

2 4 6 8 12 16 20 24


Res

ol 1

28Res

ol 2

56Res

ol 5

120

200

400

600

800

1000

1200

2 4 6 8 12 16 20 24

0

200

400

600

800

1000

1200

1400

2 4 6 8 12 16 20 24

ASIC

Equ

ival

ent

gate

s

Phases


UPM


0

10

20

30

40

50

0 20 40 60 80



0

10

20

30

40

50

0 20 40 60 80



Iout

Pow

erlo

sses

(W)

80

84

88

92

96

0 10 20 30 40 50 60 70 80

6 phases

8 phases12 phases

16 phases

4 phases



Iout

Effic

ienc

y(

)

80

84

88

92

96

0 10 20 30 40 50 60 70 80

6 phases

8 phases12 phases

16 phases

4 phases



Iout

Effic

ienc

y(

)



42


UPM





UPM


RFAmp

Pow

erSt

age

Control

iRF

vs

VS

variable VS


24V

9Vfmax=35kHz

Input voltage = 28V





43


UPM


Cs

M1

L

M2

Cs

M1

L

M2

Cs

M1

L

M2

Cs

M1

L

M2

Ve Vout

CAR

GA




UPM


SW

CLK

ff Resolution =

Pipeline

fCLK

f = 25MHz f = 45MHz

Resolution required



fselected = 32MHz


44


UPM

33 33 DitherDither

SW

CLK

ff Resolution gt

d = 42

d =43

d =425

T=2TSW=8μs

Output voltage

2 solutions

V=50mV

TSW=4μs 1 solution

T=4μs

Output voltage

V=25mV

SW

CLKNVirtual



Average duty cycle

It gives 1 more bit


UPM



SimulatedSimulated

MeasuredMeasured



)(

4110780250 22




45


UPM






UPM


f = 200Hz f = 15kHz

f = 3kHz f = 5kHz

46


UPM





UPM



2 2 micromicross

Vo

1 V

2 V

VRM for DVS5 V

Io = 20 A max

1V - 2 V

Io

02 V max02 V max

0 A

20 A

500 Amicros

Vo




47


UPM


10-1 100 101

100

L-C diagram

C2 micros

200 mV

20A




C = 35 C = 35 μμFF



UPM






fsw = 520 kHz

(125 mΩ eq Rds_on)





48


UPM


0

1

To drivers

New vref

vo dig

N-phases_tran

N-phases

New vref

vo dig

New vref

vo dig


ic


NON-LINEAR CONTROL





UPM


vref

vo

0

1

To drivers

clk_sample

clk_sample

ADC

N-phases_tran

N-phases

vo dig

LINEAR CONTROL



49


UPM


vref

vo

0

1

To drivers

New vref

vo dig

clk_sample

clk_sample

ADC

N-phases_tran

N-phases

vo dig

New vref

LINEAR CONTROL

NON-LINEAR CONTROL

vo dig

New vrefvo dig


ic



Beware


UPM


UpUp--stepstep

ConverterFPGA

tt11



DownDown--stepstep

t1 t2 t1 t2

ddnn

tt22vref

500 kHz

LUT


05

1

15

2

25

0 02 04 06 08 1 12 14 16 18-10

0

10

20

30

40

50

ton toff

Tmin

05

1

15

2

25

0 02 04 06 08 1 12 14 16 18-10

0

10

20

30

40

50

ton toff

Tmin

i L(A

)i L

(A)

V o(V

)V o

(V)


50


UPM


t1 t2 t1 t2

094 096 098 1 102 104 106 108 11

x 10-4

14

16

18

2

22

24

26

28

3

32

094 096 098 1 102 104 106 108 11

x 10-4

0

1

2

3

4

5092 094 096 098 1 102 104 106 108 11 112

x 10-4

14

16

18

2

22

24

26

28

3

32

092 094 096 098 1 102 104 106 108 11 112

x 10-4

0

05

1

15

2

25

3

35

4

45

Transient





Beware


UPM

ΔIo

iL

Io

vo

ic 0 ATrip point 1

Trip point 2

ΔIo

ic





51


UPM


05358z02236z07417)(z3767G(z) 2 +sdotminus

+sdot=

B G(s)

G(z)




N = 4

ESR = 125 mΩ

( )CL

1sRESRL1s

CL1)1sCESR(V

)s(Gdv

L2

ino

sdot+sdot+sdot+


==

~ VinmiddotdCo

ESR

RphaseN LphaseN

Expected by design


DC resistance


model


Beware


UPM


Pole-Zero Map

Real Axis

-1 -08 -06 -04 -02 0 02 04 06 08 1-1

-08

-06

-04

-02

0

02

04

06

08

1

09

0807060504

03

02

01

26e5

234e5

208e5

182e5

156e513e5

104e5

781e4

521e4

26e4

26e5

234e5

208e5

182e5

156e513e5

104e5

781e4

521e4

26e4

x

x

x




Duty cycle

30 micros


1z00372)z(Rminus

=

1zK)z(R 1

minus=

Controller delay

05358z02236z07417)(z3767G(z) 2 +sdotminus

+sdot=Converter

x

x

x Duty cycle

Output voltage

52


UPM

10 micros


xx

x

x

x

x

x

x




00775)(z1)(z037)(z00378R(z)

minussdotminus+sdot

=

Duty cycle

Output voltage


UPM


75 micros

xx

x

x

x

xx

x



minussdotminus+sdot

=

53


UPM


Duty

a1 = -0922548 b1 = 0037759b2 = 0051742a2 = 0

b1

b2

δ-1

δ-1

δ-1

a1

a2

Error

bn0

No b0

δ-1

Z-1

+

00775)(z1)(z037)(z00378R(z)

minussdotminus+sdot

=




UPM


z2d_m ( tf ([00378 0013986] [1 -10775 00775] 192e-6) )




=Tsample = Tsw

⎪⎩

⎪⎨⎧

rarrδ

+=δ δδ

s


54


UPM


Reference

Switched model

7 bits

8 bits

Not quantizied


PWM

ADC

111






UPM

Reference


PWM

ADC






hellip

222

55


UPM



a1 = -0922548 b1 = 0037759b2 = 0051742a2 = 0

b1

b2

δ-1

δ-1

δ-1

a1

a2

Error

bn0

No b0


UPM


0lt Duty cycle lt1


Hardware adders






Beware

56


UPM

0 1 2 30

05

1

15

2

25








UPM



0 1 2 3

x 10-4

0

05

1

15

2

25

100 usdiv100 usdiv



57


UPM






UPM




58


UPM


13 14 15 16 17 18 19

x 10-4

12

14

16

18

2

22

08 V drop

10 microsdiv

2 V





UPM



Vo

1 V

2 V



11 A11 A

20 mV

520 kHz



59


UPM


Vo

Io

200 mV







UPM


Vo

1 V

2 V





60


UPM





Beware



UPM



8


UPM


TSWITCH

TADC TPROCTDRIVER











UPM


High fADC butADC

latADC fNT 1

=

latencystages

stage perbitsstages

totalbit

NN

NN

N

=

= minusminus

latencyBeware

latency


9


UPM



25075

25050

25025

25000

24975

24950

24925

1 1 1

1 1 0

1 0 1

1 0 0

0 1 1

0 1 0

0 0 1



(25mV resolution)


voltage

⎟⎠⎞

⎜⎝⎛ = VV 00250

25210

Saturation



UPM





Best options

ADC-CLK

N

LATCHINSTANT


DATA N-3 N-2 N-1 N


10


UPM


Low pass filters


s11)s(Fτ+

=T

bT

bzbb

)s(F τ=

τ+=

minus=

minus 10110



Tb

zbbz)s(F τ

minus=τ

+=+

+=

minus

minus 21211101

10

1



TSWITCH

TADC TPROC

TDRIVER

TADC TADCTADC

Tfilter

Samp1

Samp2

Samp3

Samp4

1 noise-freesample


D QD Q




UPM

24 DPWM24 DPWM

Counter

refgt on_off





SWITCH

CLK


fCLK = 128 MHz

Beware

Powerconv


+

-


11


UPM




PWM63

PWM62

PWM61

Vref

error3

error2

error1

error0

error-1

error-2






of the controller)



UPM











CLKCLK2

Vout

VGS

dk


Beware

12


UPM







CLK

MUX


S QR

VGS

duty(1)duty(0)

end of sync duty


duty(n-12)

Example(L=2)

Bewareof thedelay



UPM




VGHVGL


Tswitch

delay

13


UPM



Beware




sum minusminus +=k



Driver examples





VSW

VGS

ton toff

Powerconv


+

-



UPM




zbb

zaa)z(R 110

110

++++

= minus

minus

ai bi constants









Powerconv


+

-


14


UPM

zoh

foh

matched

NA

tustin

Matlab C2D




First order hold

Polezero match



Two possibilities









UPM







Two mains reasons






15


UPM








UPM





)z(G)z(R1)z(G)z(R

)z(X)z(Y)z(M

+==

))z(M1)(z(G)z(M)z(R

minus=





Beware


+ Y(z)

_

E(z)X(z)R(z) G(z)

16


UPM





k

kk



=

⎪⎭

⎪⎬⎫

⎪⎩

⎪⎨⎧

minusminus=

minus=minusrArr

minusminus

=minusminus

minusminus


z1)z(M1)z(E

11

11








UPM


10

p1=e-σmiddotejθ


θ

γe-σ




=sR


minus= eMp



17


UPM


xx

xx

OO






96730middot29412239middot6229)(


2

7211

8

+minus+

=

+++

= minusminus

minus

zzzzG

ssssG


condition)



UPM




Vout

Duty

Near unstable



18


UPM



1z110)z(R 5

minus= minus

Vout

Duty







UPM




+= minus

Vout

Duty




19


UPM


Vout

Duty





23

+minusminus+minus




UPM


xk xk-1

hellip

xk-m

X

b0

X

b1

X

bm

hellip

+

+

hellip

+

yk yk-1

hellip

yk-n

X

a1

X

an

+

+

hellip

hellip

+

-yk

nn

22

110

mm

22

110

zazazaazbzbzbb

)z(e)z(d)z(R

minusminusminus

minusminusminus

sdot++sdot+sdot+





20


UPM

Z-1

a1

a2

Z-1


Z-1

bo

eK

Z-1

b1

b2

R1(z) R2(z)YK

dK

eK

R1 R2

Z-1

Z-1

a1

bo

b1

dKeK






UPM

Difference equation


a1a2

e(z)

⎩⎨⎧

rarrδ

+=δminus=δ= δδ+


TXXXmiddotY kkkk1k

kk

Tz1 1minusminus

=δ

k1

1k

1k Y

z1zTYXminus

minusminus

minus

sdot=δ=

δ-1 δ-1

aman

δ-1 δ-1

bm

+

bo

b1

u(z)h(z)

T Z-1

δ-1

(Integral)

+




More adders

21


UPM

a1

a2

δ-1

bo

b1T

b2T2 δ-1 T2

T


Tn Tn


Z-1

+



Adapted δ-1


UPM








ek-1 isrequested

ek-1 isavailable

dk isimposed

T

22


UPM

0 1 2 3 4 5 6 7 8

x 10 -4

-04

-02

0

02

04

06

08

1

12

14

16




vo

48 5 52 54 56 58

10-4

138

14

142

144

146

148

15

152

154

156

vo

Matlabfixed-point

toolbox






UPM



00011111b0 =


Meanerror

22 143143 5252

11 333333 170170

44 3232 0606

33 6767 1717


615615 105ns105ns

12481248 168ns168ns

Mp ts

Example

160160 012ms012ms

113113 011ms011ms1


zz

( )1

222 353


zz


00101000b0 = k53

k5


00101001b0 = k853

k8

k5


222

333



00100000b0 = k3 e2 sdotminus111


1rsquos

23


UPM





D QEN

new_cycle Xek

b0

D QEN

new_cycle Xek-1

b1

+

D QEN

new_cycle Xdk-1

a1

D QEN

new_cycle Xdk-2

b2

+ D QENnew_cycle

dk

+


D Q

D Q

D Q

D Q

D Q

D Q






UPM

Fixed-point toolbox







MatlabSimulink



24


UPM

VHDL or VHDL-AMS











UPM


Applications333



323322

333333

25


UPM


IinVin

Vout

DCDCREGULATOR LO

AD

~

IoutIin


Vout

+_Vin

CONTROL

d

R1

R2

R3

R4

n1 n2LINE

LOAD

Main Switch

Vin

Iin Vout

PO=50Wf=50kHz


PO=50Wf=50kHz



UPM





Adaptive control


LOA

D

~

IoutIin

PFC CONVERTERVout

+_Vin

Controlblock

Controlblock

onoff

R1

R2

R3

R4

Vout

Iin

Vin

ADCADC

ADC

26


UPM


X


IIN-ref

Protections


VOUT max

IIN max

ldquodrdquo max

ldquoΔdrdquo max

ON-OFF Main Switch

ON-OFF Main Switch





intΣIin

gt

CalculatedOn-Off


Max






VOUT-ref

GinPI


UPM










VinGin

Multiplier

xVin

Gin(1Rin)

50 kHz



Adder

+Iin

ΣIin

Comparator

gtOnOff

20 MHz

NoPWMNoPWM


27


UPM




10 W 30 W 50 W 30 W 10 W

Vout

IinGin

StableStable

Load


Unstable

Unstable

Unstable

Unstable


UPM




Adaptive control

28


UPM



Load Change

Vout

Iin




T



UPM

Vin_dc

Iin_dc

d

Vout


OnOff

FPGAXilinx

XC4010-e

8 8 12

Vin Vout Iin

PROMXC 17512

ADC0808

ADC0808

HI 5805


ADCsADCs

Power Converter

Vout Vin_acIin_ac

PF = 099PF = 099PF = 099

29


UPM


DigitalController


switches)Digital


Measuredamp State


Analog

ADConverter

MeasuredVariables

(digital buses)

Mixed




UPM


M1

C Vout

D11n

+

_Vin

Iin

IL1

RL

IR

ON

L1OFF

M1

C Vout

D11n

+

_Vin

Iin

IL1

RL

IR

OFF

L1ON

Vout

n

ID1 = IL1 n

IC



1

kin1k1Lk1L

1L1in L

tVII

dtdILV

Δsdot+=rArr= minus

CtI

VVdt

dVCI kR1koutkout

outR


1

1kout1k1Lk1L

1L1

out

LntV

IIdt

dILnV

sdotΔsdot


minus

C

tIn

I

VVdt

dVCInI kR

1k1L

1koutkoutout

R1L

Δsdot⎟⎟⎠

⎞⎜⎜⎝

⎛minus

+=rArr=minus

minus

minus



30


UPM


VHDLVHDLVHDL

VHDL-AMS

VHDLVHDL--AMSAMS






UPM




VHDLVHDL








Simulationtime


CPU time using VHDL

models


modelsmodels



VHDL speed VHDL-AMS

speed


speedspeed

10 ms10 10 msms 69 s69 s69 s 446 s446 s446 s 641641641

100 ms100 100 msms 700 s700 s700 s 6912 s6912 s6912 s 987987987

1000 ms1000 1000 msms 6890 s6890 s6890 s 68443 s68443 s68443 s 993993993

VHDLVHDL--AMSAMS

31


UPM

42V 14V

CC

CC 42V 14V


system vehicles


Q1-1

Q2-1

Q16-1

Q16-2

Q2-2

Q1-2

L

L

L

COCIN




UPM


Q1-1

Q2-1

Q16-1

Q16-2

Q2-2

Q1-2

L

L

L

COCIN








3 prototypes


3 prototypes



32


UPM


VoVIN

L2d2

d1L1




VINd1

Battery

R1

R2

+

+ +

VINd2

1

BAT1IN1 R

VdVI minus=

2

22 R

VdVI BATIN -=


UPM







446

416

03360

03528

320

2336



1 5

CCM ndash 1000W

824

184

Not acceptable


Q1-1

Q2-1

Q16-1

Q16-2

Q2-2

Q1-2

L

L

L

33


UPM

AVGLI AVGLI


dT T

LVV OIN minus

LVOminus

AVGLI

dT T

LVV OIN minus

LVOminus

AVGLI

⎟⎟⎠

⎞⎜⎜⎝

⎛ minus=

O

OIN

i

2iIN

i VVV

fL2dVI



AVGLI AVGLI

DCMDCM


UPM


03360

03528






416

824



1 5

CCM ndash 1000W

0262002623

0275102649


1 5

DCM ndash 1000W

Not acceptable

445

490

446

454

110102

Very good


34


UPM



420 97

435 100

440 101

435 -

DC Current(A)

429 99

428 98

446 103

460 106

Deviation()

Phase 2

Phase 3

Phase 4

Phase 5

Phase 6

Phase 7

Phase 8

Average

CCM


IO=35A




UPM


ADCInterface

ampfilter

Regulator8

d1


Vout

ADCcontrol

Reset

Vin

12

MCDgenerator

12

Vout

12

Vin

Phase-shifter

8

d2

Protections

1616

Clock

16

H-Pulses L-Pulses




35


UPM




422 97

438 101

442 102

434 -

DC Current(A)

431 99

445 102

424 98

448 103

Deviation()

Phase 2Phase 2

Phase 3Phase 3

Phase 4Phase 4

Phase 5Phase 5

Phase 6Phase 6

Phase 7Phase 7

Phase 8Phase 8

AverageAverage

DCMDCM


IO=17A

IO=27A


UPM





36


UPM


-05

0

05

1

15

2

00E+00 50E-06 10E-05 15E-05 20E-05 25E-05t (s)

()

-05

0

05

1

15

2

00E+00 50E-06 10E-05 15E-05 20E-05 25E-05t (s)

()

0

20

40

60

80

100

120

140

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35

Phase number

[+6-8]

0

20

40

60

80

100

120

140

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35

Phase number

[+6-8]

Half load(500W)


Full load(1000W)

0

1

2

3

4

p

0 5μs 10μs 15μs 20μs0

1

2

3

4

p



0

20

40

60

80

100

120

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35

Phase number

+10-75

0

20

40

60

80

100

120

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35

Phase number

+10-75



UPM

Output currentDC AC

11App

70ADC


is

0 01 02 03 04 05 06 07 08 09 100102030405

060708091

Duty cycle (d)

Nor

m c

urre

nt r

ippl

e Dutyvariation

2 phases

3 phases



37


UPM

10

5

5

10

3T0 x

5

5

3T0 x

Ideal case






10

5

5

10

3T0 x

5

5

3T0 x

Non-ideal



10

5

5

10

3T0 x

5

5

3T0 x

Worse case



10

5

5

10

3T0 x

5

5

3T0 x





UPM

ΔIP-P= 40A (5Adiv)

1 phase

ΔIP-P= 12A (5Adiv)

2 phases

ΔIP-P= 5A (5Adiv)

4 phases

ΔIP-P= 22A (1Adiv)

8 phases

ΔIP-P= 16A (1Adiv)

16 phases



38


UPM

(a)

30

31

22 40

37

22 33

2830

31

22 40

37

22 33

28

(a)

Center of mass

(a)

30

31

22 40

37

22 33

2830

31

22 40

37

22 33

28

(a)

Center of mass

Phase1Phase

2

Phase3

Phase4

Phase5

Phase6

Phase7

Phase8

1st

2nd

3rd 4th

6th

5th 8th

7th

(b)

1st

2nd

3rd 4th

6th

5th 8th

7th

1st

2nd

3rd 4th

6th

5th 8th

7th

(b)

40 A

37 A30 A

33 A

22 A 28 A

31 A

22 A






UPM

18 0 18

18

18

OVERALL 67A

18 0 18

18

18

1

2

34

56

7

8

9

10

1112 13

14

15

16

MAX

MIN

18 0 18

18

18

OVERALL 05A

18 0 18

18

18

1

2

34

56

7

8

9

10

1112 13

1415

16

MAX

MIN


16151413121110987654321

Phase number

165155177152140144148128147122154158139149142133

Current ripple (A)

39


UPM

ΔIP-P= 40A

ΔIP-P= 40A

ΔIP-P= 07A

ΔIP-P= 16A

57

ΔIP-P= 11A

ΔIP-P= 22A

50

ΔIP-P= 28A

ΔIP-P= 5A

44

ΔIP-P= 11A

ΔIP-P= 12A

9






1 2 4 8 16



UPM


Tswitch

delay

Load

voutvin



COUNTERDUTY CYCLE

DRIVING SIGNAL

Load

voutvin



40


UPM



Dri

vin

gsi

gnal

s

Counter

+ hellip +


Duty cycle





UPM


Dri

vin

gD

rivi

ng

sign

als

sign

als



ltDuty cycle


Shift Register



Counter


41


UPM






ASIC

12 12 phasesphases

6 6 phasesphases

24 24 phasesphases





0

2000

4000

6000

8000

10000

12000

14000

16000

2 4 6 8 12 16 20 24

0

2000

4000

6000

8000

10000

12000

2 4 6 8 12 16 20 24

0

2000

4000

6000

8000

10000

12000

14000

16000

18000

2 4 6 8 12 16 20 24


Res

ol 1

28Res

ol 2

56Res

ol 5

12

FPGA

Equ

ival

ent

gate

s

Phases

0

200

400

600

800

1000

2 4 6 8 12 16 20 24


Res

ol 1

28Res

ol 2

56Res

ol 5

120

200

400

600

800

1000

1200

2 4 6 8 12 16 20 24

0

200

400

600

800

1000

1200

1400

2 4 6 8 12 16 20 24

ASIC

Equ

ival

ent

gate

s

Phases


UPM


0

10

20

30

40

50

0 20 40 60 80



0

10

20

30

40

50

0 20 40 60 80



Iout

Pow

erlo

sses

(W)

80

84

88

92

96

0 10 20 30 40 50 60 70 80

6 phases

8 phases12 phases

16 phases

4 phases



Iout

Effic

ienc

y(

)

80

84

88

92

96

0 10 20 30 40 50 60 70 80

6 phases

8 phases12 phases

16 phases

4 phases



Iout

Effic

ienc

y(

)



42


UPM





UPM


RFAmp

Pow

erSt

age

Control

iRF

vs

VS

variable VS


24V

9Vfmax=35kHz

Input voltage = 28V





43


UPM


Cs

M1

L

M2

Cs

M1

L

M2

Cs

M1

L

M2

Cs

M1

L

M2

Ve Vout

CAR

GA




UPM


SW

CLK

ff Resolution =

Pipeline

fCLK

f = 25MHz f = 45MHz

Resolution required



fselected = 32MHz


44


UPM

33 33 DitherDither

SW

CLK

ff Resolution gt

d = 42

d =43

d =425

T=2TSW=8μs

Output voltage

2 solutions

V=50mV

TSW=4μs 1 solution

T=4μs

Output voltage

V=25mV

SW

CLKNVirtual



Average duty cycle

It gives 1 more bit


UPM



SimulatedSimulated

MeasuredMeasured



)(

4110780250 22




45


UPM






UPM


f = 200Hz f = 15kHz

f = 3kHz f = 5kHz

46


UPM





UPM



2 2 micromicross

Vo

1 V

2 V

VRM for DVS5 V

Io = 20 A max

1V - 2 V

Io

02 V max02 V max

0 A

20 A

500 Amicros

Vo




47


UPM


10-1 100 101

100

L-C diagram

C2 micros

200 mV

20A




C = 35 C = 35 μμFF



UPM






fsw = 520 kHz

(125 mΩ eq Rds_on)





48


UPM


0

1

To drivers

New vref

vo dig

N-phases_tran

N-phases

New vref

vo dig

New vref

vo dig


ic


NON-LINEAR CONTROL





UPM


vref

vo

0

1

To drivers

clk_sample

clk_sample

ADC

N-phases_tran

N-phases

vo dig

LINEAR CONTROL



49


UPM


vref

vo

0

1

To drivers

New vref

vo dig

clk_sample

clk_sample

ADC

N-phases_tran

N-phases

vo dig

New vref

LINEAR CONTROL

NON-LINEAR CONTROL

vo dig

New vrefvo dig


ic



Beware


UPM


UpUp--stepstep

ConverterFPGA

tt11



DownDown--stepstep

t1 t2 t1 t2

ddnn

tt22vref

500 kHz

LUT


05

1

15

2

25

0 02 04 06 08 1 12 14 16 18-10

0

10

20

30

40

50

ton toff

Tmin

05

1

15

2

25

0 02 04 06 08 1 12 14 16 18-10

0

10

20

30

40

50

ton toff

Tmin

i L(A

)i L

(A)

V o(V

)V o

(V)


50


UPM


t1 t2 t1 t2

094 096 098 1 102 104 106 108 11

x 10-4

14

16

18

2

22

24

26

28

3

32

094 096 098 1 102 104 106 108 11

x 10-4

0

1

2

3

4

5092 094 096 098 1 102 104 106 108 11 112

x 10-4

14

16

18

2

22

24

26

28

3

32

092 094 096 098 1 102 104 106 108 11 112

x 10-4

0

05

1

15

2

25

3

35

4

45

Transient





Beware


UPM

ΔIo

iL

Io

vo

ic 0 ATrip point 1

Trip point 2

ΔIo

ic





51


UPM


05358z02236z07417)(z3767G(z) 2 +sdotminus

+sdot=

B G(s)

G(z)




N = 4

ESR = 125 mΩ

( )CL

1sRESRL1s

CL1)1sCESR(V

)s(Gdv

L2

ino

sdot+sdot+sdot+


==

~ VinmiddotdCo

ESR

RphaseN LphaseN

Expected by design


DC resistance


model


Beware


UPM


Pole-Zero Map

Real Axis

-1 -08 -06 -04 -02 0 02 04 06 08 1-1

-08

-06

-04

-02

0

02

04

06

08

1

09

0807060504

03

02

01

26e5

234e5

208e5

182e5

156e513e5

104e5

781e4

521e4

26e4

26e5

234e5

208e5

182e5

156e513e5

104e5

781e4

521e4

26e4

x

x

x




Duty cycle

30 micros


1z00372)z(Rminus

=

1zK)z(R 1

minus=

Controller delay

05358z02236z07417)(z3767G(z) 2 +sdotminus

+sdot=Converter

x

x

x Duty cycle

Output voltage

52


UPM

10 micros


xx

x

x

x

x

x

x




00775)(z1)(z037)(z00378R(z)

minussdotminus+sdot

=

Duty cycle

Output voltage


UPM


75 micros

xx

x

x

x

xx

x



minussdotminus+sdot

=

53


UPM


Duty

a1 = -0922548 b1 = 0037759b2 = 0051742a2 = 0

b1

b2

δ-1

δ-1

δ-1

a1

a2

Error

bn0

No b0

δ-1

Z-1

+

00775)(z1)(z037)(z00378R(z)

minussdotminus+sdot

=




UPM


z2d_m ( tf ([00378 0013986] [1 -10775 00775] 192e-6) )




=Tsample = Tsw

⎪⎩

⎪⎨⎧

rarrδ

+=δ δδ

s


54


UPM


Reference

Switched model

7 bits

8 bits

Not quantizied


PWM

ADC

111






UPM

Reference


PWM

ADC






hellip

222

55


UPM



a1 = -0922548 b1 = 0037759b2 = 0051742a2 = 0

b1

b2

δ-1

δ-1

δ-1

a1

a2

Error

bn0

No b0


UPM


0lt Duty cycle lt1


Hardware adders






Beware

56


UPM

0 1 2 30

05

1

15

2

25








UPM



0 1 2 3

x 10-4

0

05

1

15

2

25

100 usdiv100 usdiv



57


UPM






UPM




58


UPM


13 14 15 16 17 18 19

x 10-4

12

14

16

18

2

22

08 V drop

10 microsdiv

2 V





UPM



Vo

1 V

2 V



11 A11 A

20 mV

520 kHz



59


UPM


Vo

Io

200 mV







UPM


Vo

1 V

2 V





60


UPM





Beware



UPM



9


UPM



25075

25050

25025

25000

24975

24950

24925

1 1 1

1 1 0

1 0 1

1 0 0

0 1 1

0 1 0

0 0 1



(25mV resolution)


voltage

⎟⎠⎞

⎜⎝⎛ = VV 00250

25210

Saturation



UPM





Best options

ADC-CLK

N

LATCHINSTANT


DATA N-3 N-2 N-1 N


10


UPM


Low pass filters


s11)s(Fτ+

=T

bT

bzbb

)s(F τ=

τ+=

minus=

minus 10110



Tb

zbbz)s(F τ

minus=τ

+=+

+=

minus

minus 21211101

10

1



TSWITCH

TADC TPROC

TDRIVER

TADC TADCTADC

Tfilter

Samp1

Samp2

Samp3

Samp4

1 noise-freesample


D QD Q




UPM

24 DPWM24 DPWM

Counter

refgt on_off





SWITCH

CLK


fCLK = 128 MHz

Beware

Powerconv


+

-


11


UPM




PWM63

PWM62

PWM61

Vref

error3

error2

error1

error0

error-1

error-2






of the controller)



UPM











CLKCLK2

Vout

VGS

dk


Beware

12


UPM







CLK

MUX


S QR

VGS

duty(1)duty(0)

end of sync duty


duty(n-12)

Example(L=2)

Bewareof thedelay



UPM




VGHVGL


Tswitch

delay

13


UPM



Beware




sum minusminus +=k



Driver examples





VSW

VGS

ton toff

Powerconv


+

-



UPM




zbb

zaa)z(R 110

110

++++

= minus

minus

ai bi constants









Powerconv


+

-


14


UPM

zoh

foh

matched

NA

tustin

Matlab C2D




First order hold

Polezero match



Two possibilities









UPM







Two mains reasons






15


UPM








UPM





)z(G)z(R1)z(G)z(R

)z(X)z(Y)z(M

+==

))z(M1)(z(G)z(M)z(R

minus=





Beware


+ Y(z)

_

E(z)X(z)R(z) G(z)

16


UPM





k

kk



=

⎪⎭

⎪⎬⎫

⎪⎩

⎪⎨⎧

minusminus=

minus=minusrArr

minusminus

=minusminus

minusminus


z1)z(M1)z(E

11

11








UPM


10

p1=e-σmiddotejθ


θ

γe-σ




=sR


minus= eMp



17


UPM


xx

xx

OO






96730middot29412239middot6229)(


2

7211

8

+minus+

=

+++

= minusminus

minus

zzzzG

ssssG


condition)



UPM




Vout

Duty

Near unstable



18


UPM



1z110)z(R 5

minus= minus

Vout

Duty







UPM




+= minus

Vout

Duty




19


UPM


Vout

Duty





23

+minusminus+minus




UPM


xk xk-1

hellip

xk-m

X

b0

X

b1

X

bm

hellip

+

+

hellip

+

yk yk-1

hellip

yk-n

X

a1

X

an

+

+

hellip

hellip

+

-yk

nn

22

110

mm

22

110

zazazaazbzbzbb

)z(e)z(d)z(R

minusminusminus

minusminusminus

sdot++sdot+sdot+





20


UPM

Z-1

a1

a2

Z-1


Z-1

bo

eK

Z-1

b1

b2

R1(z) R2(z)YK

dK

eK

R1 R2

Z-1

Z-1

a1

bo

b1

dKeK






UPM

Difference equation


a1a2

e(z)

⎩⎨⎧

rarrδ

+=δminus=δ= δδ+


TXXXmiddotY kkkk1k

kk

Tz1 1minusminus

=δ

k1

1k

1k Y

z1zTYXminus

minusminus

minus

sdot=δ=

δ-1 δ-1

aman

δ-1 δ-1

bm

+

bo

b1

u(z)h(z)

T Z-1

δ-1

(Integral)

+




More adders

21


UPM

a1

a2

δ-1

bo

b1T

b2T2 δ-1 T2

T


Tn Tn


Z-1

+



Adapted δ-1


UPM








ek-1 isrequested

ek-1 isavailable

dk isimposed

T

22


UPM

0 1 2 3 4 5 6 7 8

x 10 -4

-04

-02

0

02

04

06

08

1

12

14

16




vo

48 5 52 54 56 58

10-4

138

14

142

144

146

148

15

152

154

156

vo

Matlabfixed-point

toolbox






UPM



00011111b0 =


Meanerror

22 143143 5252

11 333333 170170

44 3232 0606

33 6767 1717


615615 105ns105ns

12481248 168ns168ns

Mp ts

Example

160160 012ms012ms

113113 011ms011ms1


zz

( )1

222 353


zz


00101000b0 = k53

k5


00101001b0 = k853

k8

k5


222

333



00100000b0 = k3 e2 sdotminus111


1rsquos

23


UPM





D QEN

new_cycle Xek

b0

D QEN

new_cycle Xek-1

b1

+

D QEN

new_cycle Xdk-1

a1

D QEN

new_cycle Xdk-2

b2

+ D QENnew_cycle

dk

+


D Q

D Q

D Q

D Q

D Q

D Q






UPM

Fixed-point toolbox







MatlabSimulink



24


UPM

VHDL or VHDL-AMS











UPM


Applications333



323322

333333

25


UPM


IinVin

Vout

DCDCREGULATOR LO

AD

~

IoutIin


Vout

+_Vin

CONTROL

d

R1

R2

R3

R4

n1 n2LINE

LOAD

Main Switch

Vin

Iin Vout

PO=50Wf=50kHz


PO=50Wf=50kHz



UPM





Adaptive control


LOA

D

~

IoutIin

PFC CONVERTERVout

+_Vin

Controlblock

Controlblock

onoff

R1

R2

R3

R4

Vout

Iin

Vin

ADCADC

ADC

26


UPM


X


IIN-ref

Protections


VOUT max

IIN max

ldquodrdquo max

ldquoΔdrdquo max

ON-OFF Main Switch

ON-OFF Main Switch





intΣIin

gt

CalculatedOn-Off


Max






VOUT-ref

GinPI


UPM










VinGin

Multiplier

xVin

Gin(1Rin)

50 kHz



Adder

+Iin

ΣIin

Comparator

gtOnOff

20 MHz

NoPWMNoPWM


27


UPM




10 W 30 W 50 W 30 W 10 W

Vout

IinGin

StableStable

Load


Unstable

Unstable

Unstable

Unstable


UPM




Adaptive control

28


UPM



Load Change

Vout

Iin




T



UPM

Vin_dc

Iin_dc

d

Vout


OnOff

FPGAXilinx

XC4010-e

8 8 12

Vin Vout Iin

PROMXC 17512

ADC0808

ADC0808

HI 5805


ADCsADCs

Power Converter

Vout Vin_acIin_ac

PF = 099PF = 099PF = 099

29


UPM


DigitalController


switches)Digital


Measuredamp State


Analog

ADConverter

MeasuredVariables

(digital buses)

Mixed




UPM


M1

C Vout

D11n

+

_Vin

Iin

IL1

RL

IR

ON

L1OFF

M1

C Vout

D11n

+

_Vin

Iin

IL1

RL

IR

OFF

L1ON

Vout

n

ID1 = IL1 n

IC



1

kin1k1Lk1L

1L1in L

tVII

dtdILV

Δsdot+=rArr= minus

CtI

VVdt

dVCI kR1koutkout

outR


1

1kout1k1Lk1L

1L1

out

LntV

IIdt

dILnV

sdotΔsdot


minus

C

tIn

I

VVdt

dVCInI kR

1k1L

1koutkoutout

R1L

Δsdot⎟⎟⎠

⎞⎜⎜⎝

⎛minus

+=rArr=minus

minus

minus



30


UPM


VHDLVHDLVHDL

VHDL-AMS

VHDLVHDL--AMSAMS






UPM




VHDLVHDL








Simulationtime


CPU time using VHDL

models


modelsmodels



VHDL speed VHDL-AMS

speed


speedspeed

10 ms10 10 msms 69 s69 s69 s 446 s446 s446 s 641641641

100 ms100 100 msms 700 s700 s700 s 6912 s6912 s6912 s 987987987

1000 ms1000 1000 msms 6890 s6890 s6890 s 68443 s68443 s68443 s 993993993

VHDLVHDL--AMSAMS

31


UPM

42V 14V

CC

CC 42V 14V


system vehicles


Q1-1

Q2-1

Q16-1

Q16-2

Q2-2

Q1-2

L

L

L

COCIN




UPM


Q1-1

Q2-1

Q16-1

Q16-2

Q2-2

Q1-2

L

L

L

COCIN








3 prototypes


3 prototypes



32


UPM


VoVIN

L2d2

d1L1




VINd1

Battery

R1

R2

+

+ +

VINd2

1

BAT1IN1 R

VdVI minus=

2

22 R

VdVI BATIN -=


UPM







446

416

03360

03528

320

2336



1 5

CCM ndash 1000W

824

184

Not acceptable


Q1-1

Q2-1

Q16-1

Q16-2

Q2-2

Q1-2

L

L

L

33


UPM

AVGLI AVGLI


dT T

LVV OIN minus

LVOminus

AVGLI

dT T

LVV OIN minus

LVOminus

AVGLI

⎟⎟⎠

⎞⎜⎜⎝

⎛ minus=

O

OIN

i

2iIN

i VVV

fL2dVI



AVGLI AVGLI

DCMDCM


UPM


03360

03528






416

824



1 5

CCM ndash 1000W

0262002623

0275102649


1 5

DCM ndash 1000W

Not acceptable

445

490

446

454

110102

Very good


34


UPM



420 97

435 100

440 101

435 -

DC Current(A)

429 99

428 98

446 103

460 106

Deviation()

Phase 2

Phase 3

Phase 4

Phase 5

Phase 6

Phase 7

Phase 8

Average

CCM


IO=35A




UPM


ADCInterface

ampfilter

Regulator8

d1


Vout

ADCcontrol

Reset

Vin

12

MCDgenerator

12

Vout

12

Vin

Phase-shifter

8

d2

Protections

1616

Clock

16

H-Pulses L-Pulses




35


UPM




422 97

438 101

442 102

434 -

DC Current(A)

431 99

445 102

424 98

448 103

Deviation()

Phase 2Phase 2

Phase 3Phase 3

Phase 4Phase 4

Phase 5Phase 5

Phase 6Phase 6

Phase 7Phase 7

Phase 8Phase 8

AverageAverage

DCMDCM


IO=17A

IO=27A


UPM





36


UPM


-05

0

05

1

15

2

00E+00 50E-06 10E-05 15E-05 20E-05 25E-05t (s)

()

-05

0

05

1

15

2

00E+00 50E-06 10E-05 15E-05 20E-05 25E-05t (s)

()

0

20

40

60

80

100

120

140

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35

Phase number

[+6-8]

0

20

40

60

80

100

120

140

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35

Phase number

[+6-8]

Half load(500W)


Full load(1000W)

0

1

2

3

4

p

0 5μs 10μs 15μs 20μs0

1

2

3

4

p



0

20

40

60

80

100

120

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35

Phase number

+10-75

0

20

40

60

80

100

120

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35

Phase number

+10-75



UPM

Output currentDC AC

11App

70ADC


is

0 01 02 03 04 05 06 07 08 09 100102030405

060708091

Duty cycle (d)

Nor

m c

urre

nt r

ippl

e Dutyvariation

2 phases

3 phases



37


UPM

10

5

5

10

3T0 x

5

5

3T0 x

Ideal case






10

5

5

10

3T0 x

5

5

3T0 x

Non-ideal



10

5

5

10

3T0 x

5

5

3T0 x

Worse case



10

5

5

10

3T0 x

5

5

3T0 x





UPM

ΔIP-P= 40A (5Adiv)

1 phase

ΔIP-P= 12A (5Adiv)

2 phases

ΔIP-P= 5A (5Adiv)

4 phases

ΔIP-P= 22A (1Adiv)

8 phases

ΔIP-P= 16A (1Adiv)

16 phases



38


UPM

(a)

30

31

22 40

37

22 33

2830

31

22 40

37

22 33

28

(a)

Center of mass

(a)

30

31

22 40

37

22 33

2830

31

22 40

37

22 33

28

(a)

Center of mass

Phase1Phase

2

Phase3

Phase4

Phase5

Phase6

Phase7

Phase8

1st

2nd

3rd 4th

6th

5th 8th

7th

(b)

1st

2nd

3rd 4th

6th

5th 8th

7th

1st

2nd

3rd 4th

6th

5th 8th

7th

(b)

40 A

37 A30 A

33 A

22 A 28 A

31 A

22 A






UPM

18 0 18

18

18

OVERALL 67A

18 0 18

18

18

1

2

34

56

7

8

9

10

1112 13

14

15

16

MAX

MIN

18 0 18

18

18

OVERALL 05A

18 0 18

18

18

1

2

34

56

7

8

9

10

1112 13

1415

16

MAX

MIN


16151413121110987654321

Phase number

165155177152140144148128147122154158139149142133

Current ripple (A)

39


UPM

ΔIP-P= 40A

ΔIP-P= 40A

ΔIP-P= 07A

ΔIP-P= 16A

57

ΔIP-P= 11A

ΔIP-P= 22A

50

ΔIP-P= 28A

ΔIP-P= 5A

44

ΔIP-P= 11A

ΔIP-P= 12A

9






1 2 4 8 16



UPM


Tswitch

delay

Load

voutvin



COUNTERDUTY CYCLE

DRIVING SIGNAL

Load

voutvin



40


UPM



Dri

vin

gsi

gnal

s

Counter

+ hellip +


Duty cycle





UPM


Dri

vin

gD

rivi

ng

sign

als

sign

als



ltDuty cycle


Shift Register



Counter


41


UPM






ASIC

12 12 phasesphases

6 6 phasesphases

24 24 phasesphases





0

2000

4000

6000

8000

10000

12000

14000

16000

2 4 6 8 12 16 20 24

0

2000

4000

6000

8000

10000

12000

2 4 6 8 12 16 20 24

0

2000

4000

6000

8000

10000

12000

14000

16000

18000

2 4 6 8 12 16 20 24


Res

ol 1

28Res

ol 2

56Res

ol 5

12

FPGA

Equ

ival

ent

gate

s

Phases

0

200

400

600

800

1000

2 4 6 8 12 16 20 24


Res

ol 1

28Res

ol 2

56Res

ol 5

120

200

400

600

800

1000

1200

2 4 6 8 12 16 20 24

0

200

400

600

800

1000

1200

1400

2 4 6 8 12 16 20 24

ASIC

Equ

ival

ent

gate

s

Phases


UPM


0

10

20

30

40

50

0 20 40 60 80



0

10

20

30

40

50

0 20 40 60 80



Iout

Pow

erlo

sses

(W)

80

84

88

92

96

0 10 20 30 40 50 60 70 80

6 phases

8 phases12 phases

16 phases

4 phases



Iout

Effic

ienc

y(

)

80

84

88

92

96

0 10 20 30 40 50 60 70 80

6 phases

8 phases12 phases

16 phases

4 phases



Iout

Effic

ienc

y(

)



42


UPM





UPM


RFAmp

Pow

erSt

age

Control

iRF

vs

VS

variable VS


24V

9Vfmax=35kHz

Input voltage = 28V





43


UPM


Cs

M1

L

M2

Cs

M1

L

M2

Cs

M1

L

M2

Cs

M1

L

M2

Ve Vout

CAR

GA




UPM


SW

CLK

ff Resolution =

Pipeline

fCLK

f = 25MHz f = 45MHz

Resolution required



fselected = 32MHz


44


UPM

33 33 DitherDither

SW

CLK

ff Resolution gt

d = 42

d =43

d =425

T=2TSW=8μs

Output voltage

2 solutions

V=50mV

TSW=4μs 1 solution

T=4μs

Output voltage

V=25mV

SW

CLKNVirtual



Average duty cycle

It gives 1 more bit


UPM



SimulatedSimulated

MeasuredMeasured



)(

4110780250 22




45


UPM






UPM


f = 200Hz f = 15kHz

f = 3kHz f = 5kHz

46


UPM





UPM



2 2 micromicross

Vo

1 V

2 V

VRM for DVS5 V

Io = 20 A max

1V - 2 V

Io

02 V max02 V max

0 A

20 A

500 Amicros

Vo




47


UPM


10-1 100 101

100

L-C diagram

C2 micros

200 mV

20A




C = 35 C = 35 μμFF



UPM






fsw = 520 kHz

(125 mΩ eq Rds_on)





48


UPM


0

1

To drivers

New vref

vo dig

N-phases_tran

N-phases

New vref

vo dig

New vref

vo dig


ic


NON-LINEAR CONTROL





UPM


vref

vo

0

1

To drivers

clk_sample

clk_sample

ADC

N-phases_tran

N-phases

vo dig

LINEAR CONTROL



49


UPM


vref

vo

0

1

To drivers

New vref

vo dig

clk_sample

clk_sample

ADC

N-phases_tran

N-phases

vo dig

New vref

LINEAR CONTROL

NON-LINEAR CONTROL

vo dig

New vrefvo dig


ic



Beware


UPM


UpUp--stepstep

ConverterFPGA

tt11



DownDown--stepstep

t1 t2 t1 t2

ddnn

tt22vref

500 kHz

LUT


05

1

15

2

25

0 02 04 06 08 1 12 14 16 18-10

0

10

20

30

40

50

ton toff

Tmin

05

1

15

2

25

0 02 04 06 08 1 12 14 16 18-10

0

10

20

30

40

50

ton toff

Tmin

i L(A

)i L

(A)

V o(V

)V o

(V)


50


UPM


t1 t2 t1 t2

094 096 098 1 102 104 106 108 11

x 10-4

14

16

18

2

22

24

26

28

3

32

094 096 098 1 102 104 106 108 11

x 10-4

0

1

2

3

4

5092 094 096 098 1 102 104 106 108 11 112

x 10-4

14

16

18

2

22

24

26

28

3

32

092 094 096 098 1 102 104 106 108 11 112

x 10-4

0

05

1

15

2

25

3

35

4

45

Transient





Beware


UPM

ΔIo

iL

Io

vo

ic 0 ATrip point 1

Trip point 2

ΔIo

ic





51


UPM


05358z02236z07417)(z3767G(z) 2 +sdotminus

+sdot=

B G(s)

G(z)




N = 4

ESR = 125 mΩ

( )CL

1sRESRL1s

CL1)1sCESR(V

)s(Gdv

L2

ino

sdot+sdot+sdot+


==

~ VinmiddotdCo

ESR

RphaseN LphaseN

Expected by design


DC resistance


model


Beware


UPM


Pole-Zero Map

Real Axis

-1 -08 -06 -04 -02 0 02 04 06 08 1-1

-08

-06

-04

-02

0

02

04

06

08

1

09

0807060504

03

02

01

26e5

234e5

208e5

182e5

156e513e5

104e5

781e4

521e4

26e4

26e5

234e5

208e5

182e5

156e513e5

104e5

781e4

521e4

26e4

x

x

x




Duty cycle

30 micros


1z00372)z(Rminus

=

1zK)z(R 1

minus=

Controller delay

05358z02236z07417)(z3767G(z) 2 +sdotminus

+sdot=Converter

x

x

x Duty cycle

Output voltage

52


UPM

10 micros


xx

x

x

x

x

x

x




00775)(z1)(z037)(z00378R(z)

minussdotminus+sdot

=

Duty cycle

Output voltage


UPM


75 micros

xx

x

x

x

xx

x



minussdotminus+sdot

=

53


UPM


Duty

a1 = -0922548 b1 = 0037759b2 = 0051742a2 = 0

b1

b2

δ-1

δ-1

δ-1

a1

a2

Error

bn0

No b0

δ-1

Z-1

+

00775)(z1)(z037)(z00378R(z)

minussdotminus+sdot

=




UPM


z2d_m ( tf ([00378 0013986] [1 -10775 00775] 192e-6) )




=Tsample = Tsw

⎪⎩

⎪⎨⎧

rarrδ

+=δ δδ

s


54


UPM


Reference

Switched model

7 bits

8 bits

Not quantizied


PWM

ADC

111






UPM

Reference


PWM

ADC






hellip

222

55


UPM



a1 = -0922548 b1 = 0037759b2 = 0051742a2 = 0

b1

b2

δ-1

δ-1

δ-1

a1

a2

Error

bn0

No b0


UPM


0lt Duty cycle lt1


Hardware adders






Beware

56


UPM

0 1 2 30

05

1

15

2

25








UPM



0 1 2 3

x 10-4

0

05

1

15

2

25

100 usdiv100 usdiv



57


UPM






UPM




58


UPM


13 14 15 16 17 18 19

x 10-4

12

14

16

18

2

22

08 V drop

10 microsdiv

2 V





UPM



Vo

1 V

2 V



11 A11 A

20 mV

520 kHz



59


UPM


Vo

Io

200 mV







UPM


Vo

1 V

2 V





60


UPM





Beware



UPM



10


UPM


Low pass filters


s11)s(Fτ+

=T

bT

bzbb

)s(F τ=

τ+=

minus=

minus 10110



Tb

zbbz)s(F τ

minus=τ

+=+

+=

minus

minus 21211101

10

1



TSWITCH

TADC TPROC

TDRIVER

TADC TADCTADC

Tfilter

Samp1

Samp2

Samp3

Samp4

1 noise-freesample


D QD Q




UPM

24 DPWM24 DPWM

Counter

refgt on_off





SWITCH

CLK


fCLK = 128 MHz

Beware

Powerconv


+

-


11


UPM




PWM63

PWM62

PWM61

Vref

error3

error2

error1

error0

error-1

error-2






of the controller)



UPM











CLKCLK2

Vout

VGS

dk


Beware

12


UPM







CLK

MUX


S QR

VGS

duty(1)duty(0)

end of sync duty


duty(n-12)

Example(L=2)

Bewareof thedelay



UPM




VGHVGL


Tswitch

delay

13


UPM



Beware




sum minusminus +=k



Driver examples





VSW

VGS

ton toff

Powerconv


+

-



UPM




zbb

zaa)z(R 110

110

++++

= minus

minus

ai bi constants









Powerconv


+

-


14


UPM

zoh

foh

matched

NA

tustin

Matlab C2D




First order hold

Polezero match



Two possibilities









UPM







Two mains reasons






15


UPM








UPM





)z(G)z(R1)z(G)z(R

)z(X)z(Y)z(M

+==

))z(M1)(z(G)z(M)z(R

minus=





Beware


+ Y(z)

_

E(z)X(z)R(z) G(z)

16


UPM





k

kk



=

⎪⎭

⎪⎬⎫

⎪⎩

⎪⎨⎧

minusminus=

minus=minusrArr

minusminus

=minusminus

minusminus


z1)z(M1)z(E

11

11








UPM


10

p1=e-σmiddotejθ


θ

γe-σ




=sR


minus= eMp



17


UPM


xx

xx

OO






96730middot29412239middot6229)(


2

7211

8

+minus+

=

+++

= minusminus

minus

zzzzG

ssssG


condition)



UPM




Vout

Duty

Near unstable



18


UPM



1z110)z(R 5

minus= minus

Vout

Duty







UPM




+= minus

Vout

Duty




19


UPM


Vout

Duty





23

+minusminus+minus




UPM


xk xk-1

hellip

xk-m

X

b0

X

b1

X

bm

hellip

+

+

hellip

+

yk yk-1

hellip

yk-n

X

a1

X

an

+

+

hellip

hellip

+

-yk

nn

22

110

mm

22

110

zazazaazbzbzbb

)z(e)z(d)z(R

minusminusminus

minusminusminus

sdot++sdot+sdot+





20


UPM

Z-1

a1

a2

Z-1


Z-1

bo

eK

Z-1

b1

b2

R1(z) R2(z)YK

dK

eK

R1 R2

Z-1

Z-1

a1

bo

b1

dKeK






UPM

Difference equation


a1a2

e(z)

⎩⎨⎧

rarrδ

+=δminus=δ= δδ+


TXXXmiddotY kkkk1k

kk

Tz1 1minusminus

=δ

k1

1k

1k Y

z1zTYXminus

minusminus

minus

sdot=δ=

δ-1 δ-1

aman

δ-1 δ-1

bm

+

bo

b1

u(z)h(z)

T Z-1

δ-1

(Integral)

+




More adders

21


UPM

a1

a2

δ-1

bo

b1T

b2T2 δ-1 T2

T


Tn Tn


Z-1

+



Adapted δ-1


UPM








ek-1 isrequested

ek-1 isavailable

dk isimposed

T

22


UPM

0 1 2 3 4 5 6 7 8

x 10 -4

-04

-02

0

02

04

06

08

1

12

14

16




vo

48 5 52 54 56 58

10-4

138

14

142

144

146

148

15

152

154

156

vo

Matlabfixed-point

toolbox






UPM



00011111b0 =


Meanerror

22 143143 5252

11 333333 170170

44 3232 0606

33 6767 1717


615615 105ns105ns

12481248 168ns168ns

Mp ts

Example

160160 012ms012ms

113113 011ms011ms1


zz

( )1

222 353


zz


00101000b0 = k53

k5


00101001b0 = k853

k8

k5


222

333



00100000b0 = k3 e2 sdotminus111


1rsquos

23


UPM





D QEN

new_cycle Xek

b0

D QEN

new_cycle Xek-1

b1

+

D QEN

new_cycle Xdk-1

a1

D QEN

new_cycle Xdk-2

b2

+ D QENnew_cycle

dk

+


D Q

D Q

D Q

D Q

D Q

D Q






UPM

Fixed-point toolbox







MatlabSimulink



24


UPM

VHDL or VHDL-AMS











UPM


Applications333



323322

333333

25


UPM


IinVin

Vout

DCDCREGULATOR LO

AD

~

IoutIin


Vout

+_Vin

CONTROL

d

R1

R2

R3

R4

n1 n2LINE

LOAD

Main Switch

Vin

Iin Vout

PO=50Wf=50kHz


PO=50Wf=50kHz



UPM





Adaptive control


LOA

D

~

IoutIin

PFC CONVERTERVout

+_Vin

Controlblock

Controlblock

onoff

R1

R2

R3

R4

Vout

Iin

Vin

ADCADC

ADC

26


UPM


X


IIN-ref

Protections


VOUT max

IIN max

ldquodrdquo max

ldquoΔdrdquo max

ON-OFF Main Switch

ON-OFF Main Switch





intΣIin

gt

CalculatedOn-Off


Max






VOUT-ref

GinPI


UPM










VinGin

Multiplier

xVin

Gin(1Rin)

50 kHz



Adder

+Iin

ΣIin

Comparator

gtOnOff

20 MHz

NoPWMNoPWM


27


UPM




10 W 30 W 50 W 30 W 10 W

Vout

IinGin

StableStable

Load


Unstable

Unstable

Unstable

Unstable


UPM




Adaptive control

28


UPM



Load Change

Vout

Iin




T



UPM

Vin_dc

Iin_dc

d

Vout


OnOff

FPGAXilinx

XC4010-e

8 8 12

Vin Vout Iin

PROMXC 17512

ADC0808

ADC0808

HI 5805


ADCsADCs

Power Converter

Vout Vin_acIin_ac

PF = 099PF = 099PF = 099

29


UPM


DigitalController


switches)Digital


Measuredamp State


Analog

ADConverter

MeasuredVariables

(digital buses)

Mixed




UPM


M1

C Vout

D11n

+

_Vin

Iin

IL1

RL

IR

ON

L1OFF

M1

C Vout

D11n

+

_Vin

Iin

IL1

RL

IR

OFF

L1ON

Vout

n

ID1 = IL1 n

IC



1

kin1k1Lk1L

1L1in L

tVII

dtdILV

Δsdot+=rArr= minus

CtI

VVdt

dVCI kR1koutkout

outR


1

1kout1k1Lk1L

1L1

out

LntV

IIdt

dILnV

sdotΔsdot


minus

C

tIn

I

VVdt

dVCInI kR

1k1L

1koutkoutout

R1L

Δsdot⎟⎟⎠

⎞⎜⎜⎝

⎛minus

+=rArr=minus

minus

minus



30


UPM


VHDLVHDLVHDL

VHDL-AMS

VHDLVHDL--AMSAMS






UPM




VHDLVHDL








Simulationtime


CPU time using VHDL

models


modelsmodels



VHDL speed VHDL-AMS

speed


speedspeed

10 ms10 10 msms 69 s69 s69 s 446 s446 s446 s 641641641

100 ms100 100 msms 700 s700 s700 s 6912 s6912 s6912 s 987987987

1000 ms1000 1000 msms 6890 s6890 s6890 s 68443 s68443 s68443 s 993993993

VHDLVHDL--AMSAMS

31


UPM

42V 14V

CC

CC 42V 14V


system vehicles


Q1-1

Q2-1

Q16-1

Q16-2

Q2-2

Q1-2

L

L

L

COCIN




UPM


Q1-1

Q2-1

Q16-1

Q16-2

Q2-2

Q1-2

L

L

L

COCIN








3 prototypes


3 prototypes



32


UPM


VoVIN

L2d2

d1L1




VINd1

Battery

R1

R2

+

+ +

VINd2

1

BAT1IN1 R

VdVI minus=

2

22 R

VdVI BATIN -=


UPM







446

416

03360

03528

320

2336



1 5

CCM ndash 1000W

824

184

Not acceptable


Q1-1

Q2-1

Q16-1

Q16-2

Q2-2

Q1-2

L

L

L

33


UPM

AVGLI AVGLI


dT T

LVV OIN minus

LVOminus

AVGLI

dT T

LVV OIN minus

LVOminus

AVGLI

⎟⎟⎠

⎞⎜⎜⎝

⎛ minus=

O

OIN

i

2iIN

i VVV

fL2dVI



AVGLI AVGLI

DCMDCM


UPM


03360

03528






416

824



1 5

CCM ndash 1000W

0262002623

0275102649


1 5

DCM ndash 1000W

Not acceptable

445

490

446

454

110102

Very good


34


UPM



420 97

435 100

440 101

435 -

DC Current(A)

429 99

428 98

446 103

460 106

Deviation()

Phase 2

Phase 3

Phase 4

Phase 5

Phase 6

Phase 7

Phase 8

Average

CCM


IO=35A




UPM


ADCInterface

ampfilter

Regulator8

d1


Vout

ADCcontrol

Reset

Vin

12

MCDgenerator

12

Vout

12

Vin

Phase-shifter

8

d2

Protections

1616

Clock

16

H-Pulses L-Pulses




35


UPM




422 97

438 101

442 102

434 -

DC Current(A)

431 99

445 102

424 98

448 103

Deviation()

Phase 2Phase 2

Phase 3Phase 3

Phase 4Phase 4

Phase 5Phase 5

Phase 6Phase 6

Phase 7Phase 7

Phase 8Phase 8

AverageAverage

DCMDCM


IO=17A

IO=27A


UPM





36


UPM


-05

0

05

1

15

2

00E+00 50E-06 10E-05 15E-05 20E-05 25E-05t (s)

()

-05

0

05

1

15

2

00E+00 50E-06 10E-05 15E-05 20E-05 25E-05t (s)

()

0

20

40

60

80

100

120

140

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35

Phase number

[+6-8]

0

20

40

60

80

100

120

140

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35

Phase number

[+6-8]

Half load(500W)


Full load(1000W)

0

1

2

3

4

p

0 5μs 10μs 15μs 20μs0

1

2

3

4

p



0

20

40

60

80

100

120

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35

Phase number

+10-75

0

20

40

60

80

100

120

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35

Phase number

+10-75



UPM

Output currentDC AC

11App

70ADC


is

0 01 02 03 04 05 06 07 08 09 100102030405

060708091

Duty cycle (d)

Nor

m c

urre

nt r

ippl

e Dutyvariation

2 phases

3 phases



37


UPM

10

5

5

10

3T0 x

5

5

3T0 x

Ideal case






10

5

5

10

3T0 x

5

5

3T0 x

Non-ideal



10

5

5

10

3T0 x

5

5

3T0 x

Worse case



10

5

5

10

3T0 x

5

5

3T0 x





UPM

ΔIP-P= 40A (5Adiv)

1 phase

ΔIP-P= 12A (5Adiv)

2 phases

ΔIP-P= 5A (5Adiv)

4 phases

ΔIP-P= 22A (1Adiv)

8 phases

ΔIP-P= 16A (1Adiv)

16 phases



38


UPM

(a)

30

31

22 40

37

22 33

2830

31

22 40

37

22 33

28

(a)

Center of mass

(a)

30

31

22 40

37

22 33

2830

31

22 40

37

22 33

28

(a)

Center of mass

Phase1Phase

2

Phase3

Phase4

Phase5

Phase6

Phase7

Phase8

1st

2nd

3rd 4th

6th

5th 8th

7th

(b)

1st

2nd

3rd 4th

6th

5th 8th

7th

1st

2nd

3rd 4th

6th

5th 8th

7th

(b)

40 A

37 A30 A

33 A

22 A 28 A

31 A

22 A






UPM

18 0 18

18

18

OVERALL 67A

18 0 18

18

18

1

2

34

56

7

8

9

10

1112 13

14

15

16

MAX

MIN

18 0 18

18

18

OVERALL 05A

18 0 18

18

18

1

2

34

56

7

8

9

10

1112 13

1415

16

MAX

MIN


16151413121110987654321

Phase number

165155177152140144148128147122154158139149142133

Current ripple (A)

39


UPM

ΔIP-P= 40A

ΔIP-P= 40A

ΔIP-P= 07A

ΔIP-P= 16A

57

ΔIP-P= 11A

ΔIP-P= 22A

50

ΔIP-P= 28A

ΔIP-P= 5A

44

ΔIP-P= 11A

ΔIP-P= 12A

9






1 2 4 8 16



UPM


Tswitch

delay

Load

voutvin



COUNTERDUTY CYCLE

DRIVING SIGNAL

Load

voutvin



40


UPM



Dri

vin

gsi

gnal

s

Counter

+ hellip +


Duty cycle





UPM


Dri

vin

gD

rivi

ng

sign

als

sign

als



ltDuty cycle


Shift Register



Counter


41


UPM






ASIC

12 12 phasesphases

6 6 phasesphases

24 24 phasesphases





0

2000

4000

6000

8000

10000

12000

14000

16000

2 4 6 8 12 16 20 24

0

2000

4000

6000

8000

10000

12000

2 4 6 8 12 16 20 24

0

2000

4000

6000

8000

10000

12000

14000

16000

18000

2 4 6 8 12 16 20 24


Res

ol 1

28Res

ol 2

56Res

ol 5

12

FPGA

Equ

ival

ent

gate

s

Phases

0

200

400

600

800

1000

2 4 6 8 12 16 20 24


Res

ol 1

28Res

ol 2

56Res

ol 5

120

200

400

600

800

1000

1200

2 4 6 8 12 16 20 24

0

200

400

600

800

1000

1200

1400

2 4 6 8 12 16 20 24

ASIC

Equ

ival

ent

gate

s

Phases


UPM


0

10

20

30

40

50

0 20 40 60 80



0

10

20

30

40

50

0 20 40 60 80



Iout

Pow

erlo

sses

(W)

80

84

88

92

96

0 10 20 30 40 50 60 70 80

6 phases

8 phases12 phases

16 phases

4 phases



Iout

Effic

ienc

y(

)

80

84

88

92

96

0 10 20 30 40 50 60 70 80

6 phases

8 phases12 phases

16 phases

4 phases



Iout

Effic

ienc

y(

)



42


UPM





UPM


RFAmp

Pow

erSt

age

Control

iRF

vs

VS

variable VS


24V

9Vfmax=35kHz

Input voltage = 28V





43


UPM


Cs

M1

L

M2

Cs

M1

L

M2

Cs

M1

L

M2

Cs

M1

L

M2

Ve Vout

CAR

GA




UPM


SW

CLK

ff Resolution =

Pipeline

fCLK

f = 25MHz f = 45MHz

Resolution required



fselected = 32MHz


44


UPM

33 33 DitherDither

SW

CLK

ff Resolution gt

d = 42

d =43

d =425

T=2TSW=8μs

Output voltage

2 solutions

V=50mV

TSW=4μs 1 solution

T=4μs

Output voltage

V=25mV

SW

CLKNVirtual



Average duty cycle

It gives 1 more bit


UPM



SimulatedSimulated

MeasuredMeasured



)(

4110780250 22




45


UPM






UPM


f = 200Hz f = 15kHz

f = 3kHz f = 5kHz

46


UPM





UPM



2 2 micromicross

Vo

1 V

2 V

VRM for DVS5 V

Io = 20 A max

1V - 2 V

Io

02 V max02 V max

0 A

20 A

500 Amicros

Vo




47


UPM


10-1 100 101

100

L-C diagram

C2 micros

200 mV

20A




C = 35 C = 35 μμFF



UPM






fsw = 520 kHz

(125 mΩ eq Rds_on)





48


UPM


0

1

To drivers

New vref

vo dig

N-phases_tran

N-phases

New vref

vo dig

New vref

vo dig


ic


NON-LINEAR CONTROL





UPM


vref

vo

0

1

To drivers

clk_sample

clk_sample

ADC

N-phases_tran

N-phases

vo dig

LINEAR CONTROL



49


UPM


vref

vo

0

1

To drivers

New vref

vo dig

clk_sample

clk_sample

ADC

N-phases_tran

N-phases

vo dig

New vref

LINEAR CONTROL

NON-LINEAR CONTROL

vo dig

New vrefvo dig


ic



Beware


UPM


UpUp--stepstep

ConverterFPGA

tt11



DownDown--stepstep

t1 t2 t1 t2

ddnn

tt22vref

500 kHz

LUT


05

1

15

2

25

0 02 04 06 08 1 12 14 16 18-10

0

10

20

30

40

50

ton toff

Tmin

05

1

15

2

25

0 02 04 06 08 1 12 14 16 18-10

0

10

20

30

40

50

ton toff

Tmin

i L(A

)i L

(A)

V o(V

)V o

(V)


50


UPM


t1 t2 t1 t2

094 096 098 1 102 104 106 108 11

x 10-4

14

16

18

2

22

24

26

28

3

32

094 096 098 1 102 104 106 108 11

x 10-4

0

1

2

3

4

5092 094 096 098 1 102 104 106 108 11 112

x 10-4

14

16

18

2

22

24

26

28

3

32

092 094 096 098 1 102 104 106 108 11 112

x 10-4

0

05

1

15

2

25

3

35

4

45

Transient





Beware


UPM

ΔIo

iL

Io

vo

ic 0 ATrip point 1

Trip point 2

ΔIo

ic





51


UPM


05358z02236z07417)(z3767G(z) 2 +sdotminus

+sdot=

B G(s)

G(z)




N = 4

ESR = 125 mΩ

( )CL

1sRESRL1s

CL1)1sCESR(V

)s(Gdv

L2

ino

sdot+sdot+sdot+


==

~ VinmiddotdCo

ESR

RphaseN LphaseN

Expected by design


DC resistance


model


Beware


UPM


Pole-Zero Map

Real Axis

-1 -08 -06 -04 -02 0 02 04 06 08 1-1

-08

-06

-04

-02

0

02

04

06

08

1

09

0807060504

03

02

01

26e5

234e5

208e5

182e5

156e513e5

104e5

781e4

521e4

26e4

26e5

234e5

208e5

182e5

156e513e5

104e5

781e4

521e4

26e4

x

x

x




Duty cycle

30 micros


1z00372)z(Rminus

=

1zK)z(R 1

minus=

Controller delay

05358z02236z07417)(z3767G(z) 2 +sdotminus

+sdot=Converter

x

x

x Duty cycle

Output voltage

52


UPM

10 micros


xx

x

x

x

x

x

x




00775)(z1)(z037)(z00378R(z)

minussdotminus+sdot

=

Duty cycle

Output voltage


UPM


75 micros

xx

x

x

x

xx

x



minussdotminus+sdot

=

53


UPM


Duty

a1 = -0922548 b1 = 0037759b2 = 0051742a2 = 0

b1

b2

δ-1

δ-1

δ-1

a1

a2

Error

bn0

No b0

δ-1

Z-1

+

00775)(z1)(z037)(z00378R(z)

minussdotminus+sdot

=




UPM


z2d_m ( tf ([00378 0013986] [1 -10775 00775] 192e-6) )




=Tsample = Tsw

⎪⎩

⎪⎨⎧

rarrδ

+=δ δδ

s


54


UPM


Reference

Switched model

7 bits

8 bits

Not quantizied


PWM

ADC

111






UPM

Reference


PWM

ADC






hellip

222

55


UPM



a1 = -0922548 b1 = 0037759b2 = 0051742a2 = 0

b1

b2

δ-1

δ-1

δ-1

a1

a2

Error

bn0

No b0


UPM


0lt Duty cycle lt1


Hardware adders






Beware

56


UPM

0 1 2 30

05

1

15

2

25








UPM



0 1 2 3

x 10-4

0

05

1

15

2

25

100 usdiv100 usdiv



57


UPM






UPM




58


UPM


13 14 15 16 17 18 19

x 10-4

12

14

16

18

2

22

08 V drop

10 microsdiv

2 V





UPM



Vo

1 V

2 V



11 A11 A

20 mV

520 kHz



59


UPM


Vo

Io

200 mV







UPM


Vo

1 V

2 V





60


UPM





Beware



UPM



11


UPM




PWM63

PWM62

PWM61

Vref

error3

error2

error1

error0

error-1

error-2






of the controller)



UPM











CLKCLK2

Vout

VGS

dk


Beware

12


UPM







CLK

MUX


S QR

VGS

duty(1)duty(0)

end of sync duty


duty(n-12)

Example(L=2)

Bewareof thedelay



UPM




VGHVGL


Tswitch

delay

13


UPM



Beware




sum minusminus +=k



Driver examples





VSW

VGS

ton toff

Powerconv


+

-



UPM




zbb

zaa)z(R 110

110

++++

= minus

minus

ai bi constants









Powerconv


+

-


14


UPM

zoh

foh

matched

NA

tustin

Matlab C2D




First order hold

Polezero match



Two possibilities









UPM







Two mains reasons






15


UPM








UPM





)z(G)z(R1)z(G)z(R

)z(X)z(Y)z(M

+==

))z(M1)(z(G)z(M)z(R

minus=





Beware


+ Y(z)

_

E(z)X(z)R(z) G(z)

16


UPM





k

kk



=

⎪⎭

⎪⎬⎫

⎪⎩

⎪⎨⎧

minusminus=

minus=minusrArr

minusminus

=minusminus

minusminus


z1)z(M1)z(E

11

11








UPM


10

p1=e-σmiddotejθ


θ

γe-σ




=sR


minus= eMp



17


UPM


xx

xx

OO






96730middot29412239middot6229)(


2

7211

8

+minus+

=

+++

= minusminus

minus

zzzzG

ssssG


condition)



UPM




Vout

Duty

Near unstable



18


UPM



1z110)z(R 5

minus= minus

Vout

Duty







UPM




+= minus

Vout

Duty




19


UPM


Vout

Duty





23

+minusminus+minus




UPM


xk xk-1

hellip

xk-m

X

b0

X

b1

X

bm

hellip

+

+

hellip

+

yk yk-1

hellip

yk-n

X

a1

X

an

+

+

hellip

hellip

+

-yk

nn

22

110

mm

22

110

zazazaazbzbzbb

)z(e)z(d)z(R

minusminusminus

minusminusminus

sdot++sdot+sdot+





20


UPM

Z-1

a1

a2

Z-1


Z-1

bo

eK

Z-1

b1

b2

R1(z) R2(z)YK

dK

eK

R1 R2

Z-1

Z-1

a1

bo

b1

dKeK






UPM

Difference equation


a1a2

e(z)

⎩⎨⎧

rarrδ

+=δminus=δ= δδ+


TXXXmiddotY kkkk1k

kk

Tz1 1minusminus

=δ

k1

1k

1k Y

z1zTYXminus

minusminus

minus

sdot=δ=

δ-1 δ-1

aman

δ-1 δ-1

bm

+

bo

b1

u(z)h(z)

T Z-1

δ-1

(Integral)

+




More adders

21


UPM

a1

a2

δ-1

bo

b1T

b2T2 δ-1 T2

T


Tn Tn


Z-1

+



Adapted δ-1


UPM








ek-1 isrequested

ek-1 isavailable

dk isimposed

T

22


UPM

0 1 2 3 4 5 6 7 8

x 10 -4

-04

-02

0

02

04

06

08

1

12

14

16




vo

48 5 52 54 56 58

10-4

138

14

142

144

146

148

15

152

154

156

vo

Matlabfixed-point

toolbox






UPM



00011111b0 =


Meanerror

22 143143 5252

11 333333 170170

44 3232 0606

33 6767 1717


615615 105ns105ns

12481248 168ns168ns

Mp ts

Example

160160 012ms012ms

113113 011ms011ms1


zz

( )1

222 353


zz


00101000b0 = k53

k5


00101001b0 = k853

k8

k5


222

333



00100000b0 = k3 e2 sdotminus111


1rsquos

23


UPM





D QEN

new_cycle Xek

b0

D QEN

new_cycle Xek-1

b1

+

D QEN

new_cycle Xdk-1

a1

D QEN

new_cycle Xdk-2

b2

+ D QENnew_cycle

dk

+


D Q

D Q

D Q

D Q

D Q

D Q






UPM

Fixed-point toolbox







MatlabSimulink



24


UPM

VHDL or VHDL-AMS











UPM


Applications333



323322

333333

25


UPM


IinVin

Vout

DCDCREGULATOR LO

AD

~

IoutIin


Vout

+_Vin

CONTROL

d

R1

R2

R3

R4

n1 n2LINE

LOAD

Main Switch

Vin

Iin Vout

PO=50Wf=50kHz


PO=50Wf=50kHz



UPM





Adaptive control


LOA

D

~

IoutIin

PFC CONVERTERVout

+_Vin

Controlblock

Controlblock

onoff

R1

R2

R3

R4

Vout

Iin

Vin

ADCADC

ADC

26


UPM


X


IIN-ref

Protections


VOUT max

IIN max

ldquodrdquo max

ldquoΔdrdquo max

ON-OFF Main Switch

ON-OFF Main Switch





intΣIin

gt

CalculatedOn-Off


Max






VOUT-ref

GinPI


UPM










VinGin

Multiplier

xVin

Gin(1Rin)

50 kHz



Adder

+Iin

ΣIin

Comparator

gtOnOff

20 MHz

NoPWMNoPWM


27


UPM




10 W 30 W 50 W 30 W 10 W

Vout

IinGin

StableStable

Load


Unstable

Unstable

Unstable

Unstable


UPM




Adaptive control

28


UPM



Load Change

Vout

Iin




T



UPM

Vin_dc

Iin_dc

d

Vout


OnOff

FPGAXilinx

XC4010-e

8 8 12

Vin Vout Iin

PROMXC 17512

ADC0808

ADC0808

HI 5805


ADCsADCs

Power Converter

Vout Vin_acIin_ac

PF = 099PF = 099PF = 099

29


UPM


DigitalController


switches)Digital


Measuredamp State


Analog

ADConverter

MeasuredVariables

(digital buses)

Mixed




UPM


M1

C Vout

D11n

+

_Vin

Iin

IL1

RL

IR

ON

L1OFF

M1

C Vout

D11n

+

_Vin

Iin

IL1

RL

IR

OFF

L1ON

Vout

n

ID1 = IL1 n

IC



1

kin1k1Lk1L

1L1in L

tVII

dtdILV

Δsdot+=rArr= minus

CtI

VVdt

dVCI kR1koutkout

outR


1

1kout1k1Lk1L

1L1

out

LntV

IIdt

dILnV

sdotΔsdot


minus

C

tIn

I

VVdt

dVCInI kR

1k1L

1koutkoutout

R1L

Δsdot⎟⎟⎠

⎞⎜⎜⎝

⎛minus

+=rArr=minus

minus

minus



30


UPM


VHDLVHDLVHDL

VHDL-AMS

VHDLVHDL--AMSAMS






UPM




VHDLVHDL








Simulationtime


CPU time using VHDL

models


modelsmodels



VHDL speed VHDL-AMS

speed


speedspeed

10 ms10 10 msms 69 s69 s69 s 446 s446 s446 s 641641641

100 ms100 100 msms 700 s700 s700 s 6912 s6912 s6912 s 987987987

1000 ms1000 1000 msms 6890 s6890 s6890 s 68443 s68443 s68443 s 993993993

VHDLVHDL--AMSAMS

31


UPM

42V 14V

CC

CC 42V 14V


system vehicles


Q1-1

Q2-1

Q16-1

Q16-2

Q2-2

Q1-2

L

L

L

COCIN




UPM


Q1-1

Q2-1

Q16-1

Q16-2

Q2-2

Q1-2

L

L

L

COCIN








3 prototypes


3 prototypes



32


UPM


VoVIN

L2d2

d1L1




VINd1

Battery

R1

R2

+

+ +

VINd2

1

BAT1IN1 R

VdVI minus=

2

22 R

VdVI BATIN -=


UPM







446

416

03360

03528

320

2336



1 5

CCM ndash 1000W

824

184

Not acceptable


Q1-1

Q2-1

Q16-1

Q16-2

Q2-2

Q1-2

L

L

L

33


UPM

AVGLI AVGLI


dT T

LVV OIN minus

LVOminus

AVGLI

dT T

LVV OIN minus

LVOminus

AVGLI

⎟⎟⎠

⎞⎜⎜⎝

⎛ minus=

O

OIN

i

2iIN

i VVV

fL2dVI



AVGLI AVGLI

DCMDCM


UPM


03360

03528






416

824



1 5

CCM ndash 1000W

0262002623

0275102649


1 5

DCM ndash 1000W

Not acceptable

445

490

446

454

110102

Very good


34


UPM



420 97

435 100

440 101

435 -

DC Current(A)

429 99

428 98

446 103

460 106

Deviation()

Phase 2

Phase 3

Phase 4

Phase 5

Phase 6

Phase 7

Phase 8

Average

CCM


IO=35A




UPM


ADCInterface

ampfilter

Regulator8

d1


Vout

ADCcontrol

Reset

Vin

12

MCDgenerator

12

Vout

12

Vin

Phase-shifter

8

d2

Protections

1616

Clock

16

H-Pulses L-Pulses




35


UPM




422 97

438 101

442 102

434 -

DC Current(A)

431 99

445 102

424 98

448 103

Deviation()

Phase 2Phase 2

Phase 3Phase 3

Phase 4Phase 4

Phase 5Phase 5

Phase 6Phase 6

Phase 7Phase 7

Phase 8Phase 8

AverageAverage

DCMDCM


IO=17A

IO=27A


UPM





36


UPM


-05

0

05

1

15

2

00E+00 50E-06 10E-05 15E-05 20E-05 25E-05t (s)

()

-05

0

05

1

15

2

00E+00 50E-06 10E-05 15E-05 20E-05 25E-05t (s)

()

0

20

40

60

80

100

120

140

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35

Phase number

[+6-8]

0

20

40

60

80

100

120

140

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35

Phase number

[+6-8]

Half load(500W)


Full load(1000W)

0

1

2

3

4

p

0 5μs 10μs 15μs 20μs0

1

2

3

4

p



0

20

40

60

80

100

120

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35

Phase number

+10-75

0

20

40

60

80

100

120

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35

Phase number

+10-75



UPM

Output currentDC AC

11App

70ADC


is

0 01 02 03 04 05 06 07 08 09 100102030405

060708091

Duty cycle (d)

Nor

m c

urre

nt r

ippl

e Dutyvariation

2 phases

3 phases



37


UPM

10

5

5

10

3T0 x

5

5

3T0 x

Ideal case






10

5

5

10

3T0 x

5

5

3T0 x

Non-ideal



10

5

5

10

3T0 x

5

5

3T0 x

Worse case



10

5

5

10

3T0 x

5

5

3T0 x





UPM

ΔIP-P= 40A (5Adiv)

1 phase

ΔIP-P= 12A (5Adiv)

2 phases

ΔIP-P= 5A (5Adiv)

4 phases

ΔIP-P= 22A (1Adiv)

8 phases

ΔIP-P= 16A (1Adiv)

16 phases



38


UPM

(a)

30

31

22 40

37

22 33

2830

31

22 40

37

22 33

28

(a)

Center of mass

(a)

30

31

22 40

37

22 33

2830

31

22 40

37

22 33

28

(a)

Center of mass

Phase1Phase

2

Phase3

Phase4

Phase5

Phase6

Phase7

Phase8

1st

2nd

3rd 4th

6th

5th 8th

7th

(b)

1st

2nd

3rd 4th

6th

5th 8th

7th

1st

2nd

3rd 4th

6th

5th 8th

7th

(b)

40 A

37 A30 A

33 A

22 A 28 A

31 A

22 A






UPM

18 0 18

18

18

OVERALL 67A

18 0 18

18

18

1

2

34

56

7

8

9

10

1112 13

14

15

16

MAX

MIN

18 0 18

18

18

OVERALL 05A

18 0 18

18

18

1

2

34

56

7

8

9

10

1112 13

1415

16

MAX

MIN


16151413121110987654321

Phase number

165155177152140144148128147122154158139149142133

Current ripple (A)

39


UPM

ΔIP-P= 40A

ΔIP-P= 40A

ΔIP-P= 07A

ΔIP-P= 16A

57

ΔIP-P= 11A

ΔIP-P= 22A

50

ΔIP-P= 28A

ΔIP-P= 5A

44

ΔIP-P= 11A

ΔIP-P= 12A

9






1 2 4 8 16



UPM


Tswitch

delay

Load

voutvin



COUNTERDUTY CYCLE

DRIVING SIGNAL

Load

voutvin



40


UPM



Dri

vin

gsi

gnal

s

Counter

+ hellip +


Duty cycle





UPM


Dri

vin

gD

rivi

ng

sign

als

sign

als



ltDuty cycle


Shift Register



Counter


41


UPM






ASIC

12 12 phasesphases

6 6 phasesphases

24 24 phasesphases





0

2000

4000

6000

8000

10000

12000

14000

16000

2 4 6 8 12 16 20 24

0

2000

4000

6000

8000

10000

12000

2 4 6 8 12 16 20 24

0

2000

4000

6000

8000

10000

12000

14000

16000

18000

2 4 6 8 12 16 20 24


Res

ol 1

28Res

ol 2

56Res

ol 5

12

FPGA

Equ

ival

ent

gate

s

Phases

0

200

400

600

800

1000

2 4 6 8 12 16 20 24


Res

ol 1

28Res

ol 2

56Res

ol 5

120

200

400

600

800

1000

1200

2 4 6 8 12 16 20 24

0

200

400

600

800

1000

1200

1400

2 4 6 8 12 16 20 24

ASIC

Equ

ival

ent

gate

s

Phases


UPM


0

10

20

30

40

50

0 20 40 60 80



0

10

20

30

40

50

0 20 40 60 80



Iout

Pow

erlo

sses

(W)

80

84

88

92

96

0 10 20 30 40 50 60 70 80

6 phases

8 phases12 phases

16 phases

4 phases



Iout

Effic

ienc

y(

)

80

84

88

92

96

0 10 20 30 40 50 60 70 80

6 phases

8 phases12 phases

16 phases

4 phases



Iout

Effic

ienc

y(

)



42


UPM





UPM


RFAmp

Pow

erSt

age

Control

iRF

vs

VS

variable VS


24V

9Vfmax=35kHz

Input voltage = 28V





43


UPM


Cs

M1

L

M2

Cs

M1

L

M2

Cs

M1

L

M2

Cs

M1

L

M2

Ve Vout

CAR

GA




UPM


SW

CLK

ff Resolution =

Pipeline

fCLK

f = 25MHz f = 45MHz

Resolution required



fselected = 32MHz


44


UPM

33 33 DitherDither

SW

CLK

ff Resolution gt

d = 42

d =43

d =425

T=2TSW=8μs

Output voltage

2 solutions

V=50mV

TSW=4μs 1 solution

T=4μs

Output voltage

V=25mV

SW

CLKNVirtual



Average duty cycle

It gives 1 more bit


UPM



SimulatedSimulated

MeasuredMeasured



)(

4110780250 22




45


UPM






UPM


f = 200Hz f = 15kHz

f = 3kHz f = 5kHz

46


UPM





UPM



2 2 micromicross

Vo

1 V

2 V

VRM for DVS5 V

Io = 20 A max

1V - 2 V

Io

02 V max02 V max

0 A

20 A

500 Amicros

Vo




47


UPM


10-1 100 101

100

L-C diagram

C2 micros

200 mV

20A




C = 35 C = 35 μμFF



UPM






fsw = 520 kHz

(125 mΩ eq Rds_on)





48


UPM


0

1

To drivers

New vref

vo dig

N-phases_tran

N-phases

New vref

vo dig

New vref

vo dig


ic


NON-LINEAR CONTROL





UPM


vref

vo

0

1

To drivers

clk_sample

clk_sample

ADC

N-phases_tran

N-phases

vo dig

LINEAR CONTROL



49


UPM


vref

vo

0

1

To drivers

New vref

vo dig

clk_sample

clk_sample

ADC

N-phases_tran

N-phases

vo dig

New vref

LINEAR CONTROL

NON-LINEAR CONTROL

vo dig

New vrefvo dig


ic



Beware


UPM


UpUp--stepstep

ConverterFPGA

tt11



DownDown--stepstep

t1 t2 t1 t2

ddnn

tt22vref

500 kHz

LUT


05

1

15

2

25

0 02 04 06 08 1 12 14 16 18-10

0

10

20

30

40

50

ton toff

Tmin

05

1

15

2

25

0 02 04 06 08 1 12 14 16 18-10

0

10

20

30

40

50

ton toff

Tmin

i L(A

)i L

(A)

V o(V

)V o

(V)


50


UPM


t1 t2 t1 t2

094 096 098 1 102 104 106 108 11

x 10-4

14

16

18

2

22

24

26

28

3

32

094 096 098 1 102 104 106 108 11

x 10-4

0

1

2

3

4

5092 094 096 098 1 102 104 106 108 11 112

x 10-4

14

16

18

2

22

24

26

28

3

32

092 094 096 098 1 102 104 106 108 11 112

x 10-4

0

05

1

15

2

25

3

35

4

45

Transient





Beware


UPM

ΔIo

iL

Io

vo

ic 0 ATrip point 1

Trip point 2

ΔIo

ic





51


UPM


05358z02236z07417)(z3767G(z) 2 +sdotminus

+sdot=

B G(s)

G(z)




N = 4

ESR = 125 mΩ

( )CL

1sRESRL1s

CL1)1sCESR(V

)s(Gdv

L2

ino

sdot+sdot+sdot+


==

~ VinmiddotdCo

ESR

RphaseN LphaseN

Expected by design


DC resistance


model


Beware


UPM


Pole-Zero Map

Real Axis

-1 -08 -06 -04 -02 0 02 04 06 08 1-1

-08

-06

-04

-02

0

02

04

06

08

1

09

0807060504

03

02

01

26e5

234e5

208e5

182e5

156e513e5

104e5

781e4

521e4

26e4

26e5

234e5

208e5

182e5

156e513e5

104e5

781e4

521e4

26e4

x

x

x




Duty cycle

30 micros


1z00372)z(Rminus

=

1zK)z(R 1

minus=

Controller delay

05358z02236z07417)(z3767G(z) 2 +sdotminus

+sdot=Converter

x

x

x Duty cycle

Output voltage

52


UPM

10 micros


xx

x

x

x

x

x

x




00775)(z1)(z037)(z00378R(z)

minussdotminus+sdot

=

Duty cycle

Output voltage


UPM


75 micros

xx

x

x

x

xx

x



minussdotminus+sdot

=

53


UPM


Duty

a1 = -0922548 b1 = 0037759b2 = 0051742a2 = 0

b1

b2

δ-1

δ-1

δ-1

a1

a2

Error

bn0

No b0

δ-1

Z-1

+

00775)(z1)(z037)(z00378R(z)

minussdotminus+sdot

=




UPM


z2d_m ( tf ([00378 0013986] [1 -10775 00775] 192e-6) )




=Tsample = Tsw

⎪⎩

⎪⎨⎧

rarrδ

+=δ δδ

s


54


UPM


Reference

Switched model

7 bits

8 bits

Not quantizied


PWM

ADC

111






UPM

Reference


PWM

ADC






hellip

222

55


UPM



a1 = -0922548 b1 = 0037759b2 = 0051742a2 = 0

b1

b2

δ-1

δ-1

δ-1

a1

a2

Error

bn0

No b0


UPM


0lt Duty cycle lt1


Hardware adders






Beware

56


UPM

0 1 2 30

05

1

15

2

25








UPM



0 1 2 3

x 10-4

0

05

1

15

2

25

100 usdiv100 usdiv



57


UPM






UPM




58


UPM


13 14 15 16 17 18 19

x 10-4

12

14

16

18

2

22

08 V drop

10 microsdiv

2 V





UPM



Vo

1 V

2 V



11 A11 A

20 mV

520 kHz



59


UPM


Vo

Io

200 mV







UPM


Vo

1 V

2 V





60


UPM





Beware



UPM



12


UPM







CLK

MUX


S QR

VGS

duty(1)duty(0)

end of sync duty


duty(n-12)

Example(L=2)

Bewareof thedelay



UPM




VGHVGL


Tswitch

delay

13


UPM



Beware




sum minusminus +=k



Driver examples





VSW

VGS

ton toff

Powerconv


+

-



UPM




zbb

zaa)z(R 110

110

++++

= minus

minus

ai bi constants









Powerconv


+

-


14


UPM

zoh

foh

matched

NA

tustin

Matlab C2D




First order hold

Polezero match



Two possibilities









UPM







Two mains reasons






15


UPM








UPM





)z(G)z(R1)z(G)z(R

)z(X)z(Y)z(M

+==

))z(M1)(z(G)z(M)z(R

minus=





Beware


+ Y(z)

_

E(z)X(z)R(z) G(z)

16


UPM





k

kk



=

⎪⎭

⎪⎬⎫

⎪⎩

⎪⎨⎧

minusminus=

minus=minusrArr

minusminus

=minusminus

minusminus


z1)z(M1)z(E

11

11








UPM


10

p1=e-σmiddotejθ


θ

γe-σ




=sR


minus= eMp



17


UPM


xx

xx

OO






96730middot29412239middot6229)(


2

7211

8

+minus+

=

+++

= minusminus

minus

zzzzG

ssssG


condition)



UPM




Vout

Duty

Near unstable



18


UPM



1z110)z(R 5

minus= minus

Vout

Duty







UPM




+= minus

Vout

Duty




19


UPM


Vout

Duty





23

+minusminus+minus




UPM


xk xk-1

hellip

xk-m

X

b0

X

b1

X

bm

hellip

+

+

hellip

+

yk yk-1

hellip

yk-n

X

a1

X

an

+

+

hellip

hellip

+

-yk

nn

22

110

mm

22

110

zazazaazbzbzbb

)z(e)z(d)z(R

minusminusminus

minusminusminus

sdot++sdot+sdot+





20


UPM

Z-1

a1

a2

Z-1


Z-1

bo

eK

Z-1

b1

b2

R1(z) R2(z)YK

dK

eK

R1 R2

Z-1

Z-1

a1

bo

b1

dKeK






UPM

Difference equation


a1a2

e(z)

⎩⎨⎧

rarrδ

+=δminus=δ= δδ+


TXXXmiddotY kkkk1k

kk

Tz1 1minusminus

=δ

k1

1k

1k Y

z1zTYXminus

minusminus

minus

sdot=δ=

δ-1 δ-1

aman

δ-1 δ-1

bm

+

bo

b1

u(z)h(z)

T Z-1

δ-1

(Integral)

+




More adders

21


UPM

a1

a2

δ-1

bo

b1T

b2T2 δ-1 T2

T


Tn Tn


Z-1

+



Adapted δ-1


UPM








ek-1 isrequested

ek-1 isavailable

dk isimposed

T

22


UPM

0 1 2 3 4 5 6 7 8

x 10 -4

-04

-02

0

02

04

06

08

1

12

14

16




vo

48 5 52 54 56 58

10-4

138

14

142

144

146

148

15

152

154

156

vo

Matlabfixed-point

toolbox






UPM



00011111b0 =


Meanerror

22 143143 5252

11 333333 170170

44 3232 0606

33 6767 1717


615615 105ns105ns

12481248 168ns168ns

Mp ts

Example

160160 012ms012ms

113113 011ms011ms1


zz

( )1

222 353


zz


00101000b0 = k53

k5


00101001b0 = k853

k8

k5


222

333



00100000b0 = k3 e2 sdotminus111


1rsquos

23


UPM





D QEN

new_cycle Xek

b0

D QEN

new_cycle Xek-1

b1

+

D QEN

new_cycle Xdk-1

a1

D QEN

new_cycle Xdk-2

b2

+ D QENnew_cycle

dk

+


D Q

D Q

D Q

D Q

D Q

D Q






UPM

Fixed-point toolbox







MatlabSimulink



24


UPM

VHDL or VHDL-AMS











UPM


Applications333



323322

333333

25


UPM


IinVin

Vout

DCDCREGULATOR LO

AD

~

IoutIin


Vout

+_Vin

CONTROL

d

R1

R2

R3

R4

n1 n2LINE

LOAD

Main Switch

Vin

Iin Vout

PO=50Wf=50kHz


PO=50Wf=50kHz



UPM





Adaptive control


LOA

D

~

IoutIin

PFC CONVERTERVout

+_Vin

Controlblock

Controlblock

onoff

R1

R2

R3

R4

Vout

Iin

Vin

ADCADC

ADC

26


UPM


X


IIN-ref

Protections


VOUT max

IIN max

ldquodrdquo max

ldquoΔdrdquo max

ON-OFF Main Switch

ON-OFF Main Switch





intΣIin

gt

CalculatedOn-Off


Max






VOUT-ref

GinPI


UPM










VinGin

Multiplier

xVin

Gin(1Rin)

50 kHz



Adder

+Iin

ΣIin

Comparator

gtOnOff

20 MHz

NoPWMNoPWM


27


UPM




10 W 30 W 50 W 30 W 10 W

Vout

IinGin

StableStable

Load


Unstable

Unstable

Unstable

Unstable


UPM




Adaptive control

28


UPM



Load Change

Vout

Iin




T



UPM

Vin_dc

Iin_dc

d

Vout


OnOff

FPGAXilinx

XC4010-e

8 8 12

Vin Vout Iin

PROMXC 17512

ADC0808

ADC0808

HI 5805


ADCsADCs

Power Converter

Vout Vin_acIin_ac

PF = 099PF = 099PF = 099

29


UPM


DigitalController


switches)Digital


Measuredamp State


Analog

ADConverter

MeasuredVariables

(digital buses)

Mixed




UPM


M1

C Vout

D11n

+

_Vin

Iin

IL1

RL

IR

ON

L1OFF

M1

C Vout

D11n

+

_Vin

Iin

IL1

RL

IR

OFF

L1ON

Vout

n

ID1 = IL1 n

IC



1

kin1k1Lk1L

1L1in L

tVII

dtdILV

Δsdot+=rArr= minus

CtI

VVdt

dVCI kR1koutkout

outR


1

1kout1k1Lk1L

1L1

out

LntV

IIdt

dILnV

sdotΔsdot


minus

C

tIn

I

VVdt

dVCInI kR

1k1L

1koutkoutout

R1L

Δsdot⎟⎟⎠

⎞⎜⎜⎝

⎛minus

+=rArr=minus

minus

minus



30


UPM


VHDLVHDLVHDL

VHDL-AMS

VHDLVHDL--AMSAMS






UPM




VHDLVHDL








Simulationtime


CPU time using VHDL

models


modelsmodels



VHDL speed VHDL-AMS

speed


speedspeed

10 ms10 10 msms 69 s69 s69 s 446 s446 s446 s 641641641

100 ms100 100 msms 700 s700 s700 s 6912 s6912 s6912 s 987987987

1000 ms1000 1000 msms 6890 s6890 s6890 s 68443 s68443 s68443 s 993993993

VHDLVHDL--AMSAMS

31


UPM

42V 14V

CC

CC 42V 14V


system vehicles


Q1-1

Q2-1

Q16-1

Q16-2

Q2-2

Q1-2

L

L

L

COCIN




UPM


Q1-1

Q2-1

Q16-1

Q16-2

Q2-2

Q1-2

L

L

L

COCIN








3 prototypes


3 prototypes



32


UPM


VoVIN

L2d2

d1L1




VINd1

Battery

R1

R2

+

+ +

VINd2

1

BAT1IN1 R

VdVI minus=

2

22 R

VdVI BATIN -=


UPM







446

416

03360

03528

320

2336



1 5

CCM ndash 1000W

824

184

Not acceptable


Q1-1

Q2-1

Q16-1

Q16-2

Q2-2

Q1-2

L

L

L

33


UPM

AVGLI AVGLI


dT T

LVV OIN minus

LVOminus

AVGLI

dT T

LVV OIN minus

LVOminus

AVGLI

⎟⎟⎠

⎞⎜⎜⎝

⎛ minus=

O

OIN

i

2iIN

i VVV

fL2dVI



AVGLI AVGLI

DCMDCM


UPM


03360

03528






416

824



1 5

CCM ndash 1000W

0262002623

0275102649


1 5

DCM ndash 1000W

Not acceptable

445

490

446

454

110102

Very good


34


UPM



420 97

435 100

440 101

435 -

DC Current(A)

429 99

428 98

446 103

460 106

Deviation()

Phase 2

Phase 3

Phase 4

Phase 5

Phase 6

Phase 7

Phase 8

Average

CCM


IO=35A




UPM


ADCInterface

ampfilter

Regulator8

d1


Vout

ADCcontrol

Reset

Vin

12

MCDgenerator

12

Vout

12

Vin

Phase-shifter

8

d2

Protections

1616

Clock

16

H-Pulses L-Pulses




35


UPM




422 97

438 101

442 102

434 -

DC Current(A)

431 99

445 102

424 98

448 103

Deviation()

Phase 2Phase 2

Phase 3Phase 3

Phase 4Phase 4

Phase 5Phase 5

Phase 6Phase 6

Phase 7Phase 7

Phase 8Phase 8

AverageAverage

DCMDCM


IO=17A

IO=27A


UPM





36


UPM


-05

0

05

1

15

2

00E+00 50E-06 10E-05 15E-05 20E-05 25E-05t (s)

()

-05

0

05

1

15

2

00E+00 50E-06 10E-05 15E-05 20E-05 25E-05t (s)

()

0

20

40

60

80

100

120

140

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35

Phase number

[+6-8]

0

20

40

60

80

100

120

140

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35

Phase number

[+6-8]

Half load(500W)


Full load(1000W)

0

1

2

3

4

p

0 5μs 10μs 15μs 20μs0

1

2

3

4

p



0

20

40

60

80

100

120

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35

Phase number

+10-75

0

20

40

60

80

100

120

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35

Phase number

+10-75



UPM

Output currentDC AC

11App

70ADC


is

0 01 02 03 04 05 06 07 08 09 100102030405

060708091

Duty cycle (d)

Nor

m c

urre

nt r

ippl

e Dutyvariation

2 phases

3 phases



37


UPM

10

5

5

10

3T0 x

5

5

3T0 x

Ideal case






10

5

5

10

3T0 x

5

5

3T0 x

Non-ideal



10

5

5

10

3T0 x

5

5

3T0 x

Worse case



10

5

5

10

3T0 x

5

5

3T0 x





UPM

ΔIP-P= 40A (5Adiv)

1 phase

ΔIP-P= 12A (5Adiv)

2 phases

ΔIP-P= 5A (5Adiv)

4 phases

ΔIP-P= 22A (1Adiv)

8 phases

ΔIP-P= 16A (1Adiv)

16 phases



38


UPM

(a)

30

31

22 40

37

22 33

2830

31

22 40

37

22 33

28

(a)

Center of mass

(a)

30

31

22 40

37

22 33

2830

31

22 40

37

22 33

28

(a)

Center of mass

Phase1Phase

2

Phase3

Phase4

Phase5

Phase6

Phase7

Phase8

1st

2nd

3rd 4th

6th

5th 8th

7th

(b)

1st

2nd

3rd 4th

6th

5th 8th

7th

1st

2nd

3rd 4th

6th

5th 8th

7th

(b)

40 A

37 A30 A

33 A

22 A 28 A

31 A

22 A






UPM

18 0 18

18

18

OVERALL 67A

18 0 18

18

18

1

2

34

56

7

8

9

10

1112 13

14

15

16

MAX

MIN

18 0 18

18

18

OVERALL 05A

18 0 18

18

18

1

2

34

56

7

8

9

10

1112 13

1415

16

MAX

MIN


16151413121110987654321

Phase number

165155177152140144148128147122154158139149142133

Current ripple (A)

39


UPM

ΔIP-P= 40A

ΔIP-P= 40A

ΔIP-P= 07A

ΔIP-P= 16A

57

ΔIP-P= 11A

ΔIP-P= 22A

50

ΔIP-P= 28A

ΔIP-P= 5A

44

ΔIP-P= 11A

ΔIP-P= 12A

9






1 2 4 8 16



UPM


Tswitch

delay

Load

voutvin



COUNTERDUTY CYCLE

DRIVING SIGNAL

Load

voutvin



40


UPM



Dri

vin

gsi

gnal

s

Counter

+ hellip +


Duty cycle





UPM


Dri

vin

gD

rivi

ng

sign

als

sign

als



ltDuty cycle


Shift Register



Counter


41


UPM






ASIC

12 12 phasesphases

6 6 phasesphases

24 24 phasesphases





0

2000

4000

6000

8000

10000

12000

14000

16000

2 4 6 8 12 16 20 24

0

2000

4000

6000

8000

10000

12000

2 4 6 8 12 16 20 24

0

2000

4000

6000

8000

10000

12000

14000

16000

18000

2 4 6 8 12 16 20 24


Res

ol 1

28Res

ol 2

56Res

ol 5

12

FPGA

Equ

ival

ent

gate

s

Phases

0

200

400

600

800

1000

2 4 6 8 12 16 20 24


Res

ol 1

28Res

ol 2

56Res

ol 5

120

200

400

600

800

1000

1200

2 4 6 8 12 16 20 24

0

200

400

600

800

1000

1200

1400

2 4 6 8 12 16 20 24

ASIC

Equ

ival

ent

gate

s

Phases


UPM


0

10

20

30

40

50

0 20 40 60 80



0

10

20

30

40

50

0 20 40 60 80



Iout

Pow

erlo

sses

(W)

80

84

88

92

96

0 10 20 30 40 50 60 70 80

6 phases

8 phases12 phases

16 phases

4 phases



Iout

Effic

ienc

y(

)

80

84

88

92

96

0 10 20 30 40 50 60 70 80

6 phases

8 phases12 phases

16 phases

4 phases



Iout

Effic

ienc

y(

)



42


UPM





UPM


RFAmp

Pow

erSt

age

Control

iRF

vs

VS

variable VS


24V

9Vfmax=35kHz

Input voltage = 28V





43


UPM


Cs

M1

L

M2

Cs

M1

L

M2

Cs

M1

L

M2

Cs

M1

L

M2

Ve Vout

CAR

GA




UPM


SW

CLK

ff Resolution =

Pipeline

fCLK

f = 25MHz f = 45MHz

Resolution required



fselected = 32MHz


44


UPM

33 33 DitherDither

SW

CLK

ff Resolution gt

d = 42

d =43

d =425

T=2TSW=8μs

Output voltage

2 solutions

V=50mV

TSW=4μs 1 solution

T=4μs

Output voltage

V=25mV

SW

CLKNVirtual



Average duty cycle

It gives 1 more bit


UPM



SimulatedSimulated

MeasuredMeasured



)(

4110780250 22




45


UPM






UPM


f = 200Hz f = 15kHz

f = 3kHz f = 5kHz

46


UPM





UPM



2 2 micromicross

Vo

1 V

2 V

VRM for DVS5 V

Io = 20 A max

1V - 2 V

Io

02 V max02 V max

0 A

20 A

500 Amicros

Vo




47


UPM


10-1 100 101

100

L-C diagram

C2 micros

200 mV

20A




C = 35 C = 35 μμFF



UPM






fsw = 520 kHz

(125 mΩ eq Rds_on)





48


UPM


0

1

To drivers

New vref

vo dig

N-phases_tran

N-phases

New vref

vo dig

New vref

vo dig


ic


NON-LINEAR CONTROL





UPM


vref

vo

0

1

To drivers

clk_sample

clk_sample

ADC

N-phases_tran

N-phases

vo dig

LINEAR CONTROL



49


UPM


vref

vo

0

1

To drivers

New vref

vo dig

clk_sample

clk_sample

ADC

N-phases_tran

N-phases

vo dig

New vref

LINEAR CONTROL

NON-LINEAR CONTROL

vo dig

New vrefvo dig


ic



Beware


UPM


UpUp--stepstep

ConverterFPGA

tt11



DownDown--stepstep

t1 t2 t1 t2

ddnn

tt22vref

500 kHz

LUT


05

1

15

2

25

0 02 04 06 08 1 12 14 16 18-10

0

10

20

30

40

50

ton toff

Tmin

05

1

15

2

25

0 02 04 06 08 1 12 14 16 18-10

0

10

20

30

40

50

ton toff

Tmin

i L(A

)i L

(A)

V o(V

)V o

(V)


50


UPM


t1 t2 t1 t2

094 096 098 1 102 104 106 108 11

x 10-4

14

16

18

2

22

24

26

28

3

32

094 096 098 1 102 104 106 108 11

x 10-4

0

1

2

3

4

5092 094 096 098 1 102 104 106 108 11 112

x 10-4

14

16

18

2

22

24

26

28

3

32

092 094 096 098 1 102 104 106 108 11 112

x 10-4

0

05

1

15

2

25

3

35

4

45

Transient





Beware


UPM

ΔIo

iL

Io

vo

ic 0 ATrip point 1

Trip point 2

ΔIo

ic





51


UPM


05358z02236z07417)(z3767G(z) 2 +sdotminus

+sdot=

B G(s)

G(z)




N = 4

ESR = 125 mΩ

( )CL

1sRESRL1s

CL1)1sCESR(V

)s(Gdv

L2

ino

sdot+sdot+sdot+


==

~ VinmiddotdCo

ESR

RphaseN LphaseN

Expected by design


DC resistance


model


Beware


UPM


Pole-Zero Map

Real Axis

-1 -08 -06 -04 -02 0 02 04 06 08 1-1

-08

-06

-04

-02

0

02

04

06

08

1

09

0807060504

03

02

01

26e5

234e5

208e5

182e5

156e513e5

104e5

781e4

521e4

26e4

26e5

234e5

208e5

182e5

156e513e5

104e5

781e4

521e4

26e4

x

x

x




Duty cycle

30 micros


1z00372)z(Rminus

=

1zK)z(R 1

minus=

Controller delay

05358z02236z07417)(z3767G(z) 2 +sdotminus

+sdot=Converter

x

x

x Duty cycle

Output voltage

52


UPM

10 micros


xx

x

x

x

x

x

x




00775)(z1)(z037)(z00378R(z)

minussdotminus+sdot

=

Duty cycle

Output voltage


UPM


75 micros

xx

x

x

x

xx

x



minussdotminus+sdot

=

53


UPM


Duty

a1 = -0922548 b1 = 0037759b2 = 0051742a2 = 0

b1

b2

δ-1

δ-1

δ-1

a1

a2

Error

bn0

No b0

δ-1

Z-1

+

00775)(z1)(z037)(z00378R(z)

minussdotminus+sdot

=




UPM


z2d_m ( tf ([00378 0013986] [1 -10775 00775] 192e-6) )




=Tsample = Tsw

⎪⎩

⎪⎨⎧

rarrδ

+=δ δδ

s


54


UPM


Reference

Switched model

7 bits

8 bits

Not quantizied


PWM

ADC

111






UPM

Reference


PWM

ADC






hellip

222

55


UPM



a1 = -0922548 b1 = 0037759b2 = 0051742a2 = 0

b1

b2

δ-1

δ-1

δ-1

a1

a2

Error

bn0

No b0


UPM


0lt Duty cycle lt1


Hardware adders






Beware

56


UPM

0 1 2 30

05

1

15

2

25








UPM



0 1 2 3

x 10-4

0

05

1

15

2

25

100 usdiv100 usdiv



57


UPM






UPM




58


UPM


13 14 15 16 17 18 19

x 10-4

12

14

16

18

2

22

08 V drop

10 microsdiv

2 V





UPM



Vo

1 V

2 V



11 A11 A

20 mV

520 kHz



59


UPM


Vo

Io

200 mV







UPM


Vo

1 V

2 V





60


UPM





Beware



UPM



13


UPM



Beware




sum minusminus +=k



Driver examples





VSW

VGS

ton toff

Powerconv


+

-



UPM




zbb

zaa)z(R 110

110

++++

= minus

minus

ai bi constants









Powerconv


+

-


14


UPM

zoh

foh

matched

NA

tustin

Matlab C2D




First order hold

Polezero match



Two possibilities









UPM







Two mains reasons






15


UPM








UPM





)z(G)z(R1)z(G)z(R

)z(X)z(Y)z(M

+==

))z(M1)(z(G)z(M)z(R

minus=





Beware


+ Y(z)

_

E(z)X(z)R(z) G(z)

16


UPM





k

kk



=

⎪⎭

⎪⎬⎫

⎪⎩

⎪⎨⎧

minusminus=

minus=minusrArr

minusminus

=minusminus

minusminus


z1)z(M1)z(E

11

11








UPM


10

p1=e-σmiddotejθ


θ

γe-σ




=sR


minus= eMp



17


UPM


xx

xx

OO






96730middot29412239middot6229)(


2

7211

8

+minus+

=

+++

= minusminus

minus

zzzzG

ssssG


condition)



UPM




Vout

Duty

Near unstable



18


UPM



1z110)z(R 5

minus= minus

Vout

Duty







UPM




+= minus

Vout

Duty




19


UPM


Vout

Duty





23

+minusminus+minus




UPM


xk xk-1

hellip

xk-m

X

b0

X

b1

X

bm

hellip

+

+

hellip

+

yk yk-1

hellip

yk-n

X

a1

X

an

+

+

hellip

hellip

+

-yk

nn

22

110

mm

22

110

zazazaazbzbzbb

)z(e)z(d)z(R

minusminusminus

minusminusminus

sdot++sdot+sdot+





20


UPM

Z-1

a1

a2

Z-1


Z-1

bo

eK

Z-1

b1

b2

R1(z) R2(z)YK

dK

eK

R1 R2

Z-1

Z-1

a1

bo

b1

dKeK






UPM

Difference equation


a1a2

e(z)

⎩⎨⎧

rarrδ

+=δminus=δ= δδ+


TXXXmiddotY kkkk1k

kk

Tz1 1minusminus

=δ

k1

1k

1k Y

z1zTYXminus

minusminus

minus

sdot=δ=

δ-1 δ-1

aman

δ-1 δ-1

bm

+

bo

b1

u(z)h(z)

T Z-1

δ-1

(Integral)

+




More adders

21


UPM

a1

a2

δ-1

bo

b1T

b2T2 δ-1 T2

T


Tn Tn


Z-1

+



Adapted δ-1


UPM








ek-1 isrequested

ek-1 isavailable

dk isimposed

T

22


UPM

0 1 2 3 4 5 6 7 8

x 10 -4

-04

-02

0

02

04

06

08

1

12

14

16




vo

48 5 52 54 56 58

10-4

138

14

142

144

146

148

15

152

154

156

vo

Matlabfixed-point

toolbox






UPM



00011111b0 =


Meanerror

22 143143 5252

11 333333 170170

44 3232 0606

33 6767 1717


615615 105ns105ns

12481248 168ns168ns

Mp ts

Example

160160 012ms012ms

113113 011ms011ms1


zz

( )1

222 353


zz


00101000b0 = k53

k5


00101001b0 = k853

k8

k5


222

333



00100000b0 = k3 e2 sdotminus111


1rsquos

23


UPM





D QEN

new_cycle Xek

b0

D QEN

new_cycle Xek-1

b1

+

D QEN

new_cycle Xdk-1

a1

D QEN

new_cycle Xdk-2

b2

+ D QENnew_cycle

dk

+


D Q

D Q

D Q

D Q

D Q

D Q






UPM

Fixed-point toolbox







MatlabSimulink



24


UPM

VHDL or VHDL-AMS











UPM


Applications333



323322

333333

25


UPM


IinVin

Vout

DCDCREGULATOR LO

AD

~

IoutIin


Vout

+_Vin

CONTROL

d

R1

R2

R3

R4

n1 n2LINE

LOAD

Main Switch

Vin

Iin Vout

PO=50Wf=50kHz


PO=50Wf=50kHz



UPM





Adaptive control


LOA

D

~

IoutIin

PFC CONVERTERVout

+_Vin

Controlblock

Controlblock

onoff

R1

R2

R3

R4

Vout

Iin

Vin

ADCADC

ADC

26


UPM


X


IIN-ref

Protections


VOUT max

IIN max

ldquodrdquo max

ldquoΔdrdquo max

ON-OFF Main Switch

ON-OFF Main Switch





intΣIin

gt

CalculatedOn-Off


Max






VOUT-ref

GinPI


UPM










VinGin

Multiplier

xVin

Gin(1Rin)

50 kHz



Adder

+Iin

ΣIin

Comparator

gtOnOff

20 MHz

NoPWMNoPWM


27


UPM




10 W 30 W 50 W 30 W 10 W

Vout

IinGin

StableStable

Load


Unstable

Unstable

Unstable

Unstable


UPM




Adaptive control

28


UPM



Load Change

Vout

Iin




T



UPM

Vin_dc

Iin_dc

d

Vout


OnOff

FPGAXilinx

XC4010-e

8 8 12

Vin Vout Iin

PROMXC 17512

ADC0808

ADC0808

HI 5805


ADCsADCs

Power Converter

Vout Vin_acIin_ac

PF = 099PF = 099PF = 099

29


UPM


DigitalController


switches)Digital


Measuredamp State


Analog

ADConverter

MeasuredVariables

(digital buses)

Mixed




UPM


M1

C Vout

D11n

+

_Vin

Iin

IL1

RL

IR

ON

L1OFF

M1

C Vout

D11n

+

_Vin

Iin

IL1

RL

IR

OFF

L1ON

Vout

n

ID1 = IL1 n

IC



1

kin1k1Lk1L

1L1in L

tVII

dtdILV

Δsdot+=rArr= minus

CtI

VVdt

dVCI kR1koutkout

outR


1

1kout1k1Lk1L

1L1

out

LntV

IIdt

dILnV

sdotΔsdot


minus

C

tIn

I

VVdt

dVCInI kR

1k1L

1koutkoutout

R1L

Δsdot⎟⎟⎠

⎞⎜⎜⎝

⎛minus

+=rArr=minus

minus

minus



30


UPM


VHDLVHDLVHDL

VHDL-AMS

VHDLVHDL--AMSAMS






UPM




VHDLVHDL








Simulationtime


CPU time using VHDL

models


modelsmodels



VHDL speed VHDL-AMS

speed


speedspeed

10 ms10 10 msms 69 s69 s69 s 446 s446 s446 s 641641641

100 ms100 100 msms 700 s700 s700 s 6912 s6912 s6912 s 987987987

1000 ms1000 1000 msms 6890 s6890 s6890 s 68443 s68443 s68443 s 993993993

VHDLVHDL--AMSAMS

31


UPM

42V 14V

CC

CC 42V 14V


system vehicles


Q1-1

Q2-1

Q16-1

Q16-2

Q2-2

Q1-2

L

L

L

COCIN




UPM


Q1-1

Q2-1

Q16-1

Q16-2

Q2-2

Q1-2

L

L

L

COCIN








3 prototypes


3 prototypes



32


UPM


VoVIN

L2d2

d1L1




VINd1

Battery

R1

R2

+

+ +

VINd2

1

BAT1IN1 R

VdVI minus=

2

22 R

VdVI BATIN -=


UPM







446

416

03360

03528

320

2336



1 5

CCM ndash 1000W

824

184

Not acceptable


Q1-1

Q2-1

Q16-1

Q16-2

Q2-2

Q1-2

L

L

L

33


UPM

AVGLI AVGLI


dT T

LVV OIN minus

LVOminus

AVGLI

dT T

LVV OIN minus

LVOminus

AVGLI

⎟⎟⎠

⎞⎜⎜⎝

⎛ minus=

O

OIN

i

2iIN

i VVV

fL2dVI



AVGLI AVGLI

DCMDCM


UPM


03360

03528






416

824



1 5

CCM ndash 1000W

0262002623

0275102649


1 5

DCM ndash 1000W

Not acceptable

445

490

446

454

110102

Very good


34


UPM



420 97

435 100

440 101

435 -

DC Current(A)

429 99

428 98

446 103

460 106

Deviation()

Phase 2

Phase 3

Phase 4

Phase 5

Phase 6

Phase 7

Phase 8

Average

CCM


IO=35A




UPM


ADCInterface

ampfilter

Regulator8

d1


Vout

ADCcontrol

Reset

Vin

12

MCDgenerator

12

Vout

12

Vin

Phase-shifter

8

d2

Protections

1616

Clock

16

H-Pulses L-Pulses




35


UPM




422 97

438 101

442 102

434 -

DC Current(A)

431 99

445 102

424 98

448 103

Deviation()

Phase 2Phase 2

Phase 3Phase 3

Phase 4Phase 4

Phase 5Phase 5

Phase 6Phase 6

Phase 7Phase 7

Phase 8Phase 8

AverageAverage

DCMDCM


IO=17A

IO=27A


UPM





36


UPM


-05

0

05

1

15

2

00E+00 50E-06 10E-05 15E-05 20E-05 25E-05t (s)

()

-05

0

05

1

15

2

00E+00 50E-06 10E-05 15E-05 20E-05 25E-05t (s)

()

0

20

40

60

80

100

120

140

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35

Phase number

[+6-8]

0

20

40

60

80

100

120

140

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35

Phase number

[+6-8]

Half load(500W)


Full load(1000W)

0

1

2

3

4

p

0 5μs 10μs 15μs 20μs0

1

2

3

4

p



0

20

40

60

80

100

120

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35

Phase number

+10-75

0

20

40

60

80

100

120

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35

Phase number

+10-75



UPM

Output currentDC AC

11App

70ADC


is

0 01 02 03 04 05 06 07 08 09 100102030405

060708091

Duty cycle (d)

Nor

m c

urre

nt r

ippl

e Dutyvariation

2 phases

3 phases



37


UPM

10

5

5

10

3T0 x

5

5

3T0 x

Ideal case






10

5

5

10

3T0 x

5

5

3T0 x

Non-ideal



10

5

5

10

3T0 x

5

5

3T0 x

Worse case



10

5

5

10

3T0 x

5

5

3T0 x





UPM

ΔIP-P= 40A (5Adiv)

1 phase

ΔIP-P= 12A (5Adiv)

2 phases

ΔIP-P= 5A (5Adiv)

4 phases

ΔIP-P= 22A (1Adiv)

8 phases

ΔIP-P= 16A (1Adiv)

16 phases



38


UPM

(a)

30

31

22 40

37

22 33

2830

31

22 40

37

22 33

28

(a)

Center of mass

(a)

30

31

22 40

37

22 33

2830

31

22 40

37

22 33

28

(a)

Center of mass

Phase1Phase

2

Phase3

Phase4

Phase5

Phase6

Phase7

Phase8

1st

2nd

3rd 4th

6th

5th 8th

7th

(b)

1st

2nd

3rd 4th

6th

5th 8th

7th

1st

2nd

3rd 4th

6th

5th 8th

7th

(b)

40 A

37 A30 A

33 A

22 A 28 A

31 A

22 A






UPM

18 0 18

18

18

OVERALL 67A

18 0 18

18

18

1

2

34

56

7

8

9

10

1112 13

14

15

16

MAX

MIN

18 0 18

18

18

OVERALL 05A

18 0 18

18

18

1

2

34

56

7

8

9

10

1112 13

1415

16

MAX

MIN


16151413121110987654321

Phase number

165155177152140144148128147122154158139149142133

Current ripple (A)

39


UPM

ΔIP-P= 40A

ΔIP-P= 40A

ΔIP-P= 07A

ΔIP-P= 16A

57

ΔIP-P= 11A

ΔIP-P= 22A

50

ΔIP-P= 28A

ΔIP-P= 5A

44

ΔIP-P= 11A

ΔIP-P= 12A

9






1 2 4 8 16



UPM


Tswitch

delay

Load

voutvin



COUNTERDUTY CYCLE

DRIVING SIGNAL

Load

voutvin



40


UPM



Dri

vin

gsi

gnal

s

Counter

+ hellip +


Duty cycle





UPM


Dri

vin

gD

rivi

ng

sign

als

sign

als



ltDuty cycle


Shift Register



Counter


41


UPM






ASIC

12 12 phasesphases

6 6 phasesphases

24 24 phasesphases





0

2000

4000

6000

8000

10000

12000

14000

16000

2 4 6 8 12 16 20 24

0

2000

4000

6000

8000

10000

12000

2 4 6 8 12 16 20 24

0

2000

4000

6000

8000

10000

12000

14000

16000

18000

2 4 6 8 12 16 20 24


Res

ol 1

28Res

ol 2

56Res

ol 5

12

FPGA

Equ

ival

ent

gate

s

Phases

0

200

400

600

800

1000

2 4 6 8 12 16 20 24


Res

ol 1

28Res

ol 2

56Res

ol 5

120

200

400

600

800

1000

1200

2 4 6 8 12 16 20 24

0

200

400

600

800

1000

1200

1400

2 4 6 8 12 16 20 24

ASIC

Equ

ival

ent

gate

s

Phases


UPM


0

10

20

30

40

50

0 20 40 60 80



0

10

20

30

40

50

0 20 40 60 80



Iout

Pow

erlo

sses

(W)

80

84

88

92

96

0 10 20 30 40 50 60 70 80

6 phases

8 phases12 phases

16 phases

4 phases



Iout

Effic

ienc

y(

)

80

84

88

92

96

0 10 20 30 40 50 60 70 80

6 phases

8 phases12 phases

16 phases

4 phases



Iout

Effic

ienc

y(

)



42


UPM





UPM


RFAmp

Pow

erSt

age

Control

iRF

vs

VS

variable VS


24V

9Vfmax=35kHz

Input voltage = 28V





43


UPM


Cs

M1

L

M2

Cs

M1

L

M2

Cs

M1

L

M2

Cs

M1

L

M2

Ve Vout

CAR

GA




UPM


SW

CLK

ff Resolution =

Pipeline

fCLK

f = 25MHz f = 45MHz

Resolution required



fselected = 32MHz


44


UPM

33 33 DitherDither

SW

CLK

ff Resolution gt

d = 42

d =43

d =425

T=2TSW=8μs

Output voltage

2 solutions

V=50mV

TSW=4μs 1 solution

T=4μs

Output voltage

V=25mV

SW

CLKNVirtual



Average duty cycle

It gives 1 more bit


UPM



SimulatedSimulated

MeasuredMeasured



)(

4110780250 22




45


UPM






UPM


f = 200Hz f = 15kHz

f = 3kHz f = 5kHz

46


UPM





UPM



2 2 micromicross

Vo

1 V

2 V

VRM for DVS5 V

Io = 20 A max

1V - 2 V

Io

02 V max02 V max

0 A

20 A

500 Amicros

Vo




47


UPM


10-1 100 101

100

L-C diagram

C2 micros

200 mV

20A




C = 35 C = 35 μμFF



UPM






fsw = 520 kHz

(125 mΩ eq Rds_on)





48


UPM


0

1

To drivers

New vref

vo dig

N-phases_tran

N-phases

New vref

vo dig

New vref

vo dig


ic


NON-LINEAR CONTROL





UPM


vref

vo

0

1

To drivers

clk_sample

clk_sample

ADC

N-phases_tran

N-phases

vo dig

LINEAR CONTROL



49


UPM


vref

vo

0

1

To drivers

New vref

vo dig

clk_sample

clk_sample

ADC

N-phases_tran

N-phases

vo dig

New vref

LINEAR CONTROL

NON-LINEAR CONTROL

vo dig

New vrefvo dig


ic



Beware


UPM


UpUp--stepstep

ConverterFPGA

tt11



DownDown--stepstep

t1 t2 t1 t2

ddnn

tt22vref

500 kHz

LUT


05

1

15

2

25

0 02 04 06 08 1 12 14 16 18-10

0

10

20

30

40

50

ton toff

Tmin

05

1

15

2

25

0 02 04 06 08 1 12 14 16 18-10

0

10

20

30

40

50

ton toff

Tmin

i L(A

)i L

(A)

V o(V

)V o

(V)


50


UPM


t1 t2 t1 t2

094 096 098 1 102 104 106 108 11

x 10-4

14

16

18

2

22

24

26

28

3

32

094 096 098 1 102 104 106 108 11

x 10-4

0

1

2

3

4

5092 094 096 098 1 102 104 106 108 11 112

x 10-4

14

16

18

2

22

24

26

28

3

32

092 094 096 098 1 102 104 106 108 11 112

x 10-4

0

05

1

15

2

25

3

35

4

45

Transient





Beware


UPM

ΔIo

iL

Io

vo

ic 0 ATrip point 1

Trip point 2

ΔIo

ic





51


UPM


05358z02236z07417)(z3767G(z) 2 +sdotminus

+sdot=

B G(s)

G(z)




N = 4

ESR = 125 mΩ

( )CL

1sRESRL1s

CL1)1sCESR(V

)s(Gdv

L2

ino

sdot+sdot+sdot+


==

~ VinmiddotdCo

ESR

RphaseN LphaseN

Expected by design


DC resistance


model


Beware


UPM


Pole-Zero Map

Real Axis

-1 -08 -06 -04 -02 0 02 04 06 08 1-1

-08

-06

-04

-02

0

02

04

06

08

1

09

0807060504

03

02

01

26e5

234e5

208e5

182e5

156e513e5

104e5

781e4

521e4

26e4

26e5

234e5

208e5

182e5

156e513e5

104e5

781e4

521e4

26e4

x

x

x




Duty cycle

30 micros


1z00372)z(Rminus

=

1zK)z(R 1

minus=

Controller delay

05358z02236z07417)(z3767G(z) 2 +sdotminus

+sdot=Converter

x

x

x Duty cycle

Output voltage

52


UPM

10 micros


xx

x

x

x

x

x

x




00775)(z1)(z037)(z00378R(z)

minussdotminus+sdot

=

Duty cycle

Output voltage


UPM


75 micros

xx

x

x

x

xx

x



minussdotminus+sdot

=

53


UPM


Duty

a1 = -0922548 b1 = 0037759b2 = 0051742a2 = 0

b1

b2

δ-1

δ-1

δ-1

a1

a2

Error

bn0

No b0

δ-1

Z-1

+

00775)(z1)(z037)(z00378R(z)

minussdotminus+sdot

=




UPM


z2d_m ( tf ([00378 0013986] [1 -10775 00775] 192e-6) )




=Tsample = Tsw

⎪⎩

⎪⎨⎧

rarrδ

+=δ δδ

s


54


UPM


Reference

Switched model

7 bits

8 bits

Not quantizied


PWM

ADC

111






UPM

Reference


PWM

ADC






hellip

222

55


UPM



a1 = -0922548 b1 = 0037759b2 = 0051742a2 = 0

b1

b2

δ-1

δ-1

δ-1

a1

a2

Error

bn0

No b0


UPM


0lt Duty cycle lt1


Hardware adders






Beware

56


UPM

0 1 2 30

05

1

15

2

25








UPM



0 1 2 3

x 10-4

0

05

1

15

2

25

100 usdiv100 usdiv



57


UPM






UPM




58


UPM


13 14 15 16 17 18 19

x 10-4

12

14

16

18

2

22

08 V drop

10 microsdiv

2 V





UPM



Vo

1 V

2 V



11 A11 A

20 mV

520 kHz



59


UPM


Vo

Io

200 mV







UPM


Vo

1 V

2 V





60


UPM





Beware



UPM



14


UPM

zoh

foh

matched

NA

tustin

Matlab C2D




First order hold

Polezero match



Two possibilities









UPM







Two mains reasons






15


UPM








UPM





)z(G)z(R1)z(G)z(R

)z(X)z(Y)z(M

+==

))z(M1)(z(G)z(M)z(R

minus=





Beware


+ Y(z)

_

E(z)X(z)R(z) G(z)

16


UPM





k

kk



=

⎪⎭

⎪⎬⎫

⎪⎩

⎪⎨⎧

minusminus=

minus=minusrArr

minusminus

=minusminus

minusminus


z1)z(M1)z(E

11

11








UPM


10

p1=e-σmiddotejθ


θ

γe-σ




=sR


minus= eMp



17


UPM


xx

xx

OO






96730middot29412239middot6229)(


2

7211

8

+minus+

=

+++

= minusminus

minus

zzzzG

ssssG


condition)



UPM




Vout

Duty

Near unstable



18


UPM



1z110)z(R 5

minus= minus

Vout

Duty







UPM




+= minus

Vout

Duty




19


UPM


Vout

Duty





23

+minusminus+minus




UPM


xk xk-1

hellip

xk-m

X

b0

X

b1

X

bm

hellip

+

+

hellip

+

yk yk-1

hellip

yk-n

X

a1

X

an

+

+

hellip

hellip

+

-yk

nn

22

110

mm

22

110

zazazaazbzbzbb

)z(e)z(d)z(R

minusminusminus

minusminusminus

sdot++sdot+sdot+





20


UPM

Z-1

a1

a2

Z-1


Z-1

bo

eK

Z-1

b1

b2

R1(z) R2(z)YK

dK

eK

R1 R2

Z-1

Z-1

a1

bo

b1

dKeK






UPM

Difference equation


a1a2

e(z)

⎩⎨⎧

rarrδ

+=δminus=δ= δδ+


TXXXmiddotY kkkk1k

kk

Tz1 1minusminus

=δ

k1

1k

1k Y

z1zTYXminus

minusminus

minus

sdot=δ=

δ-1 δ-1

aman

δ-1 δ-1

bm

+

bo

b1

u(z)h(z)

T Z-1

δ-1

(Integral)

+




More adders

21


UPM

a1

a2

δ-1

bo

b1T

b2T2 δ-1 T2

T


Tn Tn


Z-1

+



Adapted δ-1


UPM








ek-1 isrequested

ek-1 isavailable

dk isimposed

T

22


UPM

0 1 2 3 4 5 6 7 8

x 10 -4

-04

-02

0

02

04

06

08

1

12

14

16




vo

48 5 52 54 56 58

10-4

138

14

142

144

146

148

15

152

154

156

vo

Matlabfixed-point

toolbox






UPM



00011111b0 =


Meanerror

22 143143 5252

11 333333 170170

44 3232 0606

33 6767 1717


615615 105ns105ns

12481248 168ns168ns

Mp ts

Example

160160 012ms012ms

113113 011ms011ms1


zz

( )1

222 353


zz


00101000b0 = k53

k5


00101001b0 = k853

k8

k5


222

333



00100000b0 = k3 e2 sdotminus111


1rsquos

23


UPM





D QEN

new_cycle Xek

b0

D QEN

new_cycle Xek-1

b1

+

D QEN

new_cycle Xdk-1

a1

D QEN

new_cycle Xdk-2

b2

+ D QENnew_cycle

dk

+


D Q

D Q

D Q

D Q

D Q

D Q






UPM

Fixed-point toolbox







MatlabSimulink



24


UPM

VHDL or VHDL-AMS











UPM


Applications333



323322

333333

25


UPM


IinVin

Vout

DCDCREGULATOR LO

AD

~

IoutIin


Vout

+_Vin

CONTROL

d

R1

R2

R3

R4

n1 n2LINE

LOAD

Main Switch

Vin

Iin Vout

PO=50Wf=50kHz


PO=50Wf=50kHz



UPM





Adaptive control


LOA

D

~

IoutIin

PFC CONVERTERVout

+_Vin

Controlblock

Controlblock

onoff

R1

R2

R3

R4

Vout

Iin

Vin

ADCADC

ADC

26


UPM


X


IIN-ref

Protections


VOUT max

IIN max

ldquodrdquo max

ldquoΔdrdquo max

ON-OFF Main Switch

ON-OFF Main Switch





intΣIin

gt

CalculatedOn-Off


Max






VOUT-ref

GinPI


UPM










VinGin

Multiplier

xVin

Gin(1Rin)

50 kHz



Adder

+Iin

ΣIin

Comparator

gtOnOff

20 MHz

NoPWMNoPWM


27


UPM




10 W 30 W 50 W 30 W 10 W

Vout

IinGin

StableStable

Load


Unstable

Unstable

Unstable

Unstable


UPM




Adaptive control

28


UPM



Load Change

Vout

Iin




T



UPM

Vin_dc

Iin_dc

d

Vout


OnOff

FPGAXilinx

XC4010-e

8 8 12

Vin Vout Iin

PROMXC 17512

ADC0808

ADC0808

HI 5805


ADCsADCs

Power Converter

Vout Vin_acIin_ac

PF = 099PF = 099PF = 099

29


UPM


DigitalController


switches)Digital


Measuredamp State


Analog

ADConverter

MeasuredVariables

(digital buses)

Mixed




UPM


M1

C Vout

D11n

+

_Vin

Iin

IL1

RL

IR

ON

L1OFF

M1

C Vout

D11n

+

_Vin

Iin

IL1

RL

IR

OFF

L1ON

Vout

n

ID1 = IL1 n

IC



1

kin1k1Lk1L

1L1in L

tVII

dtdILV

Δsdot+=rArr= minus

CtI

VVdt

dVCI kR1koutkout

outR


1

1kout1k1Lk1L

1L1

out

LntV

IIdt

dILnV

sdotΔsdot


minus

C

tIn

I

VVdt

dVCInI kR

1k1L

1koutkoutout

R1L

Δsdot⎟⎟⎠

⎞⎜⎜⎝

⎛minus

+=rArr=minus

minus

minus



30


UPM


VHDLVHDLVHDL

VHDL-AMS

VHDLVHDL--AMSAMS






UPM




VHDLVHDL








Simulationtime


CPU time using VHDL

models


modelsmodels



VHDL speed VHDL-AMS

speed


speedspeed

10 ms10 10 msms 69 s69 s69 s 446 s446 s446 s 641641641

100 ms100 100 msms 700 s700 s700 s 6912 s6912 s6912 s 987987987

1000 ms1000 1000 msms 6890 s6890 s6890 s 68443 s68443 s68443 s 993993993

VHDLVHDL--AMSAMS

31


UPM

42V 14V

CC

CC 42V 14V


system vehicles


Q1-1

Q2-1

Q16-1

Q16-2

Q2-2

Q1-2

L

L

L

COCIN




UPM


Q1-1

Q2-1

Q16-1

Q16-2

Q2-2

Q1-2

L

L

L

COCIN








3 prototypes


3 prototypes



32


UPM


VoVIN

L2d2

d1L1




VINd1

Battery

R1

R2

+

+ +

VINd2

1

BAT1IN1 R

VdVI minus=

2

22 R

VdVI BATIN -=


UPM







446

416

03360

03528

320

2336



1 5

CCM ndash 1000W

824

184

Not acceptable


Q1-1

Q2-1

Q16-1

Q16-2

Q2-2

Q1-2

L

L

L

33


UPM

AVGLI AVGLI


dT T

LVV OIN minus

LVOminus

AVGLI

dT T

LVV OIN minus

LVOminus

AVGLI

⎟⎟⎠

⎞⎜⎜⎝

⎛ minus=

O

OIN

i

2iIN

i VVV

fL2dVI



AVGLI AVGLI

DCMDCM


UPM


03360

03528






416

824



1 5

CCM ndash 1000W

0262002623

0275102649


1 5

DCM ndash 1000W

Not acceptable

445

490

446

454

110102

Very good


34


UPM



420 97

435 100

440 101

435 -

DC Current(A)

429 99

428 98

446 103

460 106

Deviation()

Phase 2

Phase 3

Phase 4

Phase 5

Phase 6

Phase 7

Phase 8

Average

CCM


IO=35A




UPM


ADCInterface

ampfilter

Regulator8

d1


Vout

ADCcontrol

Reset

Vin

12

MCDgenerator

12

Vout

12

Vin

Phase-shifter

8

d2

Protections

1616

Clock

16

H-Pulses L-Pulses




35


UPM




422 97

438 101

442 102

434 -

DC Current(A)

431 99

445 102

424 98

448 103

Deviation()

Phase 2Phase 2

Phase 3Phase 3

Phase 4Phase 4

Phase 5Phase 5

Phase 6Phase 6

Phase 7Phase 7

Phase 8Phase 8

AverageAverage

DCMDCM


IO=17A

IO=27A


UPM





36


UPM


-05

0

05

1

15

2

00E+00 50E-06 10E-05 15E-05 20E-05 25E-05t (s)

()

-05

0

05

1

15

2

00E+00 50E-06 10E-05 15E-05 20E-05 25E-05t (s)

()

0

20

40

60

80

100

120

140

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35

Phase number

[+6-8]

0

20

40

60

80

100

120

140

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35

Phase number

[+6-8]

Half load(500W)


Full load(1000W)

0

1

2

3

4

p

0 5μs 10μs 15μs 20μs0

1

2

3

4

p



0

20

40

60

80

100

120

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35

Phase number

+10-75

0

20

40

60

80

100

120

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35

Phase number

+10-75



UPM

Output currentDC AC

11App

70ADC


is

0 01 02 03 04 05 06 07 08 09 100102030405

060708091

Duty cycle (d)

Nor

m c

urre

nt r

ippl

e Dutyvariation

2 phases

3 phases



37


UPM

10

5

5

10

3T0 x

5

5

3T0 x

Ideal case






10

5

5

10

3T0 x

5

5

3T0 x

Non-ideal



10

5

5

10

3T0 x

5

5

3T0 x

Worse case



10

5

5

10

3T0 x

5

5

3T0 x





UPM

ΔIP-P= 40A (5Adiv)

1 phase

ΔIP-P= 12A (5Adiv)

2 phases

ΔIP-P= 5A (5Adiv)

4 phases

ΔIP-P= 22A (1Adiv)

8 phases

ΔIP-P= 16A (1Adiv)

16 phases



38


UPM

(a)

30

31

22 40

37

22 33

2830

31

22 40

37

22 33

28

(a)

Center of mass

(a)

30

31

22 40

37

22 33

2830

31

22 40

37

22 33

28

(a)

Center of mass

Phase1Phase

2

Phase3

Phase4

Phase5

Phase6

Phase7

Phase8

1st

2nd

3rd 4th

6th

5th 8th

7th

(b)

1st

2nd

3rd 4th

6th

5th 8th

7th

1st

2nd

3rd 4th

6th

5th 8th

7th

(b)

40 A

37 A30 A

33 A

22 A 28 A

31 A

22 A






UPM

18 0 18

18

18

OVERALL 67A

18 0 18

18

18

1

2

34

56

7

8

9

10

1112 13

14

15

16

MAX

MIN

18 0 18

18

18

OVERALL 05A

18 0 18

18

18

1

2

34

56

7

8

9

10

1112 13

1415

16

MAX

MIN


16151413121110987654321

Phase number

165155177152140144148128147122154158139149142133

Current ripple (A)

39


UPM

ΔIP-P= 40A

ΔIP-P= 40A

ΔIP-P= 07A

ΔIP-P= 16A

57

ΔIP-P= 11A

ΔIP-P= 22A

50

ΔIP-P= 28A

ΔIP-P= 5A

44

ΔIP-P= 11A

ΔIP-P= 12A

9






1 2 4 8 16



UPM


Tswitch

delay

Load

voutvin



COUNTERDUTY CYCLE

DRIVING SIGNAL

Load

voutvin



40


UPM



Dri

vin

gsi

gnal

s

Counter

+ hellip +


Duty cycle





UPM


Dri

vin

gD

rivi

ng

sign

als

sign

als



ltDuty cycle


Shift Register



Counter


41


UPM






ASIC

12 12 phasesphases

6 6 phasesphases

24 24 phasesphases





0

2000

4000

6000

8000

10000

12000

14000

16000

2 4 6 8 12 16 20 24

0

2000

4000

6000

8000

10000

12000

2 4 6 8 12 16 20 24

0

2000

4000

6000

8000

10000

12000

14000

16000

18000

2 4 6 8 12 16 20 24


Res

ol 1

28Res

ol 2

56Res

ol 5

12

FPGA

Equ

ival

ent

gate

s

Phases

0

200

400

600

800

1000

2 4 6 8 12 16 20 24


Res

ol 1

28Res

ol 2

56Res

ol 5

120

200

400

600

800

1000

1200

2 4 6 8 12 16 20 24

0

200

400

600

800

1000

1200

1400

2 4 6 8 12 16 20 24

ASIC

Equ

ival

ent

gate

s

Phases


UPM


0

10

20

30

40

50

0 20 40 60 80



0

10

20

30

40

50

0 20 40 60 80



Iout

Pow

erlo

sses

(W)

80

84

88

92

96

0 10 20 30 40 50 60 70 80

6 phases

8 phases12 phases

16 phases

4 phases



Iout

Effic

ienc

y(

)

80

84

88

92

96

0 10 20 30 40 50 60 70 80

6 phases

8 phases12 phases

16 phases

4 phases



Iout

Effic

ienc

y(

)



42


UPM





UPM


RFAmp

Pow

erSt

age

Control

iRF

vs

VS

variable VS


24V

9Vfmax=35kHz

Input voltage = 28V





43


UPM


Cs

M1

L

M2

Cs

M1

L

M2

Cs

M1

L

M2

Cs

M1

L

M2

Ve Vout

CAR

GA




UPM


SW

CLK

ff Resolution =

Pipeline

fCLK

f = 25MHz f = 45MHz

Resolution required



fselected = 32MHz


44


UPM

33 33 DitherDither

SW

CLK

ff Resolution gt

d = 42

d =43

d =425

T=2TSW=8μs

Output voltage

2 solutions

V=50mV

TSW=4μs 1 solution

T=4μs

Output voltage

V=25mV

SW

CLKNVirtual



Average duty cycle

It gives 1 more bit


UPM



SimulatedSimulated

MeasuredMeasured



)(

4110780250 22




45


UPM






UPM


f = 200Hz f = 15kHz

f = 3kHz f = 5kHz

46


UPM





UPM



2 2 micromicross

Vo

1 V

2 V

VRM for DVS5 V

Io = 20 A max

1V - 2 V

Io

02 V max02 V max

0 A

20 A

500 Amicros

Vo




47


UPM


10-1 100 101

100

L-C diagram

C2 micros

200 mV

20A




C = 35 C = 35 μμFF



UPM






fsw = 520 kHz

(125 mΩ eq Rds_on)





48


UPM


0

1

To drivers

New vref

vo dig

N-phases_tran

N-phases

New vref

vo dig

New vref

vo dig


ic


NON-LINEAR CONTROL





UPM


vref

vo

0

1

To drivers

clk_sample

clk_sample

ADC

N-phases_tran

N-phases

vo dig

LINEAR CONTROL



49


UPM


vref

vo

0

1

To drivers

New vref

vo dig

clk_sample

clk_sample

ADC

N-phases_tran

N-phases

vo dig

New vref

LINEAR CONTROL

NON-LINEAR CONTROL

vo dig

New vrefvo dig


ic



Beware


UPM


UpUp--stepstep

ConverterFPGA

tt11



DownDown--stepstep

t1 t2 t1 t2

ddnn

tt22vref

500 kHz

LUT


05

1

15

2

25

0 02 04 06 08 1 12 14 16 18-10

0

10

20

30

40

50

ton toff

Tmin

05

1

15

2

25

0 02 04 06 08 1 12 14 16 18-10

0

10

20

30

40

50

ton toff

Tmin

i L(A

)i L

(A)

V o(V

)V o

(V)


50


UPM


t1 t2 t1 t2

094 096 098 1 102 104 106 108 11

x 10-4

14

16

18

2

22

24

26

28

3

32

094 096 098 1 102 104 106 108 11

x 10-4

0

1

2

3

4

5092 094 096 098 1 102 104 106 108 11 112

x 10-4

14

16

18

2

22

24

26

28

3

32

092 094 096 098 1 102 104 106 108 11 112

x 10-4

0

05

1

15

2

25

3

35

4

45

Transient





Beware


UPM

ΔIo

iL

Io

vo

ic 0 ATrip point 1

Trip point 2

ΔIo

ic





51


UPM


05358z02236z07417)(z3767G(z) 2 +sdotminus

+sdot=

B G(s)

G(z)




N = 4

ESR = 125 mΩ

( )CL

1sRESRL1s

CL1)1sCESR(V

)s(Gdv

L2

ino

sdot+sdot+sdot+


==

~ VinmiddotdCo

ESR

RphaseN LphaseN

Expected by design


DC resistance


model


Beware


UPM


Pole-Zero Map

Real Axis

-1 -08 -06 -04 -02 0 02 04 06 08 1-1

-08

-06

-04

-02

0

02

04

06

08

1

09

0807060504

03

02

01

26e5

234e5

208e5

182e5

156e513e5

104e5

781e4

521e4

26e4

26e5

234e5

208e5

182e5

156e513e5

104e5

781e4

521e4

26e4

x

x

x




Duty cycle

30 micros


1z00372)z(Rminus

=

1zK)z(R 1

minus=

Controller delay

05358z02236z07417)(z3767G(z) 2 +sdotminus

+sdot=Converter

x

x

x Duty cycle

Output voltage

52


UPM

10 micros


xx

x

x

x

x

x

x




00775)(z1)(z037)(z00378R(z)

minussdotminus+sdot

=

Duty cycle

Output voltage


UPM


75 micros

xx

x

x

x

xx

x



minussdotminus+sdot

=

53


UPM


Duty

a1 = -0922548 b1 = 0037759b2 = 0051742a2 = 0

b1

b2

δ-1

δ-1

δ-1

a1

a2

Error

bn0

No b0

δ-1

Z-1

+

00775)(z1)(z037)(z00378R(z)

minussdotminus+sdot

=




UPM


z2d_m ( tf ([00378 0013986] [1 -10775 00775] 192e-6) )




=Tsample = Tsw

⎪⎩

⎪⎨⎧

rarrδ

+=δ δδ

s


54


UPM


Reference

Switched model

7 bits

8 bits

Not quantizied


PWM

ADC

111






UPM

Reference


PWM

ADC






hellip

222

55


UPM



a1 = -0922548 b1 = 0037759b2 = 0051742a2 = 0

b1

b2

δ-1

δ-1

δ-1

a1

a2

Error

bn0

No b0


UPM


0lt Duty cycle lt1


Hardware adders






Beware

56


UPM

0 1 2 30

05

1

15

2

25








UPM



0 1 2 3

x 10-4

0

05

1

15

2

25

100 usdiv100 usdiv



57


UPM






UPM




58


UPM


13 14 15 16 17 18 19

x 10-4

12

14

16

18

2

22

08 V drop

10 microsdiv

2 V





UPM



Vo

1 V

2 V



11 A11 A

20 mV

520 kHz



59


UPM


Vo

Io

200 mV







UPM


Vo

1 V

2 V





60


UPM





Beware



UPM



15


UPM








UPM





)z(G)z(R1)z(G)z(R

)z(X)z(Y)z(M

+==

))z(M1)(z(G)z(M)z(R

minus=





Beware


+ Y(z)

_

E(z)X(z)R(z) G(z)

16


UPM





k

kk



=

⎪⎭

⎪⎬⎫

⎪⎩

⎪⎨⎧

minusminus=

minus=minusrArr

minusminus

=minusminus

minusminus


z1)z(M1)z(E

11

11








UPM


10

p1=e-σmiddotejθ


θ

γe-σ




=sR


minus= eMp



17


UPM


xx

xx

OO






96730middot29412239middot6229)(


2

7211

8

+minus+

=

+++

= minusminus

minus

zzzzG

ssssG


condition)



UPM




Vout

Duty

Near unstable



18


UPM



1z110)z(R 5

minus= minus

Vout

Duty







UPM




+= minus

Vout

Duty




19


UPM


Vout

Duty





23

+minusminus+minus




UPM


xk xk-1

hellip

xk-m

X

b0

X

b1

X

bm

hellip

+

+

hellip

+

yk yk-1

hellip

yk-n

X

a1

X

an

+

+

hellip

hellip

+

-yk

nn

22

110

mm

22

110

zazazaazbzbzbb

)z(e)z(d)z(R

minusminusminus

minusminusminus

sdot++sdot+sdot+





20


UPM

Z-1

a1

a2

Z-1


Z-1

bo

eK

Z-1

b1

b2

R1(z) R2(z)YK

dK

eK

R1 R2

Z-1

Z-1

a1

bo

b1

dKeK






UPM

Difference equation


a1a2

e(z)

⎩⎨⎧

rarrδ

+=δminus=δ= δδ+


TXXXmiddotY kkkk1k

kk

Tz1 1minusminus

=δ

k1

1k

1k Y

z1zTYXminus

minusminus

minus

sdot=δ=

δ-1 δ-1

aman

δ-1 δ-1

bm

+

bo

b1

u(z)h(z)

T Z-1

δ-1

(Integral)

+




More adders

21


UPM

a1

a2

δ-1

bo

b1T

b2T2 δ-1 T2

T


Tn Tn


Z-1

+



Adapted δ-1


UPM








ek-1 isrequested

ek-1 isavailable

dk isimposed

T

22


UPM

0 1 2 3 4 5 6 7 8

x 10 -4

-04

-02

0

02

04

06

08

1

12

14

16




vo

48 5 52 54 56 58

10-4

138

14

142

144

146

148

15

152

154

156

vo

Matlabfixed-point

toolbox






UPM



00011111b0 =


Meanerror

22 143143 5252

11 333333 170170

44 3232 0606

33 6767 1717


615615 105ns105ns

12481248 168ns168ns

Mp ts

Example

160160 012ms012ms

113113 011ms011ms1


zz

( )1

222 353


zz


00101000b0 = k53

k5


00101001b0 = k853

k8

k5


222

333



00100000b0 = k3 e2 sdotminus111


1rsquos

23


UPM





D QEN

new_cycle Xek

b0

D QEN

new_cycle Xek-1

b1

+

D QEN

new_cycle Xdk-1

a1

D QEN

new_cycle Xdk-2

b2

+ D QENnew_cycle

dk

+


D Q

D Q

D Q

D Q

D Q

D Q






UPM

Fixed-point toolbox







MatlabSimulink



24


UPM

VHDL or VHDL-AMS











UPM


Applications333



323322

333333

25


UPM


IinVin

Vout

DCDCREGULATOR LO

AD

~

IoutIin


Vout

+_Vin

CONTROL

d

R1

R2

R3

R4

n1 n2LINE

LOAD

Main Switch

Vin

Iin Vout

PO=50Wf=50kHz


PO=50Wf=50kHz



UPM





Adaptive control


LOA

D

~

IoutIin

PFC CONVERTERVout

+_Vin

Controlblock

Controlblock

onoff

R1

R2

R3

R4

Vout

Iin

Vin

ADCADC

ADC

26


UPM


X


IIN-ref

Protections


VOUT max

IIN max

ldquodrdquo max

ldquoΔdrdquo max

ON-OFF Main Switch

ON-OFF Main Switch





intΣIin

gt

CalculatedOn-Off


Max






VOUT-ref

GinPI


UPM










VinGin

Multiplier

xVin

Gin(1Rin)

50 kHz



Adder

+Iin

ΣIin

Comparator

gtOnOff

20 MHz

NoPWMNoPWM


27


UPM




10 W 30 W 50 W 30 W 10 W

Vout

IinGin

StableStable

Load


Unstable

Unstable

Unstable

Unstable


UPM




Adaptive control

28


UPM



Load Change

Vout

Iin




T



UPM

Vin_dc

Iin_dc

d

Vout


OnOff

FPGAXilinx

XC4010-e

8 8 12

Vin Vout Iin

PROMXC 17512

ADC0808

ADC0808

HI 5805


ADCsADCs

Power Converter

Vout Vin_acIin_ac

PF = 099PF = 099PF = 099

29


UPM


DigitalController


switches)Digital


Measuredamp State


Analog

ADConverter

MeasuredVariables

(digital buses)

Mixed




UPM


M1

C Vout

D11n

+

_Vin

Iin

IL1

RL

IR

ON

L1OFF

M1

C Vout

D11n

+

_Vin

Iin

IL1

RL

IR

OFF

L1ON

Vout

n

ID1 = IL1 n

IC



1

kin1k1Lk1L

1L1in L

tVII

dtdILV

Δsdot+=rArr= minus

CtI

VVdt

dVCI kR1koutkout

outR


1

1kout1k1Lk1L

1L1

out

LntV

IIdt

dILnV

sdotΔsdot


minus

C

tIn

I

VVdt

dVCInI kR

1k1L

1koutkoutout

R1L

Δsdot⎟⎟⎠

⎞⎜⎜⎝

⎛minus

+=rArr=minus

minus

minus



30


UPM


VHDLVHDLVHDL

VHDL-AMS

VHDLVHDL--AMSAMS






UPM




VHDLVHDL








Simulationtime


CPU time using VHDL

models


modelsmodels



VHDL speed VHDL-AMS

speed


speedspeed

10 ms10 10 msms 69 s69 s69 s 446 s446 s446 s 641641641

100 ms100 100 msms 700 s700 s700 s 6912 s6912 s6912 s 987987987

1000 ms1000 1000 msms 6890 s6890 s6890 s 68443 s68443 s68443 s 993993993

VHDLVHDL--AMSAMS

31


UPM

42V 14V

CC

CC 42V 14V


system vehicles


Q1-1

Q2-1

Q16-1

Q16-2

Q2-2

Q1-2

L

L

L

COCIN




UPM


Q1-1

Q2-1

Q16-1

Q16-2

Q2-2

Q1-2

L

L

L

COCIN








3 prototypes


3 prototypes



32


UPM


VoVIN

L2d2

d1L1




VINd1

Battery

R1

R2

+

+ +

VINd2

1

BAT1IN1 R

VdVI minus=

2

22 R

VdVI BATIN -=


UPM







446

416

03360

03528

320

2336



1 5

CCM ndash 1000W

824

184

Not acceptable


Q1-1

Q2-1

Q16-1

Q16-2

Q2-2

Q1-2

L

L

L

33


UPM

AVGLI AVGLI


dT T

LVV OIN minus

LVOminus

AVGLI

dT T

LVV OIN minus

LVOminus

AVGLI

⎟⎟⎠

⎞⎜⎜⎝

⎛ minus=

O

OIN

i

2iIN

i VVV

fL2dVI



AVGLI AVGLI

DCMDCM


UPM


03360

03528






416

824



1 5

CCM ndash 1000W

0262002623

0275102649


1 5

DCM ndash 1000W

Not acceptable

445

490

446

454

110102

Very good


34


UPM



420 97

435 100

440 101

435 -

DC Current(A)

429 99

428 98

446 103

460 106

Deviation()

Phase 2

Phase 3

Phase 4

Phase 5

Phase 6

Phase 7

Phase 8

Average

CCM


IO=35A




UPM


ADCInterface

ampfilter

Regulator8

d1


Vout

ADCcontrol

Reset

Vin

12

MCDgenerator

12

Vout

12

Vin

Phase-shifter

8

d2

Protections

1616

Clock

16

H-Pulses L-Pulses




35


UPM




422 97

438 101

442 102

434 -

DC Current(A)

431 99

445 102

424 98

448 103

Deviation()

Phase 2Phase 2

Phase 3Phase 3

Phase 4Phase 4

Phase 5Phase 5

Phase 6Phase 6

Phase 7Phase 7

Phase 8Phase 8

AverageAverage

DCMDCM


IO=17A

IO=27A


UPM





36


UPM


-05

0

05

1

15

2

00E+00 50E-06 10E-05 15E-05 20E-05 25E-05t (s)

()

-05

0

05

1

15

2

00E+00 50E-06 10E-05 15E-05 20E-05 25E-05t (s)

()

0

20

40

60

80

100

120

140

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35

Phase number

[+6-8]

0

20

40

60

80

100

120

140

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35

Phase number

[+6-8]

Half load(500W)


Full load(1000W)

0

1

2

3

4

p

0 5μs 10μs 15μs 20μs0

1

2

3

4

p



0

20

40

60

80

100

120

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35

Phase number

+10-75

0

20

40

60

80

100

120

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35

Phase number

+10-75



UPM

Output currentDC AC

11App

70ADC


is

0 01 02 03 04 05 06 07 08 09 100102030405

060708091

Duty cycle (d)

Nor

m c

urre

nt r

ippl

e Dutyvariation

2 phases

3 phases



37


UPM

10

5

5

10

3T0 x

5

5

3T0 x

Ideal case






10

5

5

10

3T0 x

5

5

3T0 x

Non-ideal



10

5

5

10

3T0 x

5

5

3T0 x

Worse case



10

5

5

10

3T0 x

5

5

3T0 x





UPM

ΔIP-P= 40A (5Adiv)

1 phase

ΔIP-P= 12A (5Adiv)

2 phases

ΔIP-P= 5A (5Adiv)

4 phases

ΔIP-P= 22A (1Adiv)

8 phases

ΔIP-P= 16A (1Adiv)

16 phases



38


UPM

(a)

30

31

22 40

37

22 33

2830

31

22 40

37

22 33

28

(a)

Center of mass

(a)

30

31

22 40

37

22 33

2830

31

22 40

37

22 33

28

(a)

Center of mass

Phase1Phase

2

Phase3

Phase4

Phase5

Phase6

Phase7

Phase8

1st

2nd

3rd 4th

6th

5th 8th

7th

(b)

1st

2nd

3rd 4th

6th

5th 8th

7th

1st

2nd

3rd 4th

6th

5th 8th

7th

(b)

40 A

37 A30 A

33 A

22 A 28 A

31 A

22 A






UPM

18 0 18

18

18

OVERALL 67A

18 0 18

18

18

1

2

34

56

7

8

9

10

1112 13

14

15

16

MAX

MIN

18 0 18

18

18

OVERALL 05A

18 0 18

18

18

1

2

34

56

7

8

9

10

1112 13

1415

16

MAX

MIN


16151413121110987654321

Phase number

165155177152140144148128147122154158139149142133

Current ripple (A)

39


UPM

ΔIP-P= 40A

ΔIP-P= 40A

ΔIP-P= 07A

ΔIP-P= 16A

57

ΔIP-P= 11A

ΔIP-P= 22A

50

ΔIP-P= 28A

ΔIP-P= 5A

44

ΔIP-P= 11A

ΔIP-P= 12A

9






1 2 4 8 16



UPM


Tswitch

delay

Load

voutvin



COUNTERDUTY CYCLE

DRIVING SIGNAL

Load

voutvin



40


UPM



Dri

vin

gsi

gnal

s

Counter

+ hellip +


Duty cycle





UPM


Dri

vin

gD

rivi

ng

sign

als

sign

als



ltDuty cycle


Shift Register



Counter


41


UPM






ASIC

12 12 phasesphases

6 6 phasesphases

24 24 phasesphases





0

2000

4000

6000

8000

10000

12000

14000

16000

2 4 6 8 12 16 20 24

0

2000

4000

6000

8000

10000

12000

2 4 6 8 12 16 20 24

0

2000

4000

6000

8000

10000

12000

14000

16000

18000

2 4 6 8 12 16 20 24


Res

ol 1

28Res

ol 2

56Res

ol 5

12

FPGA

Equ

ival

ent

gate

s

Phases

0

200

400

600

800

1000

2 4 6 8 12 16 20 24


Res

ol 1

28Res

ol 2

56Res

ol 5

120

200

400

600

800

1000

1200

2 4 6 8 12 16 20 24

0

200

400

600

800

1000

1200

1400

2 4 6 8 12 16 20 24

ASIC

Equ

ival

ent

gate

s

Phases


UPM


0

10

20

30

40

50

0 20 40 60 80



0

10

20

30

40

50

0 20 40 60 80



Iout

Pow

erlo

sses

(W)

80

84

88

92

96

0 10 20 30 40 50 60 70 80

6 phases

8 phases12 phases

16 phases

4 phases



Iout

Effic

ienc

y(

)

80

84

88

92

96

0 10 20 30 40 50 60 70 80

6 phases

8 phases12 phases

16 phases

4 phases



Iout

Effic

ienc

y(

)



42


UPM





UPM


RFAmp

Pow

erSt

age

Control

iRF

vs

VS

variable VS


24V

9Vfmax=35kHz

Input voltage = 28V





43


UPM


Cs

M1

L

M2

Cs

M1

L

M2

Cs

M1

L

M2

Cs

M1

L

M2

Ve Vout

CAR

GA




UPM


SW

CLK

ff Resolution =

Pipeline

fCLK

f = 25MHz f = 45MHz

Resolution required



fselected = 32MHz


44


UPM

33 33 DitherDither

SW

CLK

ff Resolution gt

d = 42

d =43

d =425

T=2TSW=8μs

Output voltage

2 solutions

V=50mV

TSW=4μs 1 solution

T=4μs

Output voltage

V=25mV

SW

CLKNVirtual



Average duty cycle

It gives 1 more bit


UPM



SimulatedSimulated

MeasuredMeasured



)(

4110780250 22




45


UPM






UPM


f = 200Hz f = 15kHz

f = 3kHz f = 5kHz

46


UPM





UPM



2 2 micromicross

Vo

1 V

2 V

VRM for DVS5 V

Io = 20 A max

1V - 2 V

Io

02 V max02 V max

0 A

20 A

500 Amicros

Vo




47


UPM


10-1 100 101

100

L-C diagram

C2 micros

200 mV

20A




C = 35 C = 35 μμFF



UPM






fsw = 520 kHz

(125 mΩ eq Rds_on)





48


UPM


0

1

To drivers

New vref

vo dig

N-phases_tran

N-phases

New vref

vo dig

New vref

vo dig


ic


NON-LINEAR CONTROL





UPM


vref

vo

0

1

To drivers

clk_sample

clk_sample

ADC

N-phases_tran

N-phases

vo dig

LINEAR CONTROL



49


UPM


vref

vo

0

1

To drivers

New vref

vo dig

clk_sample

clk_sample

ADC

N-phases_tran

N-phases

vo dig

New vref

LINEAR CONTROL

NON-LINEAR CONTROL

vo dig

New vrefvo dig


ic



Beware


UPM


UpUp--stepstep

ConverterFPGA

tt11



DownDown--stepstep

t1 t2 t1 t2

ddnn

tt22vref

500 kHz

LUT


05

1

15

2

25

0 02 04 06 08 1 12 14 16 18-10

0

10

20

30

40

50

ton toff

Tmin

05

1

15

2

25

0 02 04 06 08 1 12 14 16 18-10

0

10

20

30

40

50

ton toff

Tmin

i L(A

)i L

(A)

V o(V

)V o

(V)


50


UPM


t1 t2 t1 t2

094 096 098 1 102 104 106 108 11

x 10-4

14

16

18

2

22

24

26

28

3

32

094 096 098 1 102 104 106 108 11

x 10-4

0

1

2

3

4

5092 094 096 098 1 102 104 106 108 11 112

x 10-4

14

16

18

2

22

24

26

28

3

32

092 094 096 098 1 102 104 106 108 11 112

x 10-4

0

05

1

15

2

25

3

35

4

45

Transient





Beware


UPM

ΔIo

iL

Io

vo

ic 0 ATrip point 1

Trip point 2

ΔIo

ic





51


UPM


05358z02236z07417)(z3767G(z) 2 +sdotminus

+sdot=

B G(s)

G(z)




N = 4

ESR = 125 mΩ

( )CL

1sRESRL1s

CL1)1sCESR(V

)s(Gdv

L2

ino

sdot+sdot+sdot+


==

~ VinmiddotdCo

ESR

RphaseN LphaseN

Expected by design


DC resistance


model


Beware


UPM


Pole-Zero Map

Real Axis

-1 -08 -06 -04 -02 0 02 04 06 08 1-1

-08

-06

-04

-02

0

02

04

06

08

1

09

0807060504

03

02

01

26e5

234e5

208e5

182e5

156e513e5

104e5

781e4

521e4

26e4

26e5

234e5

208e5

182e5

156e513e5

104e5

781e4

521e4

26e4

x

x

x




Duty cycle

30 micros


1z00372)z(Rminus

=

1zK)z(R 1

minus=

Controller delay

05358z02236z07417)(z3767G(z) 2 +sdotminus

+sdot=Converter

x

x

x Duty cycle

Output voltage

52


UPM

10 micros


xx

x

x

x

x

x

x




00775)(z1)(z037)(z00378R(z)

minussdotminus+sdot

=

Duty cycle

Output voltage


UPM


75 micros

xx

x

x

x

xx

x



minussdotminus+sdot

=

53


UPM


Duty

a1 = -0922548 b1 = 0037759b2 = 0051742a2 = 0

b1

b2

δ-1

δ-1

δ-1

a1

a2

Error

bn0

No b0

δ-1

Z-1

+

00775)(z1)(z037)(z00378R(z)

minussdotminus+sdot

=




UPM


z2d_m ( tf ([00378 0013986] [1 -10775 00775] 192e-6) )




=Tsample = Tsw

⎪⎩

⎪⎨⎧

rarrδ

+=δ δδ

s


54


UPM


Reference

Switched model

7 bits

8 bits

Not quantizied


PWM

ADC

111






UPM

Reference


PWM

ADC






hellip

222

55


UPM



a1 = -0922548 b1 = 0037759b2 = 0051742a2 = 0

b1

b2

δ-1

δ-1

δ-1

a1

a2

Error

bn0

No b0


UPM


0lt Duty cycle lt1


Hardware adders






Beware

56


UPM

0 1 2 30

05

1

15

2

25








UPM



0 1 2 3

x 10-4

0

05

1

15

2

25

100 usdiv100 usdiv



57


UPM






UPM




58


UPM


13 14 15 16 17 18 19

x 10-4

12

14

16

18

2

22

08 V drop

10 microsdiv

2 V





UPM



Vo

1 V

2 V



11 A11 A

20 mV

520 kHz



59


UPM


Vo

Io

200 mV







UPM


Vo

1 V

2 V





60


UPM





Beware



UPM



16


UPM





k

kk



=

⎪⎭

⎪⎬⎫

⎪⎩

⎪⎨⎧

minusminus=

minus=minusrArr

minusminus

=minusminus

minusminus


z1)z(M1)z(E

11

11








UPM


10

p1=e-σmiddotejθ


θ

γe-σ




=sR


minus= eMp



17


UPM


xx

xx

OO






96730middot29412239middot6229)(


2

7211

8

+minus+

=

+++

= minusminus

minus

zzzzG

ssssG


condition)



UPM




Vout

Duty

Near unstable



18


UPM



1z110)z(R 5

minus= minus

Vout

Duty







UPM




+= minus

Vout

Duty




19


UPM


Vout

Duty





23

+minusminus+minus




UPM


xk xk-1

hellip

xk-m

X

b0

X

b1

X

bm

hellip

+

+

hellip

+

yk yk-1

hellip

yk-n

X

a1

X

an

+

+

hellip

hellip

+

-yk

nn

22

110

mm

22

110

zazazaazbzbzbb

)z(e)z(d)z(R

minusminusminus

minusminusminus

sdot++sdot+sdot+





20


UPM

Z-1

a1

a2

Z-1


Z-1

bo

eK

Z-1

b1

b2

R1(z) R2(z)YK

dK

eK

R1 R2

Z-1

Z-1

a1

bo

b1

dKeK






UPM

Difference equation


a1a2

e(z)

⎩⎨⎧

rarrδ

+=δminus=δ= δδ+


TXXXmiddotY kkkk1k

kk

Tz1 1minusminus

=δ

k1

1k

1k Y

z1zTYXminus

minusminus

minus

sdot=δ=

δ-1 δ-1

aman

δ-1 δ-1

bm

+

bo

b1

u(z)h(z)

T Z-1

δ-1

(Integral)

+




More adders

21


UPM

a1

a2

δ-1

bo

b1T

b2T2 δ-1 T2

T


Tn Tn


Z-1

+



Adapted δ-1


UPM








ek-1 isrequested

ek-1 isavailable

dk isimposed

T

22


UPM

0 1 2 3 4 5 6 7 8

x 10 -4

-04

-02

0

02

04

06

08

1

12

14

16




vo

48 5 52 54 56 58

10-4

138

14

142

144

146

148

15

152

154

156

vo

Matlabfixed-point

toolbox






UPM



00011111b0 =


Meanerror

22 143143 5252

11 333333 170170

44 3232 0606

33 6767 1717


615615 105ns105ns

12481248 168ns168ns

Mp ts

Example

160160 012ms012ms

113113 011ms011ms1


zz

( )1

222 353


zz


00101000b0 = k53

k5


00101001b0 = k853

k8

k5


222

333



00100000b0 = k3 e2 sdotminus111


1rsquos

23


UPM





D QEN

new_cycle Xek

b0

D QEN

new_cycle Xek-1

b1

+

D QEN

new_cycle Xdk-1

a1

D QEN

new_cycle Xdk-2

b2

+ D QENnew_cycle

dk

+


D Q

D Q

D Q

D Q

D Q

D Q






UPM

Fixed-point toolbox







MatlabSimulink



24


UPM

VHDL or VHDL-AMS











UPM


Applications333



323322

333333

25


UPM


IinVin

Vout

DCDCREGULATOR LO

AD

~

IoutIin


Vout

+_Vin

CONTROL

d

R1

R2

R3

R4

n1 n2LINE

LOAD

Main Switch

Vin

Iin Vout

PO=50Wf=50kHz


PO=50Wf=50kHz



UPM





Adaptive control


LOA

D

~

IoutIin

PFC CONVERTERVout

+_Vin

Controlblock

Controlblock

onoff

R1

R2

R3

R4

Vout

Iin

Vin

ADCADC

ADC

26


UPM


X


IIN-ref

Protections


VOUT max

IIN max

ldquodrdquo max

ldquoΔdrdquo max

ON-OFF Main Switch

ON-OFF Main Switch





intΣIin

gt

CalculatedOn-Off


Max






VOUT-ref

GinPI


UPM










VinGin

Multiplier

xVin

Gin(1Rin)

50 kHz



Adder

+Iin

ΣIin

Comparator

gtOnOff

20 MHz

NoPWMNoPWM


27


UPM




10 W 30 W 50 W 30 W 10 W

Vout

IinGin

StableStable

Load


Unstable

Unstable

Unstable

Unstable


UPM




Adaptive control

28


UPM



Load Change

Vout

Iin




T



UPM

Vin_dc

Iin_dc

d

Vout


OnOff

FPGAXilinx

XC4010-e

8 8 12

Vin Vout Iin

PROMXC 17512

ADC0808

ADC0808

HI 5805


ADCsADCs

Power Converter

Vout Vin_acIin_ac

PF = 099PF = 099PF = 099

29


UPM


DigitalController


switches)Digital


Measuredamp State


Analog

ADConverter

MeasuredVariables

(digital buses)

Mixed




UPM


M1

C Vout

D11n

+

_Vin

Iin

IL1

RL

IR

ON

L1OFF

M1

C Vout

D11n

+

_Vin

Iin

IL1

RL

IR

OFF

L1ON

Vout

n

ID1 = IL1 n

IC



1

kin1k1Lk1L

1L1in L

tVII

dtdILV

Δsdot+=rArr= minus

CtI

VVdt

dVCI kR1koutkout

outR


1

1kout1k1Lk1L

1L1

out

LntV

IIdt

dILnV

sdotΔsdot


minus

C

tIn

I

VVdt

dVCInI kR

1k1L

1koutkoutout

R1L

Δsdot⎟⎟⎠

⎞⎜⎜⎝

⎛minus

+=rArr=minus

minus

minus



30


UPM


VHDLVHDLVHDL

VHDL-AMS

VHDLVHDL--AMSAMS






UPM




VHDLVHDL








Simulationtime


CPU time using VHDL

models


modelsmodels



VHDL speed VHDL-AMS

speed


speedspeed

10 ms10 10 msms 69 s69 s69 s 446 s446 s446 s 641641641

100 ms100 100 msms 700 s700 s700 s 6912 s6912 s6912 s 987987987

1000 ms1000 1000 msms 6890 s6890 s6890 s 68443 s68443 s68443 s 993993993

VHDLVHDL--AMSAMS

31


UPM

42V 14V

CC

CC 42V 14V


system vehicles


Q1-1

Q2-1

Q16-1

Q16-2

Q2-2

Q1-2

L

L

L

COCIN




UPM


Q1-1

Q2-1

Q16-1

Q16-2

Q2-2

Q1-2

L

L

L

COCIN








3 prototypes


3 prototypes



32


UPM


VoVIN

L2d2

d1L1




VINd1

Battery

R1

R2

+

+ +

VINd2

1

BAT1IN1 R

VdVI minus=

2

22 R

VdVI BATIN -=


UPM







446

416

03360

03528

320

2336



1 5

CCM ndash 1000W

824

184

Not acceptable


Q1-1

Q2-1

Q16-1

Q16-2

Q2-2

Q1-2

L

L

L

33


UPM

AVGLI AVGLI


dT T

LVV OIN minus

LVOminus

AVGLI

dT T

LVV OIN minus

LVOminus

AVGLI

⎟⎟⎠

⎞⎜⎜⎝

⎛ minus=

O

OIN

i

2iIN

i VVV

fL2dVI



AVGLI AVGLI

DCMDCM


UPM


03360

03528






416

824



1 5

CCM ndash 1000W

0262002623

0275102649


1 5

DCM ndash 1000W

Not acceptable

445

490

446

454

110102

Very good


34


UPM



420 97

435 100

440 101

435 -

DC Current(A)

429 99

428 98

446 103

460 106

Deviation()

Phase 2

Phase 3

Phase 4

Phase 5

Phase 6

Phase 7

Phase 8

Average

CCM


IO=35A




UPM


ADCInterface

ampfilter

Regulator8

d1


Vout

ADCcontrol

Reset

Vin

12

MCDgenerator

12

Vout

12

Vin

Phase-shifter

8

d2

Protections

1616

Clock

16

H-Pulses L-Pulses




35


UPM




422 97

438 101

442 102

434 -

DC Current(A)

431 99

445 102

424 98

448 103

Deviation()

Phase 2Phase 2

Phase 3Phase 3

Phase 4Phase 4

Phase 5Phase 5

Phase 6Phase 6

Phase 7Phase 7

Phase 8Phase 8

AverageAverage

DCMDCM


IO=17A

IO=27A


UPM





36


UPM


-05

0

05

1

15

2

00E+00 50E-06 10E-05 15E-05 20E-05 25E-05t (s)

()

-05

0

05

1

15

2

00E+00 50E-06 10E-05 15E-05 20E-05 25E-05t (s)

()

0

20

40

60

80

100

120

140

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35

Phase number

[+6-8]

0

20

40

60

80

100

120

140

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35

Phase number

[+6-8]

Half load(500W)


Full load(1000W)

0

1

2

3

4

p

0 5μs 10μs 15μs 20μs0

1

2

3

4

p



0

20

40

60

80

100

120

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35

Phase number

+10-75

0

20

40

60

80

100

120

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35

Phase number

+10-75



UPM

Output currentDC AC

11App

70ADC


is

0 01 02 03 04 05 06 07 08 09 100102030405

060708091

Duty cycle (d)

Nor

m c

urre

nt r

ippl

e Dutyvariation

2 phases

3 phases



37


UPM

10

5

5

10

3T0 x

5

5

3T0 x

Ideal case






10

5

5

10

3T0 x

5

5

3T0 x

Non-ideal



10

5

5

10

3T0 x

5

5

3T0 x

Worse case



10

5

5

10

3T0 x

5

5

3T0 x





UPM

ΔIP-P= 40A (5Adiv)

1 phase

ΔIP-P= 12A (5Adiv)

2 phases

ΔIP-P= 5A (5Adiv)

4 phases

ΔIP-P= 22A (1Adiv)

8 phases

ΔIP-P= 16A (1Adiv)

16 phases



38


UPM

(a)

30

31

22 40

37

22 33

2830

31

22 40

37

22 33

28

(a)

Center of mass

(a)

30

31

22 40

37

22 33

2830

31

22 40

37

22 33

28

(a)

Center of mass

Phase1Phase

2

Phase3

Phase4

Phase5

Phase6

Phase7

Phase8

1st

2nd

3rd 4th

6th

5th 8th

7th

(b)

1st

2nd

3rd 4th

6th

5th 8th

7th

1st

2nd

3rd 4th

6th

5th 8th

7th

(b)

40 A

37 A30 A

33 A

22 A 28 A

31 A

22 A






UPM

18 0 18

18

18

OVERALL 67A

18 0 18

18

18

1

2

34

56

7

8

9

10

1112 13

14

15

16

MAX

MIN

18 0 18

18

18

OVERALL 05A

18 0 18

18

18

1

2

34

56

7

8

9

10

1112 13

1415

16

MAX

MIN


16151413121110987654321

Phase number

165155177152140144148128147122154158139149142133

Current ripple (A)

39


UPM

ΔIP-P= 40A

ΔIP-P= 40A

ΔIP-P= 07A

ΔIP-P= 16A

57

ΔIP-P= 11A

ΔIP-P= 22A

50

ΔIP-P= 28A

ΔIP-P= 5A

44

ΔIP-P= 11A

ΔIP-P= 12A

9






1 2 4 8 16



UPM


Tswitch

delay

Load

voutvin



COUNTERDUTY CYCLE

DRIVING SIGNAL

Load

voutvin



40


UPM



Dri

vin

gsi

gnal

s

Counter

+ hellip +


Duty cycle





UPM


Dri

vin

gD

rivi

ng

sign

als

sign

als



ltDuty cycle


Shift Register



Counter


41


UPM






ASIC

12 12 phasesphases

6 6 phasesphases

24 24 phasesphases





0

2000

4000

6000

8000

10000

12000

14000

16000

2 4 6 8 12 16 20 24

0

2000

4000

6000

8000

10000

12000

2 4 6 8 12 16 20 24

0

2000

4000

6000

8000

10000

12000

14000

16000

18000

2 4 6 8 12 16 20 24


Res

ol 1

28Res

ol 2

56Res

ol 5

12

FPGA

Equ

ival

ent

gate

s

Phases

0

200

400

600

800

1000

2 4 6 8 12 16 20 24


Res

ol 1

28Res

ol 2

56Res

ol 5

120

200

400

600

800

1000

1200

2 4 6 8 12 16 20 24

0

200

400

600

800

1000

1200

1400

2 4 6 8 12 16 20 24

ASIC

Equ

ival

ent

gate

s

Phases


UPM


0

10

20

30

40

50

0 20 40 60 80



0

10

20

30

40

50

0 20 40 60 80



Iout

Pow

erlo

sses

(W)

80

84

88

92

96

0 10 20 30 40 50 60 70 80

6 phases

8 phases12 phases

16 phases

4 phases



Iout

Effic

ienc

y(

)

80

84

88

92

96

0 10 20 30 40 50 60 70 80

6 phases

8 phases12 phases

16 phases

4 phases



Iout

Effic

ienc

y(

)



42


UPM





UPM


RFAmp

Pow

erSt

age

Control

iRF

vs

VS

variable VS


24V

9Vfmax=35kHz

Input voltage = 28V





43


UPM


Cs

M1

L

M2

Cs

M1

L

M2

Cs

M1

L

M2

Cs

M1

L

M2

Ve Vout

CAR

GA




UPM


SW

CLK

ff Resolution =

Pipeline

fCLK

f = 25MHz f = 45MHz

Resolution required



fselected = 32MHz


44


UPM

33 33 DitherDither

SW

CLK

ff Resolution gt

d = 42

d =43

d =425

T=2TSW=8μs

Output voltage

2 solutions

V=50mV

TSW=4μs 1 solution

T=4μs

Output voltage

V=25mV

SW

CLKNVirtual



Average duty cycle

It gives 1 more bit


UPM



SimulatedSimulated

MeasuredMeasured



)(

4110780250 22




45


UPM






UPM


f = 200Hz f = 15kHz

f = 3kHz f = 5kHz

46


UPM





UPM



2 2 micromicross

Vo

1 V

2 V

VRM for DVS5 V

Io = 20 A max

1V - 2 V

Io

02 V max02 V max

0 A

20 A

500 Amicros

Vo




47


UPM


10-1 100 101

100

L-C diagram

C2 micros

200 mV

20A




C = 35 C = 35 μμFF



UPM






fsw = 520 kHz

(125 mΩ eq Rds_on)





48


UPM


0

1

To drivers

New vref

vo dig

N-phases_tran

N-phases

New vref

vo dig

New vref

vo dig


ic


NON-LINEAR CONTROL





UPM


vref

vo

0

1

To drivers

clk_sample

clk_sample

ADC

N-phases_tran

N-phases

vo dig

LINEAR CONTROL



49


UPM


vref

vo

0

1

To drivers

New vref

vo dig

clk_sample

clk_sample

ADC

N-phases_tran

N-phases

vo dig

New vref

LINEAR CONTROL

NON-LINEAR CONTROL

vo dig

New vrefvo dig


ic



Beware


UPM


UpUp--stepstep

ConverterFPGA

tt11



DownDown--stepstep

t1 t2 t1 t2

ddnn

tt22vref

500 kHz

LUT


05

1

15

2

25

0 02 04 06 08 1 12 14 16 18-10

0

10

20

30

40

50

ton toff

Tmin

05

1

15

2

25

0 02 04 06 08 1 12 14 16 18-10

0

10

20

30

40

50

ton toff

Tmin

i L(A

)i L

(A)

V o(V

)V o

(V)


50


UPM


t1 t2 t1 t2

094 096 098 1 102 104 106 108 11

x 10-4

14

16

18

2

22

24

26

28

3

32

094 096 098 1 102 104 106 108 11

x 10-4

0

1

2

3

4

5092 094 096 098 1 102 104 106 108 11 112

x 10-4

14

16

18

2

22

24

26

28

3

32

092 094 096 098 1 102 104 106 108 11 112

x 10-4

0

05

1

15

2

25

3

35

4

45

Transient





Beware


UPM

ΔIo

iL

Io

vo

ic 0 ATrip point 1

Trip point 2

ΔIo

ic





51


UPM


05358z02236z07417)(z3767G(z) 2 +sdotminus

+sdot=

B G(s)

G(z)




N = 4

ESR = 125 mΩ

( )CL

1sRESRL1s

CL1)1sCESR(V

)s(Gdv

L2

ino

sdot+sdot+sdot+


==

~ VinmiddotdCo

ESR

RphaseN LphaseN

Expected by design


DC resistance


model


Beware


UPM


Pole-Zero Map

Real Axis

-1 -08 -06 -04 -02 0 02 04 06 08 1-1

-08

-06

-04

-02

0

02

04

06

08

1

09

0807060504

03

02

01

26e5

234e5

208e5

182e5

156e513e5

104e5

781e4

521e4

26e4

26e5

234e5

208e5

182e5

156e513e5

104e5

781e4

521e4

26e4

x

x

x




Duty cycle

30 micros


1z00372)z(Rminus

=

1zK)z(R 1

minus=

Controller delay

05358z02236z07417)(z3767G(z) 2 +sdotminus

+sdot=Converter

x

x

x Duty cycle

Output voltage

52


UPM

10 micros


xx

x

x

x

x

x

x




00775)(z1)(z037)(z00378R(z)

minussdotminus+sdot

=

Duty cycle

Output voltage


UPM


75 micros

xx

x

x

x

xx

x



minussdotminus+sdot

=

53


UPM


Duty

a1 = -0922548 b1 = 0037759b2 = 0051742a2 = 0

b1

b2

δ-1

δ-1

δ-1

a1

a2

Error

bn0

No b0

δ-1

Z-1

+

00775)(z1)(z037)(z00378R(z)

minussdotminus+sdot

=




UPM


z2d_m ( tf ([00378 0013986] [1 -10775 00775] 192e-6) )




=Tsample = Tsw

⎪⎩

⎪⎨⎧

rarrδ

+=δ δδ

s


54


UPM


Reference

Switched model

7 bits

8 bits

Not quantizied


PWM

ADC

111






UPM

Reference


PWM

ADC






hellip

222

55


UPM



a1 = -0922548 b1 = 0037759b2 = 0051742a2 = 0

b1

b2

δ-1

δ-1

δ-1

a1

a2

Error

bn0

No b0


UPM


0lt Duty cycle lt1


Hardware adders






Beware

56


UPM

0 1 2 30

05

1

15

2

25








UPM



0 1 2 3

x 10-4

0

05

1

15

2

25

100 usdiv100 usdiv



57


UPM






UPM




58


UPM


13 14 15 16 17 18 19

x 10-4

12

14

16

18

2

22

08 V drop

10 microsdiv

2 V





UPM



Vo

1 V

2 V



11 A11 A

20 mV

520 kHz



59


UPM


Vo

Io

200 mV







UPM


Vo

1 V

2 V





60


UPM





Beware



UPM



17


UPM


xx

xx

OO






96730middot29412239middot6229)(


2

7211

8

+minus+

=

+++

= minusminus

minus

zzzzG

ssssG


condition)



UPM




Vout

Duty

Near unstable



18


UPM



1z110)z(R 5

minus= minus

Vout

Duty







UPM




+= minus

Vout

Duty




19


UPM


Vout

Duty





23

+minusminus+minus




UPM


xk xk-1

hellip

xk-m

X

b0

X

b1

X

bm

hellip

+

+

hellip

+

yk yk-1

hellip

yk-n

X

a1

X

an

+

+

hellip

hellip

+

-yk

nn

22

110

mm

22

110

zazazaazbzbzbb

)z(e)z(d)z(R

minusminusminus

minusminusminus

sdot++sdot+sdot+





20


UPM

Z-1

a1

a2

Z-1


Z-1

bo

eK

Z-1

b1

b2

R1(z) R2(z)YK

dK

eK

R1 R2

Z-1

Z-1

a1

bo

b1

dKeK






UPM

Difference equation


a1a2

e(z)

⎩⎨⎧

rarrδ

+=δminus=δ= δδ+


TXXXmiddotY kkkk1k

kk

Tz1 1minusminus

=δ

k1

1k

1k Y

z1zTYXminus

minusminus

minus

sdot=δ=

δ-1 δ-1

aman

δ-1 δ-1

bm

+

bo

b1

u(z)h(z)

T Z-1

δ-1

(Integral)

+




More adders

21


UPM

a1

a2

δ-1

bo

b1T

b2T2 δ-1 T2

T


Tn Tn


Z-1

+



Adapted δ-1


UPM








ek-1 isrequested

ek-1 isavailable

dk isimposed

T

22


UPM

0 1 2 3 4 5 6 7 8

x 10 -4

-04

-02

0

02

04

06

08

1

12

14

16




vo

48 5 52 54 56 58

10-4

138

14

142

144

146

148

15

152

154

156

vo

Matlabfixed-point

toolbox






UPM



00011111b0 =


Meanerror

22 143143 5252

11 333333 170170

44 3232 0606

33 6767 1717


615615 105ns105ns

12481248 168ns168ns

Mp ts

Example

160160 012ms012ms

113113 011ms011ms1


zz

( )1

222 353


zz


00101000b0 = k53

k5


00101001b0 = k853

k8

k5


222

333



00100000b0 = k3 e2 sdotminus111


1rsquos

23


UPM





D QEN

new_cycle Xek

b0

D QEN

new_cycle Xek-1

b1

+

D QEN

new_cycle Xdk-1

a1

D QEN

new_cycle Xdk-2

b2

+ D QENnew_cycle

dk

+


D Q

D Q

D Q

D Q

D Q

D Q






UPM

Fixed-point toolbox







MatlabSimulink



24


UPM

VHDL or VHDL-AMS











UPM


Applications333



323322

333333

25


UPM


IinVin

Vout

DCDCREGULATOR LO

AD

~

IoutIin


Vout

+_Vin

CONTROL

d

R1

R2

R3

R4

n1 n2LINE

LOAD

Main Switch

Vin

Iin Vout

PO=50Wf=50kHz


PO=50Wf=50kHz



UPM





Adaptive control


LOA

D

~

IoutIin

PFC CONVERTERVout

+_Vin

Controlblock

Controlblock

onoff

R1

R2

R3

R4

Vout

Iin

Vin

ADCADC

ADC

26


UPM


X


IIN-ref

Protections


VOUT max

IIN max

ldquodrdquo max

ldquoΔdrdquo max

ON-OFF Main Switch

ON-OFF Main Switch





intΣIin

gt

CalculatedOn-Off


Max






VOUT-ref

GinPI


UPM










VinGin

Multiplier

xVin

Gin(1Rin)

50 kHz



Adder

+Iin

ΣIin

Comparator

gtOnOff

20 MHz

NoPWMNoPWM


27


UPM




10 W 30 W 50 W 30 W 10 W

Vout

IinGin

StableStable

Load


Unstable

Unstable

Unstable

Unstable


UPM




Adaptive control

28


UPM



Load Change

Vout

Iin




T



UPM

Vin_dc

Iin_dc

d

Vout


OnOff

FPGAXilinx

XC4010-e

8 8 12

Vin Vout Iin

PROMXC 17512

ADC0808

ADC0808

HI 5805


ADCsADCs

Power Converter

Vout Vin_acIin_ac

PF = 099PF = 099PF = 099

29


UPM


DigitalController


switches)Digital


Measuredamp State


Analog

ADConverter

MeasuredVariables

(digital buses)

Mixed




UPM


M1

C Vout

D11n

+

_Vin

Iin

IL1

RL

IR

ON

L1OFF

M1

C Vout

D11n

+

_Vin

Iin

IL1

RL

IR

OFF

L1ON

Vout

n

ID1 = IL1 n

IC



1

kin1k1Lk1L

1L1in L

tVII

dtdILV

Δsdot+=rArr= minus

CtI

VVdt

dVCI kR1koutkout

outR


1

1kout1k1Lk1L

1L1

out

LntV

IIdt

dILnV

sdotΔsdot


minus

C

tIn

I

VVdt

dVCInI kR

1k1L

1koutkoutout

R1L

Δsdot⎟⎟⎠

⎞⎜⎜⎝

⎛minus

+=rArr=minus

minus

minus



30


UPM


VHDLVHDLVHDL

VHDL-AMS

VHDLVHDL--AMSAMS






UPM




VHDLVHDL








Simulationtime


CPU time using VHDL

models


modelsmodels



VHDL speed VHDL-AMS

speed


speedspeed

10 ms10 10 msms 69 s69 s69 s 446 s446 s446 s 641641641

100 ms100 100 msms 700 s700 s700 s 6912 s6912 s6912 s 987987987

1000 ms1000 1000 msms 6890 s6890 s6890 s 68443 s68443 s68443 s 993993993

VHDLVHDL--AMSAMS

31


UPM

42V 14V

CC

CC 42V 14V


system vehicles


Q1-1

Q2-1

Q16-1

Q16-2

Q2-2

Q1-2

L

L

L

COCIN




UPM


Q1-1

Q2-1

Q16-1

Q16-2

Q2-2

Q1-2

L

L

L

COCIN








3 prototypes


3 prototypes



32


UPM


VoVIN

L2d2

d1L1




VINd1

Battery

R1

R2

+

+ +

VINd2

1

BAT1IN1 R

VdVI minus=

2

22 R

VdVI BATIN -=


UPM







446

416

03360

03528

320

2336



1 5

CCM ndash 1000W

824

184

Not acceptable


Q1-1

Q2-1

Q16-1

Q16-2

Q2-2

Q1-2

L

L

L

33


UPM

AVGLI AVGLI


dT T

LVV OIN minus

LVOminus

AVGLI

dT T

LVV OIN minus

LVOminus

AVGLI

⎟⎟⎠

⎞⎜⎜⎝

⎛ minus=

O

OIN

i

2iIN

i VVV

fL2dVI



AVGLI AVGLI

DCMDCM


UPM


03360

03528






416

824



1 5

CCM ndash 1000W

0262002623

0275102649


1 5

DCM ndash 1000W

Not acceptable

445

490

446

454

110102

Very good


34


UPM



420 97

435 100

440 101

435 -

DC Current(A)

429 99

428 98

446 103

460 106

Deviation()

Phase 2

Phase 3

Phase 4

Phase 5

Phase 6

Phase 7

Phase 8

Average

CCM


IO=35A




UPM


ADCInterface

ampfilter

Regulator8

d1


Vout

ADCcontrol

Reset

Vin

12

MCDgenerator

12

Vout

12

Vin

Phase-shifter

8

d2

Protections

1616

Clock

16

H-Pulses L-Pulses




35


UPM




422 97

438 101

442 102

434 -

DC Current(A)

431 99

445 102

424 98

448 103

Deviation()

Phase 2Phase 2

Phase 3Phase 3

Phase 4Phase 4

Phase 5Phase 5

Phase 6Phase 6

Phase 7Phase 7

Phase 8Phase 8

AverageAverage

DCMDCM


IO=17A

IO=27A


UPM





36


UPM


-05

0

05

1

15

2

00E+00 50E-06 10E-05 15E-05 20E-05 25E-05t (s)

()

-05

0

05

1

15

2

00E+00 50E-06 10E-05 15E-05 20E-05 25E-05t (s)

()

0

20

40

60

80

100

120

140

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35

Phase number

[+6-8]

0

20

40

60

80

100

120

140

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35

Phase number

[+6-8]

Half load(500W)


Full load(1000W)

0

1

2

3

4

p

0 5μs 10μs 15μs 20μs0

1

2

3

4

p



0

20

40

60

80

100

120

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35

Phase number

+10-75

0

20

40

60

80

100

120

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35

Phase number

+10-75



UPM

Output currentDC AC

11App

70ADC


is

0 01 02 03 04 05 06 07 08 09 100102030405

060708091

Duty cycle (d)

Nor

m c

urre

nt r

ippl

e Dutyvariation

2 phases

3 phases



37


UPM

10

5

5

10

3T0 x

5

5

3T0 x

Ideal case






10

5

5

10

3T0 x

5

5

3T0 x

Non-ideal



10

5

5

10

3T0 x

5

5

3T0 x

Worse case



10

5

5

10

3T0 x

5

5

3T0 x





UPM

ΔIP-P= 40A (5Adiv)

1 phase

ΔIP-P= 12A (5Adiv)

2 phases

ΔIP-P= 5A (5Adiv)

4 phases

ΔIP-P= 22A (1Adiv)

8 phases

ΔIP-P= 16A (1Adiv)

16 phases



38


UPM

(a)

30

31

22 40

37

22 33

2830

31

22 40

37

22 33

28

(a)

Center of mass

(a)

30

31

22 40

37

22 33

2830

31

22 40

37

22 33

28

(a)

Center of mass

Phase1Phase

2

Phase3

Phase4

Phase5

Phase6

Phase7

Phase8

1st

2nd

3rd 4th

6th

5th 8th

7th

(b)

1st

2nd

3rd 4th

6th

5th 8th

7th

1st

2nd

3rd 4th

6th

5th 8th

7th

(b)

40 A

37 A30 A

33 A

22 A 28 A

31 A

22 A






UPM

18 0 18

18

18

OVERALL 67A

18 0 18

18

18

1

2

34

56

7

8

9

10

1112 13

14

15

16

MAX

MIN

18 0 18

18

18

OVERALL 05A

18 0 18

18

18

1

2

34

56

7

8

9

10

1112 13

1415

16

MAX

MIN


16151413121110987654321

Phase number

165155177152140144148128147122154158139149142133

Current ripple (A)

39


UPM

ΔIP-P= 40A

ΔIP-P= 40A

ΔIP-P= 07A

ΔIP-P= 16A

57

ΔIP-P= 11A

ΔIP-P= 22A

50

ΔIP-P= 28A

ΔIP-P= 5A

44

ΔIP-P= 11A

ΔIP-P= 12A

9






1 2 4 8 16



UPM


Tswitch

delay

Load

voutvin



COUNTERDUTY CYCLE

DRIVING SIGNAL

Load

voutvin



40


UPM



Dri

vin

gsi

gnal

s

Counter

+ hellip +


Duty cycle





UPM


Dri

vin

gD

rivi

ng

sign

als

sign

als



ltDuty cycle


Shift Register



Counter


41


UPM






ASIC

12 12 phasesphases

6 6 phasesphases

24 24 phasesphases





0

2000

4000

6000

8000

10000

12000

14000

16000

2 4 6 8 12 16 20 24

0

2000

4000

6000

8000

10000

12000

2 4 6 8 12 16 20 24

0

2000

4000

6000

8000

10000

12000

14000

16000

18000

2 4 6 8 12 16 20 24


Res

ol 1

28Res

ol 2

56Res

ol 5

12

FPGA

Equ

ival

ent

gate

s

Phases

0

200

400

600

800

1000

2 4 6 8 12 16 20 24


Res

ol 1

28Res

ol 2

56Res

ol 5

120

200

400

600

800

1000

1200

2 4 6 8 12 16 20 24

0

200

400

600

800

1000

1200

1400

2 4 6 8 12 16 20 24

ASIC

Equ

ival

ent

gate

s

Phases


UPM


0

10

20

30

40

50

0 20 40 60 80



0

10

20

30

40

50

0 20 40 60 80



Iout

Pow

erlo

sses

(W)

80

84

88

92

96

0 10 20 30 40 50 60 70 80

6 phases

8 phases12 phases

16 phases

4 phases



Iout

Effic

ienc

y(

)

80

84

88

92

96

0 10 20 30 40 50 60 70 80

6 phases

8 phases12 phases

16 phases

4 phases



Iout

Effic

ienc

y(

)



42


UPM





UPM


RFAmp

Pow

erSt

age

Control

iRF

vs

VS

variable VS


24V

9Vfmax=35kHz

Input voltage = 28V





43


UPM


Cs

M1

L

M2

Cs

M1

L

M2

Cs

M1

L

M2

Cs

M1

L

M2

Ve Vout

CAR

GA




UPM


SW

CLK

ff Resolution =

Pipeline

fCLK

f = 25MHz f = 45MHz

Resolution required



fselected = 32MHz


44


UPM

33 33 DitherDither

SW

CLK

ff Resolution gt

d = 42

d =43

d =425

T=2TSW=8μs

Output voltage

2 solutions

V=50mV

TSW=4μs 1 solution

T=4μs

Output voltage

V=25mV

SW

CLKNVirtual



Average duty cycle

It gives 1 more bit


UPM



SimulatedSimulated

MeasuredMeasured



)(

4110780250 22




45


UPM






UPM


f = 200Hz f = 15kHz

f = 3kHz f = 5kHz

46


UPM





UPM



2 2 micromicross

Vo

1 V

2 V

VRM for DVS5 V

Io = 20 A max

1V - 2 V

Io

02 V max02 V max

0 A

20 A

500 Amicros

Vo




47


UPM


10-1 100 101

100

L-C diagram

C2 micros

200 mV

20A




C = 35 C = 35 μμFF



UPM






fsw = 520 kHz

(125 mΩ eq Rds_on)





48


UPM


0

1

To drivers

New vref

vo dig

N-phases_tran

N-phases

New vref

vo dig

New vref

vo dig


ic


NON-LINEAR CONTROL





UPM


vref

vo

0

1

To drivers

clk_sample

clk_sample

ADC

N-phases_tran

N-phases

vo dig

LINEAR CONTROL



49


UPM


vref

vo

0

1

To drivers

New vref

vo dig

clk_sample

clk_sample

ADC

N-phases_tran

N-phases

vo dig

New vref

LINEAR CONTROL

NON-LINEAR CONTROL

vo dig

New vrefvo dig


ic



Beware


UPM


UpUp--stepstep

ConverterFPGA

tt11



DownDown--stepstep

t1 t2 t1 t2

ddnn

tt22vref

500 kHz

LUT


05

1

15

2

25

0 02 04 06 08 1 12 14 16 18-10

0

10

20

30

40

50

ton toff

Tmin

05

1

15

2

25

0 02 04 06 08 1 12 14 16 18-10

0

10

20

30

40

50

ton toff

Tmin

i L(A

)i L

(A)

V o(V

)V o

(V)


50


UPM


t1 t2 t1 t2

094 096 098 1 102 104 106 108 11

x 10-4

14

16

18

2

22

24

26

28

3

32

094 096 098 1 102 104 106 108 11

x 10-4

0

1

2

3

4

5092 094 096 098 1 102 104 106 108 11 112

x 10-4

14

16

18

2

22

24

26

28

3

32

092 094 096 098 1 102 104 106 108 11 112

x 10-4

0

05

1

15

2

25

3

35

4

45

Transient





Beware


UPM

ΔIo

iL

Io

vo

ic 0 ATrip point 1

Trip point 2

ΔIo

ic





51


UPM


05358z02236z07417)(z3767G(z) 2 +sdotminus

+sdot=

B G(s)

G(z)




N = 4

ESR = 125 mΩ

( )CL

1sRESRL1s

CL1)1sCESR(V

)s(Gdv

L2

ino

sdot+sdot+sdot+


==

~ VinmiddotdCo

ESR

RphaseN LphaseN

Expected by design


DC resistance


model


Beware


UPM


Pole-Zero Map

Real Axis

-1 -08 -06 -04 -02 0 02 04 06 08 1-1

-08

-06

-04

-02

0

02

04

06

08

1

09

0807060504

03

02

01

26e5

234e5

208e5

182e5

156e513e5

104e5

781e4

521e4

26e4

26e5

234e5

208e5

182e5

156e513e5

104e5

781e4

521e4

26e4

x

x

x




Duty cycle

30 micros


1z00372)z(Rminus

=

1zK)z(R 1

minus=

Controller delay

05358z02236z07417)(z3767G(z) 2 +sdotminus

+sdot=Converter

x

x

x Duty cycle

Output voltage

52


UPM

10 micros


xx

x

x

x

x

x

x




00775)(z1)(z037)(z00378R(z)

minussdotminus+sdot

=

Duty cycle

Output voltage


UPM


75 micros

xx

x

x

x

xx

x



minussdotminus+sdot

=

53


UPM


Duty

a1 = -0922548 b1 = 0037759b2 = 0051742a2 = 0

b1

b2

δ-1

δ-1

δ-1

a1

a2

Error

bn0

No b0

δ-1

Z-1

+

00775)(z1)(z037)(z00378R(z)

minussdotminus+sdot

=




UPM


z2d_m ( tf ([00378 0013986] [1 -10775 00775] 192e-6) )




=Tsample = Tsw

⎪⎩

⎪⎨⎧

rarrδ

+=δ δδ

s


54


UPM


Reference

Switched model

7 bits

8 bits

Not quantizied


PWM

ADC

111






UPM

Reference


PWM

ADC






hellip

222

55


UPM



a1 = -0922548 b1 = 0037759b2 = 0051742a2 = 0

b1

b2

δ-1

δ-1

δ-1

a1

a2

Error

bn0

No b0


UPM


0lt Duty cycle lt1


Hardware adders






Beware

56


UPM

0 1 2 30

05

1

15

2

25








UPM



0 1 2 3

x 10-4

0

05

1

15

2

25

100 usdiv100 usdiv



57


UPM






UPM




58


UPM


13 14 15 16 17 18 19

x 10-4

12

14

16

18

2

22

08 V drop

10 microsdiv

2 V





UPM



Vo

1 V

2 V



11 A11 A

20 mV

520 kHz



59


UPM


Vo

Io

200 mV







UPM


Vo

1 V

2 V





60


UPM





Beware



UPM



18


UPM



1z110)z(R 5

minus= minus

Vout

Duty







UPM




+= minus

Vout

Duty




19


UPM


Vout

Duty





23

+minusminus+minus




UPM


xk xk-1

hellip

xk-m

X

b0

X

b1

X

bm

hellip

+

+

hellip

+

yk yk-1

hellip

yk-n

X

a1

X

an

+

+

hellip

hellip

+

-yk

nn

22

110

mm

22

110

zazazaazbzbzbb

)z(e)z(d)z(R

minusminusminus

minusminusminus

sdot++sdot+sdot+





20


UPM

Z-1

a1

a2

Z-1


Z-1

bo

eK

Z-1

b1

b2

R1(z) R2(z)YK

dK

eK

R1 R2

Z-1

Z-1

a1

bo

b1

dKeK






UPM

Difference equation


a1a2

e(z)

⎩⎨⎧

rarrδ

+=δminus=δ= δδ+


TXXXmiddotY kkkk1k

kk

Tz1 1minusminus

=δ

k1

1k

1k Y

z1zTYXminus

minusminus

minus

sdot=δ=

δ-1 δ-1

aman

δ-1 δ-1

bm

+

bo

b1

u(z)h(z)

T Z-1

δ-1

(Integral)

+




More adders

21


UPM

a1

a2

δ-1

bo

b1T

b2T2 δ-1 T2

T


Tn Tn


Z-1

+



Adapted δ-1


UPM








ek-1 isrequested

ek-1 isavailable

dk isimposed

T

22


UPM

0 1 2 3 4 5 6 7 8

x 10 -4

-04

-02

0

02

04

06

08

1

12

14

16




vo

48 5 52 54 56 58

10-4

138

14

142

144

146

148

15

152

154

156

vo

Matlabfixed-point

toolbox






UPM



00011111b0 =


Meanerror

22 143143 5252

11 333333 170170

44 3232 0606

33 6767 1717


615615 105ns105ns

12481248 168ns168ns

Mp ts

Example

160160 012ms012ms

113113 011ms011ms1


zz

( )1

222 353


zz


00101000b0 = k53

k5


00101001b0 = k853

k8

k5


222

333



00100000b0 = k3 e2 sdotminus111


1rsquos

23


UPM





D QEN

new_cycle Xek

b0

D QEN

new_cycle Xek-1

b1

+

D QEN

new_cycle Xdk-1

a1

D QEN

new_cycle Xdk-2

b2

+ D QENnew_cycle

dk

+


D Q

D Q

D Q

D Q

D Q

D Q






UPM

Fixed-point toolbox







MatlabSimulink



24


UPM

VHDL or VHDL-AMS











UPM


Applications333



323322

333333

25


UPM


IinVin

Vout

DCDCREGULATOR LO

AD

~

IoutIin


Vout

+_Vin

CONTROL

d

R1

R2

R3

R4

n1 n2LINE

LOAD

Main Switch

Vin

Iin Vout

PO=50Wf=50kHz


PO=50Wf=50kHz



UPM





Adaptive control


LOA

D

~

IoutIin

PFC CONVERTERVout

+_Vin

Controlblock

Controlblock

onoff

R1

R2

R3

R4

Vout

Iin

Vin

ADCADC

ADC

26


UPM


X


IIN-ref

Protections


VOUT max

IIN max

ldquodrdquo max

ldquoΔdrdquo max

ON-OFF Main Switch

ON-OFF Main Switch





intΣIin

gt

CalculatedOn-Off


Max






VOUT-ref

GinPI


UPM










VinGin

Multiplier

xVin

Gin(1Rin)

50 kHz



Adder

+Iin

ΣIin

Comparator

gtOnOff

20 MHz

NoPWMNoPWM


27


UPM




10 W 30 W 50 W 30 W 10 W

Vout

IinGin

StableStable

Load


Unstable

Unstable

Unstable

Unstable


UPM




Adaptive control

28


UPM



Load Change

Vout

Iin




T



UPM

Vin_dc

Iin_dc

d

Vout


OnOff

FPGAXilinx

XC4010-e

8 8 12

Vin Vout Iin

PROMXC 17512

ADC0808

ADC0808

HI 5805


ADCsADCs

Power Converter

Vout Vin_acIin_ac

PF = 099PF = 099PF = 099

29


UPM


DigitalController


switches)Digital


Measuredamp State


Analog

ADConverter

MeasuredVariables

(digital buses)

Mixed




UPM


M1

C Vout

D11n

+

_Vin

Iin

IL1

RL

IR

ON

L1OFF

M1

C Vout

D11n

+

_Vin

Iin

IL1

RL

IR

OFF

L1ON

Vout

n

ID1 = IL1 n

IC



1

kin1k1Lk1L

1L1in L

tVII

dtdILV

Δsdot+=rArr= minus

CtI

VVdt

dVCI kR1koutkout

outR


1

1kout1k1Lk1L

1L1

out

LntV

IIdt

dILnV

sdotΔsdot


minus

C

tIn

I

VVdt

dVCInI kR

1k1L

1koutkoutout

R1L

Δsdot⎟⎟⎠

⎞⎜⎜⎝

⎛minus

+=rArr=minus

minus

minus



30


UPM


VHDLVHDLVHDL

VHDL-AMS

VHDLVHDL--AMSAMS






UPM




VHDLVHDL








Simulationtime


CPU time using VHDL

models


modelsmodels



VHDL speed VHDL-AMS

speed


speedspeed

10 ms10 10 msms 69 s69 s69 s 446 s446 s446 s 641641641

100 ms100 100 msms 700 s700 s700 s 6912 s6912 s6912 s 987987987

1000 ms1000 1000 msms 6890 s6890 s6890 s 68443 s68443 s68443 s 993993993

VHDLVHDL--AMSAMS

31


UPM

42V 14V

CC

CC 42V 14V


system vehicles


Q1-1

Q2-1

Q16-1

Q16-2

Q2-2

Q1-2

L

L

L

COCIN




UPM


Q1-1

Q2-1

Q16-1

Q16-2

Q2-2

Q1-2

L

L

L

COCIN








3 prototypes


3 prototypes



32


UPM


VoVIN

L2d2

d1L1




VINd1

Battery

R1

R2

+

+ +

VINd2

1

BAT1IN1 R

VdVI minus=

2

22 R

VdVI BATIN -=


UPM







446

416

03360

03528

320

2336



1 5

CCM ndash 1000W

824

184

Not acceptable


Q1-1

Q2-1

Q16-1

Q16-2

Q2-2

Q1-2

L

L

L

33


UPM

AVGLI AVGLI


dT T

LVV OIN minus

LVOminus

AVGLI

dT T

LVV OIN minus

LVOminus

AVGLI

⎟⎟⎠

⎞⎜⎜⎝

⎛ minus=

O

OIN

i

2iIN

i VVV

fL2dVI



AVGLI AVGLI

DCMDCM


UPM


03360

03528






416

824



1 5

CCM ndash 1000W

0262002623

0275102649


1 5

DCM ndash 1000W

Not acceptable

445

490

446

454

110102

Very good


34


UPM



420 97

435 100

440 101

435 -

DC Current(A)

429 99

428 98

446 103

460 106

Deviation()

Phase 2

Phase 3

Phase 4

Phase 5

Phase 6

Phase 7

Phase 8

Average

CCM


IO=35A




UPM


ADCInterface

ampfilter

Regulator8

d1


Vout

ADCcontrol

Reset

Vin

12

MCDgenerator

12

Vout

12

Vin

Phase-shifter

8

d2

Protections

1616

Clock

16

H-Pulses L-Pulses




35


UPM




422 97

438 101

442 102

434 -

DC Current(A)

431 99

445 102

424 98

448 103

Deviation()

Phase 2Phase 2

Phase 3Phase 3

Phase 4Phase 4

Phase 5Phase 5

Phase 6Phase 6

Phase 7Phase 7

Phase 8Phase 8

AverageAverage

DCMDCM


IO=17A

IO=27A


UPM





36


UPM


-05

0

05

1

15

2

00E+00 50E-06 10E-05 15E-05 20E-05 25E-05t (s)

()

-05

0

05

1

15

2

00E+00 50E-06 10E-05 15E-05 20E-05 25E-05t (s)

()

0

20

40

60

80

100

120

140

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35

Phase number

[+6-8]

0

20

40

60

80

100

120

140

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35

Phase number

[+6-8]

Half load(500W)


Full load(1000W)

0

1

2

3

4

p

0 5μs 10μs 15μs 20μs0

1

2

3

4

p



0

20

40

60

80

100

120

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35

Phase number

+10-75

0

20

40

60

80

100

120

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35

Phase number

+10-75



UPM

Output currentDC AC

11App

70ADC


is

0 01 02 03 04 05 06 07 08 09 100102030405

060708091

Duty cycle (d)

Nor

m c

urre

nt r

ippl

e Dutyvariation

2 phases

3 phases



37


UPM

10

5

5

10

3T0 x

5

5

3T0 x

Ideal case






10

5

5

10

3T0 x

5

5

3T0 x

Non-ideal



10

5

5

10

3T0 x

5

5

3T0 x

Worse case



10

5

5

10

3T0 x

5

5

3T0 x





UPM

ΔIP-P= 40A (5Adiv)

1 phase

ΔIP-P= 12A (5Adiv)

2 phases

ΔIP-P= 5A (5Adiv)

4 phases

ΔIP-P= 22A (1Adiv)

8 phases

ΔIP-P= 16A (1Adiv)

16 phases



38


UPM

(a)

30

31

22 40

37

22 33

2830

31

22 40

37

22 33

28

(a)

Center of mass

(a)

30

31

22 40

37

22 33

2830

31

22 40

37

22 33

28

(a)

Center of mass

Phase1Phase

2

Phase3

Phase4

Phase5

Phase6

Phase7

Phase8

1st

2nd

3rd 4th

6th

5th 8th

7th

(b)

1st

2nd

3rd 4th

6th

5th 8th

7th

1st

2nd

3rd 4th

6th

5th 8th

7th

(b)

40 A

37 A30 A

33 A

22 A 28 A

31 A

22 A






UPM

18 0 18

18

18

OVERALL 67A

18 0 18

18

18

1

2

34

56

7

8

9

10

1112 13

14

15

16

MAX

MIN

18 0 18

18

18

OVERALL 05A

18 0 18

18

18

1

2

34

56

7

8

9

10

1112 13

1415

16

MAX

MIN


16151413121110987654321

Phase number

165155177152140144148128147122154158139149142133

Current ripple (A)

39


UPM

ΔIP-P= 40A

ΔIP-P= 40A

ΔIP-P= 07A

ΔIP-P= 16A

57

ΔIP-P= 11A

ΔIP-P= 22A

50

ΔIP-P= 28A

ΔIP-P= 5A

44

ΔIP-P= 11A

ΔIP-P= 12A

9






1 2 4 8 16



UPM


Tswitch

delay

Load

voutvin



COUNTERDUTY CYCLE

DRIVING SIGNAL

Load

voutvin



40


UPM



Dri

vin

gsi

gnal

s

Counter

+ hellip +


Duty cycle





UPM


Dri

vin

gD

rivi

ng

sign

als

sign

als



ltDuty cycle


Shift Register



Counter


41


UPM






ASIC

12 12 phasesphases

6 6 phasesphases

24 24 phasesphases





0

2000

4000

6000

8000

10000

12000

14000

16000

2 4 6 8 12 16 20 24

0

2000

4000

6000

8000

10000

12000

2 4 6 8 12 16 20 24

0

2000

4000

6000

8000

10000

12000

14000

16000

18000

2 4 6 8 12 16 20 24


Res

ol 1

28Res

ol 2

56Res

ol 5

12

FPGA

Equ

ival

ent

gate

s

Phases

0

200

400

600

800

1000

2 4 6 8 12 16 20 24


Res

ol 1

28Res

ol 2

56Res

ol 5

120

200

400

600

800

1000

1200

2 4 6 8 12 16 20 24

0

200

400

600

800

1000

1200

1400

2 4 6 8 12 16 20 24

ASIC

Equ

ival

ent

gate

s

Phases


UPM


0

10

20

30

40

50

0 20 40 60 80



0

10

20

30

40

50

0 20 40 60 80



Iout

Pow

erlo

sses

(W)

80

84

88

92

96

0 10 20 30 40 50 60 70 80

6 phases

8 phases12 phases

16 phases

4 phases



Iout

Effic

ienc

y(

)

80

84

88

92

96

0 10 20 30 40 50 60 70 80

6 phases

8 phases12 phases

16 phases

4 phases



Iout

Effic

ienc

y(

)



42


UPM





UPM


RFAmp

Pow

erSt

age

Control

iRF

vs

VS

variable VS


24V

9Vfmax=35kHz

Input voltage = 28V





43


UPM


Cs

M1

L

M2

Cs

M1

L

M2

Cs

M1

L

M2

Cs

M1

L

M2

Ve Vout

CAR

GA




UPM


SW

CLK

ff Resolution =

Pipeline

fCLK

f = 25MHz f = 45MHz

Resolution required



fselected = 32MHz


44


UPM

33 33 DitherDither

SW

CLK

ff Resolution gt

d = 42

d =43

d =425

T=2TSW=8μs

Output voltage

2 solutions

V=50mV

TSW=4μs 1 solution

T=4μs

Output voltage

V=25mV

SW

CLKNVirtual



Average duty cycle

It gives 1 more bit


UPM



SimulatedSimulated

MeasuredMeasured



)(

4110780250 22




45


UPM






UPM


f = 200Hz f = 15kHz

f = 3kHz f = 5kHz

46


UPM





UPM



2 2 micromicross

Vo

1 V

2 V

VRM for DVS5 V

Io = 20 A max

1V - 2 V

Io

02 V max02 V max

0 A

20 A

500 Amicros

Vo




47


UPM


10-1 100 101

100

L-C diagram

C2 micros

200 mV

20A




C = 35 C = 35 μμFF



UPM






fsw = 520 kHz

(125 mΩ eq Rds_on)





48


UPM


0

1

To drivers

New vref

vo dig

N-phases_tran

N-phases

New vref

vo dig

New vref

vo dig


ic


NON-LINEAR CONTROL





UPM


vref

vo

0

1

To drivers

clk_sample

clk_sample

ADC

N-phases_tran

N-phases

vo dig

LINEAR CONTROL



49


UPM


vref

vo

0

1

To drivers

New vref

vo dig

clk_sample

clk_sample

ADC

N-phases_tran

N-phases

vo dig

New vref

LINEAR CONTROL

NON-LINEAR CONTROL

vo dig

New vrefvo dig


ic



Beware


UPM


UpUp--stepstep

ConverterFPGA

tt11



DownDown--stepstep

t1 t2 t1 t2

ddnn

tt22vref

500 kHz

LUT


05

1

15

2

25

0 02 04 06 08 1 12 14 16 18-10

0

10

20

30

40

50

ton toff

Tmin

05

1

15

2

25

0 02 04 06 08 1 12 14 16 18-10

0

10

20

30

40

50

ton toff

Tmin

i L(A

)i L

(A)

V o(V

)V o

(V)


50


UPM


t1 t2 t1 t2

094 096 098 1 102 104 106 108 11

x 10-4

14

16

18

2

22

24

26

28

3

32

094 096 098 1 102 104 106 108 11

x 10-4

0

1

2

3

4

5092 094 096 098 1 102 104 106 108 11 112

x 10-4

14

16

18

2

22

24

26

28

3

32

092 094 096 098 1 102 104 106 108 11 112

x 10-4

0

05

1

15

2

25

3

35

4

45

Transient





Beware


UPM

ΔIo

iL

Io

vo

ic 0 ATrip point 1

Trip point 2

ΔIo

ic





51


UPM


05358z02236z07417)(z3767G(z) 2 +sdotminus

+sdot=

B G(s)

G(z)




N = 4

ESR = 125 mΩ

( )CL

1sRESRL1s

CL1)1sCESR(V

)s(Gdv

L2

ino

sdot+sdot+sdot+


==

~ VinmiddotdCo

ESR

RphaseN LphaseN

Expected by design


DC resistance


model


Beware


UPM


Pole-Zero Map

Real Axis

-1 -08 -06 -04 -02 0 02 04 06 08 1-1

-08

-06

-04

-02

0

02

04

06

08

1

09

0807060504

03

02

01

26e5

234e5

208e5

182e5

156e513e5

104e5

781e4

521e4

26e4

26e5

234e5

208e5

182e5

156e513e5

104e5

781e4

521e4

26e4

x

x

x




Duty cycle

30 micros


1z00372)z(Rminus

=

1zK)z(R 1

minus=

Controller delay

05358z02236z07417)(z3767G(z) 2 +sdotminus

+sdot=Converter

x

x

x Duty cycle

Output voltage

52


UPM

10 micros


xx

x

x

x

x

x

x




00775)(z1)(z037)(z00378R(z)

minussdotminus+sdot

=

Duty cycle

Output voltage


UPM


75 micros

xx

x

x

x

xx

x



minussdotminus+sdot

=

53


UPM


Duty

a1 = -0922548 b1 = 0037759b2 = 0051742a2 = 0

b1

b2

δ-1

δ-1

δ-1

a1

a2

Error

bn0

No b0

δ-1

Z-1

+

00775)(z1)(z037)(z00378R(z)

minussdotminus+sdot

=




UPM


z2d_m ( tf ([00378 0013986] [1 -10775 00775] 192e-6) )




=Tsample = Tsw

⎪⎩

⎪⎨⎧

rarrδ

+=δ δδ

s


54


UPM


Reference

Switched model

7 bits

8 bits

Not quantizied


PWM

ADC

111






UPM

Reference


PWM

ADC






hellip

222

55


UPM



a1 = -0922548 b1 = 0037759b2 = 0051742a2 = 0

b1

b2

δ-1

δ-1

δ-1

a1

a2

Error

bn0

No b0


UPM


0lt Duty cycle lt1


Hardware adders






Beware

56


UPM

0 1 2 30

05

1

15

2

25








UPM



0 1 2 3

x 10-4

0

05

1

15

2

25

100 usdiv100 usdiv



57


UPM






UPM




58


UPM


13 14 15 16 17 18 19

x 10-4

12

14

16

18

2

22

08 V drop

10 microsdiv

2 V





UPM



Vo

1 V

2 V



11 A11 A

20 mV

520 kHz



59


UPM


Vo

Io

200 mV







UPM


Vo

1 V

2 V





60


UPM





Beware



UPM



19


UPM


Vout

Duty





23

+minusminus+minus




UPM


xk xk-1

hellip

xk-m

X

b0

X

b1

X

bm

hellip

+

+

hellip

+

yk yk-1

hellip

yk-n

X

a1

X

an

+

+

hellip

hellip

+

-yk

nn

22

110

mm

22

110

zazazaazbzbzbb

)z(e)z(d)z(R

minusminusminus

minusminusminus

sdot++sdot+sdot+





20


UPM

Z-1

a1

a2

Z-1


Z-1

bo

eK

Z-1

b1

b2

R1(z) R2(z)YK

dK

eK

R1 R2

Z-1

Z-1

a1

bo

b1

dKeK






UPM

Difference equation


a1a2

e(z)

⎩⎨⎧

rarrδ

+=δminus=δ= δδ+


TXXXmiddotY kkkk1k

kk

Tz1 1minusminus

=δ

k1

1k

1k Y

z1zTYXminus

minusminus

minus

sdot=δ=

δ-1 δ-1

aman

δ-1 δ-1

bm

+

bo

b1

u(z)h(z)

T Z-1

δ-1

(Integral)

+




More adders

21


UPM

a1

a2

δ-1

bo

b1T

b2T2 δ-1 T2

T


Tn Tn


Z-1

+



Adapted δ-1


UPM








ek-1 isrequested

ek-1 isavailable

dk isimposed

T

22


UPM

0 1 2 3 4 5 6 7 8

x 10 -4

-04

-02

0

02

04

06

08

1

12

14

16




vo

48 5 52 54 56 58

10-4

138

14

142

144

146

148

15

152

154

156

vo

Matlabfixed-point

toolbox






UPM



00011111b0 =


Meanerror

22 143143 5252

11 333333 170170

44 3232 0606

33 6767 1717


615615 105ns105ns

12481248 168ns168ns

Mp ts

Example

160160 012ms012ms

113113 011ms011ms1


zz

( )1

222 353


zz


00101000b0 = k53

k5


00101001b0 = k853

k8

k5


222

333



00100000b0 = k3 e2 sdotminus111


1rsquos

23


UPM





D QEN

new_cycle Xek

b0

D QEN

new_cycle Xek-1

b1

+

D QEN

new_cycle Xdk-1

a1

D QEN

new_cycle Xdk-2

b2

+ D QENnew_cycle

dk

+


D Q

D Q

D Q

D Q

D Q

D Q






UPM

Fixed-point toolbox







MatlabSimulink



24


UPM

VHDL or VHDL-AMS











UPM


Applications333



323322

333333

25


UPM


IinVin

Vout

DCDCREGULATOR LO

AD

~

IoutIin


Vout

+_Vin

CONTROL

d

R1

R2

R3

R4

n1 n2LINE

LOAD

Main Switch

Vin

Iin Vout

PO=50Wf=50kHz


PO=50Wf=50kHz



UPM





Adaptive control


LOA

D

~

IoutIin

PFC CONVERTERVout

+_Vin

Controlblock

Controlblock

onoff

R1

R2

R3

R4

Vout

Iin

Vin

ADCADC

ADC

26


UPM


X


IIN-ref

Protections


VOUT max

IIN max

ldquodrdquo max

ldquoΔdrdquo max

ON-OFF Main Switch

ON-OFF Main Switch





intΣIin

gt

CalculatedOn-Off


Max






VOUT-ref

GinPI


UPM










VinGin

Multiplier

xVin

Gin(1Rin)

50 kHz



Adder

+Iin

ΣIin

Comparator

gtOnOff

20 MHz

NoPWMNoPWM


27


UPM




10 W 30 W 50 W 30 W 10 W

Vout

IinGin

StableStable

Load


Unstable

Unstable

Unstable

Unstable


UPM




Adaptive control

28


UPM



Load Change

Vout

Iin




T



UPM

Vin_dc

Iin_dc

d

Vout


OnOff

FPGAXilinx

XC4010-e

8 8 12

Vin Vout Iin

PROMXC 17512

ADC0808

ADC0808

HI 5805


ADCsADCs

Power Converter

Vout Vin_acIin_ac

PF = 099PF = 099PF = 099

29


UPM


DigitalController


switches)Digital


Measuredamp State


Analog

ADConverter

MeasuredVariables

(digital buses)

Mixed




UPM


M1

C Vout

D11n

+

_Vin

Iin

IL1

RL

IR

ON

L1OFF

M1

C Vout

D11n

+

_Vin

Iin

IL1

RL

IR

OFF

L1ON

Vout

n

ID1 = IL1 n

IC



1

kin1k1Lk1L

1L1in L

tVII

dtdILV

Δsdot+=rArr= minus

CtI

VVdt

dVCI kR1koutkout

outR


1

1kout1k1Lk1L

1L1

out

LntV

IIdt

dILnV

sdotΔsdot


minus

C

tIn

I

VVdt

dVCInI kR

1k1L

1koutkoutout

R1L

Δsdot⎟⎟⎠

⎞⎜⎜⎝

⎛minus

+=rArr=minus

minus

minus



30


UPM


VHDLVHDLVHDL

VHDL-AMS

VHDLVHDL--AMSAMS






UPM




VHDLVHDL








Simulationtime


CPU time using VHDL

models


modelsmodels



VHDL speed VHDL-AMS

speed


speedspeed

10 ms10 10 msms 69 s69 s69 s 446 s446 s446 s 641641641

100 ms100 100 msms 700 s700 s700 s 6912 s6912 s6912 s 987987987

1000 ms1000 1000 msms 6890 s6890 s6890 s 68443 s68443 s68443 s 993993993

VHDLVHDL--AMSAMS

31


UPM

42V 14V

CC

CC 42V 14V


system vehicles


Q1-1

Q2-1

Q16-1

Q16-2

Q2-2

Q1-2

L

L

L

COCIN




UPM


Q1-1

Q2-1

Q16-1

Q16-2

Q2-2

Q1-2

L

L

L

COCIN








3 prototypes


3 prototypes



32


UPM


VoVIN

L2d2

d1L1




VINd1

Battery

R1

R2

+

+ +

VINd2

1

BAT1IN1 R

VdVI minus=

2

22 R

VdVI BATIN -=


UPM







446

416

03360

03528

320

2336



1 5

CCM ndash 1000W

824

184

Not acceptable


Q1-1

Q2-1

Q16-1

Q16-2

Q2-2

Q1-2

L

L

L

33


UPM

AVGLI AVGLI


dT T

LVV OIN minus

LVOminus

AVGLI

dT T

LVV OIN minus

LVOminus

AVGLI

⎟⎟⎠

⎞⎜⎜⎝

⎛ minus=

O

OIN

i

2iIN

i VVV

fL2dVI



AVGLI AVGLI

DCMDCM


UPM


03360

03528






416

824



1 5

CCM ndash 1000W

0262002623

0275102649


1 5

DCM ndash 1000W

Not acceptable

445

490

446

454

110102

Very good


34


UPM



420 97

435 100

440 101

435 -

DC Current(A)

429 99

428 98

446 103

460 106

Deviation()

Phase 2

Phase 3

Phase 4

Phase 5

Phase 6

Phase 7

Phase 8

Average

CCM


IO=35A




UPM


ADCInterface

ampfilter

Regulator8

d1


Vout

ADCcontrol

Reset

Vin

12

MCDgenerator

12

Vout

12

Vin

Phase-shifter

8

d2

Protections

1616

Clock

16

H-Pulses L-Pulses




35


UPM




422 97

438 101

442 102

434 -

DC Current(A)

431 99

445 102

424 98

448 103

Deviation()

Phase 2Phase 2

Phase 3Phase 3

Phase 4Phase 4

Phase 5Phase 5

Phase 6Phase 6

Phase 7Phase 7

Phase 8Phase 8

AverageAverage

DCMDCM


IO=17A

IO=27A


UPM





36


UPM


-05

0

05

1

15

2

00E+00 50E-06 10E-05 15E-05 20E-05 25E-05t (s)

()

-05

0

05

1

15

2

00E+00 50E-06 10E-05 15E-05 20E-05 25E-05t (s)

()

0

20

40

60

80

100

120

140

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35

Phase number

[+6-8]

0

20

40

60

80

100

120

140

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35

Phase number

[+6-8]

Half load(500W)


Full load(1000W)

0

1

2

3

4

p

0 5μs 10μs 15μs 20μs0

1

2

3

4

p



0

20

40

60

80

100

120

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35

Phase number

+10-75

0

20

40

60

80

100

120

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35

Phase number

+10-75



UPM

Output currentDC AC

11App

70ADC


is

0 01 02 03 04 05 06 07 08 09 100102030405

060708091

Duty cycle (d)

Nor

m c

urre

nt r

ippl

e Dutyvariation

2 phases

3 phases



37


UPM

10

5

5

10

3T0 x

5

5

3T0 x

Ideal case






10

5

5

10

3T0 x

5

5

3T0 x

Non-ideal



10

5

5

10

3T0 x

5

5

3T0 x

Worse case



10

5

5

10

3T0 x

5

5

3T0 x





UPM

ΔIP-P= 40A (5Adiv)

1 phase

ΔIP-P= 12A (5Adiv)

2 phases

ΔIP-P= 5A (5Adiv)

4 phases

ΔIP-P= 22A (1Adiv)

8 phases

ΔIP-P= 16A (1Adiv)

16 phases



38


UPM

(a)

30

31

22 40

37

22 33

2830

31

22 40

37

22 33

28

(a)

Center of mass

(a)

30

31

22 40

37

22 33

2830

31

22 40

37

22 33

28

(a)

Center of mass

Phase1Phase

2

Phase3

Phase4

Phase5

Phase6

Phase7

Phase8

1st

2nd

3rd 4th

6th

5th 8th

7th

(b)

1st

2nd

3rd 4th

6th

5th 8th

7th

1st

2nd

3rd 4th

6th

5th 8th

7th

(b)

40 A

37 A30 A

33 A

22 A 28 A

31 A

22 A






UPM

18 0 18

18

18

OVERALL 67A

18 0 18

18

18

1

2

34

56

7

8

9

10

1112 13

14

15

16

MAX

MIN

18 0 18

18

18

OVERALL 05A

18 0 18

18

18

1

2

34

56

7

8

9

10

1112 13

1415

16

MAX

MIN


16151413121110987654321

Phase number

165155177152140144148128147122154158139149142133

Current ripple (A)

39


UPM

ΔIP-P= 40A

ΔIP-P= 40A

ΔIP-P= 07A

ΔIP-P= 16A

57

ΔIP-P= 11A

ΔIP-P= 22A

50

ΔIP-P= 28A

ΔIP-P= 5A

44

ΔIP-P= 11A

ΔIP-P= 12A

9






1 2 4 8 16



UPM


Tswitch

delay

Load

voutvin



COUNTERDUTY CYCLE

DRIVING SIGNAL

Load

voutvin



40


UPM



Dri

vin

gsi

gnal

s

Counter

+ hellip +


Duty cycle





UPM


Dri

vin

gD

rivi

ng

sign

als

sign

als



ltDuty cycle


Shift Register



Counter


41


UPM






ASIC

12 12 phasesphases

6 6 phasesphases

24 24 phasesphases





0

2000

4000

6000

8000

10000

12000

14000

16000

2 4 6 8 12 16 20 24

0

2000

4000

6000

8000

10000

12000

2 4 6 8 12 16 20 24

0

2000

4000

6000

8000

10000

12000

14000

16000

18000

2 4 6 8 12 16 20 24


Res

ol 1

28Res

ol 2

56Res

ol 5

12

FPGA

Equ

ival

ent

gate

s

Phases

0

200

400

600

800

1000

2 4 6 8 12 16 20 24


Res

ol 1

28Res

ol 2

56Res

ol 5

120

200

400

600

800

1000

1200

2 4 6 8 12 16 20 24

0

200

400

600

800

1000

1200

1400

2 4 6 8 12 16 20 24

ASIC

Equ

ival

ent

gate

s

Phases


UPM


0

10

20

30

40

50

0 20 40 60 80



0

10

20

30

40

50

0 20 40 60 80



Iout

Pow

erlo

sses

(W)

80

84

88

92

96

0 10 20 30 40 50 60 70 80

6 phases

8 phases12 phases

16 phases

4 phases



Iout

Effic

ienc

y(

)

80

84

88

92

96

0 10 20 30 40 50 60 70 80

6 phases

8 phases12 phases

16 phases

4 phases



Iout

Effic

ienc

y(

)



42


UPM





UPM


RFAmp

Pow

erSt

age

Control

iRF

vs

VS

variable VS


24V

9Vfmax=35kHz

Input voltage = 28V





43


UPM


Cs

M1

L

M2

Cs

M1

L

M2

Cs

M1

L

M2

Cs

M1

L

M2

Ve Vout

CAR

GA




UPM


SW

CLK

ff Resolution =

Pipeline

fCLK

f = 25MHz f = 45MHz

Resolution required



fselected = 32MHz


44


UPM

33 33 DitherDither

SW

CLK

ff Resolution gt

d = 42

d =43

d =425

T=2TSW=8μs

Output voltage

2 solutions

V=50mV

TSW=4μs 1 solution

T=4μs

Output voltage

V=25mV

SW

CLKNVirtual



Average duty cycle

It gives 1 more bit


UPM



SimulatedSimulated

MeasuredMeasured



)(

4110780250 22




45


UPM






UPM


f = 200Hz f = 15kHz

f = 3kHz f = 5kHz

46


UPM





UPM



2 2 micromicross

Vo

1 V

2 V

VRM for DVS5 V

Io = 20 A max

1V - 2 V

Io

02 V max02 V max

0 A

20 A

500 Amicros

Vo




47


UPM


10-1 100 101

100

L-C diagram

C2 micros

200 mV

20A




C = 35 C = 35 μμFF



UPM






fsw = 520 kHz

(125 mΩ eq Rds_on)





48


UPM


0

1

To drivers

New vref

vo dig

N-phases_tran

N-phases

New vref

vo dig

New vref

vo dig


ic


NON-LINEAR CONTROL





UPM


vref

vo

0

1

To drivers

clk_sample

clk_sample

ADC

N-phases_tran

N-phases

vo dig

LINEAR CONTROL



49


UPM


vref

vo

0

1

To drivers

New vref

vo dig

clk_sample

clk_sample

ADC

N-phases_tran

N-phases

vo dig

New vref

LINEAR CONTROL

NON-LINEAR CONTROL

vo dig

New vrefvo dig


ic



Beware


UPM


UpUp--stepstep

ConverterFPGA

tt11



DownDown--stepstep

t1 t2 t1 t2

ddnn

tt22vref

500 kHz

LUT


05

1

15

2

25

0 02 04 06 08 1 12 14 16 18-10

0

10

20

30

40

50

ton toff

Tmin

05

1

15

2

25

0 02 04 06 08 1 12 14 16 18-10

0

10

20

30

40

50

ton toff

Tmin

i L(A

)i L

(A)

V o(V

)V o

(V)


50


UPM


t1 t2 t1 t2

094 096 098 1 102 104 106 108 11

x 10-4

14

16

18

2

22

24

26

28

3

32

094 096 098 1 102 104 106 108 11

x 10-4

0

1

2

3

4

5092 094 096 098 1 102 104 106 108 11 112

x 10-4

14

16

18

2

22

24

26

28

3

32

092 094 096 098 1 102 104 106 108 11 112

x 10-4

0

05

1

15

2

25

3

35

4

45

Transient





Beware


UPM

ΔIo

iL

Io

vo

ic 0 ATrip point 1

Trip point 2

ΔIo

ic





51


UPM


05358z02236z07417)(z3767G(z) 2 +sdotminus

+sdot=

B G(s)

G(z)




N = 4

ESR = 125 mΩ

( )CL

1sRESRL1s

CL1)1sCESR(V

)s(Gdv

L2

ino

sdot+sdot+sdot+


==

~ VinmiddotdCo

ESR

RphaseN LphaseN

Expected by design


DC resistance


model


Beware


UPM


Pole-Zero Map

Real Axis

-1 -08 -06 -04 -02 0 02 04 06 08 1-1

-08

-06

-04

-02

0

02

04

06

08

1

09

0807060504

03

02

01

26e5

234e5

208e5

182e5

156e513e5

104e5

781e4

521e4

26e4

26e5

234e5

208e5

182e5

156e513e5

104e5

781e4

521e4

26e4

x

x

x




Duty cycle

30 micros


1z00372)z(Rminus

=

1zK)z(R 1

minus=

Controller delay

05358z02236z07417)(z3767G(z) 2 +sdotminus

+sdot=Converter

x

x

x Duty cycle

Output voltage

52


UPM

10 micros


xx

x

x

x

x

x

x




00775)(z1)(z037)(z00378R(z)

minussdotminus+sdot

=

Duty cycle

Output voltage


UPM


75 micros

xx

x

x

x

xx

x



minussdotminus+sdot

=

53


UPM


Duty

a1 = -0922548 b1 = 0037759b2 = 0051742a2 = 0

b1

b2

δ-1

δ-1

δ-1

a1

a2

Error

bn0

No b0

δ-1

Z-1

+

00775)(z1)(z037)(z00378R(z)

minussdotminus+sdot

=




UPM


z2d_m ( tf ([00378 0013986] [1 -10775 00775] 192e-6) )




=Tsample = Tsw

⎪⎩

⎪⎨⎧

rarrδ

+=δ δδ

s


54


UPM


Reference

Switched model

7 bits

8 bits

Not quantizied


PWM

ADC

111






UPM

Reference


PWM

ADC






hellip

222

55


UPM



a1 = -0922548 b1 = 0037759b2 = 0051742a2 = 0

b1

b2

δ-1

δ-1

δ-1

a1

a2

Error

bn0

No b0


UPM


0lt Duty cycle lt1


Hardware adders






Beware

56


UPM

0 1 2 30

05

1

15

2

25








UPM



0 1 2 3

x 10-4

0

05

1

15

2

25

100 usdiv100 usdiv



57


UPM






UPM




58


UPM


13 14 15 16 17 18 19

x 10-4

12

14

16

18

2

22

08 V drop

10 microsdiv

2 V





UPM



Vo

1 V

2 V



11 A11 A

20 mV

520 kHz



59


UPM


Vo

Io

200 mV







UPM


Vo

1 V

2 V





60


UPM





Beware



UPM



20


UPM

Z-1

a1

a2

Z-1


Z-1

bo

eK

Z-1

b1

b2

R1(z) R2(z)YK

dK

eK

R1 R2

Z-1

Z-1

a1

bo

b1

dKeK






UPM

Difference equation


a1a2

e(z)

⎩⎨⎧

rarrδ

+=δminus=δ= δδ+


TXXXmiddotY kkkk1k

kk

Tz1 1minusminus

=δ

k1

1k

1k Y

z1zTYXminus

minusminus

minus

sdot=δ=

δ-1 δ-1

aman

δ-1 δ-1

bm

+

bo

b1

u(z)h(z)

T Z-1

δ-1

(Integral)

+




More adders

21


UPM

a1

a2

δ-1

bo

b1T

b2T2 δ-1 T2

T


Tn Tn


Z-1

+



Adapted δ-1


UPM








ek-1 isrequested

ek-1 isavailable

dk isimposed

T

22


UPM

0 1 2 3 4 5 6 7 8

x 10 -4

-04

-02

0

02

04

06

08

1

12

14

16




vo

48 5 52 54 56 58

10-4

138

14

142

144

146

148

15

152

154

156

vo

Matlabfixed-point

toolbox






UPM



00011111b0 =


Meanerror

22 143143 5252

11 333333 170170

44 3232 0606

33 6767 1717


615615 105ns105ns

12481248 168ns168ns

Mp ts

Example

160160 012ms012ms

113113 011ms011ms1


zz

( )1

222 353


zz


00101000b0 = k53

k5


00101001b0 = k853

k8

k5


222

333



00100000b0 = k3 e2 sdotminus111


1rsquos

23


UPM





D QEN

new_cycle Xek

b0

D QEN

new_cycle Xek-1

b1

+

D QEN

new_cycle Xdk-1

a1

D QEN

new_cycle Xdk-2

b2

+ D QENnew_cycle

dk

+


D Q

D Q

D Q

D Q

D Q

D Q






UPM

Fixed-point toolbox







MatlabSimulink



24


UPM

VHDL or VHDL-AMS











UPM


Applications333



323322

333333

25


UPM


IinVin

Vout

DCDCREGULATOR LO

AD

~

IoutIin


Vout

+_Vin

CONTROL

d

R1

R2

R3

R4

n1 n2LINE

LOAD

Main Switch

Vin

Iin Vout

PO=50Wf=50kHz


PO=50Wf=50kHz



UPM





Adaptive control


LOA

D

~

IoutIin

PFC CONVERTERVout

+_Vin

Controlblock

Controlblock

onoff

R1

R2

R3

R4

Vout

Iin

Vin

ADCADC

ADC

26


UPM


X


IIN-ref

Protections


VOUT max

IIN max

ldquodrdquo max

ldquoΔdrdquo max

ON-OFF Main Switch

ON-OFF Main Switch





intΣIin

gt

CalculatedOn-Off


Max






VOUT-ref

GinPI


UPM










VinGin

Multiplier

xVin

Gin(1Rin)

50 kHz



Adder

+Iin

ΣIin

Comparator

gtOnOff

20 MHz

NoPWMNoPWM


27


UPM




10 W 30 W 50 W 30 W 10 W

Vout

IinGin

StableStable

Load


Unstable

Unstable

Unstable

Unstable


UPM




Adaptive control

28


UPM



Load Change

Vout

Iin




T



UPM

Vin_dc

Iin_dc

d

Vout


OnOff

FPGAXilinx

XC4010-e

8 8 12

Vin Vout Iin

PROMXC 17512

ADC0808

ADC0808

HI 5805


ADCsADCs

Power Converter

Vout Vin_acIin_ac

PF = 099PF = 099PF = 099

29


UPM


DigitalController


switches)Digital


Measuredamp State


Analog

ADConverter

MeasuredVariables

(digital buses)

Mixed




UPM


M1

C Vout

D11n

+

_Vin

Iin

IL1

RL

IR

ON

L1OFF

M1

C Vout

D11n

+

_Vin

Iin

IL1

RL

IR

OFF

L1ON

Vout

n

ID1 = IL1 n

IC



1

kin1k1Lk1L

1L1in L

tVII

dtdILV

Δsdot+=rArr= minus

CtI

VVdt

dVCI kR1koutkout

outR


1

1kout1k1Lk1L

1L1

out

LntV

IIdt

dILnV

sdotΔsdot


minus

C

tIn

I

VVdt

dVCInI kR

1k1L

1koutkoutout

R1L

Δsdot⎟⎟⎠

⎞⎜⎜⎝

⎛minus

+=rArr=minus

minus

minus



30


UPM


VHDLVHDLVHDL

VHDL-AMS

VHDLVHDL--AMSAMS






UPM




VHDLVHDL








Simulationtime


CPU time using VHDL

models


modelsmodels



VHDL speed VHDL-AMS

speed


speedspeed

10 ms10 10 msms 69 s69 s69 s 446 s446 s446 s 641641641

100 ms100 100 msms 700 s700 s700 s 6912 s6912 s6912 s 987987987

1000 ms1000 1000 msms 6890 s6890 s6890 s 68443 s68443 s68443 s 993993993

VHDLVHDL--AMSAMS

31


UPM

42V 14V

CC

CC 42V 14V


system vehicles


Q1-1

Q2-1

Q16-1

Q16-2

Q2-2

Q1-2

L

L

L

COCIN




UPM


Q1-1

Q2-1

Q16-1

Q16-2

Q2-2

Q1-2

L

L

L

COCIN








3 prototypes


3 prototypes



32


UPM


VoVIN

L2d2

d1L1




VINd1

Battery

R1

R2

+

+ +

VINd2

1

BAT1IN1 R

VdVI minus=

2

22 R

VdVI BATIN -=


UPM







446

416

03360

03528

320

2336



1 5

CCM ndash 1000W

824

184

Not acceptable


Q1-1

Q2-1

Q16-1

Q16-2

Q2-2

Q1-2

L

L

L

33


UPM

AVGLI AVGLI


dT T

LVV OIN minus

LVOminus

AVGLI

dT T

LVV OIN minus

LVOminus

AVGLI

⎟⎟⎠

⎞⎜⎜⎝

⎛ minus=

O

OIN

i

2iIN

i VVV

fL2dVI



AVGLI AVGLI

DCMDCM


UPM


03360

03528






416

824



1 5

CCM ndash 1000W

0262002623

0275102649


1 5

DCM ndash 1000W

Not acceptable

445

490

446

454

110102

Very good


34


UPM



420 97

435 100

440 101

435 -

DC Current(A)

429 99

428 98

446 103

460 106

Deviation()

Phase 2

Phase 3

Phase 4

Phase 5

Phase 6

Phase 7

Phase 8

Average

CCM


IO=35A




UPM


ADCInterface

ampfilter

Regulator8

d1


Vout

ADCcontrol

Reset

Vin

12

MCDgenerator

12

Vout

12

Vin

Phase-shifter

8

d2

Protections

1616

Clock

16

H-Pulses L-Pulses




35


UPM




422 97

438 101

442 102

434 -

DC Current(A)

431 99

445 102

424 98

448 103

Deviation()

Phase 2Phase 2

Phase 3Phase 3

Phase 4Phase 4

Phase 5Phase 5

Phase 6Phase 6

Phase 7Phase 7

Phase 8Phase 8

AverageAverage

DCMDCM


IO=17A

IO=27A


UPM





36


UPM


-05

0

05

1

15

2

00E+00 50E-06 10E-05 15E-05 20E-05 25E-05t (s)

()

-05

0

05

1

15

2

00E+00 50E-06 10E-05 15E-05 20E-05 25E-05t (s)

()

0

20

40

60

80

100

120

140

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35

Phase number

[+6-8]

0

20

40

60

80

100

120

140

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35

Phase number

[+6-8]

Half load(500W)


Full load(1000W)

0

1

2

3

4

p

0 5μs 10μs 15μs 20μs0

1

2

3

4

p



0

20

40

60

80

100

120

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35

Phase number

+10-75

0

20

40

60

80

100

120

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35

Phase number

+10-75



UPM

Output currentDC AC

11App

70ADC


is

0 01 02 03 04 05 06 07 08 09 100102030405

060708091

Duty cycle (d)

Nor

m c

urre

nt r

ippl

e Dutyvariation

2 phases

3 phases



37


UPM

10

5

5

10

3T0 x

5

5

3T0 x

Ideal case






10

5

5

10

3T0 x

5

5

3T0 x

Non-ideal



10

5

5

10

3T0 x

5

5

3T0 x

Worse case



10

5

5

10

3T0 x

5

5

3T0 x





UPM

ΔIP-P= 40A (5Adiv)

1 phase

ΔIP-P= 12A (5Adiv)

2 phases

ΔIP-P= 5A (5Adiv)

4 phases

ΔIP-P= 22A (1Adiv)

8 phases

ΔIP-P= 16A (1Adiv)

16 phases



38


UPM

(a)

30

31

22 40

37

22 33

2830

31

22 40

37

22 33

28

(a)

Center of mass

(a)

30

31

22 40

37

22 33

2830

31

22 40

37

22 33

28

(a)

Center of mass

Phase1Phase

2

Phase3

Phase4

Phase5

Phase6

Phase7

Phase8

1st

2nd

3rd 4th

6th

5th 8th

7th

(b)

1st

2nd

3rd 4th

6th

5th 8th

7th

1st

2nd

3rd 4th

6th

5th 8th

7th

(b)

40 A

37 A30 A

33 A

22 A 28 A

31 A

22 A






UPM

18 0 18

18

18

OVERALL 67A

18 0 18

18

18

1

2

34

56

7

8

9

10

1112 13

14

15

16

MAX

MIN

18 0 18

18

18

OVERALL 05A

18 0 18

18

18

1

2

34

56

7

8

9

10

1112 13

1415

16

MAX

MIN


16151413121110987654321

Phase number

165155177152140144148128147122154158139149142133

Current ripple (A)

39


UPM

ΔIP-P= 40A

ΔIP-P= 40A

ΔIP-P= 07A

ΔIP-P= 16A

57

ΔIP-P= 11A

ΔIP-P= 22A

50

ΔIP-P= 28A

ΔIP-P= 5A

44

ΔIP-P= 11A

ΔIP-P= 12A

9






1 2 4 8 16



UPM


Tswitch

delay

Load

voutvin



COUNTERDUTY CYCLE

DRIVING SIGNAL

Load

voutvin



40


UPM



Dri

vin

gsi

gnal

s

Counter

+ hellip +


Duty cycle





UPM


Dri

vin

gD

rivi

ng

sign

als

sign

als



ltDuty cycle


Shift Register



Counter


41


UPM






ASIC

12 12 phasesphases

6 6 phasesphases

24 24 phasesphases





0

2000

4000

6000

8000

10000

12000

14000

16000

2 4 6 8 12 16 20 24

0

2000

4000

6000

8000

10000

12000

2 4 6 8 12 16 20 24

0

2000

4000

6000

8000

10000

12000

14000

16000

18000

2 4 6 8 12 16 20 24


Res

ol 1

28Res

ol 2

56Res

ol 5

12

FPGA

Equ

ival

ent

gate

s

Phases

0

200

400

600

800

1000

2 4 6 8 12 16 20 24


Res

ol 1

28Res

ol 2

56Res

ol 5

120

200

400

600

800

1000

1200

2 4 6 8 12 16 20 24

0

200

400

600

800

1000

1200

1400

2 4 6 8 12 16 20 24

ASIC

Equ

ival

ent

gate

s

Phases


UPM


0

10

20

30

40

50

0 20 40 60 80



0

10

20

30

40

50

0 20 40 60 80



Iout

Pow

erlo

sses

(W)

80

84

88

92

96

0 10 20 30 40 50 60 70 80

6 phases

8 phases12 phases

16 phases

4 phases



Iout

Effic

ienc

y(

)

80

84

88

92

96

0 10 20 30 40 50 60 70 80

6 phases

8 phases12 phases

16 phases

4 phases



Iout

Effic

ienc

y(

)



42


UPM





UPM


RFAmp

Pow

erSt

age

Control

iRF

vs

VS

variable VS


24V

9Vfmax=35kHz

Input voltage = 28V





43


UPM


Cs

M1

L

M2

Cs

M1

L

M2

Cs

M1

L

M2

Cs

M1

L

M2

Ve Vout

CAR

GA




UPM


SW

CLK

ff Resolution =

Pipeline

fCLK

f = 25MHz f = 45MHz

Resolution required



fselected = 32MHz


44


UPM

33 33 DitherDither

SW

CLK

ff Resolution gt

d = 42

d =43

d =425

T=2TSW=8μs

Output voltage

2 solutions

V=50mV

TSW=4μs 1 solution

T=4μs

Output voltage

V=25mV

SW

CLKNVirtual



Average duty cycle

It gives 1 more bit


UPM



SimulatedSimulated

MeasuredMeasured



)(

4110780250 22




45


UPM






UPM


f = 200Hz f = 15kHz

f = 3kHz f = 5kHz

46


UPM





UPM



2 2 micromicross

Vo

1 V

2 V

VRM for DVS5 V

Io = 20 A max

1V - 2 V

Io

02 V max02 V max

0 A

20 A

500 Amicros

Vo




47


UPM


10-1 100 101

100

L-C diagram

C2 micros

200 mV

20A




C = 35 C = 35 μμFF



UPM






fsw = 520 kHz

(125 mΩ eq Rds_on)





48


UPM


0

1

To drivers

New vref

vo dig

N-phases_tran

N-phases

New vref

vo dig

New vref

vo dig


ic


NON-LINEAR CONTROL





UPM


vref

vo

0

1

To drivers

clk_sample

clk_sample

ADC

N-phases_tran

N-phases

vo dig

LINEAR CONTROL



49


UPM


vref

vo

0

1

To drivers

New vref

vo dig

clk_sample

clk_sample

ADC

N-phases_tran

N-phases

vo dig

New vref

LINEAR CONTROL

NON-LINEAR CONTROL

vo dig

New vrefvo dig


ic



Beware


UPM


UpUp--stepstep

ConverterFPGA

tt11



DownDown--stepstep

t1 t2 t1 t2

ddnn

tt22vref

500 kHz

LUT


05

1

15

2

25

0 02 04 06 08 1 12 14 16 18-10

0

10

20

30

40

50

ton toff

Tmin

05

1

15

2

25

0 02 04 06 08 1 12 14 16 18-10

0

10

20

30

40

50

ton toff

Tmin

i L(A

)i L

(A)

V o(V

)V o

(V)


50


UPM


t1 t2 t1 t2

094 096 098 1 102 104 106 108 11

x 10-4

14

16

18

2

22

24

26

28

3

32

094 096 098 1 102 104 106 108 11

x 10-4

0

1

2

3

4

5092 094 096 098 1 102 104 106 108 11 112

x 10-4

14

16

18

2

22

24

26

28

3

32

092 094 096 098 1 102 104 106 108 11 112

x 10-4

0

05

1

15

2

25

3

35

4

45

Transient





Beware


UPM

ΔIo

iL

Io

vo

ic 0 ATrip point 1

Trip point 2

ΔIo

ic





51


UPM


05358z02236z07417)(z3767G(z) 2 +sdotminus

+sdot=

B G(s)

G(z)




N = 4

ESR = 125 mΩ

( )CL

1sRESRL1s

CL1)1sCESR(V

)s(Gdv

L2

ino

sdot+sdot+sdot+


==

~ VinmiddotdCo

ESR

RphaseN LphaseN

Expected by design


DC resistance


model


Beware


UPM


Pole-Zero Map

Real Axis

-1 -08 -06 -04 -02 0 02 04 06 08 1-1

-08

-06

-04

-02

0

02

04

06

08

1

09

0807060504

03

02

01

26e5

234e5

208e5

182e5

156e513e5

104e5

781e4

521e4

26e4

26e5

234e5

208e5

182e5

156e513e5

104e5

781e4

521e4

26e4

x

x

x




Duty cycle

30 micros


1z00372)z(Rminus

=

1zK)z(R 1

minus=

Controller delay

05358z02236z07417)(z3767G(z) 2 +sdotminus

+sdot=Converter

x

x

x Duty cycle

Output voltage

52


UPM

10 micros


xx

x

x

x

x

x

x




00775)(z1)(z037)(z00378R(z)

minussdotminus+sdot

=

Duty cycle

Output voltage


UPM


75 micros

xx

x

x

x

xx

x



minussdotminus+sdot

=

53


UPM


Duty

a1 = -0922548 b1 = 0037759b2 = 0051742a2 = 0

b1

b2

δ-1

δ-1

δ-1

a1

a2

Error

bn0

No b0

δ-1

Z-1

+

00775)(z1)(z037)(z00378R(z)

minussdotminus+sdot

=




UPM


z2d_m ( tf ([00378 0013986] [1 -10775 00775] 192e-6) )




=Tsample = Tsw

⎪⎩

⎪⎨⎧

rarrδ

+=δ δδ

s


54


UPM


Reference

Switched model

7 bits

8 bits

Not quantizied


PWM

ADC

111






UPM

Reference


PWM

ADC






hellip

222

55


UPM



a1 = -0922548 b1 = 0037759b2 = 0051742a2 = 0

b1

b2

δ-1

δ-1

δ-1

a1

a2

Error

bn0

No b0


UPM


0lt Duty cycle lt1


Hardware adders






Beware

56


UPM

0 1 2 30

05

1

15

2

25








UPM



0 1 2 3

x 10-4

0

05

1

15

2

25

100 usdiv100 usdiv



57


UPM






UPM




58


UPM


13 14 15 16 17 18 19

x 10-4

12

14

16

18

2

22

08 V drop

10 microsdiv

2 V





UPM



Vo

1 V

2 V



11 A11 A

20 mV

520 kHz



59


UPM


Vo

Io

200 mV







UPM


Vo

1 V

2 V





60


UPM





Beware



UPM



21


UPM

a1

a2

δ-1

bo

b1T

b2T2 δ-1 T2

T


Tn Tn


Z-1

+



Adapted δ-1


UPM








ek-1 isrequested

ek-1 isavailable

dk isimposed

T

22


UPM

0 1 2 3 4 5 6 7 8

x 10 -4

-04

-02

0

02

04

06

08

1

12

14

16




vo

48 5 52 54 56 58

10-4

138

14

142

144

146

148

15

152

154

156

vo

Matlabfixed-point

toolbox






UPM



00011111b0 =


Meanerror

22 143143 5252

11 333333 170170

44 3232 0606

33 6767 1717


615615 105ns105ns

12481248 168ns168ns

Mp ts

Example

160160 012ms012ms

113113 011ms011ms1


zz

( )1

222 353


zz


00101000b0 = k53

k5


00101001b0 = k853

k8

k5


222

333



00100000b0 = k3 e2 sdotminus111


1rsquos

23


UPM





D QEN

new_cycle Xek

b0

D QEN

new_cycle Xek-1

b1

+

D QEN

new_cycle Xdk-1

a1

D QEN

new_cycle Xdk-2

b2

+ D QENnew_cycle

dk

+


D Q

D Q

D Q

D Q

D Q

D Q






UPM

Fixed-point toolbox







MatlabSimulink



24


UPM

VHDL or VHDL-AMS











UPM


Applications333



323322

333333

25


UPM


IinVin

Vout

DCDCREGULATOR LO

AD

~

IoutIin


Vout

+_Vin

CONTROL

d

R1

R2

R3

R4

n1 n2LINE

LOAD

Main Switch

Vin

Iin Vout

PO=50Wf=50kHz


PO=50Wf=50kHz



UPM





Adaptive control


LOA

D

~

IoutIin

PFC CONVERTERVout

+_Vin

Controlblock

Controlblock

onoff

R1

R2

R3

R4

Vout

Iin

Vin

ADCADC

ADC

26


UPM


X


IIN-ref

Protections


VOUT max

IIN max

ldquodrdquo max

ldquoΔdrdquo max

ON-OFF Main Switch

ON-OFF Main Switch





intΣIin

gt

CalculatedOn-Off


Max






VOUT-ref

GinPI


UPM










VinGin

Multiplier

xVin

Gin(1Rin)

50 kHz



Adder

+Iin

ΣIin

Comparator

gtOnOff

20 MHz

NoPWMNoPWM


27


UPM




10 W 30 W 50 W 30 W 10 W

Vout

IinGin

StableStable

Load


Unstable

Unstable

Unstable

Unstable


UPM




Adaptive control

28


UPM



Load Change

Vout

Iin




T



UPM

Vin_dc

Iin_dc

d

Vout


OnOff

FPGAXilinx

XC4010-e

8 8 12

Vin Vout Iin

PROMXC 17512

ADC0808

ADC0808

HI 5805


ADCsADCs

Power Converter

Vout Vin_acIin_ac

PF = 099PF = 099PF = 099

29


UPM


DigitalController


switches)Digital


Measuredamp State


Analog

ADConverter

MeasuredVariables

(digital buses)

Mixed




UPM


M1

C Vout

D11n

+

_Vin

Iin

IL1

RL

IR

ON

L1OFF

M1

C Vout

D11n

+

_Vin

Iin

IL1

RL

IR

OFF

L1ON

Vout

n

ID1 = IL1 n

IC



1

kin1k1Lk1L

1L1in L

tVII

dtdILV

Δsdot+=rArr= minus

CtI

VVdt

dVCI kR1koutkout

outR


1

1kout1k1Lk1L

1L1

out

LntV

IIdt

dILnV

sdotΔsdot


minus

C

tIn

I

VVdt

dVCInI kR

1k1L

1koutkoutout

R1L

Δsdot⎟⎟⎠

⎞⎜⎜⎝

⎛minus

+=rArr=minus

minus

minus



30


UPM


VHDLVHDLVHDL

VHDL-AMS

VHDLVHDL--AMSAMS






UPM




VHDLVHDL








Simulationtime


CPU time using VHDL

models


modelsmodels



VHDL speed VHDL-AMS

speed


speedspeed

10 ms10 10 msms 69 s69 s69 s 446 s446 s446 s 641641641

100 ms100 100 msms 700 s700 s700 s 6912 s6912 s6912 s 987987987

1000 ms1000 1000 msms 6890 s6890 s6890 s 68443 s68443 s68443 s 993993993

VHDLVHDL--AMSAMS

31


UPM

42V 14V

CC

CC 42V 14V


system vehicles


Q1-1

Q2-1

Q16-1

Q16-2

Q2-2

Q1-2

L

L

L

COCIN




UPM


Q1-1

Q2-1

Q16-1

Q16-2

Q2-2

Q1-2

L

L

L

COCIN








3 prototypes


3 prototypes



32


UPM


VoVIN

L2d2

d1L1




VINd1

Battery

R1

R2

+

+ +

VINd2

1

BAT1IN1 R

VdVI minus=

2

22 R

VdVI BATIN -=


UPM







446

416

03360

03528

320

2336



1 5

CCM ndash 1000W

824

184

Not acceptable


Q1-1

Q2-1

Q16-1

Q16-2

Q2-2

Q1-2

L

L

L

33


UPM

AVGLI AVGLI


dT T

LVV OIN minus

LVOminus

AVGLI

dT T

LVV OIN minus

LVOminus

AVGLI

⎟⎟⎠

⎞⎜⎜⎝

⎛ minus=

O

OIN

i

2iIN

i VVV

fL2dVI



AVGLI AVGLI

DCMDCM


UPM


03360

03528






416

824



1 5

CCM ndash 1000W

0262002623

0275102649


1 5

DCM ndash 1000W

Not acceptable

445

490

446

454

110102

Very good


34


UPM



420 97

435 100

440 101

435 -

DC Current(A)

429 99

428 98

446 103

460 106

Deviation()

Phase 2

Phase 3

Phase 4

Phase 5

Phase 6

Phase 7

Phase 8

Average

CCM


IO=35A




UPM


ADCInterface

ampfilter

Regulator8

d1


Vout

ADCcontrol

Reset

Vin

12

MCDgenerator

12

Vout

12

Vin

Phase-shifter

8

d2

Protections

1616

Clock

16

H-Pulses L-Pulses




35


UPM




422 97

438 101

442 102

434 -

DC Current(A)

431 99

445 102

424 98

448 103

Deviation()

Phase 2Phase 2

Phase 3Phase 3

Phase 4Phase 4

Phase 5Phase 5

Phase 6Phase 6

Phase 7Phase 7

Phase 8Phase 8

AverageAverage

DCMDCM


IO=17A

IO=27A


UPM





36


UPM


-05

0

05

1

15

2

00E+00 50E-06 10E-05 15E-05 20E-05 25E-05t (s)

()

-05

0

05

1

15

2

00E+00 50E-06 10E-05 15E-05 20E-05 25E-05t (s)

()

0

20

40

60

80

100

120

140

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35

Phase number

[+6-8]

0

20

40

60

80

100

120

140

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35

Phase number

[+6-8]

Half load(500W)


Full load(1000W)

0

1

2

3

4

p

0 5μs 10μs 15μs 20μs0

1

2

3

4

p



0

20

40

60

80

100

120

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35

Phase number

+10-75

0

20

40

60

80

100

120

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35

Phase number

+10-75



UPM

Output currentDC AC

11App

70ADC


is

0 01 02 03 04 05 06 07 08 09 100102030405

060708091

Duty cycle (d)

Nor

m c

urre

nt r

ippl

e Dutyvariation

2 phases

3 phases



37


UPM

10

5

5

10

3T0 x

5

5

3T0 x

Ideal case






10

5

5

10

3T0 x

5

5

3T0 x

Non-ideal



10

5

5

10

3T0 x

5

5

3T0 x

Worse case



10

5

5

10

3T0 x

5

5

3T0 x





UPM

ΔIP-P= 40A (5Adiv)

1 phase

ΔIP-P= 12A (5Adiv)

2 phases

ΔIP-P= 5A (5Adiv)

4 phases

ΔIP-P= 22A (1Adiv)

8 phases

ΔIP-P= 16A (1Adiv)

16 phases



38


UPM

(a)

30

31

22 40

37

22 33

2830

31

22 40

37

22 33

28

(a)

Center of mass

(a)

30

31

22 40

37

22 33

2830

31

22 40

37

22 33

28

(a)

Center of mass

Phase1Phase

2

Phase3

Phase4

Phase5

Phase6

Phase7

Phase8

1st

2nd

3rd 4th

6th

5th 8th

7th

(b)

1st

2nd

3rd 4th

6th

5th 8th

7th

1st

2nd

3rd 4th

6th

5th 8th

7th

(b)

40 A

37 A30 A

33 A

22 A 28 A

31 A

22 A






UPM

18 0 18

18

18

OVERALL 67A

18 0 18

18

18

1

2

34

56

7

8

9

10

1112 13

14

15

16

MAX

MIN

18 0 18

18

18

OVERALL 05A

18 0 18

18

18

1

2

34

56

7

8

9

10

1112 13

1415

16

MAX

MIN


16151413121110987654321

Phase number

165155177152140144148128147122154158139149142133

Current ripple (A)

39


UPM

ΔIP-P= 40A

ΔIP-P= 40A

ΔIP-P= 07A

ΔIP-P= 16A

57

ΔIP-P= 11A

ΔIP-P= 22A

50

ΔIP-P= 28A

ΔIP-P= 5A

44

ΔIP-P= 11A

ΔIP-P= 12A

9






1 2 4 8 16



UPM


Tswitch

delay

Load

voutvin



COUNTERDUTY CYCLE

DRIVING SIGNAL

Load

voutvin



40


UPM



Dri

vin

gsi

gnal

s

Counter

+ hellip +


Duty cycle





UPM


Dri

vin

gD

rivi

ng

sign

als

sign

als



ltDuty cycle


Shift Register



Counter


41


UPM






ASIC

12 12 phasesphases

6 6 phasesphases

24 24 phasesphases





0

2000

4000

6000

8000

10000

12000

14000

16000

2 4 6 8 12 16 20 24

0

2000

4000

6000

8000

10000

12000

2 4 6 8 12 16 20 24

0

2000

4000

6000

8000

10000

12000

14000

16000

18000

2 4 6 8 12 16 20 24


Res

ol 1

28Res

ol 2

56Res

ol 5

12

FPGA

Equ

ival

ent

gate

s

Phases

0

200

400

600

800

1000

2 4 6 8 12 16 20 24


Res

ol 1

28Res

ol 2

56Res

ol 5

120

200

400

600

800

1000

1200

2 4 6 8 12 16 20 24

0

200

400

600

800

1000

1200

1400

2 4 6 8 12 16 20 24

ASIC

Equ

ival

ent

gate

s

Phases


UPM


0

10

20

30

40

50

0 20 40 60 80



0

10

20

30

40

50

0 20 40 60 80



Iout

Pow

erlo

sses

(W)

80

84

88

92

96

0 10 20 30 40 50 60 70 80

6 phases

8 phases12 phases

16 phases

4 phases



Iout

Effic

ienc

y(

)

80

84

88

92

96

0 10 20 30 40 50 60 70 80

6 phases

8 phases12 phases

16 phases

4 phases



Iout

Effic

ienc

y(

)



42


UPM





UPM


RFAmp

Pow

erSt

age

Control

iRF

vs

VS

variable VS


24V

9Vfmax=35kHz

Input voltage = 28V





43


UPM


Cs

M1

L

M2

Cs

M1

L

M2

Cs

M1

L

M2

Cs

M1

L

M2

Ve Vout

CAR

GA




UPM


SW

CLK

ff Resolution =

Pipeline

fCLK

f = 25MHz f = 45MHz

Resolution required



fselected = 32MHz


44


UPM

33 33 DitherDither

SW

CLK

ff Resolution gt

d = 42

d =43

d =425

T=2TSW=8μs

Output voltage

2 solutions

V=50mV

TSW=4μs 1 solution

T=4μs

Output voltage

V=25mV

SW

CLKNVirtual



Average duty cycle

It gives 1 more bit


UPM



SimulatedSimulated

MeasuredMeasured



)(

4110780250 22




45


UPM






UPM


f = 200Hz f = 15kHz

f = 3kHz f = 5kHz

46


UPM





UPM



2 2 micromicross

Vo

1 V

2 V

VRM for DVS5 V

Io = 20 A max

1V - 2 V

Io

02 V max02 V max

0 A

20 A

500 Amicros

Vo




47


UPM


10-1 100 101

100

L-C diagram

C2 micros

200 mV

20A




C = 35 C = 35 μμFF



UPM






fsw = 520 kHz

(125 mΩ eq Rds_on)





48


UPM


0

1

To drivers

New vref

vo dig

N-phases_tran

N-phases

New vref

vo dig

New vref

vo dig


ic


NON-LINEAR CONTROL





UPM


vref

vo

0

1

To drivers

clk_sample

clk_sample

ADC

N-phases_tran

N-phases

vo dig

LINEAR CONTROL



49


UPM


vref

vo

0

1

To drivers

New vref

vo dig

clk_sample

clk_sample

ADC

N-phases_tran

N-phases

vo dig

New vref

LINEAR CONTROL

NON-LINEAR CONTROL

vo dig

New vrefvo dig


ic



Beware


UPM


UpUp--stepstep

ConverterFPGA

tt11



DownDown--stepstep

t1 t2 t1 t2

ddnn

tt22vref

500 kHz

LUT


05

1

15

2

25

0 02 04 06 08 1 12 14 16 18-10

0

10

20

30

40

50

ton toff

Tmin

05

1

15

2

25

0 02 04 06 08 1 12 14 16 18-10

0

10

20

30

40

50

ton toff

Tmin

i L(A

)i L

(A)

V o(V

)V o

(V)


50


UPM


t1 t2 t1 t2

094 096 098 1 102 104 106 108 11

x 10-4

14

16

18

2

22

24

26

28

3

32

094 096 098 1 102 104 106 108 11

x 10-4

0

1

2

3

4

5092 094 096 098 1 102 104 106 108 11 112

x 10-4

14

16

18

2

22

24

26

28

3

32

092 094 096 098 1 102 104 106 108 11 112

x 10-4

0

05

1

15

2

25

3

35

4

45

Transient





Beware


UPM

ΔIo

iL

Io

vo

ic 0 ATrip point 1

Trip point 2

ΔIo

ic





51


UPM


05358z02236z07417)(z3767G(z) 2 +sdotminus

+sdot=

B G(s)

G(z)




N = 4

ESR = 125 mΩ

( )CL

1sRESRL1s

CL1)1sCESR(V

)s(Gdv

L2

ino

sdot+sdot+sdot+


==

~ VinmiddotdCo

ESR

RphaseN LphaseN

Expected by design


DC resistance


model


Beware


UPM


Pole-Zero Map

Real Axis

-1 -08 -06 -04 -02 0 02 04 06 08 1-1

-08

-06

-04

-02

0

02

04

06

08

1

09

0807060504

03

02

01

26e5

234e5

208e5

182e5

156e513e5

104e5

781e4

521e4

26e4

26e5

234e5

208e5

182e5

156e513e5

104e5

781e4

521e4

26e4

x

x

x




Duty cycle

30 micros


1z00372)z(Rminus

=

1zK)z(R 1

minus=

Controller delay

05358z02236z07417)(z3767G(z) 2 +sdotminus

+sdot=Converter

x

x

x Duty cycle

Output voltage

52


UPM

10 micros


xx

x

x

x

x

x

x




00775)(z1)(z037)(z00378R(z)

minussdotminus+sdot

=

Duty cycle

Output voltage


UPM


75 micros

xx

x

x

x

xx

x



minussdotminus+sdot

=

53


UPM


Duty

a1 = -0922548 b1 = 0037759b2 = 0051742a2 = 0

b1

b2

δ-1

δ-1

δ-1

a1

a2

Error

bn0

No b0

δ-1

Z-1

+

00775)(z1)(z037)(z00378R(z)

minussdotminus+sdot

=




UPM


z2d_m ( tf ([00378 0013986] [1 -10775 00775] 192e-6) )




=Tsample = Tsw

⎪⎩

⎪⎨⎧

rarrδ

+=δ δδ

s


54


UPM


Reference

Switched model

7 bits

8 bits

Not quantizied


PWM

ADC

111






UPM

Reference


PWM

ADC






hellip

222

55


UPM



a1 = -0922548 b1 = 0037759b2 = 0051742a2 = 0

b1

b2

δ-1

δ-1

δ-1

a1

a2

Error

bn0

No b0


UPM


0lt Duty cycle lt1


Hardware adders






Beware

56


UPM

0 1 2 30

05

1

15

2

25








UPM



0 1 2 3

x 10-4

0

05

1

15

2

25

100 usdiv100 usdiv



57


UPM






UPM




58


UPM


13 14 15 16 17 18 19

x 10-4

12

14

16

18

2

22

08 V drop

10 microsdiv

2 V





UPM



Vo

1 V

2 V



11 A11 A

20 mV

520 kHz



59


UPM


Vo

Io

200 mV







UPM


Vo

1 V

2 V





60


UPM





Beware



UPM



22


UPM

0 1 2 3 4 5 6 7 8

x 10 -4

-04

-02

0

02

04

06

08

1

12

14

16




vo

48 5 52 54 56 58

10-4

138

14

142

144

146

148

15

152

154

156

vo

Matlabfixed-point

toolbox






UPM



00011111b0 =


Meanerror

22 143143 5252

11 333333 170170

44 3232 0606

33 6767 1717


615615 105ns105ns

12481248 168ns168ns

Mp ts

Example

160160 012ms012ms

113113 011ms011ms1


zz

( )1

222 353


zz


00101000b0 = k53

k5


00101001b0 = k853

k8

k5


222

333



00100000b0 = k3 e2 sdotminus111


1rsquos

23


UPM





D QEN

new_cycle Xek

b0

D QEN

new_cycle Xek-1

b1

+

D QEN

new_cycle Xdk-1

a1

D QEN

new_cycle Xdk-2

b2

+ D QENnew_cycle

dk

+


D Q

D Q

D Q

D Q

D Q

D Q






UPM

Fixed-point toolbox







MatlabSimulink



24


UPM

VHDL or VHDL-AMS











UPM


Applications333



323322

333333

25


UPM


IinVin

Vout

DCDCREGULATOR LO

AD

~

IoutIin


Vout

+_Vin

CONTROL

d

R1

R2

R3

R4

n1 n2LINE

LOAD

Main Switch

Vin

Iin Vout

PO=50Wf=50kHz


PO=50Wf=50kHz



UPM





Adaptive control


LOA

D

~

IoutIin

PFC CONVERTERVout

+_Vin

Controlblock

Controlblock

onoff

R1

R2

R3

R4

Vout

Iin

Vin

ADCADC

ADC

26


UPM


X


IIN-ref

Protections


VOUT max

IIN max

ldquodrdquo max

ldquoΔdrdquo max

ON-OFF Main Switch

ON-OFF Main Switch





intΣIin

gt

CalculatedOn-Off


Max






VOUT-ref

GinPI


UPM










VinGin

Multiplier

xVin

Gin(1Rin)

50 kHz



Adder

+Iin

ΣIin

Comparator

gtOnOff

20 MHz

NoPWMNoPWM


27


UPM




10 W 30 W 50 W 30 W 10 W

Vout

IinGin

StableStable

Load


Unstable

Unstable

Unstable

Unstable


UPM




Adaptive control

28


UPM



Load Change

Vout

Iin




T



UPM

Vin_dc

Iin_dc

d

Vout


OnOff

FPGAXilinx

XC4010-e

8 8 12

Vin Vout Iin

PROMXC 17512

ADC0808

ADC0808

HI 5805


ADCsADCs

Power Converter

Vout Vin_acIin_ac

PF = 099PF = 099PF = 099

29


UPM


DigitalController


switches)Digital


Measuredamp State


Analog

ADConverter

MeasuredVariables

(digital buses)

Mixed




UPM


M1

C Vout

D11n

+

_Vin

Iin

IL1

RL

IR

ON

L1OFF

M1

C Vout

D11n

+

_Vin

Iin

IL1

RL

IR

OFF

L1ON

Vout

n

ID1 = IL1 n

IC



1

kin1k1Lk1L

1L1in L

tVII

dtdILV

Δsdot+=rArr= minus

CtI

VVdt

dVCI kR1koutkout

outR


1

1kout1k1Lk1L

1L1

out

LntV

IIdt

dILnV

sdotΔsdot


minus

C

tIn

I

VVdt

dVCInI kR

1k1L

1koutkoutout

R1L

Δsdot⎟⎟⎠

⎞⎜⎜⎝

⎛minus

+=rArr=minus

minus

minus



30


UPM


VHDLVHDLVHDL

VHDL-AMS

VHDLVHDL--AMSAMS






UPM




VHDLVHDL








Simulationtime


CPU time using VHDL

models


modelsmodels



VHDL speed VHDL-AMS

speed


speedspeed

10 ms10 10 msms 69 s69 s69 s 446 s446 s446 s 641641641

100 ms100 100 msms 700 s700 s700 s 6912 s6912 s6912 s 987987987

1000 ms1000 1000 msms 6890 s6890 s6890 s 68443 s68443 s68443 s 993993993

VHDLVHDL--AMSAMS

31


UPM

42V 14V

CC

CC 42V 14V


system vehicles


Q1-1

Q2-1

Q16-1

Q16-2

Q2-2

Q1-2

L

L

L

COCIN




UPM


Q1-1

Q2-1

Q16-1

Q16-2

Q2-2

Q1-2

L

L

L

COCIN








3 prototypes


3 prototypes



32


UPM


VoVIN

L2d2

d1L1




VINd1

Battery

R1

R2

+

+ +

VINd2

1

BAT1IN1 R

VdVI minus=

2

22 R

VdVI BATIN -=


UPM







446

416

03360

03528

320

2336



1 5

CCM ndash 1000W

824

184

Not acceptable


Q1-1

Q2-1

Q16-1

Q16-2

Q2-2

Q1-2

L

L

L

33


UPM

AVGLI AVGLI


dT T

LVV OIN minus

LVOminus

AVGLI

dT T

LVV OIN minus

LVOminus

AVGLI

⎟⎟⎠

⎞⎜⎜⎝

⎛ minus=

O

OIN

i

2iIN

i VVV

fL2dVI



AVGLI AVGLI

DCMDCM


UPM


03360

03528






416

824



1 5

CCM ndash 1000W

0262002623

0275102649


1 5

DCM ndash 1000W

Not acceptable

445

490

446

454

110102

Very good


34


UPM



420 97

435 100

440 101

435 -

DC Current(A)

429 99

428 98

446 103

460 106

Deviation()

Phase 2

Phase 3

Phase 4

Phase 5

Phase 6

Phase 7

Phase 8

Average

CCM


IO=35A




UPM


ADCInterface

ampfilter

Regulator8

d1


Vout

ADCcontrol

Reset

Vin

12

MCDgenerator

12

Vout

12

Vin

Phase-shifter

8

d2

Protections

1616

Clock

16

H-Pulses L-Pulses




35


UPM




422 97

438 101

442 102

434 -

DC Current(A)

431 99

445 102

424 98

448 103

Deviation()

Phase 2Phase 2

Phase 3Phase 3

Phase 4Phase 4

Phase 5Phase 5

Phase 6Phase 6

Phase 7Phase 7

Phase 8Phase 8

AverageAverage

DCMDCM


IO=17A

IO=27A


UPM





36


UPM


-05

0

05

1

15

2

00E+00 50E-06 10E-05 15E-05 20E-05 25E-05t (s)

()

-05

0

05

1

15

2

00E+00 50E-06 10E-05 15E-05 20E-05 25E-05t (s)

()

0

20

40

60

80

100

120

140

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35

Phase number

[+6-8]

0

20

40

60

80

100

120

140

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35

Phase number

[+6-8]

Half load(500W)


Full load(1000W)

0

1

2

3

4

p

0 5μs 10μs 15μs 20μs0

1

2

3

4

p



0

20

40

60

80

100

120

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35

Phase number

+10-75

0

20

40

60

80

100

120

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35

Phase number

+10-75



UPM

Output currentDC AC

11App

70ADC


is

0 01 02 03 04 05 06 07 08 09 100102030405

060708091

Duty cycle (d)

Nor

m c

urre

nt r

ippl

e Dutyvariation

2 phases

3 phases



37


UPM

10

5

5

10

3T0 x

5

5

3T0 x

Ideal case






10

5

5

10

3T0 x

5

5

3T0 x

Non-ideal



10

5

5

10

3T0 x

5

5

3T0 x

Worse case



10

5

5

10

3T0 x

5

5

3T0 x





UPM

ΔIP-P= 40A (5Adiv)

1 phase

ΔIP-P= 12A (5Adiv)

2 phases

ΔIP-P= 5A (5Adiv)

4 phases

ΔIP-P= 22A (1Adiv)

8 phases

ΔIP-P= 16A (1Adiv)

16 phases



38


UPM

(a)

30

31

22 40

37

22 33

2830

31

22 40

37

22 33

28

(a)

Center of mass

(a)

30

31

22 40

37

22 33

2830

31

22 40

37

22 33

28

(a)

Center of mass

Phase1Phase

2

Phase3

Phase4

Phase5

Phase6

Phase7

Phase8

1st

2nd

3rd 4th

6th

5th 8th

7th

(b)

1st

2nd

3rd 4th

6th

5th 8th

7th

1st

2nd

3rd 4th

6th

5th 8th

7th

(b)

40 A

37 A30 A

33 A

22 A 28 A

31 A

22 A






UPM

18 0 18

18

18

OVERALL 67A

18 0 18

18

18

1

2

34

56

7

8

9

10

1112 13

14

15

16

MAX

MIN

18 0 18

18

18

OVERALL 05A

18 0 18

18

18

1

2

34

56

7

8

9

10

1112 13

1415

16

MAX

MIN


16151413121110987654321

Phase number

165155177152140144148128147122154158139149142133

Current ripple (A)

39


UPM

ΔIP-P= 40A

ΔIP-P= 40A

ΔIP-P= 07A

ΔIP-P= 16A

57

ΔIP-P= 11A

ΔIP-P= 22A

50

ΔIP-P= 28A

ΔIP-P= 5A

44

ΔIP-P= 11A

ΔIP-P= 12A

9






1 2 4 8 16



UPM


Tswitch

delay

Load

voutvin



COUNTERDUTY CYCLE

DRIVING SIGNAL

Load

voutvin



40


UPM



Dri

vin

gsi

gnal

s

Counter

+ hellip +


Duty cycle





UPM


Dri

vin

gD

rivi

ng

sign

als

sign

als



ltDuty cycle


Shift Register



Counter


41


UPM






ASIC

12 12 phasesphases

6 6 phasesphases

24 24 phasesphases





0

2000

4000

6000

8000

10000

12000

14000

16000

2 4 6 8 12 16 20 24

0

2000

4000

6000

8000

10000

12000

2 4 6 8 12 16 20 24

0

2000

4000

6000

8000

10000

12000

14000

16000

18000

2 4 6 8 12 16 20 24


Res

ol 1

28Res

ol 2

56Res

ol 5

12

FPGA

Equ

ival

ent

gate

s

Phases

0

200

400

600

800

1000

2 4 6 8 12 16 20 24


Res

ol 1

28Res

ol 2

56Res

ol 5

120

200

400

600

800

1000

1200

2 4 6 8 12 16 20 24

0

200

400

600

800

1000

1200

1400

2 4 6 8 12 16 20 24

ASIC

Equ

ival

ent

gate

s

Phases


UPM


0

10

20

30

40

50

0 20 40 60 80



0

10

20

30

40

50

0 20 40 60 80



Iout

Pow

erlo

sses

(W)

80

84

88

92

96

0 10 20 30 40 50 60 70 80

6 phases

8 phases12 phases

16 phases

4 phases



Iout

Effic

ienc

y(

)

80

84

88

92

96

0 10 20 30 40 50 60 70 80

6 phases

8 phases12 phases

16 phases

4 phases



Iout

Effic

ienc

y(

)



42


UPM





UPM


RFAmp

Pow

erSt

age

Control

iRF

vs

VS

variable VS


24V

9Vfmax=35kHz

Input voltage = 28V





43


UPM


Cs

M1

L

M2

Cs

M1

L

M2

Cs

M1

L

M2

Cs

M1

L

M2

Ve Vout

CAR

GA




UPM


SW

CLK

ff Resolution =

Pipeline

fCLK

f = 25MHz f = 45MHz

Resolution required



fselected = 32MHz


44


UPM

33 33 DitherDither

SW

CLK

ff Resolution gt

d = 42

d =43

d =425

T=2TSW=8μs

Output voltage

2 solutions

V=50mV

TSW=4μs 1 solution

T=4μs

Output voltage

V=25mV

SW

CLKNVirtual



Average duty cycle

It gives 1 more bit


UPM



SimulatedSimulated

MeasuredMeasured



)(

4110780250 22




45


UPM






UPM


f = 200Hz f = 15kHz

f = 3kHz f = 5kHz

46


UPM





UPM



2 2 micromicross

Vo

1 V

2 V

VRM for DVS5 V

Io = 20 A max

1V - 2 V

Io

02 V max02 V max

0 A

20 A

500 Amicros

Vo




47


UPM


10-1 100 101

100

L-C diagram

C2 micros

200 mV

20A




C = 35 C = 35 μμFF



UPM






fsw = 520 kHz

(125 mΩ eq Rds_on)





48


UPM


0

1

To drivers

New vref

vo dig

N-phases_tran

N-phases

New vref

vo dig

New vref

vo dig


ic


NON-LINEAR CONTROL





UPM


vref

vo

0

1

To drivers

clk_sample

clk_sample

ADC

N-phases_tran

N-phases

vo dig

LINEAR CONTROL



49


UPM


vref

vo

0

1

To drivers

New vref

vo dig

clk_sample

clk_sample

ADC

N-phases_tran

N-phases

vo dig

New vref

LINEAR CONTROL

NON-LINEAR CONTROL

vo dig

New vrefvo dig


ic



Beware


UPM


UpUp--stepstep

ConverterFPGA

tt11



DownDown--stepstep

t1 t2 t1 t2

ddnn

tt22vref

500 kHz

LUT


05

1

15

2

25

0 02 04 06 08 1 12 14 16 18-10

0

10

20

30

40

50

ton toff

Tmin

05

1

15

2

25

0 02 04 06 08 1 12 14 16 18-10

0

10

20

30

40

50

ton toff

Tmin

i L(A

)i L

(A)

V o(V

)V o

(V)


50


UPM


t1 t2 t1 t2

094 096 098 1 102 104 106 108 11

x 10-4

14

16

18

2

22

24

26

28

3

32

094 096 098 1 102 104 106 108 11

x 10-4

0

1

2

3

4

5092 094 096 098 1 102 104 106 108 11 112

x 10-4

14

16

18

2

22

24

26

28

3

32

092 094 096 098 1 102 104 106 108 11 112

x 10-4

0

05

1

15

2

25

3

35

4

45

Transient





Beware


UPM

ΔIo

iL

Io

vo

ic 0 ATrip point 1

Trip point 2

ΔIo

ic





51


UPM


05358z02236z07417)(z3767G(z) 2 +sdotminus

+sdot=

B G(s)

G(z)




N = 4

ESR = 125 mΩ

( )CL

1sRESRL1s

CL1)1sCESR(V

)s(Gdv

L2

ino

sdot+sdot+sdot+


==

~ VinmiddotdCo

ESR

RphaseN LphaseN

Expected by design


DC resistance


model


Beware


UPM


Pole-Zero Map

Real Axis

-1 -08 -06 -04 -02 0 02 04 06 08 1-1

-08

-06

-04

-02

0

02

04

06

08

1

09

0807060504

03

02

01

26e5

234e5

208e5

182e5

156e513e5

104e5

781e4

521e4

26e4

26e5

234e5

208e5

182e5

156e513e5

104e5

781e4

521e4

26e4

x

x

x




Duty cycle

30 micros


1z00372)z(Rminus

=

1zK)z(R 1

minus=

Controller delay

05358z02236z07417)(z3767G(z) 2 +sdotminus

+sdot=Converter

x

x

x Duty cycle

Output voltage

52


UPM

10 micros


xx

x

x

x

x

x

x




00775)(z1)(z037)(z00378R(z)

minussdotminus+sdot

=

Duty cycle

Output voltage


UPM


75 micros

xx

x

x

x

xx

x



minussdotminus+sdot

=

53


UPM


Duty

a1 = -0922548 b1 = 0037759b2 = 0051742a2 = 0

b1

b2

δ-1

δ-1

δ-1

a1

a2

Error

bn0

No b0

δ-1

Z-1

+

00775)(z1)(z037)(z00378R(z)

minussdotminus+sdot

=




UPM


z2d_m ( tf ([00378 0013986] [1 -10775 00775] 192e-6) )




=Tsample = Tsw

⎪⎩

⎪⎨⎧

rarrδ

+=δ δδ

s


54


UPM


Reference

Switched model

7 bits

8 bits

Not quantizied


PWM

ADC

111






UPM

Reference


PWM

ADC






hellip

222

55


UPM



a1 = -0922548 b1 = 0037759b2 = 0051742a2 = 0

b1

b2

δ-1

δ-1

δ-1

a1

a2

Error

bn0

No b0


UPM


0lt Duty cycle lt1


Hardware adders






Beware

56


UPM

0 1 2 30

05

1

15

2

25








UPM



0 1 2 3

x 10-4

0

05

1

15

2

25

100 usdiv100 usdiv



57


UPM






UPM




58


UPM


13 14 15 16 17 18 19

x 10-4

12

14

16

18

2

22

08 V drop

10 microsdiv

2 V





UPM



Vo

1 V

2 V



11 A11 A

20 mV

520 kHz



59


UPM


Vo

Io

200 mV







UPM


Vo

1 V

2 V





60


UPM





Beware



UPM



23


UPM





D QEN

new_cycle Xek

b0

D QEN

new_cycle Xek-1

b1

+

D QEN

new_cycle Xdk-1

a1

D QEN

new_cycle Xdk-2

b2

+ D QENnew_cycle

dk

+


D Q

D Q

D Q

D Q

D Q

D Q






UPM

Fixed-point toolbox







MatlabSimulink



24


UPM

VHDL or VHDL-AMS











UPM


Applications333



323322

333333

25


UPM


IinVin

Vout

DCDCREGULATOR LO

AD

~

IoutIin


Vout

+_Vin

CONTROL

d

R1

R2

R3

R4

n1 n2LINE

LOAD

Main Switch

Vin

Iin Vout

PO=50Wf=50kHz


PO=50Wf=50kHz



UPM





Adaptive control


LOA

D

~

IoutIin

PFC CONVERTERVout

+_Vin

Controlblock

Controlblock

onoff

R1

R2

R3

R4

Vout

Iin

Vin

ADCADC

ADC

26


UPM


X


IIN-ref

Protections


VOUT max

IIN max

ldquodrdquo max

ldquoΔdrdquo max

ON-OFF Main Switch

ON-OFF Main Switch





intΣIin

gt

CalculatedOn-Off


Max






VOUT-ref

GinPI


UPM










VinGin

Multiplier

xVin

Gin(1Rin)

50 kHz



Adder

+Iin

ΣIin

Comparator

gtOnOff

20 MHz

NoPWMNoPWM


27


UPM




10 W 30 W 50 W 30 W 10 W

Vout

IinGin

StableStable

Load


Unstable

Unstable

Unstable

Unstable


UPM




Adaptive control

28


UPM



Load Change

Vout

Iin




T



UPM

Vin_dc

Iin_dc

d

Vout


OnOff

FPGAXilinx

XC4010-e

8 8 12

Vin Vout Iin

PROMXC 17512

ADC0808

ADC0808

HI 5805


ADCsADCs

Power Converter

Vout Vin_acIin_ac

PF = 099PF = 099PF = 099

29


UPM


DigitalController


switches)Digital


Measuredamp State


Analog

ADConverter

MeasuredVariables

(digital buses)

Mixed




UPM


M1

C Vout

D11n

+

_Vin

Iin

IL1

RL

IR

ON

L1OFF

M1

C Vout

D11n

+

_Vin

Iin

IL1

RL

IR

OFF

L1ON

Vout

n

ID1 = IL1 n

IC



1

kin1k1Lk1L

1L1in L

tVII

dtdILV

Δsdot+=rArr= minus

CtI

VVdt

dVCI kR1koutkout

outR


1

1kout1k1Lk1L

1L1

out

LntV

IIdt

dILnV

sdotΔsdot


minus

C

tIn

I

VVdt

dVCInI kR

1k1L

1koutkoutout

R1L

Δsdot⎟⎟⎠

⎞⎜⎜⎝

⎛minus

+=rArr=minus

minus

minus



30


UPM


VHDLVHDLVHDL

VHDL-AMS

VHDLVHDL--AMSAMS






UPM




VHDLVHDL








Simulationtime


CPU time using VHDL

models


modelsmodels



VHDL speed VHDL-AMS

speed


speedspeed

10 ms10 10 msms 69 s69 s69 s 446 s446 s446 s 641641641

100 ms100 100 msms 700 s700 s700 s 6912 s6912 s6912 s 987987987

1000 ms1000 1000 msms 6890 s6890 s6890 s 68443 s68443 s68443 s 993993993

VHDLVHDL--AMSAMS

31


UPM

42V 14V

CC

CC 42V 14V


system vehicles


Q1-1

Q2-1

Q16-1

Q16-2

Q2-2

Q1-2

L

L

L

COCIN




UPM


Q1-1

Q2-1

Q16-1

Q16-2

Q2-2

Q1-2

L

L

L

COCIN








3 prototypes


3 prototypes



32


UPM


VoVIN

L2d2

d1L1




VINd1

Battery

R1

R2

+

+ +

VINd2

1

BAT1IN1 R

VdVI minus=

2

22 R

VdVI BATIN -=


UPM







446

416

03360

03528

320

2336



1 5

CCM ndash 1000W

824

184

Not acceptable


Q1-1

Q2-1

Q16-1

Q16-2

Q2-2

Q1-2

L

L

L

33


UPM

AVGLI AVGLI


dT T

LVV OIN minus

LVOminus

AVGLI

dT T

LVV OIN minus

LVOminus

AVGLI

⎟⎟⎠

⎞⎜⎜⎝

⎛ minus=

O

OIN

i

2iIN

i VVV

fL2dVI



AVGLI AVGLI

DCMDCM


UPM


03360

03528






416

824



1 5

CCM ndash 1000W

0262002623

0275102649


1 5

DCM ndash 1000W

Not acceptable

445

490

446

454

110102

Very good


34


UPM



420 97

435 100

440 101

435 -

DC Current(A)

429 99

428 98

446 103

460 106

Deviation()

Phase 2

Phase 3

Phase 4

Phase 5

Phase 6

Phase 7

Phase 8

Average

CCM


IO=35A




UPM


ADCInterface

ampfilter

Regulator8

d1


Vout

ADCcontrol

Reset

Vin

12

MCDgenerator

12

Vout

12

Vin

Phase-shifter

8

d2

Protections

1616

Clock

16

H-Pulses L-Pulses




35


UPM




422 97

438 101

442 102

434 -

DC Current(A)

431 99

445 102

424 98

448 103

Deviation()

Phase 2Phase 2

Phase 3Phase 3

Phase 4Phase 4

Phase 5Phase 5

Phase 6Phase 6

Phase 7Phase 7

Phase 8Phase 8

AverageAverage

DCMDCM


IO=17A

IO=27A


UPM





36


UPM


-05

0

05

1

15

2

00E+00 50E-06 10E-05 15E-05 20E-05 25E-05t (s)

()

-05

0

05

1

15

2

00E+00 50E-06 10E-05 15E-05 20E-05 25E-05t (s)

()

0

20

40

60

80

100

120

140

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35

Phase number

[+6-8]

0

20

40

60

80

100

120

140

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35

Phase number

[+6-8]

Half load(500W)


Full load(1000W)

0

1

2

3

4

p

0 5μs 10μs 15μs 20μs0

1

2

3

4

p



0

20

40

60

80

100

120

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35

Phase number

+10-75

0

20

40

60

80

100

120

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35

Phase number

+10-75



UPM

Output currentDC AC

11App

70ADC


is

0 01 02 03 04 05 06 07 08 09 100102030405

060708091

Duty cycle (d)

Nor

m c

urre

nt r

ippl

e Dutyvariation

2 phases

3 phases



37


UPM

10

5

5

10

3T0 x

5

5

3T0 x

Ideal case






10

5

5

10

3T0 x

5

5

3T0 x

Non-ideal



10

5

5

10

3T0 x

5

5

3T0 x

Worse case



10

5

5

10

3T0 x

5

5

3T0 x





UPM

ΔIP-P= 40A (5Adiv)

1 phase

ΔIP-P= 12A (5Adiv)

2 phases

ΔIP-P= 5A (5Adiv)

4 phases

ΔIP-P= 22A (1Adiv)

8 phases

ΔIP-P= 16A (1Adiv)

16 phases



38


UPM

(a)

30

31

22 40

37

22 33

2830

31

22 40

37

22 33

28

(a)

Center of mass

(a)

30

31

22 40

37

22 33

2830

31

22 40

37

22 33

28

(a)

Center of mass

Phase1Phase

2

Phase3

Phase4

Phase5

Phase6

Phase7

Phase8

1st

2nd

3rd 4th

6th

5th 8th

7th

(b)

1st

2nd

3rd 4th

6th

5th 8th

7th

1st

2nd

3rd 4th

6th

5th 8th

7th

(b)

40 A

37 A30 A

33 A

22 A 28 A

31 A

22 A






UPM

18 0 18

18

18

OVERALL 67A

18 0 18

18

18

1

2

34

56

7

8

9

10

1112 13

14

15

16

MAX

MIN

18 0 18

18

18

OVERALL 05A

18 0 18

18

18

1

2

34

56

7

8

9

10

1112 13

1415

16

MAX

MIN


16151413121110987654321

Phase number

165155177152140144148128147122154158139149142133

Current ripple (A)

39


UPM

ΔIP-P= 40A

ΔIP-P= 40A

ΔIP-P= 07A

ΔIP-P= 16A

57

ΔIP-P= 11A

ΔIP-P= 22A

50

ΔIP-P= 28A

ΔIP-P= 5A

44

ΔIP-P= 11A

ΔIP-P= 12A

9






1 2 4 8 16



UPM


Tswitch

delay

Load

voutvin



COUNTERDUTY CYCLE

DRIVING SIGNAL

Load

voutvin



40


UPM



Dri

vin

gsi

gnal

s

Counter

+ hellip +


Duty cycle





UPM


Dri

vin

gD

rivi

ng

sign

als

sign

als



ltDuty cycle


Shift Register



Counter


41


UPM






ASIC

12 12 phasesphases

6 6 phasesphases

24 24 phasesphases





0

2000

4000

6000

8000

10000

12000

14000

16000

2 4 6 8 12 16 20 24

0

2000

4000

6000

8000

10000

12000

2 4 6 8 12 16 20 24

0

2000

4000

6000

8000

10000

12000

14000

16000

18000

2 4 6 8 12 16 20 24


Res

ol 1

28Res

ol 2

56Res

ol 5

12

FPGA

Equ

ival

ent

gate

s

Phases

0

200

400

600

800

1000

2 4 6 8 12 16 20 24


Res

ol 1

28Res

ol 2

56Res

ol 5

120

200

400

600

800

1000

1200

2 4 6 8 12 16 20 24

0

200

400

600

800

1000

1200

1400

2 4 6 8 12 16 20 24

ASIC

Equ

ival

ent

gate

s

Phases


UPM


0

10

20

30

40

50

0 20 40 60 80



0

10

20

30

40

50

0 20 40 60 80



Iout

Pow

erlo

sses

(W)

80

84

88

92

96

0 10 20 30 40 50 60 70 80

6 phases

8 phases12 phases

16 phases

4 phases



Iout

Effic

ienc

y(

)

80

84

88

92

96

0 10 20 30 40 50 60 70 80

6 phases

8 phases12 phases

16 phases

4 phases



Iout

Effic

ienc

y(

)



42


UPM





UPM


RFAmp

Pow

erSt

age

Control

iRF

vs

VS

variable VS


24V

9Vfmax=35kHz

Input voltage = 28V





43


UPM


Cs

M1

L

M2

Cs

M1

L

M2

Cs

M1

L

M2

Cs

M1

L

M2

Ve Vout

CAR

GA




UPM


SW

CLK

ff Resolution =

Pipeline

fCLK

f = 25MHz f = 45MHz

Resolution required



fselected = 32MHz


44


UPM

33 33 DitherDither

SW

CLK

ff Resolution gt

d = 42

d =43

d =425

T=2TSW=8μs

Output voltage

2 solutions

V=50mV

TSW=4μs 1 solution

T=4μs

Output voltage

V=25mV

SW

CLKNVirtual



Average duty cycle

It gives 1 more bit


UPM



SimulatedSimulated

MeasuredMeasured



)(

4110780250 22




45


UPM






UPM


f = 200Hz f = 15kHz

f = 3kHz f = 5kHz

46


UPM





UPM



2 2 micromicross

Vo

1 V

2 V

VRM for DVS5 V

Io = 20 A max

1V - 2 V

Io

02 V max02 V max

0 A

20 A

500 Amicros

Vo




47


UPM


10-1 100 101

100

L-C diagram

C2 micros

200 mV

20A




C = 35 C = 35 μμFF



UPM






fsw = 520 kHz

(125 mΩ eq Rds_on)





48


UPM


0

1

To drivers

New vref

vo dig

N-phases_tran

N-phases

New vref

vo dig

New vref

vo dig


ic


NON-LINEAR CONTROL





UPM


vref

vo

0

1

To drivers

clk_sample

clk_sample

ADC

N-phases_tran

N-phases

vo dig

LINEAR CONTROL



49


UPM


vref

vo

0

1

To drivers

New vref

vo dig

clk_sample

clk_sample

ADC

N-phases_tran

N-phases

vo dig

New vref

LINEAR CONTROL

NON-LINEAR CONTROL

vo dig

New vrefvo dig


ic



Beware


UPM


UpUp--stepstep

ConverterFPGA

tt11



DownDown--stepstep

t1 t2 t1 t2

ddnn

tt22vref

500 kHz

LUT


05

1

15

2

25

0 02 04 06 08 1 12 14 16 18-10

0

10

20

30

40

50

ton toff

Tmin

05

1

15

2

25

0 02 04 06 08 1 12 14 16 18-10

0

10

20

30

40

50

ton toff

Tmin

i L(A

)i L

(A)

V o(V

)V o

(V)


50


UPM


t1 t2 t1 t2

094 096 098 1 102 104 106 108 11

x 10-4

14

16

18

2

22

24

26

28

3

32

094 096 098 1 102 104 106 108 11

x 10-4

0

1

2

3

4

5092 094 096 098 1 102 104 106 108 11 112

x 10-4

14

16

18

2

22

24

26

28

3

32

092 094 096 098 1 102 104 106 108 11 112

x 10-4

0

05

1

15

2

25

3

35

4

45

Transient





Beware


UPM

ΔIo

iL

Io

vo

ic 0 ATrip point 1

Trip point 2

ΔIo

ic





51


UPM


05358z02236z07417)(z3767G(z) 2 +sdotminus

+sdot=

B G(s)

G(z)




N = 4

ESR = 125 mΩ

( )CL

1sRESRL1s

CL1)1sCESR(V

)s(Gdv

L2

ino

sdot+sdot+sdot+


==

~ VinmiddotdCo

ESR

RphaseN LphaseN

Expected by design


DC resistance


model


Beware


UPM


Pole-Zero Map

Real Axis

-1 -08 -06 -04 -02 0 02 04 06 08 1-1

-08

-06

-04

-02

0

02

04

06

08

1

09

0807060504

03

02

01

26e5

234e5

208e5

182e5

156e513e5

104e5

781e4

521e4

26e4

26e5

234e5

208e5

182e5

156e513e5

104e5

781e4

521e4

26e4

x

x

x




Duty cycle

30 micros


1z00372)z(Rminus

=

1zK)z(R 1

minus=

Controller delay

05358z02236z07417)(z3767G(z) 2 +sdotminus

+sdot=Converter

x

x

x Duty cycle

Output voltage

52


UPM

10 micros


xx

x

x

x

x

x

x




00775)(z1)(z037)(z00378R(z)

minussdotminus+sdot

=

Duty cycle

Output voltage


UPM


75 micros

xx

x

x

x

xx

x



minussdotminus+sdot

=

53


UPM


Duty

a1 = -0922548 b1 = 0037759b2 = 0051742a2 = 0

b1

b2

δ-1

δ-1

δ-1

a1

a2

Error

bn0

No b0

δ-1

Z-1

+

00775)(z1)(z037)(z00378R(z)

minussdotminus+sdot

=




UPM


z2d_m ( tf ([00378 0013986] [1 -10775 00775] 192e-6) )




=Tsample = Tsw

⎪⎩

⎪⎨⎧

rarrδ

+=δ δδ

s


54


UPM


Reference

Switched model

7 bits

8 bits

Not quantizied


PWM

ADC

111






UPM

Reference


PWM

ADC






hellip

222

55


UPM



a1 = -0922548 b1 = 0037759b2 = 0051742a2 = 0

b1

b2

δ-1

δ-1

δ-1

a1

a2

Error

bn0

No b0


UPM


0lt Duty cycle lt1


Hardware adders






Beware

56


UPM

0 1 2 30

05

1

15

2

25








UPM



0 1 2 3

x 10-4

0

05

1

15

2

25

100 usdiv100 usdiv



57


UPM






UPM




58


UPM


13 14 15 16 17 18 19

x 10-4

12

14

16

18

2

22

08 V drop

10 microsdiv

2 V





UPM



Vo

1 V

2 V



11 A11 A

20 mV

520 kHz



59


UPM


Vo

Io

200 mV







UPM


Vo

1 V

2 V





60


UPM





Beware



UPM



24


UPM

VHDL or VHDL-AMS











UPM


Applications333



323322

333333

25


UPM


IinVin

Vout

DCDCREGULATOR LO

AD

~

IoutIin


Vout

+_Vin

CONTROL

d

R1

R2

R3

R4

n1 n2LINE

LOAD

Main Switch

Vin

Iin Vout

PO=50Wf=50kHz


PO=50Wf=50kHz



UPM





Adaptive control


LOA

D

~

IoutIin

PFC CONVERTERVout

+_Vin

Controlblock

Controlblock

onoff

R1

R2

R3

R4

Vout

Iin

Vin

ADCADC

ADC

26


UPM


X


IIN-ref

Protections


VOUT max

IIN max

ldquodrdquo max

ldquoΔdrdquo max

ON-OFF Main Switch

ON-OFF Main Switch





intΣIin

gt

CalculatedOn-Off


Max






VOUT-ref

GinPI


UPM










VinGin

Multiplier

xVin

Gin(1Rin)

50 kHz



Adder

+Iin

ΣIin

Comparator

gtOnOff

20 MHz

NoPWMNoPWM


27


UPM




10 W 30 W 50 W 30 W 10 W

Vout

IinGin

StableStable

Load


Unstable

Unstable

Unstable

Unstable


UPM




Adaptive control

28


UPM



Load Change

Vout

Iin




T



UPM

Vin_dc

Iin_dc

d

Vout


OnOff

FPGAXilinx

XC4010-e

8 8 12

Vin Vout Iin

PROMXC 17512

ADC0808

ADC0808

HI 5805


ADCsADCs

Power Converter

Vout Vin_acIin_ac

PF = 099PF = 099PF = 099

29


UPM


DigitalController


switches)Digital


Measuredamp State


Analog

ADConverter

MeasuredVariables

(digital buses)

Mixed




UPM


M1

C Vout

D11n

+

_Vin

Iin

IL1

RL

IR

ON

L1OFF

M1

C Vout

D11n

+

_Vin

Iin

IL1

RL

IR

OFF

L1ON

Vout

n

ID1 = IL1 n

IC



1

kin1k1Lk1L

1L1in L

tVII

dtdILV

Δsdot+=rArr= minus

CtI

VVdt

dVCI kR1koutkout

outR


1

1kout1k1Lk1L

1L1

out

LntV

IIdt

dILnV

sdotΔsdot


minus

C

tIn

I

VVdt

dVCInI kR

1k1L

1koutkoutout

R1L

Δsdot⎟⎟⎠

⎞⎜⎜⎝

⎛minus

+=rArr=minus

minus

minus



30


UPM


VHDLVHDLVHDL

VHDL-AMS

VHDLVHDL--AMSAMS






UPM




VHDLVHDL








Simulationtime


CPU time using VHDL

models


modelsmodels



VHDL speed VHDL-AMS

speed


speedspeed

10 ms10 10 msms 69 s69 s69 s 446 s446 s446 s 641641641

100 ms100 100 msms 700 s700 s700 s 6912 s6912 s6912 s 987987987

1000 ms1000 1000 msms 6890 s6890 s6890 s 68443 s68443 s68443 s 993993993

VHDLVHDL--AMSAMS

31


UPM

42V 14V

CC

CC 42V 14V


system vehicles


Q1-1

Q2-1

Q16-1

Q16-2

Q2-2

Q1-2

L

L

L

COCIN




UPM


Q1-1

Q2-1

Q16-1

Q16-2

Q2-2

Q1-2

L

L

L

COCIN








3 prototypes


3 prototypes



32


UPM


VoVIN

L2d2

d1L1




VINd1

Battery

R1

R2

+

+ +

VINd2

1

BAT1IN1 R

VdVI minus=

2

22 R

VdVI BATIN -=


UPM







446

416

03360

03528

320

2336



1 5

CCM ndash 1000W

824

184

Not acceptable


Q1-1

Q2-1

Q16-1

Q16-2

Q2-2

Q1-2

L

L

L

33


UPM

AVGLI AVGLI


dT T

LVV OIN minus

LVOminus

AVGLI

dT T

LVV OIN minus

LVOminus

AVGLI

⎟⎟⎠

⎞⎜⎜⎝

⎛ minus=

O

OIN

i

2iIN

i VVV

fL2dVI



AVGLI AVGLI

DCMDCM


UPM


03360

03528






416

824



1 5

CCM ndash 1000W

0262002623

0275102649


1 5

DCM ndash 1000W

Not acceptable

445

490

446

454

110102

Very good


34


UPM



420 97

435 100

440 101

435 -

DC Current(A)

429 99

428 98

446 103

460 106

Deviation()

Phase 2

Phase 3

Phase 4

Phase 5

Phase 6

Phase 7

Phase 8

Average

CCM


IO=35A




UPM


ADCInterface

ampfilter

Regulator8

d1


Vout

ADCcontrol

Reset

Vin

12

MCDgenerator

12

Vout

12

Vin

Phase-shifter

8

d2

Protections

1616

Clock

16

H-Pulses L-Pulses




35


UPM




422 97

438 101

442 102

434 -

DC Current(A)

431 99

445 102

424 98

448 103

Deviation()

Phase 2Phase 2

Phase 3Phase 3

Phase 4Phase 4

Phase 5Phase 5

Phase 6Phase 6

Phase 7Phase 7

Phase 8Phase 8

AverageAverage

DCMDCM


IO=17A

IO=27A


UPM





36


UPM


-05

0

05

1

15

2

00E+00 50E-06 10E-05 15E-05 20E-05 25E-05t (s)

()

-05

0

05

1

15

2

00E+00 50E-06 10E-05 15E-05 20E-05 25E-05t (s)

()

0

20

40

60

80

100

120

140

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35

Phase number

[+6-8]

0

20

40

60

80

100

120

140

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35

Phase number

[+6-8]

Half load(500W)


Full load(1000W)

0

1

2

3

4

p

0 5μs 10μs 15μs 20μs0

1

2

3

4

p



0

20

40

60

80

100

120

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35

Phase number

+10-75

0

20

40

60

80

100

120

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35

Phase number

+10-75



UPM

Output currentDC AC

11App

70ADC


is

0 01 02 03 04 05 06 07 08 09 100102030405

060708091

Duty cycle (d)

Nor

m c

urre

nt r

ippl

e Dutyvariation

2 phases

3 phases



37


UPM

10

5

5

10

3T0 x

5

5

3T0 x

Ideal case






10

5

5

10

3T0 x

5

5

3T0 x

Non-ideal



10

5

5

10

3T0 x

5

5

3T0 x

Worse case



10

5

5

10

3T0 x

5

5

3T0 x





UPM

ΔIP-P= 40A (5Adiv)

1 phase

ΔIP-P= 12A (5Adiv)

2 phases

ΔIP-P= 5A (5Adiv)

4 phases

ΔIP-P= 22A (1Adiv)

8 phases

ΔIP-P= 16A (1Adiv)

16 phases



38


UPM

(a)

30

31

22 40

37

22 33

2830

31

22 40

37

22 33

28

(a)

Center of mass

(a)

30

31

22 40

37

22 33

2830

31

22 40

37

22 33

28

(a)

Center of mass

Phase1Phase

2

Phase3

Phase4

Phase5

Phase6

Phase7

Phase8

1st

2nd

3rd 4th

6th

5th 8th

7th

(b)

1st

2nd

3rd 4th

6th

5th 8th

7th

1st

2nd

3rd 4th

6th

5th 8th

7th

(b)

40 A

37 A30 A

33 A

22 A 28 A

31 A

22 A






UPM

18 0 18

18

18

OVERALL 67A

18 0 18

18

18

1

2

34

56

7

8

9

10

1112 13

14

15

16

MAX

MIN

18 0 18

18

18

OVERALL 05A

18 0 18

18

18

1

2

34

56

7

8

9

10

1112 13

1415

16

MAX

MIN


16151413121110987654321

Phase number

165155177152140144148128147122154158139149142133

Current ripple (A)

39


UPM

ΔIP-P= 40A

ΔIP-P= 40A

ΔIP-P= 07A

ΔIP-P= 16A

57

ΔIP-P= 11A

ΔIP-P= 22A

50

ΔIP-P= 28A

ΔIP-P= 5A

44

ΔIP-P= 11A

ΔIP-P= 12A

9






1 2 4 8 16



UPM


Tswitch

delay

Load

voutvin



COUNTERDUTY CYCLE

DRIVING SIGNAL

Load

voutvin



40


UPM



Dri

vin

gsi

gnal

s

Counter

+ hellip +


Duty cycle





UPM


Dri

vin

gD

rivi

ng

sign

als

sign

als



ltDuty cycle


Shift Register



Counter


41


UPM






ASIC

12 12 phasesphases

6 6 phasesphases

24 24 phasesphases





0

2000

4000

6000

8000

10000

12000

14000

16000

2 4 6 8 12 16 20 24

0

2000

4000

6000

8000

10000

12000

2 4 6 8 12 16 20 24

0

2000

4000

6000

8000

10000

12000

14000

16000

18000

2 4 6 8 12 16 20 24


Res

ol 1

28Res

ol 2

56Res

ol 5

12

FPGA

Equ

ival

ent

gate

s

Phases

0

200

400

600

800

1000

2 4 6 8 12 16 20 24


Res

ol 1

28Res

ol 2

56Res

ol 5

120

200

400

600

800

1000

1200

2 4 6 8 12 16 20 24

0

200

400

600

800

1000

1200

1400

2 4 6 8 12 16 20 24

ASIC

Equ

ival

ent

gate

s

Phases


UPM


0

10

20

30

40

50

0 20 40 60 80



0

10

20

30

40

50

0 20 40 60 80



Iout

Pow

erlo

sses

(W)

80

84

88

92

96

0 10 20 30 40 50 60 70 80

6 phases

8 phases12 phases

16 phases

4 phases



Iout

Effic

ienc

y(

)

80

84

88

92

96

0 10 20 30 40 50 60 70 80

6 phases

8 phases12 phases

16 phases

4 phases



Iout

Effic

ienc

y(

)



42


UPM





UPM


RFAmp

Pow

erSt

age

Control

iRF

vs

VS

variable VS


24V

9Vfmax=35kHz

Input voltage = 28V





43


UPM


Cs

M1

L

M2

Cs

M1

L

M2

Cs

M1

L

M2

Cs

M1

L

M2

Ve Vout

CAR

GA




UPM


SW

CLK

ff Resolution =

Pipeline

fCLK

f = 25MHz f = 45MHz

Resolution required



fselected = 32MHz


44


UPM

33 33 DitherDither

SW

CLK

ff Resolution gt

d = 42

d =43

d =425

T=2TSW=8μs

Output voltage

2 solutions

V=50mV

TSW=4μs 1 solution

T=4μs

Output voltage

V=25mV

SW

CLKNVirtual



Average duty cycle

It gives 1 more bit


UPM



SimulatedSimulated

MeasuredMeasured



)(

4110780250 22




45


UPM






UPM


f = 200Hz f = 15kHz

f = 3kHz f = 5kHz

46


UPM





UPM



2 2 micromicross

Vo

1 V

2 V

VRM for DVS5 V

Io = 20 A max

1V - 2 V

Io

02 V max02 V max

0 A

20 A

500 Amicros

Vo




47


UPM


10-1 100 101

100

L-C diagram

C2 micros

200 mV

20A




C = 35 C = 35 μμFF



UPM






fsw = 520 kHz

(125 mΩ eq Rds_on)





48


UPM


0

1

To drivers

New vref

vo dig

N-phases_tran

N-phases

New vref

vo dig

New vref

vo dig


ic


NON-LINEAR CONTROL





UPM


vref

vo

0

1

To drivers

clk_sample

clk_sample

ADC

N-phases_tran

N-phases

vo dig

LINEAR CONTROL



49


UPM


vref

vo

0

1

To drivers

New vref

vo dig

clk_sample

clk_sample

ADC

N-phases_tran

N-phases

vo dig

New vref

LINEAR CONTROL

NON-LINEAR CONTROL

vo dig

New vrefvo dig


ic



Beware


UPM


UpUp--stepstep

ConverterFPGA

tt11



DownDown--stepstep

t1 t2 t1 t2

ddnn

tt22vref

500 kHz

LUT


05

1

15

2

25

0 02 04 06 08 1 12 14 16 18-10

0

10

20

30

40

50

ton toff

Tmin

05

1

15

2

25

0 02 04 06 08 1 12 14 16 18-10

0

10

20

30

40

50

ton toff

Tmin

i L(A

)i L

(A)

V o(V

)V o

(V)


50


UPM


t1 t2 t1 t2

094 096 098 1 102 104 106 108 11

x 10-4

14

16

18

2

22

24

26

28

3

32

094 096 098 1 102 104 106 108 11

x 10-4

0

1

2

3

4

5092 094 096 098 1 102 104 106 108 11 112

x 10-4

14

16

18

2

22

24

26

28

3

32

092 094 096 098 1 102 104 106 108 11 112

x 10-4

0

05

1

15

2

25

3

35

4

45

Transient





Beware


UPM

ΔIo

iL

Io

vo

ic 0 ATrip point 1

Trip point 2

ΔIo

ic





51


UPM


05358z02236z07417)(z3767G(z) 2 +sdotminus

+sdot=

B G(s)

G(z)




N = 4

ESR = 125 mΩ

( )CL

1sRESRL1s

CL1)1sCESR(V

)s(Gdv

L2

ino

sdot+sdot+sdot+


==

~ VinmiddotdCo

ESR

RphaseN LphaseN

Expected by design


DC resistance


model


Beware


UPM


Pole-Zero Map

Real Axis

-1 -08 -06 -04 -02 0 02 04 06 08 1-1

-08

-06

-04

-02

0

02

04

06

08

1

09

0807060504

03

02

01

26e5

234e5

208e5

182e5

156e513e5

104e5

781e4

521e4

26e4

26e5

234e5

208e5

182e5

156e513e5

104e5

781e4

521e4

26e4

x

x

x




Duty cycle

30 micros


1z00372)z(Rminus

=

1zK)z(R 1

minus=

Controller delay

05358z02236z07417)(z3767G(z) 2 +sdotminus

+sdot=Converter

x

x

x Duty cycle

Output voltage

52


UPM

10 micros


xx

x

x

x

x

x

x




00775)(z1)(z037)(z00378R(z)

minussdotminus+sdot

=

Duty cycle

Output voltage


UPM


75 micros

xx

x

x

x

xx

x



minussdotminus+sdot

=

53


UPM


Duty

a1 = -0922548 b1 = 0037759b2 = 0051742a2 = 0

b1

b2

δ-1

δ-1

δ-1

a1

a2

Error

bn0

No b0

δ-1

Z-1

+

00775)(z1)(z037)(z00378R(z)

minussdotminus+sdot

=




UPM


z2d_m ( tf ([00378 0013986] [1 -10775 00775] 192e-6) )




=Tsample = Tsw

⎪⎩

⎪⎨⎧

rarrδ

+=δ δδ

s


54


UPM


Reference

Switched model

7 bits

8 bits

Not quantizied


PWM

ADC

111






UPM

Reference


PWM

ADC






hellip

222

55


UPM



a1 = -0922548 b1 = 0037759b2 = 0051742a2 = 0

b1

b2

δ-1

δ-1

δ-1

a1

a2

Error

bn0

No b0


UPM


0lt Duty cycle lt1


Hardware adders






Beware

56


UPM

0 1 2 30

05

1

15

2

25








UPM



0 1 2 3

x 10-4

0

05

1

15

2

25

100 usdiv100 usdiv



57


UPM






UPM




58


UPM


13 14 15 16 17 18 19

x 10-4

12

14

16

18

2

22

08 V drop

10 microsdiv

2 V





UPM



Vo

1 V

2 V



11 A11 A

20 mV

520 kHz



59


UPM


Vo

Io

200 mV







UPM


Vo

1 V

2 V





60


UPM





Beware



UPM



25


UPM


IinVin

Vout

DCDCREGULATOR LO

AD

~

IoutIin


Vout

+_Vin

CONTROL

d

R1

R2

R3

R4

n1 n2LINE

LOAD

Main Switch

Vin

Iin Vout

PO=50Wf=50kHz


PO=50Wf=50kHz



UPM





Adaptive control


LOA

D

~

IoutIin

PFC CONVERTERVout

+_Vin

Controlblock

Controlblock

onoff

R1

R2

R3

R4

Vout

Iin

Vin

ADCADC

ADC

26


UPM


X


IIN-ref

Protections


VOUT max

IIN max

ldquodrdquo max

ldquoΔdrdquo max

ON-OFF Main Switch

ON-OFF Main Switch





intΣIin

gt

CalculatedOn-Off


Max






VOUT-ref

GinPI


UPM










VinGin

Multiplier

xVin

Gin(1Rin)

50 kHz



Adder

+Iin

ΣIin

Comparator

gtOnOff

20 MHz

NoPWMNoPWM


27


UPM




10 W 30 W 50 W 30 W 10 W

Vout

IinGin

StableStable

Load


Unstable

Unstable

Unstable

Unstable


UPM




Adaptive control

28


UPM



Load Change

Vout

Iin




T



UPM

Vin_dc

Iin_dc

d

Vout


OnOff

FPGAXilinx

XC4010-e

8 8 12

Vin Vout Iin

PROMXC 17512

ADC0808

ADC0808

HI 5805


ADCsADCs

Power Converter

Vout Vin_acIin_ac

PF = 099PF = 099PF = 099

29


UPM


DigitalController


switches)Digital


Measuredamp State


Analog

ADConverter

MeasuredVariables

(digital buses)

Mixed




UPM


M1

C Vout

D11n

+

_Vin

Iin

IL1

RL

IR

ON

L1OFF

M1

C Vout

D11n

+

_Vin

Iin

IL1

RL

IR

OFF

L1ON

Vout

n

ID1 = IL1 n

IC



1

kin1k1Lk1L

1L1in L

tVII

dtdILV

Δsdot+=rArr= minus

CtI

VVdt

dVCI kR1koutkout

outR


1

1kout1k1Lk1L

1L1

out

LntV

IIdt

dILnV

sdotΔsdot


minus

C

tIn

I

VVdt

dVCInI kR

1k1L

1koutkoutout

R1L

Δsdot⎟⎟⎠

⎞⎜⎜⎝

⎛minus

+=rArr=minus

minus

minus



30


UPM


VHDLVHDLVHDL

VHDL-AMS

VHDLVHDL--AMSAMS






UPM




VHDLVHDL








Simulationtime


CPU time using VHDL

models


modelsmodels



VHDL speed VHDL-AMS

speed


speedspeed

10 ms10 10 msms 69 s69 s69 s 446 s446 s446 s 641641641

100 ms100 100 msms 700 s700 s700 s 6912 s6912 s6912 s 987987987

1000 ms1000 1000 msms 6890 s6890 s6890 s 68443 s68443 s68443 s 993993993

VHDLVHDL--AMSAMS

31


UPM

42V 14V

CC

CC 42V 14V


system vehicles


Q1-1

Q2-1

Q16-1

Q16-2

Q2-2

Q1-2

L

L

L

COCIN




UPM


Q1-1

Q2-1

Q16-1

Q16-2

Q2-2

Q1-2

L

L

L

COCIN








3 prototypes


3 prototypes



32


UPM


VoVIN

L2d2

d1L1




VINd1

Battery

R1

R2

+

+ +

VINd2

1

BAT1IN1 R

VdVI minus=

2

22 R

VdVI BATIN -=


UPM







446

416

03360

03528

320

2336



1 5

CCM ndash 1000W

824

184

Not acceptable


Q1-1

Q2-1

Q16-1

Q16-2

Q2-2

Q1-2

L

L

L

33


UPM

AVGLI AVGLI


dT T

LVV OIN minus

LVOminus

AVGLI

dT T

LVV OIN minus

LVOminus

AVGLI

⎟⎟⎠

⎞⎜⎜⎝

⎛ minus=

O

OIN

i

2iIN

i VVV

fL2dVI



AVGLI AVGLI

DCMDCM


UPM


03360

03528






416

824



1 5

CCM ndash 1000W

0262002623

0275102649


1 5

DCM ndash 1000W

Not acceptable

445

490

446

454

110102

Very good


34


UPM



420 97

435 100

440 101

435 -

DC Current(A)

429 99

428 98

446 103

460 106

Deviation()

Phase 2

Phase 3

Phase 4

Phase 5

Phase 6

Phase 7

Phase 8

Average

CCM


IO=35A




UPM


ADCInterface

ampfilter

Regulator8

d1


Vout

ADCcontrol

Reset

Vin

12

MCDgenerator

12

Vout

12

Vin

Phase-shifter

8

d2

Protections

1616

Clock

16

H-Pulses L-Pulses




35


UPM




422 97

438 101

442 102

434 -

DC Current(A)

431 99

445 102

424 98

448 103

Deviation()

Phase 2Phase 2

Phase 3Phase 3

Phase 4Phase 4

Phase 5Phase 5

Phase 6Phase 6

Phase 7Phase 7

Phase 8Phase 8

AverageAverage

DCMDCM


IO=17A

IO=27A


UPM





36


UPM


-05

0

05

1

15

2

00E+00 50E-06 10E-05 15E-05 20E-05 25E-05t (s)

()

-05

0

05

1

15

2

00E+00 50E-06 10E-05 15E-05 20E-05 25E-05t (s)

()

0

20

40

60

80

100

120

140

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35

Phase number

[+6-8]

0

20

40

60

80

100

120

140

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35

Phase number

[+6-8]

Half load(500W)


Full load(1000W)

0

1

2

3

4

p

0 5μs 10μs 15μs 20μs0

1

2

3

4

p



0

20

40

60

80

100

120

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35

Phase number

+10-75

0

20

40

60

80

100

120

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35

Phase number

+10-75



UPM

Output currentDC AC

11App

70ADC


is

0 01 02 03 04 05 06 07 08 09 100102030405

060708091

Duty cycle (d)

Nor

m c

urre

nt r

ippl

e Dutyvariation

2 phases

3 phases



37


UPM

10

5

5

10

3T0 x

5

5

3T0 x

Ideal case






10

5

5

10

3T0 x

5

5

3T0 x

Non-ideal



10

5

5

10

3T0 x

5

5

3T0 x

Worse case



10

5

5

10

3T0 x

5

5

3T0 x





UPM

ΔIP-P= 40A (5Adiv)

1 phase

ΔIP-P= 12A (5Adiv)

2 phases

ΔIP-P= 5A (5Adiv)

4 phases

ΔIP-P= 22A (1Adiv)

8 phases

ΔIP-P= 16A (1Adiv)

16 phases



38


UPM

(a)

30

31

22 40

37

22 33

2830

31

22 40

37

22 33

28

(a)

Center of mass

(a)

30

31

22 40

37

22 33

2830

31

22 40

37

22 33

28

(a)

Center of mass

Phase1Phase

2

Phase3

Phase4

Phase5

Phase6

Phase7

Phase8

1st

2nd

3rd 4th

6th

5th 8th

7th

(b)

1st

2nd

3rd 4th

6th

5th 8th

7th

1st

2nd

3rd 4th

6th

5th 8th

7th

(b)

40 A

37 A30 A

33 A

22 A 28 A

31 A

22 A






UPM

18 0 18

18

18

OVERALL 67A

18 0 18

18

18

1

2

34

56

7

8

9

10

1112 13

14

15

16

MAX

MIN

18 0 18

18

18

OVERALL 05A

18 0 18

18

18

1

2

34

56

7

8

9

10

1112 13

1415

16

MAX

MIN


16151413121110987654321

Phase number

165155177152140144148128147122154158139149142133

Current ripple (A)

39


UPM

ΔIP-P= 40A

ΔIP-P= 40A

ΔIP-P= 07A

ΔIP-P= 16A

57

ΔIP-P= 11A

ΔIP-P= 22A

50

ΔIP-P= 28A

ΔIP-P= 5A

44

ΔIP-P= 11A

ΔIP-P= 12A

9






1 2 4 8 16



UPM


Tswitch

delay

Load

voutvin



COUNTERDUTY CYCLE

DRIVING SIGNAL

Load

voutvin



40


UPM



Dri

vin

gsi

gnal

s

Counter

+ hellip +


Duty cycle





UPM


Dri

vin

gD

rivi

ng

sign

als

sign

als



ltDuty cycle


Shift Register



Counter


41


UPM






ASIC

12 12 phasesphases

6 6 phasesphases

24 24 phasesphases





0

2000

4000

6000

8000

10000

12000

14000

16000

2 4 6 8 12 16 20 24

0

2000

4000

6000

8000

10000

12000

2 4 6 8 12 16 20 24

0

2000

4000

6000

8000

10000

12000

14000

16000

18000

2 4 6 8 12 16 20 24


Res

ol 1

28Res

ol 2

56Res

ol 5

12

FPGA

Equ

ival

ent

gate

s

Phases

0

200

400

600

800

1000

2 4 6 8 12 16 20 24


Res

ol 1

28Res

ol 2

56Res

ol 5

120

200

400

600

800

1000

1200

2 4 6 8 12 16 20 24

0

200

400

600

800

1000

1200

1400

2 4 6 8 12 16 20 24

ASIC

Equ

ival

ent

gate

s

Phases


UPM


0

10

20

30

40

50

0 20 40 60 80



0

10

20

30

40

50

0 20 40 60 80



Iout

Pow

erlo

sses

(W)

80

84

88

92

96

0 10 20 30 40 50 60 70 80

6 phases

8 phases12 phases

16 phases

4 phases



Iout

Effic

ienc

y(

)

80

84

88

92

96

0 10 20 30 40 50 60 70 80

6 phases

8 phases12 phases

16 phases

4 phases



Iout

Effic

ienc

y(

)



42


UPM





UPM


RFAmp

Pow

erSt

age

Control

iRF

vs

VS

variable VS


24V

9Vfmax=35kHz

Input voltage = 28V





43


UPM


Cs

M1

L

M2

Cs

M1

L

M2

Cs

M1

L

M2

Cs

M1

L

M2

Ve Vout

CAR

GA




UPM


SW

CLK

ff Resolution =

Pipeline

fCLK

f = 25MHz f = 45MHz

Resolution required



fselected = 32MHz


44


UPM

33 33 DitherDither

SW

CLK

ff Resolution gt

d = 42

d =43

d =425

T=2TSW=8μs

Output voltage

2 solutions

V=50mV

TSW=4μs 1 solution

T=4μs

Output voltage

V=25mV

SW

CLKNVirtual



Average duty cycle

It gives 1 more bit


UPM



SimulatedSimulated

MeasuredMeasured



)(

4110780250 22




45


UPM






UPM


f = 200Hz f = 15kHz

f = 3kHz f = 5kHz

46


UPM





UPM



2 2 micromicross

Vo

1 V

2 V

VRM for DVS5 V

Io = 20 A max

1V - 2 V

Io

02 V max02 V max

0 A

20 A

500 Amicros

Vo




47


UPM


10-1 100 101

100

L-C diagram

C2 micros

200 mV

20A




C = 35 C = 35 μμFF



UPM






fsw = 520 kHz

(125 mΩ eq Rds_on)





48


UPM


0

1

To drivers

New vref

vo dig

N-phases_tran

N-phases

New vref

vo dig

New vref

vo dig


ic


NON-LINEAR CONTROL





UPM


vref

vo

0

1

To drivers

clk_sample

clk_sample

ADC

N-phases_tran

N-phases

vo dig

LINEAR CONTROL



49


UPM


vref

vo

0

1

To drivers

New vref

vo dig

clk_sample

clk_sample

ADC

N-phases_tran

N-phases

vo dig

New vref

LINEAR CONTROL

NON-LINEAR CONTROL

vo dig

New vrefvo dig


ic



Beware


UPM


UpUp--stepstep

ConverterFPGA

tt11



DownDown--stepstep

t1 t2 t1 t2

ddnn

tt22vref

500 kHz

LUT


05

1

15

2

25

0 02 04 06 08 1 12 14 16 18-10

0

10

20

30

40

50

ton toff

Tmin

05

1

15

2

25

0 02 04 06 08 1 12 14 16 18-10

0

10

20

30

40

50

ton toff

Tmin

i L(A

)i L

(A)

V o(V

)V o

(V)


50


UPM


t1 t2 t1 t2

094 096 098 1 102 104 106 108 11

x 10-4

14

16

18

2

22

24

26

28

3

32

094 096 098 1 102 104 106 108 11

x 10-4

0

1

2

3

4

5092 094 096 098 1 102 104 106 108 11 112

x 10-4

14

16

18

2

22

24

26

28

3

32

092 094 096 098 1 102 104 106 108 11 112

x 10-4

0

05

1

15

2

25

3

35

4

45

Transient





Beware


UPM

ΔIo

iL

Io

vo

ic 0 ATrip point 1

Trip point 2

ΔIo

ic





51


UPM


05358z02236z07417)(z3767G(z) 2 +sdotminus

+sdot=

B G(s)

G(z)




N = 4

ESR = 125 mΩ

( )CL

1sRESRL1s

CL1)1sCESR(V

)s(Gdv

L2

ino

sdot+sdot+sdot+


==

~ VinmiddotdCo

ESR

RphaseN LphaseN

Expected by design


DC resistance


model


Beware


UPM


Pole-Zero Map

Real Axis

-1 -08 -06 -04 -02 0 02 04 06 08 1-1

-08

-06

-04

-02

0

02

04

06

08

1

09

0807060504

03

02

01

26e5

234e5

208e5

182e5

156e513e5

104e5

781e4

521e4

26e4

26e5

234e5

208e5

182e5

156e513e5

104e5

781e4

521e4

26e4

x

x

x




Duty cycle

30 micros


1z00372)z(Rminus

=

1zK)z(R 1

minus=

Controller delay

05358z02236z07417)(z3767G(z) 2 +sdotminus

+sdot=Converter

x

x

x Duty cycle

Output voltage

52


UPM

10 micros


xx

x

x

x

x

x

x




00775)(z1)(z037)(z00378R(z)

minussdotminus+sdot

=

Duty cycle

Output voltage


UPM


75 micros

xx

x

x

x

xx

x



minussdotminus+sdot

=

53


UPM


Duty

a1 = -0922548 b1 = 0037759b2 = 0051742a2 = 0

b1

b2

δ-1

δ-1

δ-1

a1

a2

Error

bn0

No b0

δ-1

Z-1

+

00775)(z1)(z037)(z00378R(z)

minussdotminus+sdot

=




UPM


z2d_m ( tf ([00378 0013986] [1 -10775 00775] 192e-6) )




=Tsample = Tsw

⎪⎩

⎪⎨⎧

rarrδ

+=δ δδ

s


54


UPM


Reference

Switched model

7 bits

8 bits

Not quantizied


PWM

ADC

111






UPM

Reference


PWM

ADC






hellip

222

55


UPM



a1 = -0922548 b1 = 0037759b2 = 0051742a2 = 0

b1

b2

δ-1

δ-1

δ-1

a1

a2

Error

bn0

No b0


UPM


0lt Duty cycle lt1


Hardware adders






Beware

56


UPM

0 1 2 30

05

1

15

2

25








UPM



0 1 2 3

x 10-4

0

05

1

15

2

25

100 usdiv100 usdiv



57


UPM






UPM




58


UPM


13 14 15 16 17 18 19

x 10-4

12

14

16

18

2

22

08 V drop

10 microsdiv

2 V





UPM



Vo

1 V

2 V



11 A11 A

20 mV

520 kHz



59


UPM


Vo

Io

200 mV







UPM


Vo

1 V

2 V





60


UPM





Beware



UPM



26


UPM


X


IIN-ref

Protections


VOUT max

IIN max

ldquodrdquo max

ldquoΔdrdquo max

ON-OFF Main Switch

ON-OFF Main Switch





intΣIin

gt

CalculatedOn-Off


Max






VOUT-ref

GinPI


UPM










VinGin

Multiplier

xVin

Gin(1Rin)

50 kHz



Adder

+Iin

ΣIin

Comparator

gtOnOff

20 MHz

NoPWMNoPWM


27


UPM




10 W 30 W 50 W 30 W 10 W

Vout

IinGin

StableStable

Load


Unstable

Unstable

Unstable

Unstable


UPM




Adaptive control

28


UPM



Load Change

Vout

Iin




T



UPM

Vin_dc

Iin_dc

d

Vout


OnOff

FPGAXilinx

XC4010-e

8 8 12

Vin Vout Iin

PROMXC 17512

ADC0808

ADC0808

HI 5805


ADCsADCs

Power Converter

Vout Vin_acIin_ac

PF = 099PF = 099PF = 099

29


UPM


DigitalController


switches)Digital


Measuredamp State


Analog

ADConverter

MeasuredVariables

(digital buses)

Mixed




UPM


M1

C Vout

D11n

+

_Vin

Iin

IL1

RL

IR

ON

L1OFF

M1

C Vout

D11n

+

_Vin

Iin

IL1

RL

IR

OFF

L1ON

Vout

n

ID1 = IL1 n

IC



1

kin1k1Lk1L

1L1in L

tVII

dtdILV

Δsdot+=rArr= minus

CtI

VVdt

dVCI kR1koutkout

outR


1

1kout1k1Lk1L

1L1

out

LntV

IIdt

dILnV

sdotΔsdot


minus

C

tIn

I

VVdt

dVCInI kR

1k1L

1koutkoutout

R1L

Δsdot⎟⎟⎠

⎞⎜⎜⎝

⎛minus

+=rArr=minus

minus

minus



30


UPM


VHDLVHDLVHDL

VHDL-AMS

VHDLVHDL--AMSAMS






UPM




VHDLVHDL








Simulationtime


CPU time using VHDL

models


modelsmodels



VHDL speed VHDL-AMS

speed


speedspeed

10 ms10 10 msms 69 s69 s69 s 446 s446 s446 s 641641641

100 ms100 100 msms 700 s700 s700 s 6912 s6912 s6912 s 987987987

1000 ms1000 1000 msms 6890 s6890 s6890 s 68443 s68443 s68443 s 993993993

VHDLVHDL--AMSAMS

31


UPM

42V 14V

CC

CC 42V 14V


system vehicles


Q1-1

Q2-1

Q16-1

Q16-2

Q2-2

Q1-2

L

L

L

COCIN




UPM


Q1-1

Q2-1

Q16-1

Q16-2

Q2-2

Q1-2

L

L

L

COCIN








3 prototypes


3 prototypes



32


UPM


VoVIN

L2d2

d1L1




VINd1

Battery

R1

R2

+

+ +

VINd2

1

BAT1IN1 R

VdVI minus=

2

22 R

VdVI BATIN -=


UPM







446

416

03360

03528

320

2336



1 5

CCM ndash 1000W

824

184

Not acceptable


Q1-1

Q2-1

Q16-1

Q16-2

Q2-2

Q1-2

L

L

L

33


UPM

AVGLI AVGLI


dT T

LVV OIN minus

LVOminus

AVGLI

dT T

LVV OIN minus

LVOminus

AVGLI

⎟⎟⎠

⎞⎜⎜⎝

⎛ minus=

O

OIN

i

2iIN

i VVV

fL2dVI



AVGLI AVGLI

DCMDCM


UPM


03360

03528






416

824



1 5

CCM ndash 1000W

0262002623

0275102649


1 5

DCM ndash 1000W

Not acceptable

445

490

446

454

110102

Very good


34


UPM



420 97

435 100

440 101

435 -

DC Current(A)

429 99

428 98

446 103

460 106

Deviation()

Phase 2

Phase 3

Phase 4

Phase 5

Phase 6

Phase 7

Phase 8

Average

CCM


IO=35A




UPM


ADCInterface

ampfilter

Regulator8

d1


Vout

ADCcontrol

Reset

Vin

12

MCDgenerator

12

Vout

12

Vin

Phase-shifter

8

d2

Protections

1616

Clock

16

H-Pulses L-Pulses




35


UPM




422 97

438 101

442 102

434 -

DC Current(A)

431 99

445 102

424 98

448 103

Deviation()

Phase 2Phase 2

Phase 3Phase 3

Phase 4Phase 4

Phase 5Phase 5

Phase 6Phase 6

Phase 7Phase 7

Phase 8Phase 8

AverageAverage

DCMDCM


IO=17A

IO=27A


UPM





36


UPM


-05

0

05

1

15

2

00E+00 50E-06 10E-05 15E-05 20E-05 25E-05t (s)

()

-05

0

05

1

15

2

00E+00 50E-06 10E-05 15E-05 20E-05 25E-05t (s)

()

0

20

40

60

80

100

120

140

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35

Phase number

[+6-8]

0

20

40

60

80

100

120

140

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35

Phase number

[+6-8]

Half load(500W)


Full load(1000W)

0

1

2

3

4

p

0 5μs 10μs 15μs 20μs0

1

2

3

4

p



0

20

40

60

80

100

120

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35

Phase number

+10-75

0

20

40

60

80

100

120

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35

Phase number

+10-75



UPM

Output currentDC AC

11App

70ADC


is

0 01 02 03 04 05 06 07 08 09 100102030405

060708091

Duty cycle (d)

Nor

m c

urre

nt r

ippl

e Dutyvariation

2 phases

3 phases



37


UPM

10

5

5

10

3T0 x

5

5

3T0 x

Ideal case






10

5

5

10

3T0 x

5

5

3T0 x

Non-ideal



10

5

5

10

3T0 x

5

5

3T0 x

Worse case



10

5

5

10

3T0 x

5

5

3T0 x





UPM

ΔIP-P= 40A (5Adiv)

1 phase

ΔIP-P= 12A (5Adiv)

2 phases

ΔIP-P= 5A (5Adiv)

4 phases

ΔIP-P= 22A (1Adiv)

8 phases

ΔIP-P= 16A (1Adiv)

16 phases



38


UPM

(a)

30

31

22 40

37

22 33

2830

31

22 40

37

22 33

28

(a)

Center of mass

(a)

30

31

22 40

37

22 33

2830

31

22 40

37

22 33

28

(a)

Center of mass

Phase1Phase

2

Phase3

Phase4

Phase5

Phase6

Phase7

Phase8

1st

2nd

3rd 4th

6th

5th 8th

7th

(b)

1st

2nd

3rd 4th

6th

5th 8th

7th

1st

2nd

3rd 4th

6th

5th 8th

7th

(b)

40 A

37 A30 A

33 A

22 A 28 A

31 A

22 A






UPM

18 0 18

18

18

OVERALL 67A

18 0 18

18

18

1

2

34

56

7

8

9

10

1112 13

14

15

16

MAX

MIN

18 0 18

18

18

OVERALL 05A

18 0 18

18

18

1

2

34

56

7

8

9

10

1112 13

1415

16

MAX

MIN


16151413121110987654321

Phase number

165155177152140144148128147122154158139149142133

Current ripple (A)

39


UPM

ΔIP-P= 40A

ΔIP-P= 40A

ΔIP-P= 07A

ΔIP-P= 16A

57

ΔIP-P= 11A

ΔIP-P= 22A

50

ΔIP-P= 28A

ΔIP-P= 5A

44

ΔIP-P= 11A

ΔIP-P= 12A

9






1 2 4 8 16



UPM


Tswitch

delay

Load

voutvin



COUNTERDUTY CYCLE

DRIVING SIGNAL

Load

voutvin



40


UPM



Dri

vin

gsi

gnal

s

Counter

+ hellip +


Duty cycle





UPM


Dri

vin

gD

rivi

ng

sign

als

sign

als



ltDuty cycle


Shift Register



Counter


41


UPM






ASIC

12 12 phasesphases

6 6 phasesphases

24 24 phasesphases





0

2000

4000

6000

8000

10000

12000

14000

16000

2 4 6 8 12 16 20 24

0

2000

4000

6000

8000

10000

12000

2 4 6 8 12 16 20 24

0

2000

4000

6000

8000

10000

12000

14000

16000

18000

2 4 6 8 12 16 20 24


Res

ol 1

28Res

ol 2

56Res

ol 5

12

FPGA

Equ

ival

ent

gate

s

Phases

0

200

400

600

800

1000

2 4 6 8 12 16 20 24


Res

ol 1

28Res

ol 2

56Res

ol 5

120

200

400

600

800

1000

1200

2 4 6 8 12 16 20 24

0

200

400

600

800

1000

1200

1400

2 4 6 8 12 16 20 24

ASIC

Equ

ival

ent

gate

s

Phases


UPM


0

10

20

30

40

50

0 20 40 60 80



0

10

20

30

40

50

0 20 40 60 80



Iout

Pow

erlo

sses

(W)

80

84

88

92

96

0 10 20 30 40 50 60 70 80

6 phases

8 phases12 phases

16 phases

4 phases



Iout

Effic

ienc

y(

)

80

84

88

92

96

0 10 20 30 40 50 60 70 80

6 phases

8 phases12 phases

16 phases

4 phases



Iout

Effic

ienc

y(

)



42


UPM





UPM


RFAmp

Pow

erSt

age

Control

iRF

vs

VS

variable VS


24V

9Vfmax=35kHz

Input voltage = 28V





43


UPM


Cs

M1

L

M2

Cs

M1

L

M2

Cs

M1

L

M2

Cs

M1

L

M2

Ve Vout

CAR

GA




UPM


SW

CLK

ff Resolution =

Pipeline

fCLK

f = 25MHz f = 45MHz

Resolution required



fselected = 32MHz


44


UPM

33 33 DitherDither

SW

CLK

ff Resolution gt

d = 42

d =43

d =425

T=2TSW=8μs

Output voltage

2 solutions

V=50mV

TSW=4μs 1 solution

T=4μs

Output voltage

V=25mV

SW

CLKNVirtual



Average duty cycle

It gives 1 more bit


UPM



SimulatedSimulated

MeasuredMeasured



)(

4110780250 22




45


UPM






UPM


f = 200Hz f = 15kHz

f = 3kHz f = 5kHz

46


UPM





UPM



2 2 micromicross

Vo

1 V

2 V

VRM for DVS5 V

Io = 20 A max

1V - 2 V

Io

02 V max02 V max

0 A

20 A

500 Amicros

Vo




47


UPM


10-1 100 101

100

L-C diagram

C2 micros

200 mV

20A




C = 35 C = 35 μμFF



UPM






fsw = 520 kHz

(125 mΩ eq Rds_on)





48


UPM


0

1

To drivers

New vref

vo dig

N-phases_tran

N-phases

New vref

vo dig

New vref

vo dig


ic


NON-LINEAR CONTROL





UPM


vref

vo

0

1

To drivers

clk_sample

clk_sample

ADC

N-phases_tran

N-phases

vo dig

LINEAR CONTROL



49


UPM


vref

vo

0

1

To drivers

New vref

vo dig

clk_sample

clk_sample

ADC

N-phases_tran

N-phases

vo dig

New vref

LINEAR CONTROL

NON-LINEAR CONTROL

vo dig

New vrefvo dig


ic



Beware


UPM


UpUp--stepstep

ConverterFPGA

tt11



DownDown--stepstep

t1 t2 t1 t2

ddnn

tt22vref

500 kHz

LUT


05

1

15

2

25

0 02 04 06 08 1 12 14 16 18-10

0

10

20

30

40

50

ton toff

Tmin

05

1

15

2

25

0 02 04 06 08 1 12 14 16 18-10

0

10

20

30

40

50

ton toff

Tmin

i L(A

)i L

(A)

V o(V

)V o

(V)


50


UPM


t1 t2 t1 t2

094 096 098 1 102 104 106 108 11

x 10-4

14

16

18

2

22

24

26

28

3

32

094 096 098 1 102 104 106 108 11

x 10-4

0

1

2

3

4

5092 094 096 098 1 102 104 106 108 11 112

x 10-4

14

16

18

2

22

24

26

28

3

32

092 094 096 098 1 102 104 106 108 11 112

x 10-4

0

05

1

15

2

25

3

35

4

45

Transient





Beware


UPM

ΔIo

iL

Io

vo

ic 0 ATrip point 1

Trip point 2

ΔIo

ic





51


UPM


05358z02236z07417)(z3767G(z) 2 +sdotminus

+sdot=

B G(s)

G(z)




N = 4

ESR = 125 mΩ

( )CL

1sRESRL1s

CL1)1sCESR(V

)s(Gdv

L2

ino

sdot+sdot+sdot+


==

~ VinmiddotdCo

ESR

RphaseN LphaseN

Expected by design


DC resistance


model


Beware


UPM


Pole-Zero Map

Real Axis

-1 -08 -06 -04 -02 0 02 04 06 08 1-1

-08

-06

-04

-02

0

02

04

06

08

1

09

0807060504

03

02

01

26e5

234e5

208e5

182e5

156e513e5

104e5

781e4

521e4

26e4

26e5

234e5

208e5

182e5

156e513e5

104e5

781e4

521e4

26e4

x

x

x




Duty cycle

30 micros


1z00372)z(Rminus

=

1zK)z(R 1

minus=

Controller delay

05358z02236z07417)(z3767G(z) 2 +sdotminus

+sdot=Converter

x

x

x Duty cycle

Output voltage

52


UPM

10 micros


xx

x

x

x

x

x

x




00775)(z1)(z037)(z00378R(z)

minussdotminus+sdot

=

Duty cycle

Output voltage


UPM


75 micros

xx

x

x

x

xx

x



minussdotminus+sdot

=

53


UPM


Duty

a1 = -0922548 b1 = 0037759b2 = 0051742a2 = 0

b1

b2

δ-1

δ-1

δ-1

a1

a2

Error

bn0

No b0

δ-1

Z-1

+

00775)(z1)(z037)(z00378R(z)

minussdotminus+sdot

=




UPM


z2d_m ( tf ([00378 0013986] [1 -10775 00775] 192e-6) )




=Tsample = Tsw

⎪⎩

⎪⎨⎧

rarrδ

+=δ δδ

s


54


UPM


Reference

Switched model

7 bits

8 bits

Not quantizied


PWM

ADC

111






UPM

Reference


PWM

ADC






hellip

222

55


UPM



a1 = -0922548 b1 = 0037759b2 = 0051742a2 = 0

b1

b2

δ-1

δ-1

δ-1

a1

a2

Error

bn0

No b0


UPM


0lt Duty cycle lt1


Hardware adders






Beware

56


UPM

0 1 2 30

05

1

15

2

25








UPM



0 1 2 3

x 10-4

0

05

1

15

2

25

100 usdiv100 usdiv



57


UPM






UPM




58


UPM


13 14 15 16 17 18 19

x 10-4

12

14

16

18

2

22

08 V drop

10 microsdiv

2 V





UPM



Vo

1 V

2 V



11 A11 A

20 mV

520 kHz



59


UPM


Vo

Io

200 mV







UPM


Vo

1 V

2 V





60


UPM





Beware



UPM



27


UPM




10 W 30 W 50 W 30 W 10 W

Vout

IinGin

StableStable

Load


Unstable

Unstable

Unstable

Unstable


UPM




Adaptive control

28


UPM



Load Change

Vout

Iin




T



UPM

Vin_dc

Iin_dc

d

Vout


OnOff

FPGAXilinx

XC4010-e

8 8 12

Vin Vout Iin

PROMXC 17512

ADC0808

ADC0808

HI 5805


ADCsADCs

Power Converter

Vout Vin_acIin_ac

PF = 099PF = 099PF = 099

29


UPM


DigitalController


switches)Digital


Measuredamp State


Analog

ADConverter

MeasuredVariables

(digital buses)

Mixed




UPM


M1

C Vout

D11n

+

_Vin

Iin

IL1

RL

IR

ON

L1OFF

M1

C Vout

D11n

+

_Vin

Iin

IL1

RL

IR

OFF

L1ON

Vout

n

ID1 = IL1 n

IC



1

kin1k1Lk1L

1L1in L

tVII

dtdILV

Δsdot+=rArr= minus

CtI

VVdt

dVCI kR1koutkout

outR


1

1kout1k1Lk1L

1L1

out

LntV

IIdt

dILnV

sdotΔsdot


minus

C

tIn

I

VVdt

dVCInI kR

1k1L

1koutkoutout

R1L

Δsdot⎟⎟⎠

⎞⎜⎜⎝

⎛minus

+=rArr=minus

minus

minus



30


UPM


VHDLVHDLVHDL

VHDL-AMS

VHDLVHDL--AMSAMS






UPM




VHDLVHDL








Simulationtime


CPU time using VHDL

models


modelsmodels



VHDL speed VHDL-AMS

speed


speedspeed

10 ms10 10 msms 69 s69 s69 s 446 s446 s446 s 641641641

100 ms100 100 msms 700 s700 s700 s 6912 s6912 s6912 s 987987987

1000 ms1000 1000 msms 6890 s6890 s6890 s 68443 s68443 s68443 s 993993993

VHDLVHDL--AMSAMS

31


UPM

42V 14V

CC

CC 42V 14V


system vehicles


Q1-1

Q2-1

Q16-1

Q16-2

Q2-2

Q1-2

L

L

L

COCIN




UPM


Q1-1

Q2-1

Q16-1

Q16-2

Q2-2

Q1-2

L

L

L

COCIN








3 prototypes


3 prototypes



32


UPM


VoVIN

L2d2

d1L1




VINd1

Battery

R1

R2

+

+ +

VINd2

1

BAT1IN1 R

VdVI minus=

2

22 R

VdVI BATIN -=


UPM







446

416

03360

03528

320

2336



1 5

CCM ndash 1000W

824

184

Not acceptable


Q1-1

Q2-1

Q16-1

Q16-2

Q2-2

Q1-2

L

L

L

33


UPM

AVGLI AVGLI


dT T

LVV OIN minus

LVOminus

AVGLI

dT T

LVV OIN minus

LVOminus

AVGLI

⎟⎟⎠

⎞⎜⎜⎝

⎛ minus=

O

OIN

i

2iIN

i VVV

fL2dVI



AVGLI AVGLI

DCMDCM


UPM


03360

03528






416

824



1 5

CCM ndash 1000W

0262002623

0275102649


1 5

DCM ndash 1000W

Not acceptable

445

490

446

454

110102

Very good


34


UPM



420 97

435 100

440 101

435 -

DC Current(A)

429 99

428 98

446 103

460 106

Deviation()

Phase 2

Phase 3

Phase 4

Phase 5

Phase 6

Phase 7

Phase 8

Average

CCM


IO=35A




UPM


ADCInterface

ampfilter

Regulator8

d1


Vout

ADCcontrol

Reset

Vin

12

MCDgenerator

12

Vout

12

Vin

Phase-shifter

8

d2

Protections

1616

Clock

16

H-Pulses L-Pulses




35


UPM




422 97

438 101

442 102

434 -

DC Current(A)

431 99

445 102

424 98

448 103

Deviation()

Phase 2Phase 2

Phase 3Phase 3

Phase 4Phase 4

Phase 5Phase 5

Phase 6Phase 6

Phase 7Phase 7

Phase 8Phase 8

AverageAverage

DCMDCM


IO=17A

IO=27A


UPM





36


UPM


-05

0

05

1

15

2

00E+00 50E-06 10E-05 15E-05 20E-05 25E-05t (s)

()

-05

0

05

1

15

2

00E+00 50E-06 10E-05 15E-05 20E-05 25E-05t (s)

()

0

20

40

60

80

100

120

140

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35

Phase number

[+6-8]

0

20

40

60

80

100

120

140

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35

Phase number

[+6-8]

Half load(500W)


Full load(1000W)

0

1

2

3

4

p

0 5μs 10μs 15μs 20μs0

1

2

3

4

p



0

20

40

60

80

100

120

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35

Phase number

+10-75

0

20

40

60

80

100

120

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35

Phase number

+10-75



UPM

Output currentDC AC

11App

70ADC


is

0 01 02 03 04 05 06 07 08 09 100102030405

060708091

Duty cycle (d)

Nor

m c

urre

nt r

ippl

e Dutyvariation

2 phases

3 phases



37


UPM

10

5

5

10

3T0 x

5

5

3T0 x

Ideal case






10

5

5

10

3T0 x

5

5

3T0 x

Non-ideal



10

5

5

10

3T0 x

5

5

3T0 x

Worse case



10

5

5

10

3T0 x

5

5

3T0 x





UPM

ΔIP-P= 40A (5Adiv)

1 phase

ΔIP-P= 12A (5Adiv)

2 phases

ΔIP-P= 5A (5Adiv)

4 phases

ΔIP-P= 22A (1Adiv)

8 phases

ΔIP-P= 16A (1Adiv)

16 phases



38


UPM

(a)

30

31

22 40

37

22 33

2830

31

22 40

37

22 33

28

(a)

Center of mass

(a)

30

31

22 40

37

22 33

2830

31

22 40

37

22 33

28

(a)

Center of mass

Phase1Phase

2

Phase3

Phase4

Phase5

Phase6

Phase7

Phase8

1st

2nd

3rd 4th

6th

5th 8th

7th

(b)

1st

2nd

3rd 4th

6th

5th 8th

7th

1st

2nd

3rd 4th

6th

5th 8th

7th

(b)

40 A

37 A30 A

33 A

22 A 28 A

31 A

22 A






UPM

18 0 18

18

18

OVERALL 67A

18 0 18

18

18

1

2

34

56

7

8

9

10

1112 13

14

15

16

MAX

MIN

18 0 18

18

18

OVERALL 05A

18 0 18

18

18

1

2

34

56

7

8

9

10

1112 13

1415

16

MAX

MIN


16151413121110987654321

Phase number

165155177152140144148128147122154158139149142133

Current ripple (A)

39


UPM

ΔIP-P= 40A

ΔIP-P= 40A

ΔIP-P= 07A

ΔIP-P= 16A

57

ΔIP-P= 11A

ΔIP-P= 22A

50

ΔIP-P= 28A

ΔIP-P= 5A

44

ΔIP-P= 11A

ΔIP-P= 12A

9






1 2 4 8 16



UPM


Tswitch

delay

Load

voutvin



COUNTERDUTY CYCLE

DRIVING SIGNAL

Load

voutvin



40


UPM



Dri

vin

gsi

gnal

s

Counter

+ hellip +


Duty cycle





UPM


Dri

vin

gD

rivi

ng

sign

als

sign

als



ltDuty cycle


Shift Register



Counter


41


UPM






ASIC

12 12 phasesphases

6 6 phasesphases

24 24 phasesphases





0

2000

4000

6000

8000

10000

12000

14000

16000

2 4 6 8 12 16 20 24

0

2000

4000

6000

8000

10000

12000

2 4 6 8 12 16 20 24

0

2000

4000

6000

8000

10000

12000

14000

16000

18000

2 4 6 8 12 16 20 24


Res

ol 1

28Res

ol 2

56Res

ol 5

12

FPGA

Equ

ival

ent

gate

s

Phases

0

200

400

600

800

1000

2 4 6 8 12 16 20 24


Res

ol 1

28Res

ol 2

56Res

ol 5

120

200

400

600

800

1000

1200

2 4 6 8 12 16 20 24

0

200

400

600

800

1000

1200

1400

2 4 6 8 12 16 20 24

ASIC

Equ

ival

ent

gate

s

Phases


UPM


0

10

20

30

40

50

0 20 40 60 80



0

10

20

30

40

50

0 20 40 60 80



Iout

Pow

erlo

sses

(W)

80

84

88

92

96

0 10 20 30 40 50 60 70 80

6 phases

8 phases12 phases

16 phases

4 phases



Iout

Effic

ienc

y(

)

80

84

88

92

96

0 10 20 30 40 50 60 70 80

6 phases

8 phases12 phases

16 phases

4 phases



Iout

Effic

ienc

y(

)



42


UPM





UPM


RFAmp

Pow

erSt

age

Control

iRF

vs

VS

variable VS


24V

9Vfmax=35kHz

Input voltage = 28V





43


UPM


Cs

M1

L

M2

Cs

M1

L

M2

Cs

M1

L

M2

Cs

M1

L

M2

Ve Vout

CAR

GA




UPM


SW

CLK

ff Resolution =

Pipeline

fCLK

f = 25MHz f = 45MHz

Resolution required



fselected = 32MHz


44


UPM

33 33 DitherDither

SW

CLK

ff Resolution gt

d = 42

d =43

d =425

T=2TSW=8μs

Output voltage

2 solutions

V=50mV

TSW=4μs 1 solution

T=4μs

Output voltage

V=25mV

SW

CLKNVirtual



Average duty cycle

It gives 1 more bit


UPM



SimulatedSimulated

MeasuredMeasured



)(

4110780250 22




45


UPM






UPM


f = 200Hz f = 15kHz

f = 3kHz f = 5kHz

46


UPM





UPM



2 2 micromicross

Vo

1 V

2 V

VRM for DVS5 V

Io = 20 A max

1V - 2 V

Io

02 V max02 V max

0 A

20 A

500 Amicros

Vo




47


UPM


10-1 100 101

100

L-C diagram

C2 micros

200 mV

20A




C = 35 C = 35 μμFF



UPM






fsw = 520 kHz

(125 mΩ eq Rds_on)





48


UPM


0

1

To drivers

New vref

vo dig

N-phases_tran

N-phases

New vref

vo dig

New vref

vo dig


ic


NON-LINEAR CONTROL





UPM


vref

vo

0

1

To drivers

clk_sample

clk_sample

ADC

N-phases_tran

N-phases

vo dig

LINEAR CONTROL



49


UPM


vref

vo

0

1

To drivers

New vref

vo dig

clk_sample

clk_sample

ADC

N-phases_tran

N-phases

vo dig

New vref

LINEAR CONTROL

NON-LINEAR CONTROL

vo dig

New vrefvo dig


ic



Beware


UPM


UpUp--stepstep

ConverterFPGA

tt11



DownDown--stepstep

t1 t2 t1 t2

ddnn

tt22vref

500 kHz

LUT


05

1

15

2

25

0 02 04 06 08 1 12 14 16 18-10

0

10

20

30

40

50

ton toff

Tmin

05

1

15

2

25

0 02 04 06 08 1 12 14 16 18-10

0

10

20

30

40

50

ton toff

Tmin

i L(A

)i L

(A)

V o(V

)V o

(V)


50


UPM


t1 t2 t1 t2

094 096 098 1 102 104 106 108 11

x 10-4

14

16

18

2

22

24

26

28

3

32

094 096 098 1 102 104 106 108 11

x 10-4

0

1

2

3

4

5092 094 096 098 1 102 104 106 108 11 112

x 10-4

14

16

18

2

22

24

26

28

3

32

092 094 096 098 1 102 104 106 108 11 112

x 10-4

0

05

1

15

2

25

3

35

4

45

Transient





Beware


UPM

ΔIo

iL

Io

vo

ic 0 ATrip point 1

Trip point 2

ΔIo

ic





51


UPM


05358z02236z07417)(z3767G(z) 2 +sdotminus

+sdot=

B G(s)

G(z)




N = 4

ESR = 125 mΩ

( )CL

1sRESRL1s

CL1)1sCESR(V

)s(Gdv

L2

ino

sdot+sdot+sdot+


==

~ VinmiddotdCo

ESR

RphaseN LphaseN

Expected by design


DC resistance


model


Beware


UPM


Pole-Zero Map

Real Axis

-1 -08 -06 -04 -02 0 02 04 06 08 1-1

-08

-06

-04

-02

0

02

04

06

08

1

09

0807060504

03

02

01

26e5

234e5

208e5

182e5

156e513e5

104e5

781e4

521e4

26e4

26e5

234e5

208e5

182e5

156e513e5

104e5

781e4

521e4

26e4

x

x

x




Duty cycle

30 micros


1z00372)z(Rminus

=

1zK)z(R 1

minus=

Controller delay

05358z02236z07417)(z3767G(z) 2 +sdotminus

+sdot=Converter

x

x

x Duty cycle

Output voltage

52


UPM

10 micros


xx

x

x

x

x

x

x




00775)(z1)(z037)(z00378R(z)

minussdotminus+sdot

=

Duty cycle

Output voltage


UPM


75 micros

xx

x

x

x

xx

x



minussdotminus+sdot

=

53


UPM


Duty

a1 = -0922548 b1 = 0037759b2 = 0051742a2 = 0

b1

b2

δ-1

δ-1

δ-1

a1

a2

Error

bn0

No b0

δ-1

Z-1

+

00775)(z1)(z037)(z00378R(z)

minussdotminus+sdot

=




UPM


z2d_m ( tf ([00378 0013986] [1 -10775 00775] 192e-6) )




=Tsample = Tsw

⎪⎩

⎪⎨⎧

rarrδ

+=δ δδ

s


54


UPM


Reference

Switched model

7 bits

8 bits

Not quantizied


PWM

ADC

111






UPM

Reference


PWM

ADC






hellip

222

55


UPM



a1 = -0922548 b1 = 0037759b2 = 0051742a2 = 0

b1

b2

δ-1

δ-1

δ-1

a1

a2

Error

bn0

No b0


UPM


0lt Duty cycle lt1


Hardware adders






Beware

56


UPM

0 1 2 30

05

1

15

2

25








UPM



0 1 2 3

x 10-4

0

05

1

15

2

25

100 usdiv100 usdiv



57


UPM






UPM




58


UPM


13 14 15 16 17 18 19

x 10-4

12

14

16

18

2

22

08 V drop

10 microsdiv

2 V





UPM



Vo

1 V

2 V



11 A11 A

20 mV

520 kHz



59


UPM


Vo

Io

200 mV







UPM


Vo

1 V

2 V





60


UPM





Beware



UPM



28


UPM



Load Change

Vout

Iin




T



UPM

Vin_dc

Iin_dc

d

Vout


OnOff

FPGAXilinx

XC4010-e

8 8 12

Vin Vout Iin

PROMXC 17512

ADC0808

ADC0808

HI 5805


ADCsADCs

Power Converter

Vout Vin_acIin_ac

PF = 099PF = 099PF = 099

29


UPM


DigitalController


switches)Digital


Measuredamp State


Analog

ADConverter

MeasuredVariables

(digital buses)

Mixed




UPM


M1

C Vout

D11n

+

_Vin

Iin

IL1

RL

IR

ON

L1OFF

M1

C Vout

D11n

+

_Vin

Iin

IL1

RL

IR

OFF

L1ON

Vout

n

ID1 = IL1 n

IC



1

kin1k1Lk1L

1L1in L

tVII

dtdILV

Δsdot+=rArr= minus

CtI

VVdt

dVCI kR1koutkout

outR


1

1kout1k1Lk1L

1L1

out

LntV

IIdt

dILnV

sdotΔsdot


minus

C

tIn

I

VVdt

dVCInI kR

1k1L

1koutkoutout

R1L

Δsdot⎟⎟⎠

⎞⎜⎜⎝

⎛minus

+=rArr=minus

minus

minus



30


UPM


VHDLVHDLVHDL

VHDL-AMS

VHDLVHDL--AMSAMS






UPM




VHDLVHDL








Simulationtime


CPU time using VHDL

models


modelsmodels



VHDL speed VHDL-AMS

speed


speedspeed

10 ms10 10 msms 69 s69 s69 s 446 s446 s446 s 641641641

100 ms100 100 msms 700 s700 s700 s 6912 s6912 s6912 s 987987987

1000 ms1000 1000 msms 6890 s6890 s6890 s 68443 s68443 s68443 s 993993993

VHDLVHDL--AMSAMS

31


UPM

42V 14V

CC

CC 42V 14V


system vehicles


Q1-1

Q2-1

Q16-1

Q16-2

Q2-2

Q1-2

L

L

L

COCIN




UPM


Q1-1

Q2-1

Q16-1

Q16-2

Q2-2

Q1-2

L

L

L

COCIN








3 prototypes


3 prototypes



32


UPM


VoVIN

L2d2

d1L1




VINd1

Battery

R1

R2

+

+ +

VINd2

1

BAT1IN1 R

VdVI minus=

2

22 R

VdVI BATIN -=


UPM







446

416

03360

03528

320

2336



1 5

CCM ndash 1000W

824

184

Not acceptable


Q1-1

Q2-1

Q16-1

Q16-2

Q2-2

Q1-2

L

L

L

33


UPM

AVGLI AVGLI


dT T

LVV OIN minus

LVOminus

AVGLI

dT T

LVV OIN minus

LVOminus

AVGLI

⎟⎟⎠

⎞⎜⎜⎝

⎛ minus=

O

OIN

i

2iIN

i VVV

fL2dVI



AVGLI AVGLI

DCMDCM


UPM


03360

03528






416

824



1 5

CCM ndash 1000W

0262002623

0275102649


1 5

DCM ndash 1000W

Not acceptable

445

490

446

454

110102

Very good


34


UPM



420 97

435 100

440 101

435 -

DC Current(A)

429 99

428 98

446 103

460 106

Deviation()

Phase 2

Phase 3

Phase 4

Phase 5

Phase 6

Phase 7

Phase 8

Average

CCM


IO=35A




UPM


ADCInterface

ampfilter

Regulator8

d1


Vout

ADCcontrol

Reset

Vin

12

MCDgenerator

12

Vout

12

Vin

Phase-shifter

8

d2

Protections

1616

Clock

16

H-Pulses L-Pulses




35


UPM




422 97

438 101

442 102

434 -

DC Current(A)

431 99

445 102

424 98

448 103

Deviation()

Phase 2Phase 2

Phase 3Phase 3

Phase 4Phase 4

Phase 5Phase 5

Phase 6Phase 6

Phase 7Phase 7

Phase 8Phase 8

AverageAverage

DCMDCM


IO=17A

IO=27A


UPM





36


UPM


-05

0

05

1

15

2

00E+00 50E-06 10E-05 15E-05 20E-05 25E-05t (s)

()

-05

0

05

1

15

2

00E+00 50E-06 10E-05 15E-05 20E-05 25E-05t (s)

()

0

20

40

60

80

100

120

140

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35

Phase number

[+6-8]

0

20

40

60

80

100

120

140

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35

Phase number

[+6-8]

Half load(500W)


Full load(1000W)

0

1

2

3

4

p

0 5μs 10μs 15μs 20μs0

1

2

3

4

p



0

20

40

60

80

100

120

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35

Phase number

+10-75

0

20

40

60

80

100

120

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35

Phase number

+10-75



UPM

Output currentDC AC

11App

70ADC


is

0 01 02 03 04 05 06 07 08 09 100102030405

060708091

Duty cycle (d)

Nor

m c

urre

nt r

ippl

e Dutyvariation

2 phases

3 phases



37


UPM

10

5

5

10

3T0 x

5

5

3T0 x

Ideal case






10

5

5

10

3T0 x

5

5

3T0 x

Non-ideal



10

5

5

10

3T0 x

5

5

3T0 x

Worse case



10

5

5

10

3T0 x

5

5

3T0 x





UPM

ΔIP-P= 40A (5Adiv)

1 phase

ΔIP-P= 12A (5Adiv)

2 phases

ΔIP-P= 5A (5Adiv)

4 phases

ΔIP-P= 22A (1Adiv)

8 phases

ΔIP-P= 16A (1Adiv)

16 phases



38


UPM

(a)

30

31

22 40

37

22 33

2830

31

22 40

37

22 33

28

(a)

Center of mass

(a)

30

31

22 40

37

22 33

2830

31

22 40

37

22 33

28

(a)

Center of mass

Phase1Phase

2

Phase3

Phase4

Phase5

Phase6

Phase7

Phase8

1st

2nd

3rd 4th

6th

5th 8th

7th

(b)

1st

2nd

3rd 4th

6th

5th 8th

7th

1st

2nd

3rd 4th

6th

5th 8th

7th

(b)

40 A

37 A30 A

33 A

22 A 28 A

31 A

22 A






UPM

18 0 18

18

18

OVERALL 67A

18 0 18

18

18

1

2

34

56

7

8

9

10

1112 13

14

15

16

MAX

MIN

18 0 18

18

18

OVERALL 05A

18 0 18

18

18

1

2

34

56

7

8

9

10

1112 13

1415

16

MAX

MIN


16151413121110987654321

Phase number

165155177152140144148128147122154158139149142133

Current ripple (A)

39


UPM

ΔIP-P= 40A

ΔIP-P= 40A

ΔIP-P= 07A

ΔIP-P= 16A

57

ΔIP-P= 11A

ΔIP-P= 22A

50

ΔIP-P= 28A

ΔIP-P= 5A

44

ΔIP-P= 11A

ΔIP-P= 12A

9






1 2 4 8 16



UPM


Tswitch

delay

Load

voutvin



COUNTERDUTY CYCLE

DRIVING SIGNAL

Load

voutvin



40


UPM



Dri

vin

gsi

gnal

s

Counter

+ hellip +


Duty cycle





UPM


Dri

vin

gD

rivi

ng

sign

als

sign

als



ltDuty cycle


Shift Register



Counter


41


UPM






ASIC

12 12 phasesphases

6 6 phasesphases

24 24 phasesphases





0

2000

4000

6000

8000

10000

12000

14000

16000

2 4 6 8 12 16 20 24

0

2000

4000

6000

8000

10000

12000

2 4 6 8 12 16 20 24

0

2000

4000

6000

8000

10000

12000

14000

16000

18000

2 4 6 8 12 16 20 24


Res

ol 1

28Res

ol 2

56Res

ol 5

12

FPGA

Equ

ival

ent

gate

s

Phases

0

200

400

600

800

1000

2 4 6 8 12 16 20 24


Res

ol 1

28Res

ol 2

56Res

ol 5

120

200

400

600

800

1000

1200

2 4 6 8 12 16 20 24

0

200

400

600

800

1000

1200

1400

2 4 6 8 12 16 20 24

ASIC

Equ

ival

ent

gate

s

Phases


UPM


0

10

20

30

40

50

0 20 40 60 80



0

10

20

30

40

50

0 20 40 60 80



Iout

Pow

erlo

sses

(W)

80

84

88

92

96

0 10 20 30 40 50 60 70 80

6 phases

8 phases12 phases

16 phases

4 phases



Iout

Effic

ienc

y(

)

80

84

88

92

96

0 10 20 30 40 50 60 70 80

6 phases

8 phases12 phases

16 phases

4 phases



Iout

Effic

ienc

y(

)



42


UPM





UPM


RFAmp

Pow

erSt

age

Control

iRF

vs

VS

variable VS


24V

9Vfmax=35kHz

Input voltage = 28V





43


UPM


Cs

M1

L

M2

Cs

M1

L

M2

Cs

M1

L

M2

Cs

M1

L

M2

Ve Vout

CAR

GA




UPM


SW

CLK

ff Resolution =

Pipeline

fCLK

f = 25MHz f = 45MHz

Resolution required



fselected = 32MHz


44


UPM

33 33 DitherDither

SW

CLK

ff Resolution gt

d = 42

d =43

d =425

T=2TSW=8μs

Output voltage

2 solutions

V=50mV

TSW=4μs 1 solution

T=4μs

Output voltage

V=25mV

SW

CLKNVirtual



Average duty cycle

It gives 1 more bit


UPM



SimulatedSimulated

MeasuredMeasured



)(

4110780250 22




45


UPM






UPM


f = 200Hz f = 15kHz

f = 3kHz f = 5kHz

46


UPM





UPM



2 2 micromicross

Vo

1 V

2 V

VRM for DVS5 V

Io = 20 A max

1V - 2 V

Io

02 V max02 V max

0 A

20 A

500 Amicros

Vo




47


UPM


10-1 100 101

100

L-C diagram

C2 micros

200 mV

20A




C = 35 C = 35 μμFF



UPM






fsw = 520 kHz

(125 mΩ eq Rds_on)





48


UPM


0

1

To drivers

New vref

vo dig

N-phases_tran

N-phases

New vref

vo dig

New vref

vo dig


ic


NON-LINEAR CONTROL





UPM


vref

vo

0

1

To drivers

clk_sample

clk_sample

ADC

N-phases_tran

N-phases

vo dig

LINEAR CONTROL



49


UPM


vref

vo

0

1

To drivers

New vref

vo dig

clk_sample

clk_sample

ADC

N-phases_tran

N-phases

vo dig

New vref

LINEAR CONTROL

NON-LINEAR CONTROL

vo dig

New vrefvo dig


ic



Beware


UPM


UpUp--stepstep

ConverterFPGA

tt11



DownDown--stepstep

t1 t2 t1 t2

ddnn

tt22vref

500 kHz

LUT


05

1

15

2

25

0 02 04 06 08 1 12 14 16 18-10

0

10

20

30

40

50

ton toff

Tmin

05

1

15

2

25

0 02 04 06 08 1 12 14 16 18-10

0

10

20

30

40

50

ton toff

Tmin

i L(A

)i L

(A)

V o(V

)V o

(V)


50


UPM


t1 t2 t1 t2

094 096 098 1 102 104 106 108 11

x 10-4

14

16

18

2

22

24

26

28

3

32

094 096 098 1 102 104 106 108 11

x 10-4

0

1

2

3

4

5092 094 096 098 1 102 104 106 108 11 112

x 10-4

14

16

18

2

22

24

26

28

3

32

092 094 096 098 1 102 104 106 108 11 112

x 10-4

0

05

1

15

2

25

3

35

4

45

Transient





Beware


UPM

ΔIo

iL

Io

vo

ic 0 ATrip point 1

Trip point 2

ΔIo

ic





51


UPM


05358z02236z07417)(z3767G(z) 2 +sdotminus

+sdot=

B G(s)

G(z)




N = 4

ESR = 125 mΩ

( )CL

1sRESRL1s

CL1)1sCESR(V

)s(Gdv

L2

ino

sdot+sdot+sdot+


==

~ VinmiddotdCo

ESR

RphaseN LphaseN

Expected by design


DC resistance


model


Beware


UPM


Pole-Zero Map

Real Axis

-1 -08 -06 -04 -02 0 02 04 06 08 1-1

-08

-06

-04

-02

0

02

04

06

08

1

09

0807060504

03

02

01

26e5

234e5

208e5

182e5

156e513e5

104e5

781e4

521e4

26e4

26e5

234e5

208e5

182e5

156e513e5

104e5

781e4

521e4

26e4

x

x

x




Duty cycle

30 micros


1z00372)z(Rminus

=

1zK)z(R 1

minus=

Controller delay

05358z02236z07417)(z3767G(z) 2 +sdotminus

+sdot=Converter

x

x

x Duty cycle

Output voltage

52


UPM

10 micros


xx

x

x

x

x

x

x




00775)(z1)(z037)(z00378R(z)

minussdotminus+sdot

=

Duty cycle

Output voltage


UPM


75 micros

xx

x

x

x

xx

x



minussdotminus+sdot

=

53


UPM


Duty

a1 = -0922548 b1 = 0037759b2 = 0051742a2 = 0

b1

b2

δ-1

δ-1

δ-1

a1

a2

Error

bn0

No b0

δ-1

Z-1

+

00775)(z1)(z037)(z00378R(z)

minussdotminus+sdot

=




UPM


z2d_m ( tf ([00378 0013986] [1 -10775 00775] 192e-6) )




=Tsample = Tsw

⎪⎩

⎪⎨⎧

rarrδ

+=δ δδ

s


54


UPM


Reference

Switched model

7 bits

8 bits

Not quantizied


PWM

ADC

111






UPM

Reference


PWM

ADC






hellip

222

55


UPM



a1 = -0922548 b1 = 0037759b2 = 0051742a2 = 0

b1

b2

δ-1

δ-1

δ-1

a1

a2

Error

bn0

No b0


UPM


0lt Duty cycle lt1


Hardware adders






Beware

56


UPM

0 1 2 30

05

1

15

2

25








UPM



0 1 2 3

x 10-4

0

05

1

15

2

25

100 usdiv100 usdiv



57


UPM






UPM




58


UPM


13 14 15 16 17 18 19

x 10-4

12

14

16

18

2

22

08 V drop

10 microsdiv

2 V





UPM



Vo

1 V

2 V



11 A11 A

20 mV

520 kHz



59


UPM


Vo

Io

200 mV







UPM


Vo

1 V

2 V





60


UPM





Beware



UPM



29


UPM


DigitalController


switches)Digital


Measuredamp State


Analog

ADConverter

MeasuredVariables

(digital buses)

Mixed




UPM


M1

C Vout

D11n

+

_Vin

Iin

IL1

RL

IR

ON

L1OFF

M1

C Vout

D11n

+

_Vin

Iin

IL1

RL

IR

OFF

L1ON

Vout

n

ID1 = IL1 n

IC



1

kin1k1Lk1L

1L1in L

tVII

dtdILV

Δsdot+=rArr= minus

CtI

VVdt

dVCI kR1koutkout

outR


1

1kout1k1Lk1L

1L1

out

LntV

IIdt

dILnV

sdotΔsdot


minus

C

tIn

I

VVdt

dVCInI kR

1k1L

1koutkoutout

R1L

Δsdot⎟⎟⎠

⎞⎜⎜⎝

⎛minus

+=rArr=minus

minus

minus



30


UPM


VHDLVHDLVHDL

VHDL-AMS

VHDLVHDL--AMSAMS






UPM




VHDLVHDL








Simulationtime


CPU time using VHDL

models


modelsmodels



VHDL speed VHDL-AMS

speed


speedspeed

10 ms10 10 msms 69 s69 s69 s 446 s446 s446 s 641641641

100 ms100 100 msms 700 s700 s700 s 6912 s6912 s6912 s 987987987

1000 ms1000 1000 msms 6890 s6890 s6890 s 68443 s68443 s68443 s 993993993

VHDLVHDL--AMSAMS

31


UPM

42V 14V

CC

CC 42V 14V


system vehicles


Q1-1

Q2-1

Q16-1

Q16-2

Q2-2

Q1-2

L

L

L

COCIN




UPM


Q1-1

Q2-1

Q16-1

Q16-2

Q2-2

Q1-2

L

L

L

COCIN








3 prototypes


3 prototypes



32


UPM


VoVIN

L2d2

d1L1




VINd1

Battery

R1

R2

+

+ +

VINd2

1

BAT1IN1 R

VdVI minus=

2

22 R

VdVI BATIN -=


UPM







446

416

03360

03528

320

2336



1 5

CCM ndash 1000W

824

184

Not acceptable


Q1-1

Q2-1

Q16-1

Q16-2

Q2-2

Q1-2

L

L

L

33


UPM

AVGLI AVGLI


dT T

LVV OIN minus

LVOminus

AVGLI

dT T

LVV OIN minus

LVOminus

AVGLI

⎟⎟⎠

⎞⎜⎜⎝

⎛ minus=

O

OIN

i

2iIN

i VVV

fL2dVI



AVGLI AVGLI

DCMDCM


UPM


03360

03528






416

824



1 5

CCM ndash 1000W

0262002623

0275102649


1 5

DCM ndash 1000W

Not acceptable

445

490

446

454

110102

Very good


34


UPM



420 97

435 100

440 101

435 -

DC Current(A)

429 99

428 98

446 103

460 106

Deviation()

Phase 2

Phase 3

Phase 4

Phase 5

Phase 6

Phase 7

Phase 8

Average

CCM


IO=35A




UPM


ADCInterface

ampfilter

Regulator8

d1


Vout

ADCcontrol

Reset

Vin

12

MCDgenerator

12

Vout

12

Vin

Phase-shifter

8

d2

Protections

1616

Clock

16

H-Pulses L-Pulses




35


UPM




422 97

438 101

442 102

434 -

DC Current(A)

431 99

445 102

424 98

448 103

Deviation()

Phase 2Phase 2

Phase 3Phase 3

Phase 4Phase 4

Phase 5Phase 5

Phase 6Phase 6

Phase 7Phase 7

Phase 8Phase 8

AverageAverage

DCMDCM


IO=17A

IO=27A


UPM





36


UPM


-05

0

05

1

15

2

00E+00 50E-06 10E-05 15E-05 20E-05 25E-05t (s)

()

-05

0

05

1

15

2

00E+00 50E-06 10E-05 15E-05 20E-05 25E-05t (s)

()

0

20

40

60

80

100

120

140

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35

Phase number

[+6-8]

0

20

40

60

80

100

120

140

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35

Phase number

[+6-8]

Half load(500W)


Full load(1000W)

0

1

2

3

4

p

0 5μs 10μs 15μs 20μs0

1

2

3

4

p



0

20

40

60

80

100

120

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35

Phase number

+10-75

0

20

40

60

80

100

120

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35

Phase number

+10-75



UPM

Output currentDC AC

11App

70ADC


is

0 01 02 03 04 05 06 07 08 09 100102030405

060708091

Duty cycle (d)

Nor

m c

urre

nt r

ippl

e Dutyvariation

2 phases

3 phases



37


UPM

10

5

5

10

3T0 x

5

5

3T0 x

Ideal case






10

5

5

10

3T0 x

5

5

3T0 x

Non-ideal



10

5

5

10

3T0 x

5

5

3T0 x

Worse case



10

5

5

10

3T0 x

5

5

3T0 x





UPM

ΔIP-P= 40A (5Adiv)

1 phase

ΔIP-P= 12A (5Adiv)

2 phases

ΔIP-P= 5A (5Adiv)

4 phases

ΔIP-P= 22A (1Adiv)

8 phases

ΔIP-P= 16A (1Adiv)

16 phases



38


UPM

(a)

30

31

22 40

37

22 33

2830

31

22 40

37

22 33

28

(a)

Center of mass

(a)

30

31

22 40

37

22 33

2830

31

22 40

37

22 33

28

(a)

Center of mass

Phase1Phase

2

Phase3

Phase4

Phase5

Phase6

Phase7

Phase8

1st

2nd

3rd 4th

6th

5th 8th

7th

(b)

1st

2nd

3rd 4th

6th

5th 8th

7th

1st

2nd

3rd 4th

6th

5th 8th

7th

(b)

40 A

37 A30 A

33 A

22 A 28 A

31 A

22 A






UPM

18 0 18

18

18

OVERALL 67A

18 0 18

18

18

1

2

34

56

7

8

9

10

1112 13

14

15

16

MAX

MIN

18 0 18

18

18

OVERALL 05A

18 0 18

18

18

1

2

34

56

7

8

9

10

1112 13

1415

16

MAX

MIN


16151413121110987654321

Phase number

165155177152140144148128147122154158139149142133

Current ripple (A)

39


UPM

ΔIP-P= 40A

ΔIP-P= 40A

ΔIP-P= 07A

ΔIP-P= 16A

57

ΔIP-P= 11A

ΔIP-P= 22A

50

ΔIP-P= 28A

ΔIP-P= 5A

44

ΔIP-P= 11A

ΔIP-P= 12A

9






1 2 4 8 16



UPM


Tswitch

delay

Load

voutvin



COUNTERDUTY CYCLE

DRIVING SIGNAL

Load

voutvin



40


UPM



Dri

vin

gsi

gnal

s

Counter

+ hellip +


Duty cycle





UPM


Dri

vin

gD

rivi

ng

sign

als

sign

als



ltDuty cycle


Shift Register



Counter


41


UPM






ASIC

12 12 phasesphases

6 6 phasesphases

24 24 phasesphases





0

2000

4000

6000

8000

10000

12000

14000

16000

2 4 6 8 12 16 20 24

0

2000

4000

6000

8000

10000

12000

2 4 6 8 12 16 20 24

0

2000

4000

6000

8000

10000

12000

14000

16000

18000

2 4 6 8 12 16 20 24


Res

ol 1

28Res

ol 2

56Res

ol 5

12

FPGA

Equ

ival

ent

gate

s

Phases

0

200

400

600

800

1000

2 4 6 8 12 16 20 24


Res

ol 1

28Res

ol 2

56Res

ol 5

120

200

400

600

800

1000

1200

2 4 6 8 12 16 20 24

0

200

400

600

800

1000

1200

1400

2 4 6 8 12 16 20 24

ASIC

Equ

ival

ent

gate

s

Phases


UPM


0

10

20

30

40

50

0 20 40 60 80



0

10

20

30

40

50

0 20 40 60 80



Iout

Pow

erlo

sses

(W)

80

84

88

92

96

0 10 20 30 40 50 60 70 80

6 phases

8 phases12 phases

16 phases

4 phases



Iout

Effic

ienc

y(

)

80

84

88

92

96

0 10 20 30 40 50 60 70 80

6 phases

8 phases12 phases

16 phases

4 phases



Iout

Effic

ienc

y(

)



42


UPM





UPM


RFAmp

Pow

erSt

age

Control

iRF

vs

VS

variable VS


24V

9Vfmax=35kHz

Input voltage = 28V





43


UPM


Cs

M1

L

M2

Cs

M1

L

M2

Cs

M1

L

M2

Cs

M1

L

M2

Ve Vout

CAR

GA




UPM


SW

CLK

ff Resolution =

Pipeline

fCLK

f = 25MHz f = 45MHz

Resolution required



fselected = 32MHz


44


UPM

33 33 DitherDither

SW

CLK

ff Resolution gt

d = 42

d =43

d =425

T=2TSW=8μs

Output voltage

2 solutions

V=50mV

TSW=4μs 1 solution

T=4μs

Output voltage

V=25mV

SW

CLKNVirtual



Average duty cycle

It gives 1 more bit


UPM



SimulatedSimulated

MeasuredMeasured



)(

4110780250 22




45


UPM






UPM


f = 200Hz f = 15kHz

f = 3kHz f = 5kHz

46


UPM





UPM



2 2 micromicross

Vo

1 V

2 V

VRM for DVS5 V

Io = 20 A max

1V - 2 V

Io

02 V max02 V max

0 A

20 A

500 Amicros

Vo




47


UPM


10-1 100 101

100

L-C diagram

C2 micros

200 mV

20A




C = 35 C = 35 μμFF



UPM






fsw = 520 kHz

(125 mΩ eq Rds_on)





48


UPM


0

1

To drivers

New vref

vo dig

N-phases_tran

N-phases

New vref

vo dig

New vref

vo dig


ic


NON-LINEAR CONTROL





UPM


vref

vo

0

1

To drivers

clk_sample

clk_sample

ADC

N-phases_tran

N-phases

vo dig

LINEAR CONTROL



49


UPM


vref

vo

0

1

To drivers

New vref

vo dig

clk_sample

clk_sample

ADC

N-phases_tran

N-phases

vo dig

New vref

LINEAR CONTROL

NON-LINEAR CONTROL

vo dig

New vrefvo dig


ic



Beware


UPM


UpUp--stepstep

ConverterFPGA

tt11



DownDown--stepstep

t1 t2 t1 t2

ddnn

tt22vref

500 kHz

LUT


05

1

15

2

25

0 02 04 06 08 1 12 14 16 18-10

0

10

20

30

40

50

ton toff

Tmin

05

1

15

2

25

0 02 04 06 08 1 12 14 16 18-10

0

10

20

30

40

50

ton toff

Tmin

i L(A

)i L

(A)

V o(V

)V o

(V)


50


UPM


t1 t2 t1 t2

094 096 098 1 102 104 106 108 11

x 10-4

14

16

18

2

22

24

26

28

3

32

094 096 098 1 102 104 106 108 11

x 10-4

0

1

2

3

4

5092 094 096 098 1 102 104 106 108 11 112

x 10-4

14

16

18

2

22

24

26

28

3

32

092 094 096 098 1 102 104 106 108 11 112

x 10-4

0

05

1

15

2

25

3

35

4

45

Transient





Beware


UPM

ΔIo

iL

Io

vo

ic 0 ATrip point 1

Trip point 2

ΔIo

ic





51


UPM


05358z02236z07417)(z3767G(z) 2 +sdotminus

+sdot=

B G(s)

G(z)




N = 4

ESR = 125 mΩ

( )CL

1sRESRL1s

CL1)1sCESR(V

)s(Gdv

L2

ino

sdot+sdot+sdot+


==

~ VinmiddotdCo

ESR

RphaseN LphaseN

Expected by design


DC resistance


model


Beware


UPM


Pole-Zero Map

Real Axis

-1 -08 -06 -04 -02 0 02 04 06 08 1-1

-08

-06

-04

-02

0

02

04

06

08

1

09

0807060504

03

02

01

26e5

234e5

208e5

182e5

156e513e5

104e5

781e4

521e4

26e4

26e5

234e5

208e5

182e5

156e513e5

104e5

781e4

521e4

26e4

x

x

x




Duty cycle

30 micros


1z00372)z(Rminus

=

1zK)z(R 1

minus=

Controller delay

05358z02236z07417)(z3767G(z) 2 +sdotminus

+sdot=Converter

x

x

x Duty cycle

Output voltage

52


UPM

10 micros


xx

x

x

x

x

x

x




00775)(z1)(z037)(z00378R(z)

minussdotminus+sdot

=

Duty cycle

Output voltage


UPM


75 micros

xx

x

x

x

xx

x



minussdotminus+sdot

=

53


UPM


Duty

a1 = -0922548 b1 = 0037759b2 = 0051742a2 = 0

b1

b2

δ-1

δ-1

δ-1

a1

a2

Error

bn0

No b0

δ-1

Z-1

+

00775)(z1)(z037)(z00378R(z)

minussdotminus+sdot

=




UPM


z2d_m ( tf ([00378 0013986] [1 -10775 00775] 192e-6) )




=Tsample = Tsw

⎪⎩

⎪⎨⎧

rarrδ

+=δ δδ

s


54


UPM


Reference

Switched model

7 bits

8 bits

Not quantizied


PWM

ADC

111






UPM

Reference


PWM

ADC






hellip

222

55


UPM



a1 = -0922548 b1 = 0037759b2 = 0051742a2 = 0

b1

b2

δ-1

δ-1

δ-1

a1

a2

Error

bn0

No b0


UPM


0lt Duty cycle lt1


Hardware adders






Beware

56


UPM

0 1 2 30

05

1

15

2

25








UPM



0 1 2 3

x 10-4

0

05

1

15

2

25

100 usdiv100 usdiv



57


UPM






UPM




58


UPM


13 14 15 16 17 18 19

x 10-4

12

14

16

18

2

22

08 V drop

10 microsdiv

2 V





UPM



Vo

1 V

2 V



11 A11 A

20 mV

520 kHz



59


UPM


Vo

Io

200 mV







UPM


Vo

1 V

2 V





60


UPM





Beware



UPM



30


UPM


VHDLVHDLVHDL

VHDL-AMS

VHDLVHDL--AMSAMS






UPM




VHDLVHDL








Simulationtime


CPU time using VHDL

models


modelsmodels



VHDL speed VHDL-AMS

speed


speedspeed

10 ms10 10 msms 69 s69 s69 s 446 s446 s446 s 641641641

100 ms100 100 msms 700 s700 s700 s 6912 s6912 s6912 s 987987987

1000 ms1000 1000 msms 6890 s6890 s6890 s 68443 s68443 s68443 s 993993993

VHDLVHDL--AMSAMS

31


UPM

42V 14V

CC

CC 42V 14V


system vehicles


Q1-1

Q2-1

Q16-1

Q16-2

Q2-2

Q1-2

L

L

L

COCIN




UPM


Q1-1

Q2-1

Q16-1

Q16-2

Q2-2

Q1-2

L

L

L

COCIN








3 prototypes


3 prototypes



32


UPM


VoVIN

L2d2

d1L1




VINd1

Battery

R1

R2

+

+ +

VINd2

1

BAT1IN1 R

VdVI minus=

2

22 R

VdVI BATIN -=


UPM







446

416

03360

03528

320

2336



1 5

CCM ndash 1000W

824

184

Not acceptable


Q1-1

Q2-1

Q16-1

Q16-2

Q2-2

Q1-2

L

L

L

33


UPM

AVGLI AVGLI


dT T

LVV OIN minus

LVOminus

AVGLI

dT T

LVV OIN minus

LVOminus

AVGLI

⎟⎟⎠

⎞⎜⎜⎝

⎛ minus=

O

OIN

i

2iIN

i VVV

fL2dVI



AVGLI AVGLI

DCMDCM


UPM


03360

03528






416

824



1 5

CCM ndash 1000W

0262002623

0275102649


1 5

DCM ndash 1000W

Not acceptable

445

490

446

454

110102

Very good


34


UPM



420 97

435 100

440 101

435 -

DC Current(A)

429 99

428 98

446 103

460 106

Deviation()

Phase 2

Phase 3

Phase 4

Phase 5

Phase 6

Phase 7

Phase 8

Average

CCM


IO=35A




UPM


ADCInterface

ampfilter

Regulator8

d1


Vout

ADCcontrol

Reset

Vin

12

MCDgenerator

12

Vout

12

Vin

Phase-shifter

8

d2

Protections

1616

Clock

16

H-Pulses L-Pulses




35


UPM




422 97

438 101

442 102

434 -

DC Current(A)

431 99

445 102

424 98

448 103

Deviation()

Phase 2Phase 2

Phase 3Phase 3

Phase 4Phase 4

Phase 5Phase 5

Phase 6Phase 6

Phase 7Phase 7

Phase 8Phase 8

AverageAverage

DCMDCM


IO=17A

IO=27A


UPM





36


UPM


-05

0

05

1

15

2

00E+00 50E-06 10E-05 15E-05 20E-05 25E-05t (s)

()

-05

0

05

1

15

2

00E+00 50E-06 10E-05 15E-05 20E-05 25E-05t (s)

()

0

20

40

60

80

100

120

140

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35

Phase number

[+6-8]

0

20

40

60

80

100

120

140

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35

Phase number

[+6-8]

Half load(500W)


Full load(1000W)

0

1

2

3

4

p

0 5μs 10μs 15μs 20μs0

1

2

3

4

p



0

20

40

60

80

100

120

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35

Phase number

+10-75

0

20

40

60

80

100

120

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35

Phase number

+10-75



UPM

Output currentDC AC

11App

70ADC


is

0 01 02 03 04 05 06 07 08 09 100102030405

060708091

Duty cycle (d)

Nor

m c

urre

nt r

ippl

e Dutyvariation

2 phases

3 phases



37


UPM

10

5

5

10

3T0 x

5

5

3T0 x

Ideal case






10

5

5

10

3T0 x

5

5

3T0 x

Non-ideal



10

5

5

10

3T0 x

5

5

3T0 x

Worse case



10

5

5

10

3T0 x

5

5

3T0 x





UPM

ΔIP-P= 40A (5Adiv)

1 phase

ΔIP-P= 12A (5Adiv)

2 phases

ΔIP-P= 5A (5Adiv)

4 phases

ΔIP-P= 22A (1Adiv)

8 phases

ΔIP-P= 16A (1Adiv)

16 phases



38


UPM

(a)

30

31

22 40

37

22 33

2830

31

22 40

37

22 33

28

(a)

Center of mass

(a)

30

31

22 40

37

22 33

2830

31

22 40

37

22 33

28

(a)

Center of mass

Phase1Phase

2

Phase3

Phase4

Phase5

Phase6

Phase7

Phase8

1st

2nd

3rd 4th

6th

5th 8th

7th

(b)

1st

2nd

3rd 4th

6th

5th 8th

7th

1st

2nd

3rd 4th

6th

5th 8th

7th

(b)

40 A

37 A30 A

33 A

22 A 28 A

31 A

22 A






UPM

18 0 18

18

18

OVERALL 67A

18 0 18

18

18

1

2

34

56

7

8

9

10

1112 13

14

15

16

MAX

MIN

18 0 18

18

18

OVERALL 05A

18 0 18

18

18

1

2

34

56

7

8

9

10

1112 13

1415

16

MAX

MIN


16151413121110987654321

Phase number

165155177152140144148128147122154158139149142133

Current ripple (A)

39


UPM

ΔIP-P= 40A

ΔIP-P= 40A

ΔIP-P= 07A

ΔIP-P= 16A

57

ΔIP-P= 11A

ΔIP-P= 22A

50

ΔIP-P= 28A

ΔIP-P= 5A

44

ΔIP-P= 11A

ΔIP-P= 12A

9






1 2 4 8 16



UPM


Tswitch

delay

Load

voutvin



COUNTERDUTY CYCLE

DRIVING SIGNAL

Load

voutvin



40


UPM



Dri

vin

gsi

gnal

s

Counter

+ hellip +


Duty cycle





UPM


Dri

vin

gD

rivi

ng

sign

als

sign

als



ltDuty cycle


Shift Register



Counter


41


UPM






ASIC

12 12 phasesphases

6 6 phasesphases

24 24 phasesphases





0

2000

4000

6000

8000

10000

12000

14000

16000

2 4 6 8 12 16 20 24

0

2000

4000

6000

8000

10000

12000

2 4 6 8 12 16 20 24

0

2000

4000

6000

8000

10000

12000

14000

16000

18000

2 4 6 8 12 16 20 24


Res

ol 1

28Res

ol 2

56Res

ol 5

12

FPGA

Equ

ival

ent

gate

s

Phases

0

200

400

600

800

1000

2 4 6 8 12 16 20 24


Res

ol 1

28Res

ol 2

56Res

ol 5

120

200

400

600

800

1000

1200

2 4 6 8 12 16 20 24

0

200

400

600

800

1000

1200

1400

2 4 6 8 12 16 20 24

ASIC

Equ

ival

ent

gate

s

Phases


UPM


0

10

20

30

40

50

0 20 40 60 80



0

10

20

30

40

50

0 20 40 60 80



Iout

Pow

erlo

sses

(W)

80

84

88

92

96

0 10 20 30 40 50 60 70 80

6 phases

8 phases12 phases

16 phases

4 phases



Iout

Effic

ienc

y(

)

80

84

88

92

96

0 10 20 30 40 50 60 70 80

6 phases

8 phases12 phases

16 phases

4 phases



Iout

Effic

ienc

y(

)



42


UPM





UPM


RFAmp

Pow

erSt

age

Control

iRF

vs

VS

variable VS


24V

9Vfmax=35kHz

Input voltage = 28V





43


UPM


Cs

M1

L

M2

Cs

M1

L

M2

Cs

M1

L

M2

Cs

M1

L

M2

Ve Vout

CAR

GA




UPM


SW

CLK

ff Resolution =

Pipeline

fCLK

f = 25MHz f = 45MHz

Resolution required



fselected = 32MHz


44


UPM

33 33 DitherDither

SW

CLK

ff Resolution gt

d = 42

d =43

d =425

T=2TSW=8μs

Output voltage

2 solutions

V=50mV

TSW=4μs 1 solution

T=4μs

Output voltage

V=25mV

SW

CLKNVirtual



Average duty cycle

It gives 1 more bit


UPM



SimulatedSimulated

MeasuredMeasured



)(

4110780250 22




45


UPM






UPM


f = 200Hz f = 15kHz

f = 3kHz f = 5kHz

46


UPM





UPM



2 2 micromicross

Vo

1 V

2 V

VRM for DVS5 V

Io = 20 A max

1V - 2 V

Io

02 V max02 V max

0 A

20 A

500 Amicros

Vo




47


UPM


10-1 100 101

100

L-C diagram

C2 micros

200 mV

20A




C = 35 C = 35 μμFF



UPM






fsw = 520 kHz

(125 mΩ eq Rds_on)





48


UPM


0

1

To drivers

New vref

vo dig

N-phases_tran

N-phases

New vref

vo dig

New vref

vo dig


ic


NON-LINEAR CONTROL





UPM


vref

vo

0

1

To drivers

clk_sample

clk_sample

ADC

N-phases_tran

N-phases

vo dig

LINEAR CONTROL



49


UPM


vref

vo

0

1

To drivers

New vref

vo dig

clk_sample

clk_sample

ADC

N-phases_tran

N-phases

vo dig

New vref

LINEAR CONTROL

NON-LINEAR CONTROL

vo dig

New vrefvo dig


ic



Beware


UPM


UpUp--stepstep

ConverterFPGA

tt11



DownDown--stepstep

t1 t2 t1 t2

ddnn

tt22vref

500 kHz

LUT


05

1

15

2

25

0 02 04 06 08 1 12 14 16 18-10

0

10

20

30

40

50

ton toff

Tmin

05

1

15

2

25

0 02 04 06 08 1 12 14 16 18-10

0

10

20

30

40

50

ton toff

Tmin

i L(A

)i L

(A)

V o(V

)V o

(V)


50


UPM


t1 t2 t1 t2

094 096 098 1 102 104 106 108 11

x 10-4

14

16

18

2

22

24

26

28

3

32

094 096 098 1 102 104 106 108 11

x 10-4

0

1

2

3

4

5092 094 096 098 1 102 104 106 108 11 112

x 10-4

14

16

18

2

22

24

26

28

3

32

092 094 096 098 1 102 104 106 108 11 112

x 10-4

0

05

1

15

2

25

3

35

4

45

Transient





Beware


UPM

ΔIo

iL

Io

vo

ic 0 ATrip point 1

Trip point 2

ΔIo

ic





51


UPM


05358z02236z07417)(z3767G(z) 2 +sdotminus

+sdot=

B G(s)

G(z)




N = 4

ESR = 125 mΩ

( )CL

1sRESRL1s

CL1)1sCESR(V

)s(Gdv

L2

ino

sdot+sdot+sdot+


==

~ VinmiddotdCo

ESR

RphaseN LphaseN

Expected by design


DC resistance


model


Beware


UPM


Pole-Zero Map

Real Axis

-1 -08 -06 -04 -02 0 02 04 06 08 1-1

-08

-06

-04

-02

0

02

04

06

08

1

09

0807060504

03

02

01

26e5

234e5

208e5

182e5

156e513e5

104e5

781e4

521e4

26e4

26e5

234e5

208e5

182e5

156e513e5

104e5

781e4

521e4

26e4

x

x

x




Duty cycle

30 micros


1z00372)z(Rminus

=

1zK)z(R 1

minus=

Controller delay

05358z02236z07417)(z3767G(z) 2 +sdotminus

+sdot=Converter

x

x

x Duty cycle

Output voltage

52


UPM

10 micros


xx

x

x

x

x

x

x




00775)(z1)(z037)(z00378R(z)

minussdotminus+sdot

=

Duty cycle

Output voltage


UPM


75 micros

xx

x

x

x

xx

x



minussdotminus+sdot

=

53


UPM


Duty

a1 = -0922548 b1 = 0037759b2 = 0051742a2 = 0

b1

b2

δ-1

δ-1

δ-1

a1

a2

Error

bn0

No b0

δ-1

Z-1

+

00775)(z1)(z037)(z00378R(z)

minussdotminus+sdot

=




UPM


z2d_m ( tf ([00378 0013986] [1 -10775 00775] 192e-6) )




=Tsample = Tsw

⎪⎩

⎪⎨⎧

rarrδ

+=δ δδ

s


54


UPM


Reference

Switched model

7 bits

8 bits

Not quantizied


PWM

ADC

111






UPM

Reference


PWM

ADC






hellip

222

55


UPM



a1 = -0922548 b1 = 0037759b2 = 0051742a2 = 0

b1

b2

δ-1

δ-1

δ-1

a1

a2

Error

bn0

No b0


UPM


0lt Duty cycle lt1


Hardware adders






Beware

56


UPM

0 1 2 30

05

1

15

2

25








UPM



0 1 2 3

x 10-4

0

05

1

15

2

25

100 usdiv100 usdiv



57


UPM






UPM




58


UPM


13 14 15 16 17 18 19

x 10-4

12

14

16

18

2

22

08 V drop

10 microsdiv

2 V





UPM



Vo

1 V

2 V



11 A11 A

20 mV

520 kHz



59


UPM


Vo

Io

200 mV







UPM


Vo

1 V

2 V





60


UPM





Beware



UPM



31


UPM

42V 14V

CC

CC 42V 14V


system vehicles


Q1-1

Q2-1

Q16-1

Q16-2

Q2-2

Q1-2

L

L

L

COCIN




UPM


Q1-1

Q2-1

Q16-1

Q16-2

Q2-2

Q1-2

L

L

L

COCIN








3 prototypes


3 prototypes



32


UPM


VoVIN

L2d2

d1L1




VINd1

Battery

R1

R2

+

+ +

VINd2

1

BAT1IN1 R

VdVI minus=

2

22 R

VdVI BATIN -=


UPM







446

416

03360

03528

320

2336



1 5

CCM ndash 1000W

824

184

Not acceptable


Q1-1

Q2-1

Q16-1

Q16-2

Q2-2

Q1-2

L

L

L

33


UPM

AVGLI AVGLI


dT T

LVV OIN minus

LVOminus

AVGLI

dT T

LVV OIN minus

LVOminus

AVGLI

⎟⎟⎠

⎞⎜⎜⎝

⎛ minus=

O

OIN

i

2iIN

i VVV

fL2dVI



AVGLI AVGLI

DCMDCM


UPM


03360

03528






416

824



1 5

CCM ndash 1000W

0262002623

0275102649


1 5

DCM ndash 1000W

Not acceptable

445

490

446

454

110102

Very good


34


UPM



420 97

435 100

440 101

435 -

DC Current(A)

429 99

428 98

446 103

460 106

Deviation()

Phase 2

Phase 3

Phase 4

Phase 5

Phase 6

Phase 7

Phase 8

Average

CCM


IO=35A




UPM


ADCInterface

ampfilter

Regulator8

d1


Vout

ADCcontrol

Reset

Vin

12

MCDgenerator

12

Vout

12

Vin

Phase-shifter

8

d2

Protections

1616

Clock

16

H-Pulses L-Pulses




35


UPM




422 97

438 101

442 102

434 -

DC Current(A)

431 99

445 102

424 98

448 103

Deviation()

Phase 2Phase 2

Phase 3Phase 3

Phase 4Phase 4

Phase 5Phase 5

Phase 6Phase 6

Phase 7Phase 7

Phase 8Phase 8

AverageAverage

DCMDCM


IO=17A

IO=27A


UPM





36


UPM


-05

0

05

1

15

2

00E+00 50E-06 10E-05 15E-05 20E-05 25E-05t (s)

()

-05

0

05

1

15

2

00E+00 50E-06 10E-05 15E-05 20E-05 25E-05t (s)

()

0

20

40

60

80

100

120

140

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35

Phase number

[+6-8]

0

20

40

60

80

100

120

140

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35

Phase number

[+6-8]

Half load(500W)


Full load(1000W)

0

1

2

3

4

p

0 5μs 10μs 15μs 20μs0

1

2

3

4

p



0

20

40

60

80

100

120

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35

Phase number

+10-75

0

20

40

60

80

100

120

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35

Phase number

+10-75



UPM

Output currentDC AC

11App

70ADC


is

0 01 02 03 04 05 06 07 08 09 100102030405

060708091

Duty cycle (d)

Nor

m c

urre

nt r

ippl

e Dutyvariation

2 phases

3 phases



37


UPM

10

5

5

10

3T0 x

5

5

3T0 x

Ideal case






10

5

5

10

3T0 x

5

5

3T0 x

Non-ideal



10

5

5

10

3T0 x

5

5

3T0 x

Worse case



10

5

5

10

3T0 x

5

5

3T0 x





UPM

ΔIP-P= 40A (5Adiv)

1 phase

ΔIP-P= 12A (5Adiv)

2 phases

ΔIP-P= 5A (5Adiv)

4 phases

ΔIP-P= 22A (1Adiv)

8 phases

ΔIP-P= 16A (1Adiv)

16 phases



38


UPM

(a)

30

31

22 40

37

22 33

2830

31

22 40

37

22 33

28

(a)

Center of mass

(a)

30

31

22 40

37

22 33

2830

31

22 40

37

22 33

28

(a)

Center of mass

Phase1Phase

2

Phase3

Phase4

Phase5

Phase6

Phase7

Phase8

1st

2nd

3rd 4th

6th

5th 8th

7th

(b)

1st

2nd

3rd 4th

6th

5th 8th

7th

1st

2nd

3rd 4th

6th

5th 8th

7th

(b)

40 A

37 A30 A

33 A

22 A 28 A

31 A

22 A






UPM

18 0 18

18

18

OVERALL 67A

18 0 18

18

18

1

2

34

56

7

8

9

10

1112 13

14

15

16

MAX

MIN

18 0 18

18

18

OVERALL 05A

18 0 18

18

18

1

2

34

56

7

8

9

10

1112 13

1415

16

MAX

MIN


16151413121110987654321

Phase number

165155177152140144148128147122154158139149142133

Current ripple (A)

39


UPM

ΔIP-P= 40A

ΔIP-P= 40A

ΔIP-P= 07A

ΔIP-P= 16A

57

ΔIP-P= 11A

ΔIP-P= 22A

50

ΔIP-P= 28A

ΔIP-P= 5A

44

ΔIP-P= 11A

ΔIP-P= 12A

9






1 2 4 8 16



UPM


Tswitch

delay

Load

voutvin



COUNTERDUTY CYCLE

DRIVING SIGNAL

Load

voutvin



40


UPM



Dri

vin

gsi

gnal

s

Counter

+ hellip +


Duty cycle





UPM


Dri

vin

gD

rivi

ng

sign

als

sign

als



ltDuty cycle


Shift Register



Counter


41


UPM






ASIC

12 12 phasesphases

6 6 phasesphases

24 24 phasesphases





0

2000

4000

6000

8000

10000

12000

14000

16000

2 4 6 8 12 16 20 24

0

2000

4000

6000

8000

10000

12000

2 4 6 8 12 16 20 24

0

2000

4000

6000

8000

10000

12000

14000

16000

18000

2 4 6 8 12 16 20 24


Res

ol 1

28Res

ol 2

56Res

ol 5

12

FPGA

Equ

ival

ent

gate

s

Phases

0

200

400

600

800

1000

2 4 6 8 12 16 20 24


Res

ol 1

28Res

ol 2

56Res

ol 5

120

200

400

600

800

1000

1200

2 4 6 8 12 16 20 24

0

200

400

600

800

1000

1200

1400

2 4 6 8 12 16 20 24

ASIC

Equ

ival

ent

gate

s

Phases


UPM


0

10

20

30

40

50

0 20 40 60 80



0

10

20

30

40

50

0 20 40 60 80



Iout

Pow

erlo

sses

(W)

80

84

88

92

96

0 10 20 30 40 50 60 70 80

6 phases

8 phases12 phases

16 phases

4 phases



Iout

Effic

ienc

y(

)

80

84

88

92

96

0 10 20 30 40 50 60 70 80

6 phases

8 phases12 phases

16 phases

4 phases



Iout

Effic

ienc

y(

)



42


UPM





UPM


RFAmp

Pow

erSt

age

Control

iRF

vs

VS

variable VS


24V

9Vfmax=35kHz

Input voltage = 28V





43


UPM


Cs

M1

L

M2

Cs

M1

L

M2

Cs

M1

L

M2

Cs

M1

L

M2

Ve Vout

CAR

GA




UPM


SW

CLK

ff Resolution =

Pipeline

fCLK

f = 25MHz f = 45MHz

Resolution required



fselected = 32MHz


44


UPM

33 33 DitherDither

SW

CLK

ff Resolution gt

d = 42

d =43

d =425

T=2TSW=8μs

Output voltage

2 solutions

V=50mV

TSW=4μs 1 solution

T=4μs

Output voltage

V=25mV

SW

CLKNVirtual



Average duty cycle

It gives 1 more bit


UPM



SimulatedSimulated

MeasuredMeasured



)(

4110780250 22




45


UPM






UPM


f = 200Hz f = 15kHz

f = 3kHz f = 5kHz

46


UPM





UPM



2 2 micromicross

Vo

1 V

2 V

VRM for DVS5 V

Io = 20 A max

1V - 2 V

Io

02 V max02 V max

0 A

20 A

500 Amicros

Vo




47


UPM


10-1 100 101

100

L-C diagram

C2 micros

200 mV

20A




C = 35 C = 35 μμFF



UPM






fsw = 520 kHz

(125 mΩ eq Rds_on)





48


UPM


0

1

To drivers

New vref

vo dig

N-phases_tran

N-phases

New vref

vo dig

New vref

vo dig


ic


NON-LINEAR CONTROL





UPM


vref

vo

0

1

To drivers

clk_sample

clk_sample

ADC

N-phases_tran

N-phases

vo dig

LINEAR CONTROL



49


UPM


vref

vo

0

1

To drivers

New vref

vo dig

clk_sample

clk_sample

ADC

N-phases_tran

N-phases

vo dig

New vref

LINEAR CONTROL

NON-LINEAR CONTROL

vo dig

New vrefvo dig


ic



Beware


UPM


UpUp--stepstep

ConverterFPGA

tt11



DownDown--stepstep

t1 t2 t1 t2

ddnn

tt22vref

500 kHz

LUT


05

1

15

2

25

0 02 04 06 08 1 12 14 16 18-10

0

10

20

30

40

50

ton toff

Tmin

05

1

15

2

25

0 02 04 06 08 1 12 14 16 18-10

0

10

20

30

40

50

ton toff

Tmin

i L(A

)i L

(A)

V o(V

)V o

(V)


50


UPM


t1 t2 t1 t2

094 096 098 1 102 104 106 108 11

x 10-4

14

16

18

2

22

24

26

28

3

32

094 096 098 1 102 104 106 108 11

x 10-4

0

1

2

3

4

5092 094 096 098 1 102 104 106 108 11 112

x 10-4

14

16

18

2

22

24

26

28

3

32

092 094 096 098 1 102 104 106 108 11 112

x 10-4

0

05

1

15

2

25

3

35

4

45

Transient





Beware


UPM

ΔIo

iL

Io

vo

ic 0 ATrip point 1

Trip point 2

ΔIo

ic





51


UPM


05358z02236z07417)(z3767G(z) 2 +sdotminus

+sdot=

B G(s)

G(z)




N = 4

ESR = 125 mΩ

( )CL

1sRESRL1s

CL1)1sCESR(V

)s(Gdv

L2

ino

sdot+sdot+sdot+


==

~ VinmiddotdCo

ESR

RphaseN LphaseN

Expected by design


DC resistance


model


Beware


UPM


Pole-Zero Map

Real Axis

-1 -08 -06 -04 -02 0 02 04 06 08 1-1

-08

-06

-04

-02

0

02

04

06

08

1

09

0807060504

03

02

01

26e5

234e5

208e5

182e5

156e513e5

104e5

781e4

521e4

26e4

26e5

234e5

208e5

182e5

156e513e5

104e5

781e4

521e4

26e4

x

x

x




Duty cycle

30 micros


1z00372)z(Rminus

=

1zK)z(R 1

minus=

Controller delay

05358z02236z07417)(z3767G(z) 2 +sdotminus

+sdot=Converter

x

x

x Duty cycle

Output voltage

52


UPM

10 micros


xx

x

x

x

x

x

x




00775)(z1)(z037)(z00378R(z)

minussdotminus+sdot

=

Duty cycle

Output voltage


UPM


75 micros

xx

x

x

x

xx

x



minussdotminus+sdot

=

53


UPM


Duty

a1 = -0922548 b1 = 0037759b2 = 0051742a2 = 0

b1

b2

δ-1

δ-1

δ-1

a1

a2

Error

bn0

No b0

δ-1

Z-1

+

00775)(z1)(z037)(z00378R(z)

minussdotminus+sdot

=




UPM


z2d_m ( tf ([00378 0013986] [1 -10775 00775] 192e-6) )




=Tsample = Tsw

⎪⎩

⎪⎨⎧

rarrδ

+=δ δδ

s


54


UPM


Reference

Switched model

7 bits

8 bits

Not quantizied


PWM

ADC

111






UPM

Reference


PWM

ADC






hellip

222

55


UPM



a1 = -0922548 b1 = 0037759b2 = 0051742a2 = 0

b1

b2

δ-1

δ-1

δ-1

a1

a2

Error

bn0

No b0


UPM


0lt Duty cycle lt1


Hardware adders






Beware

56


UPM

0 1 2 30

05

1

15

2

25








UPM



0 1 2 3

x 10-4

0

05

1

15

2

25

100 usdiv100 usdiv



57


UPM






UPM




58


UPM


13 14 15 16 17 18 19

x 10-4

12

14

16

18

2

22

08 V drop

10 microsdiv

2 V





UPM



Vo

1 V

2 V



11 A11 A

20 mV

520 kHz



59


UPM


Vo

Io

200 mV







UPM


Vo

1 V

2 V





60


UPM





Beware



UPM



32


UPM


VoVIN

L2d2

d1L1




VINd1

Battery

R1

R2

+

+ +

VINd2

1

BAT1IN1 R

VdVI minus=

2

22 R

VdVI BATIN -=


UPM







446

416

03360

03528

320

2336



1 5

CCM ndash 1000W

824

184

Not acceptable


Q1-1

Q2-1

Q16-1

Q16-2

Q2-2

Q1-2

L

L

L

33


UPM

AVGLI AVGLI


dT T

LVV OIN minus

LVOminus

AVGLI

dT T

LVV OIN minus

LVOminus

AVGLI

⎟⎟⎠

⎞⎜⎜⎝

⎛ minus=

O

OIN

i

2iIN

i VVV

fL2dVI



AVGLI AVGLI

DCMDCM


UPM


03360

03528






416

824



1 5

CCM ndash 1000W

0262002623

0275102649


1 5

DCM ndash 1000W

Not acceptable

445

490

446

454

110102

Very good


34


UPM



420 97

435 100

440 101

435 -

DC Current(A)

429 99

428 98

446 103

460 106

Deviation()

Phase 2

Phase 3

Phase 4

Phase 5

Phase 6

Phase 7

Phase 8

Average

CCM


IO=35A




UPM


ADCInterface

ampfilter

Regulator8

d1


Vout

ADCcontrol

Reset

Vin

12

MCDgenerator

12

Vout

12

Vin

Phase-shifter

8

d2

Protections

1616

Clock

16

H-Pulses L-Pulses




35


UPM




422 97

438 101

442 102

434 -

DC Current(A)

431 99

445 102

424 98

448 103

Deviation()

Phase 2Phase 2

Phase 3Phase 3

Phase 4Phase 4

Phase 5Phase 5

Phase 6Phase 6

Phase 7Phase 7

Phase 8Phase 8

AverageAverage

DCMDCM


IO=17A

IO=27A


UPM





36


UPM


-05

0

05

1

15

2

00E+00 50E-06 10E-05 15E-05 20E-05 25E-05t (s)

()

-05

0

05

1

15

2

00E+00 50E-06 10E-05 15E-05 20E-05 25E-05t (s)

()

0

20

40

60

80

100

120

140

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35

Phase number

[+6-8]

0

20

40

60

80

100

120

140

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35

Phase number

[+6-8]

Half load(500W)


Full load(1000W)

0

1

2

3

4

p

0 5μs 10μs 15μs 20μs0

1

2

3

4

p



0

20

40

60

80

100

120

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35

Phase number

+10-75

0

20

40

60

80

100

120

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35

Phase number

+10-75



UPM

Output currentDC AC

11App

70ADC


is

0 01 02 03 04 05 06 07 08 09 100102030405

060708091

Duty cycle (d)

Nor

m c

urre

nt r

ippl

e Dutyvariation

2 phases

3 phases



37


UPM

10

5

5

10

3T0 x

5

5

3T0 x

Ideal case






10

5

5

10

3T0 x

5

5

3T0 x

Non-ideal



10

5

5

10

3T0 x

5

5

3T0 x

Worse case



10

5

5

10

3T0 x

5

5

3T0 x





UPM

ΔIP-P= 40A (5Adiv)

1 phase

ΔIP-P= 12A (5Adiv)

2 phases

ΔIP-P= 5A (5Adiv)

4 phases

ΔIP-P= 22A (1Adiv)

8 phases

ΔIP-P= 16A (1Adiv)

16 phases



38


UPM

(a)

30

31

22 40

37

22 33

2830

31

22 40

37

22 33

28

(a)

Center of mass

(a)

30

31

22 40

37

22 33

2830

31

22 40

37

22 33

28

(a)

Center of mass

Phase1Phase

2

Phase3

Phase4

Phase5

Phase6

Phase7

Phase8

1st

2nd

3rd 4th

6th

5th 8th

7th

(b)

1st

2nd

3rd 4th

6th

5th 8th

7th

1st

2nd

3rd 4th

6th

5th 8th

7th

(b)

40 A

37 A30 A

33 A

22 A 28 A

31 A

22 A






UPM

18 0 18

18

18

OVERALL 67A

18 0 18

18

18

1

2

34

56

7

8

9

10

1112 13

14

15

16

MAX

MIN

18 0 18

18

18

OVERALL 05A

18 0 18

18

18

1

2

34

56

7

8

9

10

1112 13

1415

16

MAX

MIN


16151413121110987654321

Phase number

165155177152140144148128147122154158139149142133

Current ripple (A)

39


UPM

ΔIP-P= 40A

ΔIP-P= 40A

ΔIP-P= 07A

ΔIP-P= 16A

57

ΔIP-P= 11A

ΔIP-P= 22A

50

ΔIP-P= 28A

ΔIP-P= 5A

44

ΔIP-P= 11A

ΔIP-P= 12A

9






1 2 4 8 16



UPM


Tswitch

delay

Load

voutvin



COUNTERDUTY CYCLE

DRIVING SIGNAL

Load

voutvin



40


UPM



Dri

vin

gsi

gnal

s

Counter

+ hellip +


Duty cycle





UPM


Dri

vin

gD

rivi

ng

sign

als

sign

als



ltDuty cycle


Shift Register



Counter


41


UPM






ASIC

12 12 phasesphases

6 6 phasesphases

24 24 phasesphases





0

2000

4000

6000

8000

10000

12000

14000

16000

2 4 6 8 12 16 20 24

0

2000

4000

6000

8000

10000

12000

2 4 6 8 12 16 20 24

0

2000

4000

6000

8000

10000

12000

14000

16000

18000

2 4 6 8 12 16 20 24


Res

ol 1

28Res

ol 2

56Res

ol 5

12

FPGA

Equ

ival

ent

gate

s

Phases

0

200

400

600

800

1000

2 4 6 8 12 16 20 24


Res

ol 1

28Res

ol 2

56Res

ol 5

120

200

400

600

800

1000

1200

2 4 6 8 12 16 20 24

0

200

400

600

800

1000

1200

1400

2 4 6 8 12 16 20 24

ASIC

Equ

ival

ent

gate

s

Phases


UPM


0

10

20

30

40

50

0 20 40 60 80



0

10

20

30

40

50

0 20 40 60 80



Iout

Pow

erlo

sses

(W)

80

84

88

92

96

0 10 20 30 40 50 60 70 80

6 phases

8 phases12 phases

16 phases

4 phases



Iout

Effic

ienc

y(

)

80

84

88

92

96

0 10 20 30 40 50 60 70 80

6 phases

8 phases12 phases

16 phases

4 phases



Iout

Effic

ienc

y(

)



42


UPM





UPM


RFAmp

Pow

erSt

age

Control

iRF

vs

VS

variable VS


24V

9Vfmax=35kHz

Input voltage = 28V





43


UPM


Cs

M1

L

M2

Cs

M1

L

M2

Cs

M1

L

M2

Cs

M1

L

M2

Ve Vout

CAR

GA




UPM


SW

CLK

ff Resolution =

Pipeline

fCLK

f = 25MHz f = 45MHz

Resolution required



fselected = 32MHz


44


UPM

33 33 DitherDither

SW

CLK

ff Resolution gt

d = 42

d =43

d =425

T=2TSW=8μs

Output voltage

2 solutions

V=50mV

TSW=4μs 1 solution

T=4μs

Output voltage

V=25mV

SW

CLKNVirtual



Average duty cycle

It gives 1 more bit


UPM



SimulatedSimulated

MeasuredMeasured



)(

4110780250 22




45


UPM






UPM


f = 200Hz f = 15kHz

f = 3kHz f = 5kHz

46


UPM





UPM



2 2 micromicross

Vo

1 V

2 V

VRM for DVS5 V

Io = 20 A max

1V - 2 V

Io

02 V max02 V max

0 A

20 A

500 Amicros

Vo




47


UPM


10-1 100 101

100

L-C diagram

C2 micros

200 mV

20A




C = 35 C = 35 μμFF



UPM






fsw = 520 kHz

(125 mΩ eq Rds_on)





48


UPM


0

1

To drivers

New vref

vo dig

N-phases_tran

N-phases

New vref

vo dig

New vref

vo dig


ic


NON-LINEAR CONTROL





UPM


vref

vo

0

1

To drivers

clk_sample

clk_sample

ADC

N-phases_tran

N-phases

vo dig

LINEAR CONTROL



49


UPM


vref

vo

0

1

To drivers

New vref

vo dig

clk_sample

clk_sample

ADC

N-phases_tran

N-phases

vo dig

New vref

LINEAR CONTROL

NON-LINEAR CONTROL

vo dig

New vrefvo dig


ic



Beware


UPM


UpUp--stepstep

ConverterFPGA

tt11



DownDown--stepstep

t1 t2 t1 t2

ddnn

tt22vref

500 kHz

LUT


05

1

15

2

25

0 02 04 06 08 1 12 14 16 18-10

0

10

20

30

40

50

ton toff

Tmin

05

1

15

2

25

0 02 04 06 08 1 12 14 16 18-10

0

10

20

30

40

50

ton toff

Tmin

i L(A

)i L

(A)

V o(V

)V o

(V)


50


UPM


t1 t2 t1 t2

094 096 098 1 102 104 106 108 11

x 10-4

14

16

18

2

22

24

26

28

3

32

094 096 098 1 102 104 106 108 11

x 10-4

0

1

2

3

4

5092 094 096 098 1 102 104 106 108 11 112

x 10-4

14

16

18

2

22

24

26

28

3

32

092 094 096 098 1 102 104 106 108 11 112

x 10-4

0

05

1

15

2

25

3

35

4

45

Transient





Beware


UPM

ΔIo

iL

Io

vo

ic 0 ATrip point 1

Trip point 2

ΔIo

ic





51


UPM


05358z02236z07417)(z3767G(z) 2 +sdotminus

+sdot=

B G(s)

G(z)




N = 4

ESR = 125 mΩ

( )CL

1sRESRL1s

CL1)1sCESR(V

)s(Gdv

L2

ino

sdot+sdot+sdot+


==

~ VinmiddotdCo

ESR

RphaseN LphaseN

Expected by design


DC resistance


model


Beware


UPM


Pole-Zero Map

Real Axis

-1 -08 -06 -04 -02 0 02 04 06 08 1-1

-08

-06

-04

-02

0

02

04

06

08

1

09

0807060504

03

02

01

26e5

234e5

208e5

182e5

156e513e5

104e5

781e4

521e4

26e4

26e5

234e5

208e5

182e5

156e513e5

104e5

781e4

521e4

26e4

x

x

x




Duty cycle

30 micros


1z00372)z(Rminus

=

1zK)z(R 1

minus=

Controller delay

05358z02236z07417)(z3767G(z) 2 +sdotminus

+sdot=Converter

x

x

x Duty cycle

Output voltage

52


UPM

10 micros


xx

x

x

x

x

x

x




00775)(z1)(z037)(z00378R(z)

minussdotminus+sdot

=

Duty cycle

Output voltage


UPM


75 micros

xx

x

x

x

xx

x



minussdotminus+sdot

=

53


UPM


Duty

a1 = -0922548 b1 = 0037759b2 = 0051742a2 = 0

b1

b2

δ-1

δ-1

δ-1

a1

a2

Error

bn0

No b0

δ-1

Z-1

+

00775)(z1)(z037)(z00378R(z)

minussdotminus+sdot

=




UPM


z2d_m ( tf ([00378 0013986] [1 -10775 00775] 192e-6) )




=Tsample = Tsw

⎪⎩

⎪⎨⎧

rarrδ

+=δ δδ

s


54


UPM


Reference

Switched model

7 bits

8 bits

Not quantizied


PWM

ADC

111






UPM

Reference


PWM

ADC






hellip

222

55


UPM



a1 = -0922548 b1 = 0037759b2 = 0051742a2 = 0

b1

b2

δ-1

δ-1

δ-1

a1

a2

Error

bn0

No b0


UPM


0lt Duty cycle lt1


Hardware adders






Beware

56


UPM

0 1 2 30

05

1

15

2

25








UPM



0 1 2 3

x 10-4

0

05

1

15

2

25

100 usdiv100 usdiv



57


UPM






UPM




58


UPM


13 14 15 16 17 18 19

x 10-4

12

14

16

18

2

22

08 V drop

10 microsdiv

2 V





UPM



Vo

1 V

2 V



11 A11 A

20 mV

520 kHz



59


UPM


Vo

Io

200 mV







UPM


Vo

1 V

2 V





60


UPM





Beware



UPM



33


UPM

AVGLI AVGLI


dT T

LVV OIN minus

LVOminus

AVGLI

dT T

LVV OIN minus

LVOminus

AVGLI

⎟⎟⎠

⎞⎜⎜⎝

⎛ minus=

O

OIN

i

2iIN

i VVV

fL2dVI



AVGLI AVGLI

DCMDCM


UPM


03360

03528






416

824



1 5

CCM ndash 1000W

0262002623

0275102649


1 5

DCM ndash 1000W

Not acceptable

445

490

446

454

110102

Very good


34


UPM



420 97

435 100

440 101

435 -

DC Current(A)

429 99

428 98

446 103

460 106

Deviation()

Phase 2

Phase 3

Phase 4

Phase 5

Phase 6

Phase 7

Phase 8

Average

CCM


IO=35A




UPM


ADCInterface

ampfilter

Regulator8

d1


Vout

ADCcontrol

Reset

Vin

12

MCDgenerator

12

Vout

12

Vin

Phase-shifter

8

d2

Protections

1616

Clock

16

H-Pulses L-Pulses




35


UPM




422 97

438 101

442 102

434 -

DC Current(A)

431 99

445 102

424 98

448 103

Deviation()

Phase 2Phase 2

Phase 3Phase 3

Phase 4Phase 4

Phase 5Phase 5

Phase 6Phase 6

Phase 7Phase 7

Phase 8Phase 8

AverageAverage

DCMDCM


IO=17A

IO=27A


UPM





36


UPM


-05

0

05

1

15

2

00E+00 50E-06 10E-05 15E-05 20E-05 25E-05t (s)

()

-05

0

05

1

15

2

00E+00 50E-06 10E-05 15E-05 20E-05 25E-05t (s)

()

0

20

40

60

80

100

120

140

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35

Phase number

[+6-8]

0

20

40

60

80

100

120

140

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35

Phase number

[+6-8]

Half load(500W)


Full load(1000W)

0

1

2

3

4

p

0 5μs 10μs 15μs 20μs0

1

2

3

4

p



0

20

40

60

80

100

120

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35

Phase number

+10-75

0

20

40

60

80

100

120

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35

Phase number

+10-75



UPM

Output currentDC AC

11App

70ADC


is

0 01 02 03 04 05 06 07 08 09 100102030405

060708091

Duty cycle (d)

Nor

m c

urre

nt r

ippl

e Dutyvariation

2 phases

3 phases



37


UPM

10

5

5

10

3T0 x

5

5

3T0 x

Ideal case






10

5

5

10

3T0 x

5

5

3T0 x

Non-ideal



10

5

5

10

3T0 x

5

5

3T0 x

Worse case



10

5

5

10

3T0 x

5

5

3T0 x





UPM

ΔIP-P= 40A (5Adiv)

1 phase

ΔIP-P= 12A (5Adiv)

2 phases

ΔIP-P= 5A (5Adiv)

4 phases

ΔIP-P= 22A (1Adiv)

8 phases

ΔIP-P= 16A (1Adiv)

16 phases



38


UPM

(a)

30

31

22 40

37

22 33

2830

31

22 40

37

22 33

28

(a)

Center of mass

(a)

30

31

22 40

37

22 33

2830

31

22 40

37

22 33

28

(a)

Center of mass

Phase1Phase

2

Phase3

Phase4

Phase5

Phase6

Phase7

Phase8

1st

2nd

3rd 4th

6th

5th 8th

7th

(b)

1st

2nd

3rd 4th

6th

5th 8th

7th

1st

2nd

3rd 4th

6th

5th 8th

7th

(b)

40 A

37 A30 A

33 A

22 A 28 A

31 A

22 A






UPM

18 0 18

18

18

OVERALL 67A

18 0 18

18

18

1

2

34

56

7

8

9

10

1112 13

14

15

16

MAX

MIN

18 0 18

18

18

OVERALL 05A

18 0 18

18

18

1

2

34

56

7

8

9

10

1112 13

1415

16

MAX

MIN


16151413121110987654321

Phase number

165155177152140144148128147122154158139149142133

Current ripple (A)

39


UPM

ΔIP-P= 40A

ΔIP-P= 40A

ΔIP-P= 07A

ΔIP-P= 16A

57

ΔIP-P= 11A

ΔIP-P= 22A

50

ΔIP-P= 28A

ΔIP-P= 5A

44

ΔIP-P= 11A

ΔIP-P= 12A

9






1 2 4 8 16



UPM


Tswitch

delay

Load

voutvin



COUNTERDUTY CYCLE

DRIVING SIGNAL

Load

voutvin



40


UPM



Dri

vin

gsi

gnal

s

Counter

+ hellip +


Duty cycle





UPM


Dri

vin

gD

rivi

ng

sign

als

sign

als



ltDuty cycle


Shift Register



Counter


41


UPM






ASIC

12 12 phasesphases

6 6 phasesphases

24 24 phasesphases





0

2000

4000

6000

8000

10000

12000

14000

16000

2 4 6 8 12 16 20 24

0

2000

4000

6000

8000

10000

12000

2 4 6 8 12 16 20 24

0

2000

4000

6000

8000

10000

12000

14000

16000

18000

2 4 6 8 12 16 20 24


Res

ol 1

28Res

ol 2

56Res

ol 5

12

FPGA

Equ

ival

ent

gate

s

Phases

0

200

400

600

800

1000

2 4 6 8 12 16 20 24


Res

ol 1

28Res

ol 2

56Res

ol 5

120

200

400

600

800

1000

1200

2 4 6 8 12 16 20 24

0

200

400

600

800

1000

1200

1400

2 4 6 8 12 16 20 24

ASIC

Equ

ival

ent

gate

s

Phases


UPM


0

10

20

30

40

50

0 20 40 60 80



0

10

20

30

40

50

0 20 40 60 80



Iout

Pow

erlo

sses

(W)

80

84

88

92

96

0 10 20 30 40 50 60 70 80

6 phases

8 phases12 phases

16 phases

4 phases



Iout

Effic

ienc

y(

)

80

84

88

92

96

0 10 20 30 40 50 60 70 80

6 phases

8 phases12 phases

16 phases

4 phases



Iout

Effic

ienc

y(

)



42


UPM





UPM


RFAmp

Pow

erSt

age

Control

iRF

vs

VS

variable VS


24V

9Vfmax=35kHz

Input voltage = 28V





43


UPM


Cs

M1

L

M2

Cs

M1

L

M2

Cs

M1

L

M2

Cs

M1

L

M2

Ve Vout

CAR

GA




UPM


SW

CLK

ff Resolution =

Pipeline

fCLK

f = 25MHz f = 45MHz

Resolution required



fselected = 32MHz


44


UPM

33 33 DitherDither

SW

CLK

ff Resolution gt

d = 42

d =43

d =425

T=2TSW=8μs

Output voltage

2 solutions

V=50mV

TSW=4μs 1 solution

T=4μs

Output voltage

V=25mV

SW

CLKNVirtual



Average duty cycle

It gives 1 more bit


UPM



SimulatedSimulated

MeasuredMeasured



)(

4110780250 22




45


UPM






UPM


f = 200Hz f = 15kHz

f = 3kHz f = 5kHz

46


UPM





UPM



2 2 micromicross

Vo

1 V

2 V

VRM for DVS5 V

Io = 20 A max

1V - 2 V

Io

02 V max02 V max

0 A

20 A

500 Amicros

Vo




47


UPM


10-1 100 101

100

L-C diagram

C2 micros

200 mV

20A




C = 35 C = 35 μμFF



UPM






fsw = 520 kHz

(125 mΩ eq Rds_on)





48


UPM


0

1

To drivers

New vref

vo dig

N-phases_tran

N-phases

New vref

vo dig

New vref

vo dig


ic


NON-LINEAR CONTROL





UPM


vref

vo

0

1

To drivers

clk_sample

clk_sample

ADC

N-phases_tran

N-phases

vo dig

LINEAR CONTROL



49


UPM


vref

vo

0

1

To drivers

New vref

vo dig

clk_sample

clk_sample

ADC

N-phases_tran

N-phases

vo dig

New vref

LINEAR CONTROL

NON-LINEAR CONTROL

vo dig

New vrefvo dig


ic



Beware


UPM


UpUp--stepstep

ConverterFPGA

tt11



DownDown--stepstep

t1 t2 t1 t2

ddnn

tt22vref

500 kHz

LUT


05

1

15

2

25

0 02 04 06 08 1 12 14 16 18-10

0

10

20

30

40

50

ton toff

Tmin

05

1

15

2

25

0 02 04 06 08 1 12 14 16 18-10

0

10

20

30

40

50

ton toff

Tmin

i L(A

)i L

(A)

V o(V

)V o

(V)


50


UPM


t1 t2 t1 t2

094 096 098 1 102 104 106 108 11

x 10-4

14

16

18

2

22

24

26

28

3

32

094 096 098 1 102 104 106 108 11

x 10-4

0

1

2

3

4

5092 094 096 098 1 102 104 106 108 11 112

x 10-4

14

16

18

2

22

24

26

28

3

32

092 094 096 098 1 102 104 106 108 11 112

x 10-4

0

05

1

15

2

25

3

35

4

45

Transient





Beware


UPM

ΔIo

iL

Io

vo

ic 0 ATrip point 1

Trip point 2

ΔIo

ic





51


UPM


05358z02236z07417)(z3767G(z) 2 +sdotminus

+sdot=

B G(s)

G(z)




N = 4

ESR = 125 mΩ

( )CL

1sRESRL1s

CL1)1sCESR(V

)s(Gdv

L2

ino

sdot+sdot+sdot+


==

~ VinmiddotdCo

ESR

RphaseN LphaseN

Expected by design


DC resistance


model


Beware


UPM


Pole-Zero Map

Real Axis

-1 -08 -06 -04 -02 0 02 04 06 08 1-1

-08

-06

-04

-02

0

02

04

06

08

1

09

0807060504

03

02

01

26e5

234e5

208e5

182e5

156e513e5

104e5

781e4

521e4

26e4

26e5

234e5

208e5

182e5

156e513e5

104e5

781e4

521e4

26e4

x

x

x




Duty cycle

30 micros


1z00372)z(Rminus

=

1zK)z(R 1

minus=

Controller delay

05358z02236z07417)(z3767G(z) 2 +sdotminus

+sdot=Converter

x

x

x Duty cycle

Output voltage

52


UPM

10 micros


xx

x

x

x

x

x

x




00775)(z1)(z037)(z00378R(z)

minussdotminus+sdot

=

Duty cycle

Output voltage


UPM


75 micros

xx

x

x

x

xx

x



minussdotminus+sdot

=

53


UPM


Duty

a1 = -0922548 b1 = 0037759b2 = 0051742a2 = 0

b1

b2

δ-1

δ-1

δ-1

a1

a2

Error

bn0

No b0

δ-1

Z-1

+

00775)(z1)(z037)(z00378R(z)

minussdotminus+sdot

=




UPM


z2d_m ( tf ([00378 0013986] [1 -10775 00775] 192e-6) )




=Tsample = Tsw

⎪⎩

⎪⎨⎧

rarrδ

+=δ δδ

s


54


UPM


Reference

Switched model

7 bits

8 bits

Not quantizied


PWM

ADC

111






UPM

Reference


PWM

ADC






hellip

222

55


UPM



a1 = -0922548 b1 = 0037759b2 = 0051742a2 = 0

b1

b2

δ-1

δ-1

δ-1

a1

a2

Error

bn0

No b0


UPM


0lt Duty cycle lt1


Hardware adders






Beware

56


UPM

0 1 2 30

05

1

15

2

25








UPM



0 1 2 3

x 10-4

0

05

1

15

2

25

100 usdiv100 usdiv



57


UPM






UPM




58


UPM


13 14 15 16 17 18 19

x 10-4

12

14

16

18

2

22

08 V drop

10 microsdiv

2 V





UPM



Vo

1 V

2 V



11 A11 A

20 mV

520 kHz



59


UPM


Vo

Io

200 mV







UPM


Vo

1 V

2 V





60


UPM





Beware



UPM



34


UPM



420 97

435 100

440 101

435 -

DC Current(A)

429 99

428 98

446 103

460 106

Deviation()

Phase 2

Phase 3

Phase 4

Phase 5

Phase 6

Phase 7

Phase 8

Average

CCM


IO=35A




UPM


ADCInterface

ampfilter

Regulator8

d1


Vout

ADCcontrol

Reset

Vin

12

MCDgenerator

12

Vout

12

Vin

Phase-shifter

8

d2

Protections

1616

Clock

16

H-Pulses L-Pulses




35


UPM




422 97

438 101

442 102

434 -

DC Current(A)

431 99

445 102

424 98

448 103

Deviation()

Phase 2Phase 2

Phase 3Phase 3

Phase 4Phase 4

Phase 5Phase 5

Phase 6Phase 6

Phase 7Phase 7

Phase 8Phase 8

AverageAverage

DCMDCM


IO=17A

IO=27A


UPM





36


UPM


-05

0

05

1

15

2

00E+00 50E-06 10E-05 15E-05 20E-05 25E-05t (s)

()

-05

0

05

1

15

2

00E+00 50E-06 10E-05 15E-05 20E-05 25E-05t (s)

()

0

20

40

60

80

100

120

140

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35

Phase number

[+6-8]

0

20

40

60

80

100

120

140

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35

Phase number

[+6-8]

Half load(500W)


Full load(1000W)

0

1

2

3

4

p

0 5μs 10μs 15μs 20μs0

1

2

3

4

p



0

20

40

60

80

100

120

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35

Phase number

+10-75

0

20

40

60

80

100

120

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35

Phase number

+10-75



UPM

Output currentDC AC

11App

70ADC


is

0 01 02 03 04 05 06 07 08 09 100102030405

060708091

Duty cycle (d)

Nor

m c

urre

nt r

ippl

e Dutyvariation

2 phases

3 phases



37


UPM

10

5

5

10

3T0 x

5

5

3T0 x

Ideal case






10

5

5

10

3T0 x

5

5

3T0 x

Non-ideal



10

5

5

10

3T0 x

5

5

3T0 x

Worse case



10

5

5

10

3T0 x

5

5

3T0 x





UPM

ΔIP-P= 40A (5Adiv)

1 phase

ΔIP-P= 12A (5Adiv)

2 phases

ΔIP-P= 5A (5Adiv)

4 phases

ΔIP-P= 22A (1Adiv)

8 phases

ΔIP-P= 16A (1Adiv)

16 phases



38


UPM

(a)

30

31

22 40

37

22 33

2830

31

22 40

37

22 33

28

(a)

Center of mass

(a)

30

31

22 40

37

22 33

2830

31

22 40

37

22 33

28

(a)

Center of mass

Phase1Phase

2

Phase3

Phase4

Phase5

Phase6

Phase7

Phase8

1st

2nd

3rd 4th

6th

5th 8th

7th

(b)

1st

2nd

3rd 4th

6th

5th 8th

7th

1st

2nd

3rd 4th

6th

5th 8th

7th

(b)

40 A

37 A30 A

33 A

22 A 28 A

31 A

22 A






UPM

18 0 18

18

18

OVERALL 67A

18 0 18

18

18

1

2

34

56

7

8

9

10

1112 13

14

15

16

MAX

MIN

18 0 18

18

18

OVERALL 05A

18 0 18

18

18

1

2

34

56

7

8

9

10

1112 13

1415

16

MAX

MIN


16151413121110987654321

Phase number

165155177152140144148128147122154158139149142133

Current ripple (A)

39


UPM

ΔIP-P= 40A

ΔIP-P= 40A

ΔIP-P= 07A

ΔIP-P= 16A

57

ΔIP-P= 11A

ΔIP-P= 22A

50

ΔIP-P= 28A

ΔIP-P= 5A

44

ΔIP-P= 11A

ΔIP-P= 12A

9






1 2 4 8 16



UPM


Tswitch

delay

Load

voutvin



COUNTERDUTY CYCLE

DRIVING SIGNAL

Load

voutvin



40


UPM



Dri

vin

gsi

gnal

s

Counter

+ hellip +


Duty cycle





UPM


Dri

vin

gD

rivi

ng

sign

als

sign

als



ltDuty cycle


Shift Register



Counter


41


UPM






ASIC

12 12 phasesphases

6 6 phasesphases

24 24 phasesphases





0

2000

4000

6000

8000

10000

12000

14000

16000

2 4 6 8 12 16 20 24

0

2000

4000

6000

8000

10000

12000

2 4 6 8 12 16 20 24

0

2000

4000

6000

8000

10000

12000

14000

16000

18000

2 4 6 8 12 16 20 24


Res

ol 1

28Res

ol 2

56Res

ol 5

12

FPGA

Equ

ival

ent

gate

s

Phases

0

200

400

600

800

1000

2 4 6 8 12 16 20 24


Res

ol 1

28Res

ol 2

56Res

ol 5

120

200

400

600

800

1000

1200

2 4 6 8 12 16 20 24

0

200

400

600

800

1000

1200

1400

2 4 6 8 12 16 20 24

ASIC

Equ

ival

ent

gate

s

Phases


UPM


0

10

20

30

40

50

0 20 40 60 80



0

10

20

30

40

50

0 20 40 60 80



Iout

Pow

erlo

sses

(W)

80

84

88

92

96

0 10 20 30 40 50 60 70 80

6 phases

8 phases12 phases

16 phases

4 phases



Iout

Effic

ienc

y(

)

80

84

88

92

96

0 10 20 30 40 50 60 70 80

6 phases

8 phases12 phases

16 phases

4 phases



Iout

Effic

ienc

y(

)



42


UPM





UPM


RFAmp

Pow

erSt

age

Control

iRF

vs

VS

variable VS


24V

9Vfmax=35kHz

Input voltage = 28V





43


UPM


Cs

M1

L

M2

Cs

M1

L

M2

Cs

M1

L

M2

Cs

M1

L

M2

Ve Vout

CAR

GA




UPM


SW

CLK

ff Resolution =

Pipeline

fCLK

f = 25MHz f = 45MHz

Resolution required



fselected = 32MHz


44


UPM

33 33 DitherDither

SW

CLK

ff Resolution gt

d = 42

d =43

d =425

T=2TSW=8μs

Output voltage

2 solutions

V=50mV

TSW=4μs 1 solution

T=4μs

Output voltage

V=25mV

SW

CLKNVirtual



Average duty cycle

It gives 1 more bit


UPM



SimulatedSimulated

MeasuredMeasured



)(

4110780250 22




45


UPM






UPM


f = 200Hz f = 15kHz

f = 3kHz f = 5kHz

46


UPM





UPM



2 2 micromicross

Vo

1 V

2 V

VRM for DVS5 V

Io = 20 A max

1V - 2 V

Io

02 V max02 V max

0 A

20 A

500 Amicros

Vo




47


UPM


10-1 100 101

100

L-C diagram

C2 micros

200 mV

20A




C = 35 C = 35 μμFF



UPM






fsw = 520 kHz

(125 mΩ eq Rds_on)





48


UPM


0

1

To drivers

New vref

vo dig

N-phases_tran

N-phases

New vref

vo dig

New vref

vo dig


ic


NON-LINEAR CONTROL





UPM


vref

vo

0

1

To drivers

clk_sample

clk_sample

ADC

N-phases_tran

N-phases

vo dig

LINEAR CONTROL



49


UPM


vref

vo

0

1

To drivers

New vref

vo dig

clk_sample

clk_sample

ADC

N-phases_tran

N-phases

vo dig

New vref

LINEAR CONTROL

NON-LINEAR CONTROL

vo dig

New vrefvo dig


ic



Beware


UPM


UpUp--stepstep

ConverterFPGA

tt11



DownDown--stepstep

t1 t2 t1 t2

ddnn

tt22vref

500 kHz

LUT


05

1

15

2

25

0 02 04 06 08 1 12 14 16 18-10

0

10

20

30

40

50

ton toff

Tmin

05

1

15

2

25

0 02 04 06 08 1 12 14 16 18-10

0

10

20

30

40

50

ton toff

Tmin

i L(A

)i L

(A)

V o(V

)V o

(V)


50


UPM


t1 t2 t1 t2

094 096 098 1 102 104 106 108 11

x 10-4

14

16

18

2

22

24

26

28

3

32

094 096 098 1 102 104 106 108 11

x 10-4

0

1

2

3

4

5092 094 096 098 1 102 104 106 108 11 112

x 10-4

14

16

18

2

22

24

26

28

3

32

092 094 096 098 1 102 104 106 108 11 112

x 10-4

0

05

1

15

2

25

3

35

4

45

Transient





Beware


UPM

ΔIo

iL

Io

vo

ic 0 ATrip point 1

Trip point 2

ΔIo

ic





51


UPM


05358z02236z07417)(z3767G(z) 2 +sdotminus

+sdot=

B G(s)

G(z)




N = 4

ESR = 125 mΩ

( )CL

1sRESRL1s

CL1)1sCESR(V

)s(Gdv

L2

ino

sdot+sdot+sdot+


==

~ VinmiddotdCo

ESR

RphaseN LphaseN

Expected by design


DC resistance


model


Beware


UPM


Pole-Zero Map

Real Axis

-1 -08 -06 -04 -02 0 02 04 06 08 1-1

-08

-06

-04

-02

0

02

04

06

08

1

09

0807060504

03

02

01

26e5

234e5

208e5

182e5

156e513e5

104e5

781e4

521e4

26e4

26e5

234e5

208e5

182e5

156e513e5

104e5

781e4

521e4

26e4

x

x

x




Duty cycle

30 micros


1z00372)z(Rminus

=

1zK)z(R 1

minus=

Controller delay

05358z02236z07417)(z3767G(z) 2 +sdotminus

+sdot=Converter

x

x

x Duty cycle

Output voltage

52


UPM

10 micros


xx

x

x

x

x

x

x




00775)(z1)(z037)(z00378R(z)

minussdotminus+sdot

=

Duty cycle

Output voltage


UPM


75 micros

xx

x

x

x

xx

x



minussdotminus+sdot

=

53


UPM


Duty

a1 = -0922548 b1 = 0037759b2 = 0051742a2 = 0

b1

b2

δ-1

δ-1

δ-1

a1

a2

Error

bn0

No b0

δ-1

Z-1

+

00775)(z1)(z037)(z00378R(z)

minussdotminus+sdot

=




UPM


z2d_m ( tf ([00378 0013986] [1 -10775 00775] 192e-6) )




=Tsample = Tsw

⎪⎩

⎪⎨⎧

rarrδ

+=δ δδ

s


54


UPM


Reference

Switched model

7 bits

8 bits

Not quantizied


PWM

ADC

111






UPM

Reference


PWM

ADC






hellip

222

55


UPM



a1 = -0922548 b1 = 0037759b2 = 0051742a2 = 0

b1

b2

δ-1

δ-1

δ-1

a1

a2

Error

bn0

No b0


UPM


0lt Duty cycle lt1


Hardware adders






Beware

56


UPM

0 1 2 30

05

1

15

2

25








UPM



0 1 2 3

x 10-4

0

05

1

15

2

25

100 usdiv100 usdiv



57


UPM






UPM




58


UPM


13 14 15 16 17 18 19

x 10-4

12

14

16

18

2

22

08 V drop

10 microsdiv

2 V





UPM



Vo

1 V

2 V



11 A11 A

20 mV

520 kHz



59


UPM


Vo

Io

200 mV







UPM


Vo

1 V

2 V





60


UPM





Beware



UPM



35


UPM




422 97

438 101

442 102

434 -

DC Current(A)

431 99

445 102

424 98

448 103

Deviation()

Phase 2Phase 2

Phase 3Phase 3

Phase 4Phase 4

Phase 5Phase 5

Phase 6Phase 6

Phase 7Phase 7

Phase 8Phase 8

AverageAverage

DCMDCM


IO=17A

IO=27A


UPM





36


UPM


-05

0

05

1

15

2

00E+00 50E-06 10E-05 15E-05 20E-05 25E-05t (s)

()

-05

0

05

1

15

2

00E+00 50E-06 10E-05 15E-05 20E-05 25E-05t (s)

()

0

20

40

60

80

100

120

140

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35

Phase number

[+6-8]

0

20

40

60

80

100

120

140

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35

Phase number

[+6-8]

Half load(500W)


Full load(1000W)

0

1

2

3

4

p

0 5μs 10μs 15μs 20μs0

1

2

3

4

p



0

20

40

60

80

100

120

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35

Phase number

+10-75

0

20

40

60

80

100

120

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35

Phase number

+10-75



UPM

Output currentDC AC

11App

70ADC


is

0 01 02 03 04 05 06 07 08 09 100102030405

060708091

Duty cycle (d)

Nor

m c

urre

nt r

ippl

e Dutyvariation

2 phases

3 phases



37


UPM

10

5

5

10

3T0 x

5

5

3T0 x

Ideal case






10

5

5

10

3T0 x

5

5

3T0 x

Non-ideal



10

5

5

10

3T0 x

5

5

3T0 x

Worse case



10

5

5

10

3T0 x

5

5

3T0 x





UPM

ΔIP-P= 40A (5Adiv)

1 phase

ΔIP-P= 12A (5Adiv)

2 phases

ΔIP-P= 5A (5Adiv)

4 phases

ΔIP-P= 22A (1Adiv)

8 phases

ΔIP-P= 16A (1Adiv)

16 phases



38


UPM

(a)

30

31

22 40

37

22 33

2830

31

22 40

37

22 33

28

(a)

Center of mass

(a)

30

31

22 40

37

22 33

2830

31

22 40

37

22 33

28

(a)

Center of mass

Phase1Phase

2

Phase3

Phase4

Phase5

Phase6

Phase7

Phase8

1st

2nd

3rd 4th

6th

5th 8th

7th

(b)

1st

2nd

3rd 4th

6th

5th 8th

7th

1st

2nd

3rd 4th

6th

5th 8th

7th

(b)

40 A

37 A30 A

33 A

22 A 28 A

31 A

22 A






UPM

18 0 18

18

18

OVERALL 67A

18 0 18

18

18

1

2

34

56

7

8

9

10

1112 13

14

15

16

MAX

MIN

18 0 18

18

18

OVERALL 05A

18 0 18

18

18

1

2

34

56

7

8

9

10

1112 13

1415

16

MAX

MIN


16151413121110987654321

Phase number

165155177152140144148128147122154158139149142133

Current ripple (A)

39


UPM

ΔIP-P= 40A

ΔIP-P= 40A

ΔIP-P= 07A

ΔIP-P= 16A

57

ΔIP-P= 11A

ΔIP-P= 22A

50

ΔIP-P= 28A

ΔIP-P= 5A

44

ΔIP-P= 11A

ΔIP-P= 12A

9






1 2 4 8 16



UPM


Tswitch

delay

Load

voutvin



COUNTERDUTY CYCLE

DRIVING SIGNAL

Load

voutvin



40


UPM



Dri

vin

gsi

gnal

s

Counter

+ hellip +


Duty cycle





UPM


Dri

vin

gD

rivi

ng

sign

als

sign

als



ltDuty cycle


Shift Register



Counter


41


UPM






ASIC

12 12 phasesphases

6 6 phasesphases

24 24 phasesphases





0

2000

4000

6000

8000

10000

12000

14000

16000

2 4 6 8 12 16 20 24

0

2000

4000

6000

8000

10000

12000

2 4 6 8 12 16 20 24

0

2000

4000

6000

8000

10000

12000

14000

16000

18000

2 4 6 8 12 16 20 24


Res

ol 1

28Res

ol 2

56Res

ol 5

12

FPGA

Equ

ival

ent

gate

s

Phases

0

200

400

600

800

1000

2 4 6 8 12 16 20 24


Res

ol 1

28Res

ol 2

56Res

ol 5

120

200

400

600

800

1000

1200

2 4 6 8 12 16 20 24

0

200

400

600

800

1000

1200

1400

2 4 6 8 12 16 20 24

ASIC

Equ

ival

ent

gate

s

Phases


UPM


0

10

20

30

40

50

0 20 40 60 80



0

10

20

30

40

50

0 20 40 60 80



Iout

Pow

erlo

sses

(W)

80

84

88

92

96

0 10 20 30 40 50 60 70 80

6 phases

8 phases12 phases

16 phases

4 phases



Iout

Effic

ienc

y(

)

80

84

88

92

96

0 10 20 30 40 50 60 70 80

6 phases

8 phases12 phases

16 phases

4 phases



Iout

Effic

ienc

y(

)



42


UPM





UPM


RFAmp

Pow

erSt

age

Control

iRF

vs

VS

variable VS


24V

9Vfmax=35kHz

Input voltage = 28V





43


UPM


Cs

M1

L

M2

Cs

M1

L

M2

Cs

M1

L

M2

Cs

M1

L

M2

Ve Vout

CAR

GA




UPM


SW

CLK

ff Resolution =

Pipeline

fCLK

f = 25MHz f = 45MHz

Resolution required



fselected = 32MHz


44


UPM

33 33 DitherDither

SW

CLK

ff Resolution gt

d = 42

d =43

d =425

T=2TSW=8μs

Output voltage

2 solutions

V=50mV

TSW=4μs 1 solution

T=4μs

Output voltage

V=25mV

SW

CLKNVirtual



Average duty cycle

It gives 1 more bit


UPM



SimulatedSimulated

MeasuredMeasured



)(

4110780250 22




45


UPM






UPM


f = 200Hz f = 15kHz

f = 3kHz f = 5kHz

46


UPM





UPM



2 2 micromicross

Vo

1 V

2 V

VRM for DVS5 V

Io = 20 A max

1V - 2 V

Io

02 V max02 V max

0 A

20 A

500 Amicros

Vo




47


UPM


10-1 100 101

100

L-C diagram

C2 micros

200 mV

20A




C = 35 C = 35 μμFF



UPM






fsw = 520 kHz

(125 mΩ eq Rds_on)





48


UPM


0

1

To drivers

New vref

vo dig

N-phases_tran

N-phases

New vref

vo dig

New vref

vo dig


ic


NON-LINEAR CONTROL





UPM


vref

vo

0

1

To drivers

clk_sample

clk_sample

ADC

N-phases_tran

N-phases

vo dig

LINEAR CONTROL



49


UPM


vref

vo

0

1

To drivers

New vref

vo dig

clk_sample

clk_sample

ADC

N-phases_tran

N-phases

vo dig

New vref

LINEAR CONTROL

NON-LINEAR CONTROL

vo dig

New vrefvo dig


ic



Beware


UPM


UpUp--stepstep

ConverterFPGA

tt11



DownDown--stepstep

t1 t2 t1 t2

ddnn

tt22vref

500 kHz

LUT


05

1

15

2

25

0 02 04 06 08 1 12 14 16 18-10

0

10

20

30

40

50

ton toff

Tmin

05

1

15

2

25

0 02 04 06 08 1 12 14 16 18-10

0

10

20

30

40

50

ton toff

Tmin

i L(A

)i L

(A)

V o(V

)V o

(V)


50


UPM


t1 t2 t1 t2

094 096 098 1 102 104 106 108 11

x 10-4

14

16

18

2

22

24

26

28

3

32

094 096 098 1 102 104 106 108 11

x 10-4

0

1

2

3

4

5092 094 096 098 1 102 104 106 108 11 112

x 10-4

14

16

18

2

22

24

26

28

3

32

092 094 096 098 1 102 104 106 108 11 112

x 10-4

0

05

1

15

2

25

3

35

4

45

Transient





Beware


UPM

ΔIo

iL

Io

vo

ic 0 ATrip point 1

Trip point 2

ΔIo

ic





51


UPM


05358z02236z07417)(z3767G(z) 2 +sdotminus

+sdot=

B G(s)

G(z)




N = 4

ESR = 125 mΩ

( )CL

1sRESRL1s

CL1)1sCESR(V

)s(Gdv

L2

ino

sdot+sdot+sdot+


==

~ VinmiddotdCo

ESR

RphaseN LphaseN

Expected by design


DC resistance


model


Beware


UPM


Pole-Zero Map

Real Axis

-1 -08 -06 -04 -02 0 02 04 06 08 1-1

-08

-06

-04

-02

0

02

04

06

08

1

09

0807060504

03

02

01

26e5

234e5

208e5

182e5

156e513e5

104e5

781e4

521e4

26e4

26e5

234e5

208e5

182e5

156e513e5

104e5

781e4

521e4

26e4

x

x

x




Duty cycle

30 micros


1z00372)z(Rminus

=

1zK)z(R 1

minus=

Controller delay

05358z02236z07417)(z3767G(z) 2 +sdotminus

+sdot=Converter

x

x

x Duty cycle

Output voltage

52


UPM

10 micros


xx

x

x

x

x

x

x




00775)(z1)(z037)(z00378R(z)

minussdotminus+sdot

=

Duty cycle

Output voltage


UPM


75 micros

xx

x

x

x

xx

x



minussdotminus+sdot

=

53


UPM


Duty

a1 = -0922548 b1 = 0037759b2 = 0051742a2 = 0

b1

b2

δ-1

δ-1

δ-1

a1

a2

Error

bn0

No b0

δ-1

Z-1

+

00775)(z1)(z037)(z00378R(z)

minussdotminus+sdot

=




UPM


z2d_m ( tf ([00378 0013986] [1 -10775 00775] 192e-6) )




=Tsample = Tsw

⎪⎩

⎪⎨⎧

rarrδ

+=δ δδ

s


54


UPM


Reference

Switched model

7 bits

8 bits

Not quantizied


PWM

ADC

111






UPM

Reference


PWM

ADC






hellip

222

55


UPM



a1 = -0922548 b1 = 0037759b2 = 0051742a2 = 0

b1

b2

δ-1

δ-1

δ-1

a1

a2

Error

bn0

No b0


UPM


0lt Duty cycle lt1


Hardware adders






Beware

56


UPM

0 1 2 30

05

1

15

2

25








UPM



0 1 2 3

x 10-4

0

05

1

15

2

25

100 usdiv100 usdiv



57


UPM






UPM




58


UPM


13 14 15 16 17 18 19

x 10-4

12

14

16

18

2

22

08 V drop

10 microsdiv

2 V





UPM



Vo

1 V

2 V



11 A11 A

20 mV

520 kHz



59


UPM


Vo

Io

200 mV







UPM


Vo

1 V

2 V





60


UPM





Beware



UPM



36


UPM


-05

0

05

1

15

2

00E+00 50E-06 10E-05 15E-05 20E-05 25E-05t (s)

()

-05

0

05

1

15

2

00E+00 50E-06 10E-05 15E-05 20E-05 25E-05t (s)

()

0

20

40

60

80

100

120

140

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35

Phase number

[+6-8]

0

20

40

60

80

100

120

140

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35

Phase number

[+6-8]

Half load(500W)


Full load(1000W)

0

1

2

3

4

p

0 5μs 10μs 15μs 20μs0

1

2

3

4

p



0

20

40

60

80

100

120

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35

Phase number

+10-75

0

20

40

60

80

100

120

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35

Phase number

+10-75



UPM

Output currentDC AC

11App

70ADC


is

0 01 02 03 04 05 06 07 08 09 100102030405

060708091

Duty cycle (d)

Nor

m c

urre

nt r

ippl

e Dutyvariation

2 phases

3 phases



37


UPM

10

5

5

10

3T0 x

5

5

3T0 x

Ideal case






10

5

5

10

3T0 x

5

5

3T0 x

Non-ideal



10

5

5

10

3T0 x

5

5

3T0 x

Worse case



10

5

5

10

3T0 x

5

5

3T0 x





UPM

ΔIP-P= 40A (5Adiv)

1 phase

ΔIP-P= 12A (5Adiv)

2 phases

ΔIP-P= 5A (5Adiv)

4 phases

ΔIP-P= 22A (1Adiv)

8 phases

ΔIP-P= 16A (1Adiv)

16 phases



38


UPM

(a)

30

31

22 40

37

22 33

2830

31

22 40

37

22 33

28

(a)

Center of mass

(a)

30

31

22 40

37

22 33

2830

31

22 40

37

22 33

28

(a)

Center of mass

Phase1Phase

2

Phase3

Phase4

Phase5

Phase6

Phase7

Phase8

1st

2nd

3rd 4th

6th

5th 8th

7th

(b)

1st

2nd

3rd 4th

6th

5th 8th

7th

1st

2nd

3rd 4th

6th

5th 8th

7th

(b)

40 A

37 A30 A

33 A

22 A 28 A

31 A

22 A






UPM

18 0 18

18

18

OVERALL 67A

18 0 18

18

18

1

2

34

56

7

8

9

10

1112 13

14

15

16

MAX

MIN

18 0 18

18

18

OVERALL 05A

18 0 18

18

18

1

2

34

56

7

8

9

10

1112 13

1415

16

MAX

MIN


16151413121110987654321

Phase number

165155177152140144148128147122154158139149142133

Current ripple (A)

39


UPM

ΔIP-P= 40A

ΔIP-P= 40A

ΔIP-P= 07A

ΔIP-P= 16A

57

ΔIP-P= 11A

ΔIP-P= 22A

50

ΔIP-P= 28A

ΔIP-P= 5A

44

ΔIP-P= 11A

ΔIP-P= 12A

9






1 2 4 8 16



UPM


Tswitch

delay

Load

voutvin



COUNTERDUTY CYCLE

DRIVING SIGNAL

Load

voutvin



40


UPM



Dri

vin

gsi

gnal

s

Counter

+ hellip +


Duty cycle





UPM


Dri

vin

gD

rivi

ng

sign

als

sign

als



ltDuty cycle


Shift Register



Counter


41


UPM






ASIC

12 12 phasesphases

6 6 phasesphases

24 24 phasesphases





0

2000

4000

6000

8000

10000

12000

14000

16000

2 4 6 8 12 16 20 24

0

2000

4000

6000

8000

10000

12000

2 4 6 8 12 16 20 24

0

2000

4000

6000

8000

10000

12000

14000

16000

18000

2 4 6 8 12 16 20 24


Res

ol 1

28Res

ol 2

56Res

ol 5

12

FPGA

Equ

ival

ent

gate

s

Phases

0

200

400

600

800

1000

2 4 6 8 12 16 20 24


Res

ol 1

28Res

ol 2

56Res

ol 5

120

200

400

600

800

1000

1200

2 4 6 8 12 16 20 24

0

200

400

600

800

1000

1200

1400

2 4 6 8 12 16 20 24

ASIC

Equ

ival

ent

gate

s

Phases


UPM


0

10

20

30

40

50

0 20 40 60 80



0

10

20

30

40

50

0 20 40 60 80



Iout

Pow

erlo

sses

(W)

80

84

88

92

96

0 10 20 30 40 50 60 70 80

6 phases

8 phases12 phases

16 phases

4 phases



Iout

Effic

ienc

y(

)

80

84

88

92

96

0 10 20 30 40 50 60 70 80

6 phases

8 phases12 phases

16 phases

4 phases



Iout

Effic

ienc

y(

)



42


UPM





UPM


RFAmp

Pow

erSt

age

Control

iRF

vs

VS

variable VS


24V

9Vfmax=35kHz

Input voltage = 28V





43


UPM


Cs

M1

L

M2

Cs

M1

L

M2

Cs

M1

L

M2

Cs

M1

L

M2

Ve Vout

CAR

GA




UPM


SW

CLK

ff Resolution =

Pipeline

fCLK

f = 25MHz f = 45MHz

Resolution required



fselected = 32MHz


44


UPM

33 33 DitherDither

SW

CLK

ff Resolution gt

d = 42

d =43

d =425

T=2TSW=8μs

Output voltage

2 solutions

V=50mV

TSW=4μs 1 solution

T=4μs

Output voltage

V=25mV

SW

CLKNVirtual



Average duty cycle

It gives 1 more bit


UPM



SimulatedSimulated

MeasuredMeasured



)(

4110780250 22




45


UPM






UPM


f = 200Hz f = 15kHz

f = 3kHz f = 5kHz

46


UPM





UPM



2 2 micromicross

Vo

1 V

2 V

VRM for DVS5 V

Io = 20 A max

1V - 2 V

Io

02 V max02 V max

0 A

20 A

500 Amicros

Vo




47


UPM


10-1 100 101

100

L-C diagram

C2 micros

200 mV

20A




C = 35 C = 35 μμFF



UPM






fsw = 520 kHz

(125 mΩ eq Rds_on)





48


UPM


0

1

To drivers

New vref

vo dig

N-phases_tran

N-phases

New vref

vo dig

New vref

vo dig


ic


NON-LINEAR CONTROL





UPM


vref

vo

0

1

To drivers

clk_sample

clk_sample

ADC

N-phases_tran

N-phases

vo dig

LINEAR CONTROL



49


UPM


vref

vo

0

1

To drivers

New vref

vo dig

clk_sample

clk_sample

ADC

N-phases_tran

N-phases

vo dig

New vref

LINEAR CONTROL

NON-LINEAR CONTROL

vo dig

New vrefvo dig


ic



Beware


UPM


UpUp--stepstep

ConverterFPGA

tt11



DownDown--stepstep

t1 t2 t1 t2

ddnn

tt22vref

500 kHz

LUT


05

1

15

2

25

0 02 04 06 08 1 12 14 16 18-10

0

10

20

30

40

50

ton toff

Tmin

05

1

15

2

25

0 02 04 06 08 1 12 14 16 18-10

0

10

20

30

40

50

ton toff

Tmin

i L(A

)i L

(A)

V o(V

)V o

(V)


50


UPM


t1 t2 t1 t2

094 096 098 1 102 104 106 108 11

x 10-4

14

16

18

2

22

24

26

28

3

32

094 096 098 1 102 104 106 108 11

x 10-4

0

1

2

3

4

5092 094 096 098 1 102 104 106 108 11 112

x 10-4

14

16

18

2

22

24

26

28

3

32

092 094 096 098 1 102 104 106 108 11 112

x 10-4

0

05

1

15

2

25

3

35

4

45

Transient





Beware


UPM

ΔIo

iL

Io

vo

ic 0 ATrip point 1

Trip point 2

ΔIo

ic





51


UPM


05358z02236z07417)(z3767G(z) 2 +sdotminus

+sdot=

B G(s)

G(z)




N = 4

ESR = 125 mΩ

( )CL

1sRESRL1s

CL1)1sCESR(V

)s(Gdv

L2

ino

sdot+sdot+sdot+


==

~ VinmiddotdCo

ESR

RphaseN LphaseN

Expected by design


DC resistance


model


Beware


UPM


Pole-Zero Map

Real Axis

-1 -08 -06 -04 -02 0 02 04 06 08 1-1

-08

-06

-04

-02

0

02

04

06

08

1

09

0807060504

03

02

01

26e5

234e5

208e5

182e5

156e513e5

104e5

781e4

521e4

26e4

26e5

234e5

208e5

182e5

156e513e5

104e5

781e4

521e4

26e4

x

x

x




Duty cycle

30 micros


1z00372)z(Rminus

=

1zK)z(R 1

minus=

Controller delay

05358z02236z07417)(z3767G(z) 2 +sdotminus

+sdot=Converter

x

x

x Duty cycle

Output voltage

52


UPM

10 micros


xx

x

x

x

x

x

x




00775)(z1)(z037)(z00378R(z)

minussdotminus+sdot

=

Duty cycle

Output voltage


UPM


75 micros

xx

x

x

x

xx

x



minussdotminus+sdot

=

53


UPM


Duty

a1 = -0922548 b1 = 0037759b2 = 0051742a2 = 0

b1

b2

δ-1

δ-1

δ-1

a1

a2

Error

bn0

No b0

δ-1

Z-1

+

00775)(z1)(z037)(z00378R(z)

minussdotminus+sdot

=




UPM


z2d_m ( tf ([00378 0013986] [1 -10775 00775] 192e-6) )




=Tsample = Tsw

⎪⎩

⎪⎨⎧

rarrδ

+=δ δδ

s


54


UPM


Reference

Switched model

7 bits

8 bits

Not quantizied


PWM

ADC

111






UPM

Reference


PWM

ADC






hellip

222

55


UPM



a1 = -0922548 b1 = 0037759b2 = 0051742a2 = 0

b1

b2

δ-1

δ-1

δ-1

a1

a2

Error

bn0

No b0


UPM


0lt Duty cycle lt1


Hardware adders






Beware

56


UPM

0 1 2 30

05

1

15

2

25








UPM



0 1 2 3

x 10-4

0

05

1

15

2

25

100 usdiv100 usdiv



57


UPM






UPM




58


UPM


13 14 15 16 17 18 19

x 10-4

12

14

16

18

2

22

08 V drop

10 microsdiv

2 V





UPM



Vo

1 V

2 V



11 A11 A

20 mV

520 kHz



59


UPM


Vo

Io

200 mV







UPM


Vo

1 V

2 V





60


UPM





Beware



UPM



37


UPM

10

5

5

10

3T0 x

5

5

3T0 x

Ideal case






10

5

5

10

3T0 x

5

5

3T0 x

Non-ideal



10

5

5

10

3T0 x

5

5

3T0 x

Worse case



10

5

5

10

3T0 x

5

5

3T0 x





UPM

ΔIP-P= 40A (5Adiv)

1 phase

ΔIP-P= 12A (5Adiv)

2 phases

ΔIP-P= 5A (5Adiv)

4 phases

ΔIP-P= 22A (1Adiv)

8 phases

ΔIP-P= 16A (1Adiv)

16 phases



38


UPM

(a)

30

31

22 40

37

22 33

2830

31

22 40

37

22 33

28

(a)

Center of mass

(a)

30

31

22 40

37

22 33

2830

31

22 40

37

22 33

28

(a)

Center of mass

Phase1Phase

2

Phase3

Phase4

Phase5

Phase6

Phase7

Phase8

1st

2nd

3rd 4th

6th

5th 8th

7th

(b)

1st

2nd

3rd 4th

6th

5th 8th

7th

1st

2nd

3rd 4th

6th

5th 8th

7th

(b)

40 A

37 A30 A

33 A

22 A 28 A

31 A

22 A






UPM

18 0 18

18

18

OVERALL 67A

18 0 18

18

18

1

2

34

56

7

8

9

10

1112 13

14

15

16

MAX

MIN

18 0 18

18

18

OVERALL 05A

18 0 18

18

18

1

2

34

56

7

8

9

10

1112 13

1415

16

MAX

MIN


16151413121110987654321

Phase number

165155177152140144148128147122154158139149142133

Current ripple (A)

39


UPM

ΔIP-P= 40A

ΔIP-P= 40A

ΔIP-P= 07A

ΔIP-P= 16A

57

ΔIP-P= 11A

ΔIP-P= 22A

50

ΔIP-P= 28A

ΔIP-P= 5A

44

ΔIP-P= 11A

ΔIP-P= 12A

9






1 2 4 8 16



UPM


Tswitch

delay

Load

voutvin



COUNTERDUTY CYCLE

DRIVING SIGNAL

Load

voutvin



40


UPM



Dri

vin

gsi

gnal

s

Counter

+ hellip +


Duty cycle





UPM


Dri

vin

gD

rivi

ng

sign

als

sign

als



ltDuty cycle


Shift Register



Counter


41


UPM






ASIC

12 12 phasesphases

6 6 phasesphases

24 24 phasesphases





0

2000

4000

6000

8000

10000

12000

14000

16000

2 4 6 8 12 16 20 24

0

2000

4000

6000

8000

10000

12000

2 4 6 8 12 16 20 24

0

2000

4000

6000

8000

10000

12000

14000

16000

18000

2 4 6 8 12 16 20 24


Res

ol 1

28Res

ol 2

56Res

ol 5

12

FPGA

Equ

ival

ent

gate

s

Phases

0

200

400

600

800

1000

2 4 6 8 12 16 20 24


Res

ol 1

28Res

ol 2

56Res

ol 5

120

200

400

600

800

1000

1200

2 4 6 8 12 16 20 24

0

200

400

600

800

1000

1200

1400

2 4 6 8 12 16 20 24

ASIC

Equ

ival

ent

gate

s

Phases


UPM


0

10

20

30

40

50

0 20 40 60 80



0

10

20

30

40

50

0 20 40 60 80



Iout

Pow

erlo

sses

(W)

80

84

88

92

96

0 10 20 30 40 50 60 70 80

6 phases

8 phases12 phases

16 phases

4 phases



Iout

Effic

ienc

y(

)

80

84

88

92

96

0 10 20 30 40 50 60 70 80

6 phases

8 phases12 phases

16 phases

4 phases



Iout

Effic

ienc

y(

)



42


UPM





UPM


RFAmp

Pow

erSt

age

Control

iRF

vs

VS

variable VS


24V

9Vfmax=35kHz

Input voltage = 28V





43


UPM


Cs

M1

L

M2

Cs

M1

L

M2

Cs

M1

L

M2

Cs

M1

L

M2

Ve Vout

CAR

GA




UPM


SW

CLK

ff Resolution =

Pipeline

fCLK

f = 25MHz f = 45MHz

Resolution required



fselected = 32MHz


44


UPM

33 33 DitherDither

SW

CLK

ff Resolution gt

d = 42

d =43

d =425

T=2TSW=8μs

Output voltage

2 solutions

V=50mV

TSW=4μs 1 solution

T=4μs

Output voltage

V=25mV

SW

CLKNVirtual



Average duty cycle

It gives 1 more bit


UPM



SimulatedSimulated

MeasuredMeasured



)(

4110780250 22




45


UPM






UPM


f = 200Hz f = 15kHz

f = 3kHz f = 5kHz

46


UPM





UPM



2 2 micromicross

Vo

1 V

2 V

VRM for DVS5 V

Io = 20 A max

1V - 2 V

Io

02 V max02 V max

0 A

20 A

500 Amicros

Vo




47


UPM


10-1 100 101

100

L-C diagram

C2 micros

200 mV

20A




C = 35 C = 35 μμFF



UPM






fsw = 520 kHz

(125 mΩ eq Rds_on)





48


UPM


0

1

To drivers

New vref

vo dig

N-phases_tran

N-phases

New vref

vo dig

New vref

vo dig


ic


NON-LINEAR CONTROL





UPM


vref

vo

0

1

To drivers

clk_sample

clk_sample

ADC

N-phases_tran

N-phases

vo dig

LINEAR CONTROL



49


UPM


vref

vo

0

1

To drivers

New vref

vo dig

clk_sample

clk_sample

ADC

N-phases_tran

N-phases

vo dig

New vref

LINEAR CONTROL

NON-LINEAR CONTROL

vo dig

New vrefvo dig


ic



Beware


UPM


UpUp--stepstep

ConverterFPGA

tt11



DownDown--stepstep

t1 t2 t1 t2

ddnn

tt22vref

500 kHz

LUT


05

1

15

2

25

0 02 04 06 08 1 12 14 16 18-10

0

10

20

30

40

50

ton toff

Tmin

05

1

15

2

25

0 02 04 06 08 1 12 14 16 18-10

0

10

20

30

40

50

ton toff

Tmin

i L(A

)i L

(A)

V o(V

)V o

(V)


50


UPM


t1 t2 t1 t2

094 096 098 1 102 104 106 108 11

x 10-4

14

16

18

2

22

24

26

28

3

32

094 096 098 1 102 104 106 108 11

x 10-4

0

1

2

3

4

5092 094 096 098 1 102 104 106 108 11 112

x 10-4

14

16

18

2

22

24

26

28

3

32

092 094 096 098 1 102 104 106 108 11 112

x 10-4

0

05

1

15

2

25

3

35

4

45

Transient





Beware


UPM

ΔIo

iL

Io

vo

ic 0 ATrip point 1

Trip point 2

ΔIo

ic





51


UPM


05358z02236z07417)(z3767G(z) 2 +sdotminus

+sdot=

B G(s)

G(z)




N = 4

ESR = 125 mΩ

( )CL

1sRESRL1s

CL1)1sCESR(V

)s(Gdv

L2

ino

sdot+sdot+sdot+


==

~ VinmiddotdCo

ESR

RphaseN LphaseN

Expected by design


DC resistance


model


Beware


UPM


Pole-Zero Map

Real Axis

-1 -08 -06 -04 -02 0 02 04 06 08 1-1

-08

-06

-04

-02

0

02

04

06

08

1

09

0807060504

03

02

01

26e5

234e5

208e5

182e5

156e513e5

104e5

781e4

521e4

26e4

26e5

234e5

208e5

182e5

156e513e5

104e5

781e4

521e4

26e4

x

x

x




Duty cycle

30 micros


1z00372)z(Rminus

=

1zK)z(R 1

minus=

Controller delay

05358z02236z07417)(z3767G(z) 2 +sdotminus

+sdot=Converter

x

x

x Duty cycle

Output voltage

52


UPM

10 micros


xx

x

x

x

x

x

x




00775)(z1)(z037)(z00378R(z)

minussdotminus+sdot

=

Duty cycle

Output voltage


UPM


75 micros

xx

x

x

x

xx

x



minussdotminus+sdot

=

53


UPM


Duty

a1 = -0922548 b1 = 0037759b2 = 0051742a2 = 0

b1

b2

δ-1

δ-1

δ-1

a1

a2

Error

bn0

No b0

δ-1

Z-1

+

00775)(z1)(z037)(z00378R(z)

minussdotminus+sdot

=




UPM


z2d_m ( tf ([00378 0013986] [1 -10775 00775] 192e-6) )




=Tsample = Tsw

⎪⎩

⎪⎨⎧

rarrδ

+=δ δδ

s


54


UPM


Reference

Switched model

7 bits

8 bits

Not quantizied


PWM

ADC

111






UPM

Reference


PWM

ADC






hellip

222

55


UPM



a1 = -0922548 b1 = 0037759b2 = 0051742a2 = 0

b1

b2

δ-1

δ-1

δ-1

a1

a2

Error

bn0

No b0


UPM


0lt Duty cycle lt1


Hardware adders






Beware

56


UPM

0 1 2 30

05

1

15

2

25








UPM



0 1 2 3

x 10-4

0

05

1

15

2

25

100 usdiv100 usdiv



57


UPM






UPM




58


UPM


13 14 15 16 17 18 19

x 10-4

12

14

16

18

2

22

08 V drop

10 microsdiv

2 V





UPM



Vo

1 V

2 V



11 A11 A

20 mV

520 kHz



59


UPM


Vo

Io

200 mV







UPM


Vo

1 V

2 V





60


UPM





Beware



UPM



38


UPM

(a)

30

31

22 40

37

22 33

2830

31

22 40

37

22 33

28

(a)

Center of mass

(a)

30

31

22 40

37

22 33

2830

31

22 40

37

22 33

28

(a)

Center of mass

Phase1Phase

2

Phase3

Phase4

Phase5

Phase6

Phase7

Phase8

1st

2nd

3rd 4th

6th

5th 8th

7th

(b)

1st

2nd

3rd 4th

6th

5th 8th

7th

1st

2nd

3rd 4th

6th

5th 8th

7th

(b)

40 A

37 A30 A

33 A

22 A 28 A

31 A

22 A






UPM

18 0 18

18

18

OVERALL 67A

18 0 18

18

18

1

2

34

56

7

8

9

10

1112 13

14

15

16

MAX

MIN

18 0 18

18

18

OVERALL 05A

18 0 18

18

18

1

2

34

56

7

8

9

10

1112 13

1415

16

MAX

MIN


16151413121110987654321

Phase number

165155177152140144148128147122154158139149142133

Current ripple (A)

39


UPM

ΔIP-P= 40A

ΔIP-P= 40A

ΔIP-P= 07A

ΔIP-P= 16A

57

ΔIP-P= 11A

ΔIP-P= 22A

50

ΔIP-P= 28A

ΔIP-P= 5A

44

ΔIP-P= 11A

ΔIP-P= 12A

9






1 2 4 8 16



UPM


Tswitch

delay

Load

voutvin



COUNTERDUTY CYCLE

DRIVING SIGNAL

Load

voutvin



40


UPM



Dri

vin

gsi

gnal

s

Counter

+ hellip +


Duty cycle





UPM


Dri

vin

gD

rivi

ng

sign

als

sign

als



ltDuty cycle


Shift Register



Counter


41


UPM






ASIC

12 12 phasesphases

6 6 phasesphases

24 24 phasesphases





0

2000

4000

6000

8000

10000

12000

14000

16000

2 4 6 8 12 16 20 24

0

2000

4000

6000

8000

10000

12000

2 4 6 8 12 16 20 24

0

2000

4000

6000

8000

10000

12000

14000

16000

18000

2 4 6 8 12 16 20 24


Res

ol 1

28Res

ol 2

56Res

ol 5

12

FPGA

Equ

ival

ent

gate

s

Phases

0

200

400

600

800

1000

2 4 6 8 12 16 20 24


Res

ol 1

28Res

ol 2

56Res

ol 5

120

200

400

600

800

1000

1200

2 4 6 8 12 16 20 24

0

200

400

600

800

1000

1200

1400

2 4 6 8 12 16 20 24

ASIC

Equ

ival

ent

gate

s

Phases


UPM


0

10

20

30

40

50

0 20 40 60 80



0

10

20

30

40

50

0 20 40 60 80



Iout

Pow

erlo

sses

(W)

80

84

88

92

96

0 10 20 30 40 50 60 70 80

6 phases

8 phases12 phases

16 phases

4 phases



Iout

Effic

ienc

y(

)

80

84

88

92

96

0 10 20 30 40 50 60 70 80

6 phases

8 phases12 phases

16 phases

4 phases



Iout

Effic

ienc

y(

)



42


UPM





UPM


RFAmp

Pow

erSt

age

Control

iRF

vs

VS

variable VS


24V

9Vfmax=35kHz

Input voltage = 28V





43


UPM


Cs

M1

L

M2

Cs

M1

L

M2

Cs

M1

L

M2

Cs

M1

L

M2

Ve Vout

CAR

GA




UPM


SW

CLK

ff Resolution =

Pipeline

fCLK

f = 25MHz f = 45MHz

Resolution required



fselected = 32MHz


44


UPM

33 33 DitherDither

SW

CLK

ff Resolution gt

d = 42

d =43

d =425

T=2TSW=8μs

Output voltage

2 solutions

V=50mV

TSW=4μs 1 solution

T=4μs

Output voltage

V=25mV

SW

CLKNVirtual



Average duty cycle

It gives 1 more bit


UPM



SimulatedSimulated

MeasuredMeasured



)(

4110780250 22




45


UPM






UPM


f = 200Hz f = 15kHz

f = 3kHz f = 5kHz

46


UPM





UPM



2 2 micromicross

Vo

1 V

2 V

VRM for DVS5 V

Io = 20 A max

1V - 2 V

Io

02 V max02 V max

0 A

20 A

500 Amicros

Vo




47


UPM


10-1 100 101

100

L-C diagram

C2 micros

200 mV

20A




C = 35 C = 35 μμFF



UPM






fsw = 520 kHz

(125 mΩ eq Rds_on)





48


UPM


0

1

To drivers

New vref

vo dig

N-phases_tran

N-phases

New vref

vo dig

New vref

vo dig


ic


NON-LINEAR CONTROL





UPM


vref

vo

0

1

To drivers

clk_sample

clk_sample

ADC

N-phases_tran

N-phases

vo dig

LINEAR CONTROL



49


UPM


vref

vo

0

1

To drivers

New vref

vo dig

clk_sample

clk_sample

ADC

N-phases_tran

N-phases

vo dig

New vref

LINEAR CONTROL

NON-LINEAR CONTROL

vo dig

New vrefvo dig


ic



Beware


UPM


UpUp--stepstep

ConverterFPGA

tt11



DownDown--stepstep

t1 t2 t1 t2

ddnn

tt22vref

500 kHz

LUT


05

1

15

2

25

0 02 04 06 08 1 12 14 16 18-10

0

10

20

30

40

50

ton toff

Tmin

05

1

15

2

25

0 02 04 06 08 1 12 14 16 18-10

0

10

20

30

40

50

ton toff

Tmin

i L(A

)i L

(A)

V o(V

)V o

(V)


50


UPM


t1 t2 t1 t2

094 096 098 1 102 104 106 108 11

x 10-4

14

16

18

2

22

24

26

28

3

32

094 096 098 1 102 104 106 108 11

x 10-4

0

1

2

3

4

5092 094 096 098 1 102 104 106 108 11 112

x 10-4

14

16

18

2

22

24

26

28

3

32

092 094 096 098 1 102 104 106 108 11 112

x 10-4

0

05

1

15

2

25

3

35

4

45

Transient





Beware


UPM

ΔIo

iL

Io

vo

ic 0 ATrip point 1

Trip point 2

ΔIo

ic





51


UPM


05358z02236z07417)(z3767G(z) 2 +sdotminus

+sdot=

B G(s)

G(z)




N = 4

ESR = 125 mΩ

( )CL

1sRESRL1s

CL1)1sCESR(V

)s(Gdv

L2

ino

sdot+sdot+sdot+


==

~ VinmiddotdCo

ESR

RphaseN LphaseN

Expected by design


DC resistance


model


Beware


UPM


Pole-Zero Map

Real Axis

-1 -08 -06 -04 -02 0 02 04 06 08 1-1

-08

-06

-04

-02

0

02

04

06

08

1

09

0807060504

03

02

01

26e5

234e5

208e5

182e5

156e513e5

104e5

781e4

521e4

26e4

26e5

234e5

208e5

182e5

156e513e5

104e5

781e4

521e4

26e4

x

x

x




Duty cycle

30 micros


1z00372)z(Rminus

=

1zK)z(R 1

minus=

Controller delay

05358z02236z07417)(z3767G(z) 2 +sdotminus

+sdot=Converter

x

x

x Duty cycle

Output voltage

52


UPM

10 micros


xx

x

x

x

x

x

x




00775)(z1)(z037)(z00378R(z)

minussdotminus+sdot

=

Duty cycle

Output voltage


UPM


75 micros

xx

x

x

x

xx

x



minussdotminus+sdot

=

53


UPM


Duty

a1 = -0922548 b1 = 0037759b2 = 0051742a2 = 0

b1

b2

δ-1

δ-1

δ-1

a1

a2

Error

bn0

No b0

δ-1

Z-1

+

00775)(z1)(z037)(z00378R(z)

minussdotminus+sdot

=




UPM


z2d_m ( tf ([00378 0013986] [1 -10775 00775] 192e-6) )




=Tsample = Tsw

⎪⎩

⎪⎨⎧

rarrδ

+=δ δδ

s


54


UPM


Reference

Switched model

7 bits

8 bits

Not quantizied


PWM

ADC

111






UPM

Reference


PWM

ADC






hellip

222

55


UPM



a1 = -0922548 b1 = 0037759b2 = 0051742a2 = 0

b1

b2

δ-1

δ-1

δ-1

a1

a2

Error

bn0

No b0


UPM


0lt Duty cycle lt1


Hardware adders






Beware

56


UPM

0 1 2 30

05

1

15

2

25








UPM



0 1 2 3

x 10-4

0

05

1

15

2

25

100 usdiv100 usdiv



57


UPM






UPM




58


UPM


13 14 15 16 17 18 19

x 10-4

12

14

16

18

2

22

08 V drop

10 microsdiv

2 V





UPM



Vo

1 V

2 V



11 A11 A

20 mV

520 kHz



59


UPM


Vo

Io

200 mV







UPM


Vo

1 V

2 V





60


UPM





Beware



UPM



39


UPM

ΔIP-P= 40A

ΔIP-P= 40A

ΔIP-P= 07A

ΔIP-P= 16A

57

ΔIP-P= 11A

ΔIP-P= 22A

50

ΔIP-P= 28A

ΔIP-P= 5A

44

ΔIP-P= 11A

ΔIP-P= 12A

9






1 2 4 8 16



UPM


Tswitch

delay

Load

voutvin



COUNTERDUTY CYCLE

DRIVING SIGNAL

Load

voutvin



40


UPM



Dri

vin

gsi

gnal

s

Counter

+ hellip +


Duty cycle





UPM


Dri

vin

gD

rivi

ng

sign

als

sign

als



ltDuty cycle


Shift Register



Counter


41


UPM






ASIC

12 12 phasesphases

6 6 phasesphases

24 24 phasesphases





0

2000

4000

6000

8000

10000

12000

14000

16000

2 4 6 8 12 16 20 24

0

2000

4000

6000

8000

10000

12000

2 4 6 8 12 16 20 24

0

2000

4000

6000

8000

10000

12000

14000

16000

18000

2 4 6 8 12 16 20 24


Res

ol 1

28Res

ol 2

56Res

ol 5

12

FPGA

Equ

ival

ent

gate

s

Phases

0

200

400

600

800

1000

2 4 6 8 12 16 20 24


Res

ol 1

28Res

ol 2

56Res

ol 5

120

200

400

600

800

1000

1200

2 4 6 8 12 16 20 24

0

200

400

600

800

1000

1200

1400

2 4 6 8 12 16 20 24

ASIC

Equ

ival

ent

gate

s

Phases


UPM


0

10

20

30

40

50

0 20 40 60 80



0

10

20

30

40

50

0 20 40 60 80



Iout

Pow

erlo

sses

(W)

80

84

88

92

96

0 10 20 30 40 50 60 70 80

6 phases

8 phases12 phases

16 phases

4 phases



Iout

Effic

ienc

y(

)

80

84

88

92

96

0 10 20 30 40 50 60 70 80

6 phases

8 phases12 phases

16 phases

4 phases



Iout

Effic

ienc

y(

)



42


UPM





UPM


RFAmp

Pow

erSt

age

Control

iRF

vs

VS

variable VS


24V

9Vfmax=35kHz

Input voltage = 28V





43


UPM


Cs

M1

L

M2

Cs

M1

L

M2

Cs

M1

L

M2

Cs

M1

L

M2

Ve Vout

CAR

GA




UPM


SW

CLK

ff Resolution =

Pipeline

fCLK

f = 25MHz f = 45MHz

Resolution required



fselected = 32MHz


44


UPM

33 33 DitherDither

SW

CLK

ff Resolution gt

d = 42

d =43

d =425

T=2TSW=8μs

Output voltage

2 solutions

V=50mV

TSW=4μs 1 solution

T=4μs

Output voltage

V=25mV

SW

CLKNVirtual



Average duty cycle

It gives 1 more bit


UPM



SimulatedSimulated

MeasuredMeasured



)(

4110780250 22




45


UPM






UPM


f = 200Hz f = 15kHz

f = 3kHz f = 5kHz

46


UPM





UPM



2 2 micromicross

Vo

1 V

2 V

VRM for DVS5 V

Io = 20 A max

1V - 2 V

Io

02 V max02 V max

0 A

20 A

500 Amicros

Vo




47


UPM


10-1 100 101

100

L-C diagram

C2 micros

200 mV

20A




C = 35 C = 35 μμFF



UPM






fsw = 520 kHz

(125 mΩ eq Rds_on)





48


UPM


0

1

To drivers

New vref

vo dig

N-phases_tran

N-phases

New vref

vo dig

New vref

vo dig


ic


NON-LINEAR CONTROL





UPM


vref

vo

0

1

To drivers

clk_sample

clk_sample

ADC

N-phases_tran

N-phases

vo dig

LINEAR CONTROL



49


UPM


vref

vo

0

1

To drivers

New vref

vo dig

clk_sample

clk_sample

ADC

N-phases_tran

N-phases

vo dig

New vref

LINEAR CONTROL

NON-LINEAR CONTROL

vo dig

New vrefvo dig


ic



Beware


UPM


UpUp--stepstep

ConverterFPGA

tt11



DownDown--stepstep

t1 t2 t1 t2

ddnn

tt22vref

500 kHz

LUT


05

1

15

2

25

0 02 04 06 08 1 12 14 16 18-10

0

10

20

30

40

50

ton toff

Tmin

05

1

15

2

25

0 02 04 06 08 1 12 14 16 18-10

0

10

20

30

40

50

ton toff

Tmin

i L(A

)i L

(A)

V o(V

)V o

(V)


50


UPM


t1 t2 t1 t2

094 096 098 1 102 104 106 108 11

x 10-4

14

16

18

2

22

24

26

28

3

32

094 096 098 1 102 104 106 108 11

x 10-4

0

1

2

3

4

5092 094 096 098 1 102 104 106 108 11 112

x 10-4

14

16

18

2

22

24

26

28

3

32

092 094 096 098 1 102 104 106 108 11 112

x 10-4

0

05

1

15

2

25

3

35

4

45

Transient





Beware


UPM

ΔIo

iL

Io

vo

ic 0 ATrip point 1

Trip point 2

ΔIo

ic





51


UPM


05358z02236z07417)(z3767G(z) 2 +sdotminus

+sdot=

B G(s)

G(z)




N = 4

ESR = 125 mΩ

( )CL

1sRESRL1s

CL1)1sCESR(V

)s(Gdv

L2

ino

sdot+sdot+sdot+


==

~ VinmiddotdCo

ESR

RphaseN LphaseN

Expected by design


DC resistance


model


Beware


UPM


Pole-Zero Map

Real Axis

-1 -08 -06 -04 -02 0 02 04 06 08 1-1

-08

-06

-04

-02

0

02

04

06

08

1

09

0807060504

03

02

01

26e5

234e5

208e5

182e5

156e513e5

104e5

781e4

521e4

26e4

26e5

234e5

208e5

182e5

156e513e5

104e5

781e4

521e4

26e4

x

x

x




Duty cycle

30 micros


1z00372)z(Rminus

=

1zK)z(R 1

minus=

Controller delay

05358z02236z07417)(z3767G(z) 2 +sdotminus

+sdot=Converter

x

x

x Duty cycle

Output voltage

52


UPM

10 micros


xx

x

x

x

x

x

x




00775)(z1)(z037)(z00378R(z)

minussdotminus+sdot

=

Duty cycle

Output voltage


UPM


75 micros

xx

x

x

x

xx

x



minussdotminus+sdot

=

53


UPM


Duty

a1 = -0922548 b1 = 0037759b2 = 0051742a2 = 0

b1

b2

δ-1

δ-1

δ-1

a1

a2

Error

bn0

No b0

δ-1

Z-1

+

00775)(z1)(z037)(z00378R(z)

minussdotminus+sdot

=




UPM


z2d_m ( tf ([00378 0013986] [1 -10775 00775] 192e-6) )




=Tsample = Tsw

⎪⎩

⎪⎨⎧

rarrδ

+=δ δδ

s


54


UPM


Reference

Switched model

7 bits

8 bits

Not quantizied


PWM

ADC

111






UPM

Reference


PWM

ADC






hellip

222

55


UPM



a1 = -0922548 b1 = 0037759b2 = 0051742a2 = 0

b1

b2

δ-1

δ-1

δ-1

a1

a2

Error

bn0

No b0


UPM


0lt Duty cycle lt1


Hardware adders






Beware

56


UPM

0 1 2 30

05

1

15

2

25








UPM



0 1 2 3

x 10-4

0

05

1

15

2

25

100 usdiv100 usdiv



57


UPM






UPM




58


UPM


13 14 15 16 17 18 19

x 10-4

12

14

16

18

2

22

08 V drop

10 microsdiv

2 V





UPM



Vo

1 V

2 V



11 A11 A

20 mV

520 kHz



59


UPM


Vo

Io

200 mV







UPM


Vo

1 V

2 V





60


UPM





Beware



UPM



40


UPM



Dri

vin

gsi

gnal

s

Counter

+ hellip +


Duty cycle





UPM


Dri

vin

gD

rivi

ng

sign

als

sign

als



ltDuty cycle


Shift Register



Counter


41


UPM






ASIC

12 12 phasesphases

6 6 phasesphases

24 24 phasesphases





0

2000

4000

6000

8000

10000

12000

14000

16000

2 4 6 8 12 16 20 24

0

2000

4000

6000

8000

10000

12000

2 4 6 8 12 16 20 24

0

2000

4000

6000

8000

10000

12000

14000

16000

18000

2 4 6 8 12 16 20 24


Res

ol 1

28Res

ol 2

56Res

ol 5

12

FPGA

Equ

ival

ent

gate

s

Phases

0

200

400

600

800

1000

2 4 6 8 12 16 20 24


Res

ol 1

28Res

ol 2

56Res

ol 5

120

200

400

600

800

1000

1200

2 4 6 8 12 16 20 24

0

200

400

600

800

1000

1200

1400

2 4 6 8 12 16 20 24

ASIC

Equ

ival

ent

gate

s

Phases


UPM


0

10

20

30

40

50

0 20 40 60 80



0

10

20

30

40

50

0 20 40 60 80



Iout

Pow

erlo

sses

(W)

80

84

88

92

96

0 10 20 30 40 50 60 70 80

6 phases

8 phases12 phases

16 phases

4 phases



Iout

Effic

ienc

y(

)

80

84

88

92

96

0 10 20 30 40 50 60 70 80

6 phases

8 phases12 phases

16 phases

4 phases



Iout

Effic

ienc

y(

)



42


UPM





UPM


RFAmp

Pow

erSt

age

Control

iRF

vs

VS

variable VS


24V

9Vfmax=35kHz

Input voltage = 28V





43


UPM


Cs

M1

L

M2

Cs

M1

L

M2

Cs

M1

L

M2

Cs

M1

L

M2

Ve Vout

CAR

GA




UPM


SW

CLK

ff Resolution =

Pipeline

fCLK

f = 25MHz f = 45MHz

Resolution required



fselected = 32MHz


44


UPM

33 33 DitherDither

SW

CLK

ff Resolution gt

d = 42

d =43

d =425

T=2TSW=8μs

Output voltage

2 solutions

V=50mV

TSW=4μs 1 solution

T=4μs

Output voltage

V=25mV

SW

CLKNVirtual



Average duty cycle

It gives 1 more bit


UPM



SimulatedSimulated

MeasuredMeasured



)(

4110780250 22




45


UPM






UPM


f = 200Hz f = 15kHz

f = 3kHz f = 5kHz

46


UPM





UPM



2 2 micromicross

Vo

1 V

2 V

VRM for DVS5 V

Io = 20 A max

1V - 2 V

Io

02 V max02 V max

0 A

20 A

500 Amicros

Vo




47


UPM


10-1 100 101

100

L-C diagram

C2 micros

200 mV

20A




C = 35 C = 35 μμFF



UPM






fsw = 520 kHz

(125 mΩ eq Rds_on)





48


UPM


0

1

To drivers

New vref

vo dig

N-phases_tran

N-phases

New vref

vo dig

New vref

vo dig


ic


NON-LINEAR CONTROL





UPM


vref

vo

0

1

To drivers

clk_sample

clk_sample

ADC

N-phases_tran

N-phases

vo dig

LINEAR CONTROL



49


UPM


vref

vo

0

1

To drivers

New vref

vo dig

clk_sample

clk_sample

ADC

N-phases_tran

N-phases

vo dig

New vref

LINEAR CONTROL

NON-LINEAR CONTROL

vo dig

New vrefvo dig


ic



Beware


UPM


UpUp--stepstep

ConverterFPGA

tt11



DownDown--stepstep

t1 t2 t1 t2

ddnn

tt22vref

500 kHz

LUT


05

1

15

2

25

0 02 04 06 08 1 12 14 16 18-10

0

10

20

30

40

50

ton toff

Tmin

05

1

15

2

25

0 02 04 06 08 1 12 14 16 18-10

0

10

20

30

40

50

ton toff

Tmin

i L(A

)i L

(A)

V o(V

)V o

(V)


50


UPM


t1 t2 t1 t2

094 096 098 1 102 104 106 108 11

x 10-4

14

16

18

2

22

24

26

28

3

32

094 096 098 1 102 104 106 108 11

x 10-4

0

1

2

3

4

5092 094 096 098 1 102 104 106 108 11 112

x 10-4

14

16

18

2

22

24

26

28

3

32

092 094 096 098 1 102 104 106 108 11 112

x 10-4

0

05

1

15

2

25

3

35

4

45

Transient





Beware


UPM

ΔIo

iL

Io

vo

ic 0 ATrip point 1

Trip point 2

ΔIo

ic





51


UPM


05358z02236z07417)(z3767G(z) 2 +sdotminus

+sdot=

B G(s)

G(z)




N = 4

ESR = 125 mΩ

( )CL

1sRESRL1s

CL1)1sCESR(V

)s(Gdv

L2

ino

sdot+sdot+sdot+


==

~ VinmiddotdCo

ESR

RphaseN LphaseN

Expected by design


DC resistance


model


Beware


UPM


Pole-Zero Map

Real Axis

-1 -08 -06 -04 -02 0 02 04 06 08 1-1

-08

-06

-04

-02

0

02

04

06

08

1

09

0807060504

03

02

01

26e5

234e5

208e5

182e5

156e513e5

104e5

781e4

521e4

26e4

26e5

234e5

208e5

182e5

156e513e5

104e5

781e4

521e4

26e4

x

x

x




Duty cycle

30 micros


1z00372)z(Rminus

=

1zK)z(R 1

minus=

Controller delay

05358z02236z07417)(z3767G(z) 2 +sdotminus

+sdot=Converter

x

x

x Duty cycle

Output voltage

52


UPM

10 micros


xx

x

x

x

x

x

x




00775)(z1)(z037)(z00378R(z)

minussdotminus+sdot

=

Duty cycle

Output voltage


UPM


75 micros

xx

x

x

x

xx

x



minussdotminus+sdot

=

53


UPM


Duty

a1 = -0922548 b1 = 0037759b2 = 0051742a2 = 0

b1

b2

δ-1

δ-1

δ-1

a1

a2

Error

bn0

No b0

δ-1

Z-1

+

00775)(z1)(z037)(z00378R(z)

minussdotminus+sdot

=




UPM


z2d_m ( tf ([00378 0013986] [1 -10775 00775] 192e-6) )




=Tsample = Tsw

⎪⎩

⎪⎨⎧

rarrδ

+=δ δδ

s


54


UPM


Reference

Switched model

7 bits

8 bits

Not quantizied


PWM

ADC

111






UPM

Reference


PWM

ADC






hellip

222

55


UPM



a1 = -0922548 b1 = 0037759b2 = 0051742a2 = 0

b1

b2

δ-1

δ-1

δ-1

a1

a2

Error

bn0

No b0


UPM


0lt Duty cycle lt1


Hardware adders






Beware

56


UPM

0 1 2 30

05

1

15

2

25








UPM



0 1 2 3

x 10-4

0

05

1

15

2

25

100 usdiv100 usdiv



57


UPM






UPM




58


UPM


13 14 15 16 17 18 19

x 10-4

12

14

16

18

2

22

08 V drop

10 microsdiv

2 V





UPM



Vo

1 V

2 V



11 A11 A

20 mV

520 kHz



59


UPM


Vo

Io

200 mV







UPM


Vo

1 V

2 V





60


UPM





Beware



UPM



41


UPM






ASIC

12 12 phasesphases

6 6 phasesphases

24 24 phasesphases





0

2000

4000

6000

8000

10000

12000

14000

16000

2 4 6 8 12 16 20 24

0

2000

4000

6000

8000

10000

12000

2 4 6 8 12 16 20 24

0

2000

4000

6000

8000

10000

12000

14000

16000

18000

2 4 6 8 12 16 20 24


Res

ol 1

28Res

ol 2

56Res

ol 5

12

FPGA

Equ

ival

ent

gate

s

Phases

0

200

400

600

800

1000

2 4 6 8 12 16 20 24


Res

ol 1

28Res

ol 2

56Res

ol 5

120

200

400

600

800

1000

1200

2 4 6 8 12 16 20 24

0

200

400

600

800

1000

1200

1400

2 4 6 8 12 16 20 24

ASIC

Equ

ival

ent

gate

s

Phases


UPM


0

10

20

30

40

50

0 20 40 60 80



0

10

20

30

40

50

0 20 40 60 80



Iout

Pow

erlo

sses

(W)

80

84

88

92

96

0 10 20 30 40 50 60 70 80

6 phases

8 phases12 phases

16 phases

4 phases



Iout

Effic

ienc

y(

)

80

84

88

92

96

0 10 20 30 40 50 60 70 80

6 phases

8 phases12 phases

16 phases

4 phases



Iout

Effic

ienc

y(

)



42


UPM





UPM


RFAmp

Pow

erSt

age

Control

iRF

vs

VS

variable VS


24V

9Vfmax=35kHz

Input voltage = 28V





43


UPM


Cs

M1

L

M2

Cs

M1

L

M2

Cs

M1

L

M2

Cs

M1

L

M2

Ve Vout

CAR

GA




UPM


SW

CLK

ff Resolution =

Pipeline

fCLK

f = 25MHz f = 45MHz

Resolution required



fselected = 32MHz


44


UPM

33 33 DitherDither

SW

CLK

ff Resolution gt

d = 42

d =43

d =425

T=2TSW=8μs

Output voltage

2 solutions

V=50mV

TSW=4μs 1 solution

T=4μs

Output voltage

V=25mV

SW

CLKNVirtual



Average duty cycle

It gives 1 more bit


UPM



SimulatedSimulated

MeasuredMeasured



)(

4110780250 22




45


UPM






UPM


f = 200Hz f = 15kHz

f = 3kHz f = 5kHz

46


UPM





UPM



2 2 micromicross

Vo

1 V

2 V

VRM for DVS5 V

Io = 20 A max

1V - 2 V

Io

02 V max02 V max

0 A

20 A

500 Amicros

Vo




47


UPM


10-1 100 101

100

L-C diagram

C2 micros

200 mV

20A




C = 35 C = 35 μμFF



UPM






fsw = 520 kHz

(125 mΩ eq Rds_on)





48


UPM


0

1

To drivers

New vref

vo dig

N-phases_tran

N-phases

New vref

vo dig

New vref

vo dig


ic


NON-LINEAR CONTROL





UPM


vref

vo

0

1

To drivers

clk_sample

clk_sample

ADC

N-phases_tran

N-phases

vo dig

LINEAR CONTROL



49


UPM


vref

vo

0

1

To drivers

New vref

vo dig

clk_sample

clk_sample

ADC

N-phases_tran

N-phases

vo dig

New vref

LINEAR CONTROL

NON-LINEAR CONTROL

vo dig

New vrefvo dig


ic



Beware


UPM


UpUp--stepstep

ConverterFPGA

tt11



DownDown--stepstep

t1 t2 t1 t2

ddnn

tt22vref

500 kHz

LUT


05

1

15

2

25

0 02 04 06 08 1 12 14 16 18-10

0

10

20

30

40

50

ton toff

Tmin

05

1

15

2

25

0 02 04 06 08 1 12 14 16 18-10

0

10

20

30

40

50

ton toff

Tmin

i L(A

)i L

(A)

V o(V

)V o

(V)


50


UPM


t1 t2 t1 t2

094 096 098 1 102 104 106 108 11

x 10-4

14

16

18

2

22

24

26

28

3

32

094 096 098 1 102 104 106 108 11

x 10-4

0

1

2

3

4

5092 094 096 098 1 102 104 106 108 11 112

x 10-4

14

16

18

2

22

24

26

28

3

32

092 094 096 098 1 102 104 106 108 11 112

x 10-4

0

05

1

15

2

25

3

35

4

45

Transient





Beware


UPM

ΔIo

iL

Io

vo

ic 0 ATrip point 1

Trip point 2

ΔIo

ic





51


UPM


05358z02236z07417)(z3767G(z) 2 +sdotminus

+sdot=

B G(s)

G(z)




N = 4

ESR = 125 mΩ

( )CL

1sRESRL1s

CL1)1sCESR(V

)s(Gdv

L2

ino

sdot+sdot+sdot+


==

~ VinmiddotdCo

ESR

RphaseN LphaseN

Expected by design


DC resistance


model


Beware


UPM


Pole-Zero Map

Real Axis

-1 -08 -06 -04 -02 0 02 04 06 08 1-1

-08

-06

-04

-02

0

02

04

06

08

1

09

0807060504

03

02

01

26e5

234e5

208e5

182e5

156e513e5

104e5

781e4

521e4

26e4

26e5

234e5

208e5

182e5

156e513e5

104e5

781e4

521e4

26e4

x

x

x




Duty cycle

30 micros


1z00372)z(Rminus

=

1zK)z(R 1

minus=

Controller delay

05358z02236z07417)(z3767G(z) 2 +sdotminus

+sdot=Converter

x

x

x Duty cycle

Output voltage

52


UPM

10 micros


xx

x

x

x

x

x

x




00775)(z1)(z037)(z00378R(z)

minussdotminus+sdot

=

Duty cycle

Output voltage


UPM


75 micros

xx

x

x

x

xx

x



minussdotminus+sdot

=

53


UPM


Duty

a1 = -0922548 b1 = 0037759b2 = 0051742a2 = 0

b1

b2

δ-1

δ-1

δ-1

a1

a2

Error

bn0

No b0

δ-1

Z-1

+

00775)(z1)(z037)(z00378R(z)

minussdotminus+sdot

=




UPM


z2d_m ( tf ([00378 0013986] [1 -10775 00775] 192e-6) )




=Tsample = Tsw

⎪⎩

⎪⎨⎧

rarrδ

+=δ δδ

s


54


UPM


Reference

Switched model

7 bits

8 bits

Not quantizied


PWM

ADC

111






UPM

Reference


PWM

ADC






hellip

222

55


UPM



a1 = -0922548 b1 = 0037759b2 = 0051742a2 = 0

b1

b2

δ-1

δ-1

δ-1

a1

a2

Error

bn0

No b0


UPM


0lt Duty cycle lt1


Hardware adders






Beware

56


UPM

0 1 2 30

05

1

15

2

25








UPM



0 1 2 3

x 10-4

0

05

1

15

2

25

100 usdiv100 usdiv



57


UPM






UPM




58


UPM


13 14 15 16 17 18 19

x 10-4

12

14

16

18

2

22

08 V drop

10 microsdiv

2 V





UPM



Vo

1 V

2 V



11 A11 A

20 mV

520 kHz



59


UPM


Vo

Io

200 mV







UPM


Vo

1 V

2 V





60


UPM





Beware



UPM



42


UPM





UPM


RFAmp

Pow

erSt

age

Control

iRF

vs

VS

variable VS


24V

9Vfmax=35kHz

Input voltage = 28V





43


UPM


Cs

M1

L

M2

Cs

M1

L

M2

Cs

M1

L

M2

Cs

M1

L

M2

Ve Vout

CAR

GA




UPM


SW

CLK

ff Resolution =

Pipeline

fCLK

f = 25MHz f = 45MHz

Resolution required



fselected = 32MHz


44


UPM

33 33 DitherDither

SW

CLK

ff Resolution gt

d = 42

d =43

d =425

T=2TSW=8μs

Output voltage

2 solutions

V=50mV

TSW=4μs 1 solution

T=4μs

Output voltage

V=25mV

SW

CLKNVirtual



Average duty cycle

It gives 1 more bit


UPM



SimulatedSimulated

MeasuredMeasured



)(

4110780250 22




45


UPM






UPM


f = 200Hz f = 15kHz

f = 3kHz f = 5kHz

46


UPM





UPM



2 2 micromicross

Vo

1 V

2 V

VRM for DVS5 V

Io = 20 A max

1V - 2 V

Io

02 V max02 V max

0 A

20 A

500 Amicros

Vo




47


UPM


10-1 100 101

100

L-C diagram

C2 micros

200 mV

20A




C = 35 C = 35 μμFF



UPM






fsw = 520 kHz

(125 mΩ eq Rds_on)





48


UPM


0

1

To drivers

New vref

vo dig

N-phases_tran

N-phases

New vref

vo dig

New vref

vo dig


ic


NON-LINEAR CONTROL





UPM


vref

vo

0

1

To drivers

clk_sample

clk_sample

ADC

N-phases_tran

N-phases

vo dig

LINEAR CONTROL



49


UPM


vref

vo

0

1

To drivers

New vref

vo dig

clk_sample

clk_sample

ADC

N-phases_tran

N-phases

vo dig

New vref

LINEAR CONTROL

NON-LINEAR CONTROL

vo dig

New vrefvo dig


ic



Beware


UPM


UpUp--stepstep

ConverterFPGA

tt11



DownDown--stepstep

t1 t2 t1 t2

ddnn

tt22vref

500 kHz

LUT


05

1

15

2

25

0 02 04 06 08 1 12 14 16 18-10

0

10

20

30

40

50

ton toff

Tmin

05

1

15

2

25

0 02 04 06 08 1 12 14 16 18-10

0

10

20

30

40

50

ton toff

Tmin

i L(A

)i L

(A)

V o(V

)V o

(V)


50


UPM


t1 t2 t1 t2

094 096 098 1 102 104 106 108 11

x 10-4

14

16

18

2

22

24

26

28

3

32

094 096 098 1 102 104 106 108 11

x 10-4

0

1

2

3

4

5092 094 096 098 1 102 104 106 108 11 112

x 10-4

14

16

18

2

22

24

26

28

3

32

092 094 096 098 1 102 104 106 108 11 112

x 10-4

0

05

1

15

2

25

3

35

4

45

Transient





Beware


UPM

ΔIo

iL

Io

vo

ic 0 ATrip point 1

Trip point 2

ΔIo

ic





51


UPM


05358z02236z07417)(z3767G(z) 2 +sdotminus

+sdot=

B G(s)

G(z)




N = 4

ESR = 125 mΩ

( )CL

1sRESRL1s

CL1)1sCESR(V

)s(Gdv

L2

ino

sdot+sdot+sdot+


==

~ VinmiddotdCo

ESR

RphaseN LphaseN

Expected by design


DC resistance


model


Beware


UPM


Pole-Zero Map

Real Axis

-1 -08 -06 -04 -02 0 02 04 06 08 1-1

-08

-06

-04

-02

0

02

04

06

08

1

09

0807060504

03

02

01

26e5

234e5

208e5

182e5

156e513e5

104e5

781e4

521e4

26e4

26e5

234e5

208e5

182e5

156e513e5

104e5

781e4

521e4

26e4

x

x

x




Duty cycle

30 micros


1z00372)z(Rminus

=

1zK)z(R 1

minus=

Controller delay

05358z02236z07417)(z3767G(z) 2 +sdotminus

+sdot=Converter

x

x

x Duty cycle

Output voltage

52


UPM

10 micros


xx

x

x

x

x

x

x




00775)(z1)(z037)(z00378R(z)

minussdotminus+sdot

=

Duty cycle

Output voltage


UPM


75 micros

xx

x

x

x

xx

x



minussdotminus+sdot

=

53


UPM


Duty

a1 = -0922548 b1 = 0037759b2 = 0051742a2 = 0

b1

b2

δ-1

δ-1

δ-1

a1

a2

Error

bn0

No b0

δ-1

Z-1

+

00775)(z1)(z037)(z00378R(z)

minussdotminus+sdot

=




UPM


z2d_m ( tf ([00378 0013986] [1 -10775 00775] 192e-6) )




=Tsample = Tsw

⎪⎩

⎪⎨⎧

rarrδ

+=δ δδ

s


54


UPM


Reference

Switched model

7 bits

8 bits

Not quantizied


PWM

ADC

111






UPM

Reference


PWM

ADC






hellip

222

55


UPM



a1 = -0922548 b1 = 0037759b2 = 0051742a2 = 0

b1

b2

δ-1

δ-1

δ-1

a1

a2

Error

bn0

No b0


UPM


0lt Duty cycle lt1


Hardware adders






Beware

56


UPM

0 1 2 30

05

1

15

2

25








UPM



0 1 2 3

x 10-4

0

05

1

15

2

25

100 usdiv100 usdiv



57


UPM






UPM




58


UPM


13 14 15 16 17 18 19

x 10-4

12

14

16

18

2

22

08 V drop

10 microsdiv

2 V





UPM



Vo

1 V

2 V



11 A11 A

20 mV

520 kHz



59


UPM


Vo

Io

200 mV







UPM


Vo

1 V

2 V





60


UPM





Beware



UPM



43


UPM


Cs

M1

L

M2

Cs

M1

L

M2

Cs

M1

L

M2

Cs

M1

L

M2

Ve Vout

CAR

GA




UPM


SW

CLK

ff Resolution =

Pipeline

fCLK

f = 25MHz f = 45MHz

Resolution required



fselected = 32MHz


44


UPM

33 33 DitherDither

SW

CLK

ff Resolution gt

d = 42

d =43

d =425

T=2TSW=8μs

Output voltage

2 solutions

V=50mV

TSW=4μs 1 solution

T=4μs

Output voltage

V=25mV

SW

CLKNVirtual



Average duty cycle

It gives 1 more bit


UPM



SimulatedSimulated

MeasuredMeasured



)(

4110780250 22




45


UPM






UPM


f = 200Hz f = 15kHz

f = 3kHz f = 5kHz

46


UPM





UPM



2 2 micromicross

Vo

1 V

2 V

VRM for DVS5 V

Io = 20 A max

1V - 2 V

Io

02 V max02 V max

0 A

20 A

500 Amicros

Vo




47


UPM


10-1 100 101

100

L-C diagram

C2 micros

200 mV

20A




C = 35 C = 35 μμFF



UPM






fsw = 520 kHz

(125 mΩ eq Rds_on)





48


UPM


0

1

To drivers

New vref

vo dig

N-phases_tran

N-phases

New vref

vo dig

New vref

vo dig


ic


NON-LINEAR CONTROL





UPM


vref

vo

0

1

To drivers

clk_sample

clk_sample

ADC

N-phases_tran

N-phases

vo dig

LINEAR CONTROL



49


UPM


vref

vo

0

1

To drivers

New vref

vo dig

clk_sample

clk_sample

ADC

N-phases_tran

N-phases

vo dig

New vref

LINEAR CONTROL

NON-LINEAR CONTROL

vo dig

New vrefvo dig


ic



Beware


UPM


UpUp--stepstep

ConverterFPGA

tt11



DownDown--stepstep

t1 t2 t1 t2

ddnn

tt22vref

500 kHz

LUT


05

1

15

2

25

0 02 04 06 08 1 12 14 16 18-10

0

10

20

30

40

50

ton toff

Tmin

05

1

15

2

25

0 02 04 06 08 1 12 14 16 18-10

0

10

20

30

40

50

ton toff

Tmin

i L(A

)i L

(A)

V o(V

)V o

(V)


50


UPM


t1 t2 t1 t2

094 096 098 1 102 104 106 108 11

x 10-4

14

16

18

2

22

24

26

28

3

32

094 096 098 1 102 104 106 108 11

x 10-4

0

1

2

3

4

5092 094 096 098 1 102 104 106 108 11 112

x 10-4

14

16

18

2

22

24

26

28

3

32

092 094 096 098 1 102 104 106 108 11 112

x 10-4

0

05

1

15

2

25

3

35

4

45

Transient





Beware


UPM

ΔIo

iL

Io

vo

ic 0 ATrip point 1

Trip point 2

ΔIo

ic





51


UPM


05358z02236z07417)(z3767G(z) 2 +sdotminus

+sdot=

B G(s)

G(z)




N = 4

ESR = 125 mΩ

( )CL

1sRESRL1s

CL1)1sCESR(V

)s(Gdv

L2

ino

sdot+sdot+sdot+


==

~ VinmiddotdCo

ESR

RphaseN LphaseN

Expected by design


DC resistance


model


Beware


UPM


Pole-Zero Map

Real Axis

-1 -08 -06 -04 -02 0 02 04 06 08 1-1

-08

-06

-04

-02

0

02

04

06

08

1

09

0807060504

03

02

01

26e5

234e5

208e5

182e5

156e513e5

104e5

781e4

521e4

26e4

26e5

234e5

208e5

182e5

156e513e5

104e5

781e4

521e4

26e4

x

x

x




Duty cycle

30 micros


1z00372)z(Rminus

=

1zK)z(R 1

minus=

Controller delay

05358z02236z07417)(z3767G(z) 2 +sdotminus

+sdot=Converter

x

x

x Duty cycle

Output voltage

52


UPM

10 micros


xx

x

x

x

x

x

x




00775)(z1)(z037)(z00378R(z)

minussdotminus+sdot

=

Duty cycle

Output voltage


UPM


75 micros

xx

x

x

x

xx

x



minussdotminus+sdot

=

53


UPM


Duty

a1 = -0922548 b1 = 0037759b2 = 0051742a2 = 0

b1

b2

δ-1

δ-1

δ-1

a1

a2

Error

bn0

No b0

δ-1

Z-1

+

00775)(z1)(z037)(z00378R(z)

minussdotminus+sdot

=




UPM


z2d_m ( tf ([00378 0013986] [1 -10775 00775] 192e-6) )




=Tsample = Tsw

⎪⎩

⎪⎨⎧

rarrδ

+=δ δδ

s


54


UPM


Reference

Switched model

7 bits

8 bits

Not quantizied


PWM

ADC

111






UPM

Reference


PWM

ADC






hellip

222

55


UPM



a1 = -0922548 b1 = 0037759b2 = 0051742a2 = 0

b1

b2

δ-1

δ-1

δ-1

a1

a2

Error

bn0

No b0


UPM


0lt Duty cycle lt1


Hardware adders






Beware

56


UPM

0 1 2 30

05

1

15

2

25








UPM



0 1 2 3

x 10-4

0

05

1

15

2

25

100 usdiv100 usdiv



57


UPM






UPM




58


UPM


13 14 15 16 17 18 19

x 10-4

12

14

16

18

2

22

08 V drop

10 microsdiv

2 V





UPM



Vo

1 V

2 V



11 A11 A

20 mV

520 kHz



59


UPM


Vo

Io

200 mV







UPM


Vo

1 V

2 V





60


UPM





Beware



UPM



44


UPM

33 33 DitherDither

SW

CLK

ff Resolution gt

d = 42

d =43

d =425

T=2TSW=8μs

Output voltage

2 solutions

V=50mV

TSW=4μs 1 solution

T=4μs

Output voltage

V=25mV

SW

CLKNVirtual



Average duty cycle

It gives 1 more bit


UPM



SimulatedSimulated

MeasuredMeasured



)(

4110780250 22




45


UPM






UPM


f = 200Hz f = 15kHz

f = 3kHz f = 5kHz

46


UPM





UPM



2 2 micromicross

Vo

1 V

2 V

VRM for DVS5 V

Io = 20 A max

1V - 2 V

Io

02 V max02 V max

0 A

20 A

500 Amicros

Vo




47


UPM


10-1 100 101

100

L-C diagram

C2 micros

200 mV

20A




C = 35 C = 35 μμFF



UPM






fsw = 520 kHz

(125 mΩ eq Rds_on)





48


UPM


0

1

To drivers

New vref

vo dig

N-phases_tran

N-phases

New vref

vo dig

New vref

vo dig


ic


NON-LINEAR CONTROL





UPM


vref

vo

0

1

To drivers

clk_sample

clk_sample

ADC

N-phases_tran

N-phases

vo dig

LINEAR CONTROL



49


UPM


vref

vo

0

1

To drivers

New vref

vo dig

clk_sample

clk_sample

ADC

N-phases_tran

N-phases

vo dig

New vref

LINEAR CONTROL

NON-LINEAR CONTROL

vo dig

New vrefvo dig


ic



Beware


UPM


UpUp--stepstep

ConverterFPGA

tt11



DownDown--stepstep

t1 t2 t1 t2

ddnn

tt22vref

500 kHz

LUT


05

1

15

2

25

0 02 04 06 08 1 12 14 16 18-10

0

10

20

30

40

50

ton toff

Tmin

05

1

15

2

25

0 02 04 06 08 1 12 14 16 18-10

0

10

20

30

40

50

ton toff

Tmin

i L(A

)i L

(A)

V o(V

)V o

(V)


50


UPM


t1 t2 t1 t2

094 096 098 1 102 104 106 108 11

x 10-4

14

16

18

2

22

24

26

28

3

32

094 096 098 1 102 104 106 108 11

x 10-4

0

1

2

3

4

5092 094 096 098 1 102 104 106 108 11 112

x 10-4

14

16

18

2

22

24

26

28

3

32

092 094 096 098 1 102 104 106 108 11 112

x 10-4

0

05

1

15

2

25

3

35

4

45

Transient





Beware


UPM

ΔIo

iL

Io

vo

ic 0 ATrip point 1

Trip point 2

ΔIo

ic





51


UPM


05358z02236z07417)(z3767G(z) 2 +sdotminus

+sdot=

B G(s)

G(z)




N = 4

ESR = 125 mΩ

( )CL

1sRESRL1s

CL1)1sCESR(V

)s(Gdv

L2

ino

sdot+sdot+sdot+


==

~ VinmiddotdCo

ESR

RphaseN LphaseN

Expected by design


DC resistance


model


Beware


UPM


Pole-Zero Map

Real Axis

-1 -08 -06 -04 -02 0 02 04 06 08 1-1

-08

-06

-04

-02

0

02

04

06

08

1

09

0807060504

03

02

01

26e5

234e5

208e5

182e5

156e513e5

104e5

781e4

521e4

26e4

26e5

234e5

208e5

182e5

156e513e5

104e5

781e4

521e4

26e4

x

x

x




Duty cycle

30 micros


1z00372)z(Rminus

=

1zK)z(R 1

minus=

Controller delay

05358z02236z07417)(z3767G(z) 2 +sdotminus

+sdot=Converter

x

x

x Duty cycle

Output voltage

52


UPM

10 micros


xx

x

x

x

x

x

x




00775)(z1)(z037)(z00378R(z)

minussdotminus+sdot

=

Duty cycle

Output voltage


UPM


75 micros

xx

x

x

x

xx

x



minussdotminus+sdot

=

53


UPM


Duty

a1 = -0922548 b1 = 0037759b2 = 0051742a2 = 0

b1

b2

δ-1

δ-1

δ-1

a1

a2

Error

bn0

No b0

δ-1

Z-1

+

00775)(z1)(z037)(z00378R(z)

minussdotminus+sdot

=




UPM


z2d_m ( tf ([00378 0013986] [1 -10775 00775] 192e-6) )




=Tsample = Tsw

⎪⎩

⎪⎨⎧

rarrδ

+=δ δδ

s


54


UPM


Reference

Switched model

7 bits

8 bits

Not quantizied


PWM

ADC

111






UPM

Reference


PWM

ADC






hellip

222

55


UPM



a1 = -0922548 b1 = 0037759b2 = 0051742a2 = 0

b1

b2

δ-1

δ-1

δ-1

a1

a2

Error

bn0

No b0


UPM


0lt Duty cycle lt1


Hardware adders






Beware

56


UPM

0 1 2 30

05

1

15

2

25








UPM



0 1 2 3

x 10-4

0

05

1

15

2

25

100 usdiv100 usdiv



57


UPM






UPM




58


UPM


13 14 15 16 17 18 19

x 10-4

12

14

16

18

2

22

08 V drop

10 microsdiv

2 V





UPM



Vo

1 V

2 V



11 A11 A

20 mV

520 kHz



59


UPM


Vo

Io

200 mV







UPM


Vo

1 V

2 V





60


UPM





Beware



UPM



45


UPM






UPM


f = 200Hz f = 15kHz

f = 3kHz f = 5kHz

46


UPM





UPM



2 2 micromicross

Vo

1 V

2 V

VRM for DVS5 V

Io = 20 A max

1V - 2 V

Io

02 V max02 V max

0 A

20 A

500 Amicros

Vo




47


UPM


10-1 100 101

100

L-C diagram

C2 micros

200 mV

20A




C = 35 C = 35 μμFF



UPM






fsw = 520 kHz

(125 mΩ eq Rds_on)





48


UPM


0

1

To drivers

New vref

vo dig

N-phases_tran

N-phases

New vref

vo dig

New vref

vo dig


ic


NON-LINEAR CONTROL





UPM


vref

vo

0

1

To drivers

clk_sample

clk_sample

ADC

N-phases_tran

N-phases

vo dig

LINEAR CONTROL



49


UPM


vref

vo

0

1

To drivers

New vref

vo dig

clk_sample

clk_sample

ADC

N-phases_tran

N-phases

vo dig

New vref

LINEAR CONTROL

NON-LINEAR CONTROL

vo dig

New vrefvo dig


ic



Beware


UPM


UpUp--stepstep

ConverterFPGA

tt11



DownDown--stepstep

t1 t2 t1 t2

ddnn

tt22vref

500 kHz

LUT


05

1

15

2

25

0 02 04 06 08 1 12 14 16 18-10

0

10

20

30

40

50

ton toff

Tmin

05

1

15

2

25

0 02 04 06 08 1 12 14 16 18-10

0

10

20

30

40

50

ton toff

Tmin

i L(A

)i L

(A)

V o(V

)V o

(V)


50


UPM


t1 t2 t1 t2

094 096 098 1 102 104 106 108 11

x 10-4

14

16

18

2

22

24

26

28

3

32

094 096 098 1 102 104 106 108 11

x 10-4

0

1

2

3

4

5092 094 096 098 1 102 104 106 108 11 112

x 10-4

14

16

18

2

22

24

26

28

3

32

092 094 096 098 1 102 104 106 108 11 112

x 10-4

0

05

1

15

2

25

3

35

4

45

Transient





Beware


UPM

ΔIo

iL

Io

vo

ic 0 ATrip point 1

Trip point 2

ΔIo

ic





51


UPM


05358z02236z07417)(z3767G(z) 2 +sdotminus

+sdot=

B G(s)

G(z)




N = 4

ESR = 125 mΩ

( )CL

1sRESRL1s

CL1)1sCESR(V

)s(Gdv

L2

ino

sdot+sdot+sdot+


==

~ VinmiddotdCo

ESR

RphaseN LphaseN

Expected by design


DC resistance


model


Beware


UPM


Pole-Zero Map

Real Axis

-1 -08 -06 -04 -02 0 02 04 06 08 1-1

-08

-06

-04

-02

0

02

04

06

08

1

09

0807060504

03

02

01

26e5

234e5

208e5

182e5

156e513e5

104e5

781e4

521e4

26e4

26e5

234e5

208e5

182e5

156e513e5

104e5

781e4

521e4

26e4

x

x

x




Duty cycle

30 micros


1z00372)z(Rminus

=

1zK)z(R 1

minus=

Controller delay

05358z02236z07417)(z3767G(z) 2 +sdotminus

+sdot=Converter

x

x

x Duty cycle

Output voltage

52


UPM

10 micros


xx

x

x

x

x

x

x




00775)(z1)(z037)(z00378R(z)

minussdotminus+sdot

=

Duty cycle

Output voltage


UPM


75 micros

xx

x

x

x

xx

x



minussdotminus+sdot

=

53


UPM


Duty

a1 = -0922548 b1 = 0037759b2 = 0051742a2 = 0

b1

b2

δ-1

δ-1

δ-1

a1

a2

Error

bn0

No b0

δ-1

Z-1

+

00775)(z1)(z037)(z00378R(z)

minussdotminus+sdot

=




UPM


z2d_m ( tf ([00378 0013986] [1 -10775 00775] 192e-6) )




=Tsample = Tsw

⎪⎩

⎪⎨⎧

rarrδ

+=δ δδ

s


54


UPM


Reference

Switched model

7 bits

8 bits

Not quantizied


PWM

ADC

111






UPM

Reference


PWM

ADC






hellip

222

55


UPM



a1 = -0922548 b1 = 0037759b2 = 0051742a2 = 0

b1

b2

δ-1

δ-1

δ-1

a1

a2

Error

bn0

No b0


UPM


0lt Duty cycle lt1


Hardware adders






Beware

56


UPM

0 1 2 30

05

1

15

2

25








UPM



0 1 2 3

x 10-4

0

05

1

15

2

25

100 usdiv100 usdiv



57


UPM






UPM




58


UPM


13 14 15 16 17 18 19

x 10-4

12

14

16

18

2

22

08 V drop

10 microsdiv

2 V





UPM



Vo

1 V

2 V



11 A11 A

20 mV

520 kHz



59


UPM


Vo

Io

200 mV







UPM


Vo

1 V

2 V





60


UPM





Beware



UPM



46


UPM





UPM



2 2 micromicross

Vo

1 V

2 V

VRM for DVS5 V

Io = 20 A max

1V - 2 V

Io

02 V max02 V max

0 A

20 A

500 Amicros

Vo




47


UPM


10-1 100 101

100

L-C diagram

C2 micros

200 mV

20A




C = 35 C = 35 μμFF



UPM






fsw = 520 kHz

(125 mΩ eq Rds_on)





48


UPM


0

1

To drivers

New vref

vo dig

N-phases_tran

N-phases

New vref

vo dig

New vref

vo dig


ic


NON-LINEAR CONTROL





UPM


vref

vo

0

1

To drivers

clk_sample

clk_sample

ADC

N-phases_tran

N-phases

vo dig

LINEAR CONTROL



49


UPM


vref

vo

0

1

To drivers

New vref

vo dig

clk_sample

clk_sample

ADC

N-phases_tran

N-phases

vo dig

New vref

LINEAR CONTROL

NON-LINEAR CONTROL

vo dig

New vrefvo dig


ic



Beware


UPM


UpUp--stepstep

ConverterFPGA

tt11



DownDown--stepstep

t1 t2 t1 t2

ddnn

tt22vref

500 kHz

LUT


05

1

15

2

25

0 02 04 06 08 1 12 14 16 18-10

0

10

20

30

40

50

ton toff

Tmin

05

1

15

2

25

0 02 04 06 08 1 12 14 16 18-10

0

10

20

30

40

50

ton toff

Tmin

i L(A

)i L

(A)

V o(V

)V o

(V)


50


UPM


t1 t2 t1 t2

094 096 098 1 102 104 106 108 11

x 10-4

14

16

18

2

22

24

26

28

3

32

094 096 098 1 102 104 106 108 11

x 10-4

0

1

2

3

4

5092 094 096 098 1 102 104 106 108 11 112

x 10-4

14

16

18

2

22

24

26

28

3

32

092 094 096 098 1 102 104 106 108 11 112

x 10-4

0

05

1

15

2

25

3

35

4

45

Transient





Beware


UPM

ΔIo

iL

Io

vo

ic 0 ATrip point 1

Trip point 2

ΔIo

ic





51


UPM


05358z02236z07417)(z3767G(z) 2 +sdotminus

+sdot=

B G(s)

G(z)




N = 4

ESR = 125 mΩ

( )CL

1sRESRL1s

CL1)1sCESR(V

)s(Gdv

L2

ino

sdot+sdot+sdot+


==

~ VinmiddotdCo

ESR

RphaseN LphaseN

Expected by design


DC resistance


model


Beware


UPM


Pole-Zero Map

Real Axis

-1 -08 -06 -04 -02 0 02 04 06 08 1-1

-08

-06

-04

-02

0

02

04

06

08

1

09

0807060504

03

02

01

26e5

234e5

208e5

182e5

156e513e5

104e5

781e4

521e4

26e4

26e5

234e5

208e5

182e5

156e513e5

104e5

781e4

521e4

26e4

x

x

x




Duty cycle

30 micros


1z00372)z(Rminus

=

1zK)z(R 1

minus=

Controller delay

05358z02236z07417)(z3767G(z) 2 +sdotminus

+sdot=Converter

x

x

x Duty cycle

Output voltage

52


UPM

10 micros


xx

x

x

x

x

x

x




00775)(z1)(z037)(z00378R(z)

minussdotminus+sdot

=

Duty cycle

Output voltage


UPM


75 micros

xx

x

x

x

xx

x



minussdotminus+sdot

=

53


UPM


Duty

a1 = -0922548 b1 = 0037759b2 = 0051742a2 = 0

b1

b2

δ-1

δ-1

δ-1

a1

a2

Error

bn0

No b0

δ-1

Z-1

+

00775)(z1)(z037)(z00378R(z)

minussdotminus+sdot

=




UPM


z2d_m ( tf ([00378 0013986] [1 -10775 00775] 192e-6) )




=Tsample = Tsw

⎪⎩

⎪⎨⎧

rarrδ

+=δ δδ

s


54


UPM


Reference

Switched model

7 bits

8 bits

Not quantizied


PWM

ADC

111






UPM

Reference


PWM

ADC






hellip

222

55


UPM



a1 = -0922548 b1 = 0037759b2 = 0051742a2 = 0

b1

b2

δ-1

δ-1

δ-1

a1

a2

Error

bn0

No b0


UPM


0lt Duty cycle lt1


Hardware adders






Beware

56


UPM

0 1 2 30

05

1

15

2

25








UPM



0 1 2 3

x 10-4

0

05

1

15

2

25

100 usdiv100 usdiv



57


UPM






UPM




58


UPM


13 14 15 16 17 18 19

x 10-4

12

14

16

18

2

22

08 V drop

10 microsdiv

2 V





UPM



Vo

1 V

2 V



11 A11 A

20 mV

520 kHz



59


UPM


Vo

Io

200 mV







UPM


Vo

1 V

2 V





60


UPM





Beware



UPM



47


UPM


10-1 100 101

100

L-C diagram

C2 micros

200 mV

20A




C = 35 C = 35 μμFF



UPM






fsw = 520 kHz

(125 mΩ eq Rds_on)





48


UPM


0

1

To drivers

New vref

vo dig

N-phases_tran

N-phases

New vref

vo dig

New vref

vo dig


ic


NON-LINEAR CONTROL





UPM


vref

vo

0

1

To drivers

clk_sample

clk_sample

ADC

N-phases_tran

N-phases

vo dig

LINEAR CONTROL



49


UPM


vref

vo

0

1

To drivers

New vref

vo dig

clk_sample

clk_sample

ADC

N-phases_tran

N-phases

vo dig

New vref

LINEAR CONTROL

NON-LINEAR CONTROL

vo dig

New vrefvo dig


ic



Beware


UPM


UpUp--stepstep

ConverterFPGA

tt11



DownDown--stepstep

t1 t2 t1 t2

ddnn

tt22vref

500 kHz

LUT


05

1

15

2

25

0 02 04 06 08 1 12 14 16 18-10

0

10

20

30

40

50

ton toff

Tmin

05

1

15

2

25

0 02 04 06 08 1 12 14 16 18-10

0

10

20

30

40

50

ton toff

Tmin

i L(A

)i L

(A)

V o(V

)V o

(V)


50


UPM


t1 t2 t1 t2

094 096 098 1 102 104 106 108 11

x 10-4

14

16

18

2

22

24

26

28

3

32

094 096 098 1 102 104 106 108 11

x 10-4

0

1

2

3

4

5092 094 096 098 1 102 104 106 108 11 112

x 10-4

14

16

18

2

22

24

26

28

3

32

092 094 096 098 1 102 104 106 108 11 112

x 10-4

0

05

1

15

2

25

3

35

4

45

Transient





Beware


UPM

ΔIo

iL

Io

vo

ic 0 ATrip point 1

Trip point 2

ΔIo

ic





51


UPM


05358z02236z07417)(z3767G(z) 2 +sdotminus

+sdot=

B G(s)

G(z)




N = 4

ESR = 125 mΩ

( )CL

1sRESRL1s

CL1)1sCESR(V

)s(Gdv

L2

ino

sdot+sdot+sdot+


==

~ VinmiddotdCo

ESR

RphaseN LphaseN

Expected by design


DC resistance


model


Beware


UPM


Pole-Zero Map

Real Axis

-1 -08 -06 -04 -02 0 02 04 06 08 1-1

-08

-06

-04

-02

0

02

04

06

08

1

09

0807060504

03

02

01

26e5

234e5

208e5

182e5

156e513e5

104e5

781e4

521e4

26e4

26e5

234e5

208e5

182e5

156e513e5

104e5

781e4

521e4

26e4

x

x

x




Duty cycle

30 micros


1z00372)z(Rminus

=

1zK)z(R 1

minus=

Controller delay

05358z02236z07417)(z3767G(z) 2 +sdotminus

+sdot=Converter

x

x

x Duty cycle

Output voltage

52


UPM

10 micros


xx

x

x

x

x

x

x




00775)(z1)(z037)(z00378R(z)

minussdotminus+sdot

=

Duty cycle

Output voltage


UPM


75 micros

xx

x

x

x

xx

x



minussdotminus+sdot

=

53


UPM


Duty

a1 = -0922548 b1 = 0037759b2 = 0051742a2 = 0

b1

b2

δ-1

δ-1

δ-1

a1

a2

Error

bn0

No b0

δ-1

Z-1

+

00775)(z1)(z037)(z00378R(z)

minussdotminus+sdot

=




UPM


z2d_m ( tf ([00378 0013986] [1 -10775 00775] 192e-6) )




=Tsample = Tsw

⎪⎩

⎪⎨⎧

rarrδ

+=δ δδ

s


54


UPM


Reference

Switched model

7 bits

8 bits

Not quantizied


PWM

ADC

111






UPM

Reference


PWM

ADC






hellip

222

55


UPM



a1 = -0922548 b1 = 0037759b2 = 0051742a2 = 0

b1

b2

δ-1

δ-1

δ-1

a1

a2

Error

bn0

No b0


UPM


0lt Duty cycle lt1


Hardware adders






Beware

56


UPM

0 1 2 30

05

1

15

2

25








UPM



0 1 2 3

x 10-4

0

05

1

15

2

25

100 usdiv100 usdiv



57


UPM






UPM




58


UPM


13 14 15 16 17 18 19

x 10-4

12

14

16

18

2

22

08 V drop

10 microsdiv

2 V





UPM



Vo

1 V

2 V



11 A11 A

20 mV

520 kHz



59


UPM


Vo

Io

200 mV







UPM


Vo

1 V

2 V





60


UPM





Beware



UPM



48


UPM


0

1

To drivers

New vref

vo dig

N-phases_tran

N-phases

New vref

vo dig

New vref

vo dig


ic


NON-LINEAR CONTROL





UPM


vref

vo

0

1

To drivers

clk_sample

clk_sample

ADC

N-phases_tran

N-phases

vo dig

LINEAR CONTROL



49


UPM


vref

vo

0

1

To drivers

New vref

vo dig

clk_sample

clk_sample

ADC

N-phases_tran

N-phases

vo dig

New vref

LINEAR CONTROL

NON-LINEAR CONTROL

vo dig

New vrefvo dig


ic



Beware


UPM


UpUp--stepstep

ConverterFPGA

tt11



DownDown--stepstep

t1 t2 t1 t2

ddnn

tt22vref

500 kHz

LUT


05

1

15

2

25

0 02 04 06 08 1 12 14 16 18-10

0

10

20

30

40

50

ton toff

Tmin

05

1

15

2

25

0 02 04 06 08 1 12 14 16 18-10

0

10

20

30

40

50

ton toff

Tmin

i L(A

)i L

(A)

V o(V

)V o

(V)


50


UPM


t1 t2 t1 t2

094 096 098 1 102 104 106 108 11

x 10-4

14

16

18

2

22

24

26

28

3

32

094 096 098 1 102 104 106 108 11

x 10-4

0

1

2

3

4

5092 094 096 098 1 102 104 106 108 11 112

x 10-4

14

16

18

2

22

24

26

28

3

32

092 094 096 098 1 102 104 106 108 11 112

x 10-4

0

05

1

15

2

25

3

35

4

45

Transient





Beware


UPM

ΔIo

iL

Io

vo

ic 0 ATrip point 1

Trip point 2

ΔIo

ic





51


UPM


05358z02236z07417)(z3767G(z) 2 +sdotminus

+sdot=

B G(s)

G(z)




N = 4

ESR = 125 mΩ

( )CL

1sRESRL1s

CL1)1sCESR(V

)s(Gdv

L2

ino

sdot+sdot+sdot+


==

~ VinmiddotdCo

ESR

RphaseN LphaseN

Expected by design


DC resistance


model


Beware


UPM


Pole-Zero Map

Real Axis

-1 -08 -06 -04 -02 0 02 04 06 08 1-1

-08

-06

-04

-02

0

02

04

06

08

1

09

0807060504

03

02

01

26e5

234e5

208e5

182e5

156e513e5

104e5

781e4

521e4

26e4

26e5

234e5

208e5

182e5

156e513e5

104e5

781e4

521e4

26e4

x

x

x




Duty cycle

30 micros


1z00372)z(Rminus

=

1zK)z(R 1

minus=

Controller delay

05358z02236z07417)(z3767G(z) 2 +sdotminus

+sdot=Converter

x

x

x Duty cycle

Output voltage

52


UPM

10 micros


xx

x

x

x

x

x

x




00775)(z1)(z037)(z00378R(z)

minussdotminus+sdot

=

Duty cycle

Output voltage


UPM


75 micros

xx

x

x

x

xx

x



minussdotminus+sdot

=

53


UPM


Duty

a1 = -0922548 b1 = 0037759b2 = 0051742a2 = 0

b1

b2

δ-1

δ-1

δ-1

a1

a2

Error

bn0

No b0

δ-1

Z-1

+

00775)(z1)(z037)(z00378R(z)

minussdotminus+sdot

=




UPM


z2d_m ( tf ([00378 0013986] [1 -10775 00775] 192e-6) )




=Tsample = Tsw

⎪⎩

⎪⎨⎧

rarrδ

+=δ δδ

s


54


UPM


Reference

Switched model

7 bits

8 bits

Not quantizied


PWM

ADC

111






UPM

Reference


PWM

ADC






hellip

222

55


UPM



a1 = -0922548 b1 = 0037759b2 = 0051742a2 = 0

b1

b2

δ-1

δ-1

δ-1

a1

a2

Error

bn0

No b0


UPM


0lt Duty cycle lt1


Hardware adders






Beware

56


UPM

0 1 2 30

05

1

15

2

25








UPM



0 1 2 3

x 10-4

0

05

1

15

2

25

100 usdiv100 usdiv



57


UPM






UPM




58


UPM


13 14 15 16 17 18 19

x 10-4

12

14

16

18

2

22

08 V drop

10 microsdiv

2 V





UPM



Vo

1 V

2 V



11 A11 A

20 mV

520 kHz



59


UPM


Vo

Io

200 mV







UPM


Vo

1 V

2 V





60


UPM





Beware



UPM



49


UPM


vref

vo

0

1

To drivers

New vref

vo dig

clk_sample

clk_sample

ADC

N-phases_tran

N-phases

vo dig

New vref

LINEAR CONTROL

NON-LINEAR CONTROL

vo dig

New vrefvo dig


ic



Beware


UPM


UpUp--stepstep

ConverterFPGA

tt11



DownDown--stepstep

t1 t2 t1 t2

ddnn

tt22vref

500 kHz

LUT


05

1

15

2

25

0 02 04 06 08 1 12 14 16 18-10

0

10

20

30

40

50

ton toff

Tmin

05

1

15

2

25

0 02 04 06 08 1 12 14 16 18-10

0

10

20

30

40

50

ton toff

Tmin

i L(A

)i L

(A)

V o(V

)V o

(V)


50


UPM


t1 t2 t1 t2

094 096 098 1 102 104 106 108 11

x 10-4

14

16

18

2

22

24

26

28

3

32

094 096 098 1 102 104 106 108 11

x 10-4

0

1

2

3

4

5092 094 096 098 1 102 104 106 108 11 112

x 10-4

14

16

18

2

22

24

26

28

3

32

092 094 096 098 1 102 104 106 108 11 112

x 10-4

0

05

1

15

2

25

3

35

4

45

Transient





Beware


UPM

ΔIo

iL

Io

vo

ic 0 ATrip point 1

Trip point 2

ΔIo

ic





51


UPM


05358z02236z07417)(z3767G(z) 2 +sdotminus

+sdot=

B G(s)

G(z)




N = 4

ESR = 125 mΩ

( )CL

1sRESRL1s

CL1)1sCESR(V

)s(Gdv

L2

ino

sdot+sdot+sdot+


==

~ VinmiddotdCo

ESR

RphaseN LphaseN

Expected by design


DC resistance


model


Beware


UPM


Pole-Zero Map

Real Axis

-1 -08 -06 -04 -02 0 02 04 06 08 1-1

-08

-06

-04

-02

0

02

04

06

08

1

09

0807060504

03

02

01

26e5

234e5

208e5

182e5

156e513e5

104e5

781e4

521e4

26e4

26e5

234e5

208e5

182e5

156e513e5

104e5

781e4

521e4

26e4

x

x

x




Duty cycle

30 micros


1z00372)z(Rminus

=

1zK)z(R 1

minus=

Controller delay

05358z02236z07417)(z3767G(z) 2 +sdotminus

+sdot=Converter

x

x

x Duty cycle

Output voltage

52


UPM

10 micros


xx

x

x

x

x

x

x




00775)(z1)(z037)(z00378R(z)

minussdotminus+sdot

=

Duty cycle

Output voltage


UPM


75 micros

xx

x

x

x

xx

x



minussdotminus+sdot

=

53


UPM


Duty

a1 = -0922548 b1 = 0037759b2 = 0051742a2 = 0

b1

b2

δ-1

δ-1

δ-1

a1

a2

Error

bn0

No b0

δ-1

Z-1

+

00775)(z1)(z037)(z00378R(z)

minussdotminus+sdot

=




UPM


z2d_m ( tf ([00378 0013986] [1 -10775 00775] 192e-6) )




=Tsample = Tsw

⎪⎩

⎪⎨⎧

rarrδ

+=δ δδ

s


54


UPM


Reference

Switched model

7 bits

8 bits

Not quantizied


PWM

ADC

111






UPM

Reference


PWM

ADC






hellip

222

55


UPM



a1 = -0922548 b1 = 0037759b2 = 0051742a2 = 0

b1

b2

δ-1

δ-1

δ-1

a1

a2

Error

bn0

No b0


UPM


0lt Duty cycle lt1


Hardware adders






Beware

56


UPM

0 1 2 30

05

1

15

2

25








UPM



0 1 2 3

x 10-4

0

05

1

15

2

25

100 usdiv100 usdiv



57


UPM






UPM




58


UPM


13 14 15 16 17 18 19

x 10-4

12

14

16

18

2

22

08 V drop

10 microsdiv

2 V





UPM



Vo

1 V

2 V



11 A11 A

20 mV

520 kHz



59


UPM


Vo

Io

200 mV







UPM


Vo

1 V

2 V





60


UPM





Beware



UPM



50


UPM


t1 t2 t1 t2

094 096 098 1 102 104 106 108 11

x 10-4

14

16

18

2

22

24

26

28

3

32

094 096 098 1 102 104 106 108 11

x 10-4

0

1

2

3

4

5092 094 096 098 1 102 104 106 108 11 112

x 10-4

14

16

18

2

22

24

26

28

3

32

092 094 096 098 1 102 104 106 108 11 112

x 10-4

0

05

1

15

2

25

3

35

4

45

Transient





Beware


UPM

ΔIo

iL

Io

vo

ic 0 ATrip point 1

Trip point 2

ΔIo

ic





51


UPM


05358z02236z07417)(z3767G(z) 2 +sdotminus

+sdot=

B G(s)

G(z)




N = 4

ESR = 125 mΩ

( )CL

1sRESRL1s

CL1)1sCESR(V

)s(Gdv

L2

ino

sdot+sdot+sdot+


==

~ VinmiddotdCo

ESR

RphaseN LphaseN

Expected by design


DC resistance


model


Beware


UPM


Pole-Zero Map

Real Axis

-1 -08 -06 -04 -02 0 02 04 06 08 1-1

-08

-06

-04

-02

0

02

04

06

08

1

09

0807060504

03

02

01

26e5

234e5

208e5

182e5

156e513e5

104e5

781e4

521e4

26e4

26e5

234e5

208e5

182e5

156e513e5

104e5

781e4

521e4

26e4

x

x

x




Duty cycle

30 micros


1z00372)z(Rminus

=

1zK)z(R 1

minus=

Controller delay

05358z02236z07417)(z3767G(z) 2 +sdotminus

+sdot=Converter

x

x

x Duty cycle

Output voltage

52


UPM

10 micros


xx

x

x

x

x

x

x




00775)(z1)(z037)(z00378R(z)

minussdotminus+sdot

=

Duty cycle

Output voltage


UPM


75 micros

xx

x

x

x

xx

x



minussdotminus+sdot

=

53


UPM


Duty

a1 = -0922548 b1 = 0037759b2 = 0051742a2 = 0

b1

b2

δ-1

δ-1

δ-1

a1

a2

Error

bn0

No b0

δ-1

Z-1

+

00775)(z1)(z037)(z00378R(z)

minussdotminus+sdot

=




UPM


z2d_m ( tf ([00378 0013986] [1 -10775 00775] 192e-6) )




=Tsample = Tsw

⎪⎩

⎪⎨⎧

rarrδ

+=δ δδ

s


54


UPM


Reference

Switched model

7 bits

8 bits

Not quantizied


PWM

ADC

111






UPM

Reference


PWM

ADC






hellip

222

55


UPM



a1 = -0922548 b1 = 0037759b2 = 0051742a2 = 0

b1

b2

δ-1

δ-1

δ-1

a1

a2

Error

bn0

No b0


UPM


0lt Duty cycle lt1


Hardware adders






Beware

56


UPM

0 1 2 30

05

1

15

2

25








UPM



0 1 2 3

x 10-4

0

05

1

15

2

25

100 usdiv100 usdiv



57


UPM






UPM




58


UPM


13 14 15 16 17 18 19

x 10-4

12

14

16

18

2

22

08 V drop

10 microsdiv

2 V





UPM



Vo

1 V

2 V



11 A11 A

20 mV

520 kHz



59


UPM


Vo

Io

200 mV







UPM


Vo

1 V

2 V





60


UPM





Beware



UPM



51


UPM


05358z02236z07417)(z3767G(z) 2 +sdotminus

+sdot=

B G(s)

G(z)




N = 4

ESR = 125 mΩ

( )CL

1sRESRL1s

CL1)1sCESR(V

)s(Gdv

L2

ino

sdot+sdot+sdot+


==

~ VinmiddotdCo

ESR

RphaseN LphaseN

Expected by design


DC resistance


model


Beware


UPM


Pole-Zero Map

Real Axis

-1 -08 -06 -04 -02 0 02 04 06 08 1-1

-08

-06

-04

-02

0

02

04

06

08

1

09

0807060504

03

02

01

26e5

234e5

208e5

182e5

156e513e5

104e5

781e4

521e4

26e4

26e5

234e5

208e5

182e5

156e513e5

104e5

781e4

521e4

26e4

x

x

x




Duty cycle

30 micros


1z00372)z(Rminus

=

1zK)z(R 1

minus=

Controller delay

05358z02236z07417)(z3767G(z) 2 +sdotminus

+sdot=Converter

x

x

x Duty cycle

Output voltage

52


UPM

10 micros


xx

x

x

x

x

x

x




00775)(z1)(z037)(z00378R(z)

minussdotminus+sdot

=

Duty cycle

Output voltage


UPM


75 micros

xx

x

x

x

xx

x



minussdotminus+sdot

=

53


UPM


Duty

a1 = -0922548 b1 = 0037759b2 = 0051742a2 = 0

b1

b2

δ-1

δ-1

δ-1

a1

a2

Error

bn0

No b0

δ-1

Z-1

+

00775)(z1)(z037)(z00378R(z)

minussdotminus+sdot

=




UPM


z2d_m ( tf ([00378 0013986] [1 -10775 00775] 192e-6) )




=Tsample = Tsw

⎪⎩

⎪⎨⎧

rarrδ

+=δ δδ

s


54


UPM


Reference

Switched model

7 bits

8 bits

Not quantizied


PWM

ADC

111






UPM

Reference


PWM

ADC






hellip

222

55


UPM



a1 = -0922548 b1 = 0037759b2 = 0051742a2 = 0

b1

b2

δ-1

δ-1

δ-1

a1

a2

Error

bn0

No b0


UPM


0lt Duty cycle lt1


Hardware adders






Beware

56


UPM

0 1 2 30

05

1

15

2

25








UPM



0 1 2 3

x 10-4

0

05

1

15

2

25

100 usdiv100 usdiv



57


UPM






UPM




58


UPM


13 14 15 16 17 18 19

x 10-4

12

14

16

18

2

22

08 V drop

10 microsdiv

2 V





UPM



Vo

1 V

2 V



11 A11 A

20 mV

520 kHz



59


UPM


Vo

Io

200 mV







UPM


Vo

1 V

2 V





60


UPM





Beware



UPM



52


UPM

10 micros


xx

x

x

x

x

x

x




00775)(z1)(z037)(z00378R(z)

minussdotminus+sdot

=

Duty cycle

Output voltage


UPM


75 micros

xx

x

x

x

xx

x



minussdotminus+sdot

=

53


UPM


Duty

a1 = -0922548 b1 = 0037759b2 = 0051742a2 = 0

b1

b2

δ-1

δ-1

δ-1

a1

a2

Error

bn0

No b0

δ-1

Z-1

+

00775)(z1)(z037)(z00378R(z)

minussdotminus+sdot

=




UPM


z2d_m ( tf ([00378 0013986] [1 -10775 00775] 192e-6) )




=Tsample = Tsw

⎪⎩

⎪⎨⎧

rarrδ

+=δ δδ

s


54


UPM


Reference

Switched model

7 bits

8 bits

Not quantizied


PWM

ADC

111






UPM

Reference


PWM

ADC






hellip

222

55


UPM



a1 = -0922548 b1 = 0037759b2 = 0051742a2 = 0

b1

b2

δ-1

δ-1

δ-1

a1

a2

Error

bn0

No b0


UPM


0lt Duty cycle lt1


Hardware adders






Beware

56


UPM

0 1 2 30

05

1

15

2

25








UPM



0 1 2 3

x 10-4

0

05

1

15

2

25

100 usdiv100 usdiv



57


UPM






UPM




58


UPM


13 14 15 16 17 18 19

x 10-4

12

14

16

18

2

22

08 V drop

10 microsdiv

2 V





UPM



Vo

1 V

2 V



11 A11 A

20 mV

520 kHz



59


UPM


Vo

Io

200 mV







UPM


Vo

1 V

2 V





60


UPM





Beware



UPM



53


UPM


Duty

a1 = -0922548 b1 = 0037759b2 = 0051742a2 = 0

b1

b2

δ-1

δ-1

δ-1

a1

a2

Error

bn0

No b0

δ-1

Z-1

+

00775)(z1)(z037)(z00378R(z)

minussdotminus+sdot

=




UPM


z2d_m ( tf ([00378 0013986] [1 -10775 00775] 192e-6) )




=Tsample = Tsw

⎪⎩

⎪⎨⎧

rarrδ

+=δ δδ

s


54


UPM


Reference

Switched model

7 bits

8 bits

Not quantizied


PWM

ADC

111






UPM

Reference


PWM

ADC






hellip

222

55


UPM



a1 = -0922548 b1 = 0037759b2 = 0051742a2 = 0

b1

b2

δ-1

δ-1

δ-1

a1

a2

Error

bn0

No b0


UPM


0lt Duty cycle lt1


Hardware adders






Beware

56


UPM

0 1 2 30

05

1

15

2

25








UPM



0 1 2 3

x 10-4

0

05

1

15

2

25

100 usdiv100 usdiv



57


UPM






UPM




58


UPM


13 14 15 16 17 18 19

x 10-4

12

14

16

18

2

22

08 V drop

10 microsdiv

2 V





UPM



Vo

1 V

2 V



11 A11 A

20 mV

520 kHz



59


UPM


Vo

Io

200 mV







UPM


Vo

1 V

2 V





60


UPM





Beware



UPM



54


UPM


Reference

Switched model

7 bits

8 bits

Not quantizied


PWM

ADC

111






UPM

Reference


PWM

ADC






hellip

222

55


UPM



a1 = -0922548 b1 = 0037759b2 = 0051742a2 = 0

b1

b2

δ-1

δ-1

δ-1

a1

a2

Error

bn0

No b0


UPM


0lt Duty cycle lt1


Hardware adders






Beware

56


UPM

0 1 2 30

05

1

15

2

25








UPM



0 1 2 3

x 10-4

0

05

1

15

2

25

100 usdiv100 usdiv



57


UPM






UPM




58


UPM


13 14 15 16 17 18 19

x 10-4

12

14

16

18

2

22

08 V drop

10 microsdiv

2 V





UPM



Vo

1 V

2 V



11 A11 A

20 mV

520 kHz



59


UPM


Vo

Io

200 mV







UPM


Vo

1 V

2 V





60


UPM





Beware



UPM



55


UPM



a1 = -0922548 b1 = 0037759b2 = 0051742a2 = 0

b1

b2

δ-1

δ-1

δ-1

a1

a2

Error

bn0

No b0


UPM


0lt Duty cycle lt1


Hardware adders






Beware

56


UPM

0 1 2 30

05

1

15

2

25








UPM



0 1 2 3

x 10-4

0

05

1

15

2

25

100 usdiv100 usdiv



57


UPM






UPM




58


UPM


13 14 15 16 17 18 19

x 10-4

12

14

16

18

2

22

08 V drop

10 microsdiv

2 V





UPM



Vo

1 V

2 V



11 A11 A

20 mV

520 kHz



59


UPM


Vo

Io

200 mV







UPM


Vo

1 V

2 V





60


UPM





Beware



UPM



56


UPM

0 1 2 30

05

1

15

2

25








UPM



0 1 2 3

x 10-4

0

05

1

15

2

25

100 usdiv100 usdiv



57


UPM






UPM




58


UPM


13 14 15 16 17 18 19

x 10-4

12

14

16

18

2

22

08 V drop

10 microsdiv

2 V





UPM



Vo

1 V

2 V



11 A11 A

20 mV

520 kHz



59


UPM


Vo

Io

200 mV







UPM


Vo

1 V

2 V





60


UPM





Beware



UPM



57


UPM






UPM




58


UPM


13 14 15 16 17 18 19

x 10-4

12

14

16

18

2

22

08 V drop

10 microsdiv

2 V





UPM



Vo

1 V

2 V



11 A11 A

20 mV

520 kHz



59


UPM


Vo

Io

200 mV







UPM


Vo

1 V

2 V





60


UPM





Beware



UPM



58


UPM


13 14 15 16 17 18 19

x 10-4

12

14

16

18

2

22

08 V drop

10 microsdiv

2 V





UPM



Vo

1 V

2 V



11 A11 A

20 mV

520 kHz



59


UPM


Vo

Io

200 mV







UPM


Vo

1 V

2 V





60


UPM





Beware



UPM



59


UPM


Vo

Io

200 mV







UPM


Vo

1 V

2 V





60


UPM





Beware



UPM



60


UPM





Beware



UPM



Universidad Politécnica de Madrid - keeping an eye on digital ...Universidad Politécnica de Madrid...

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Transcript of Universidad Politécnica de Madrid - keeping an eye on digital ...Universidad Politécnica de Madrid...