UNIT II CIRCUIT CHARACTERIZATION AND SIMULATION€¦ · based on the Grove-Frohman equations...
Transcript of UNIT II CIRCUIT CHARACTERIZATION AND SIMULATION€¦ · based on the Grove-Frohman equations...
EC2354 –VLSI DESIGN III /VI ECE – PREPARED BY L.M.I.LEO JOSEPH Asst.Prof /ECE Page 1
UNIT –II CIRCUIT CHARACTERIZATION AND SIMULATION
1. What is the fundamental goal in Device modeling? [AUC APR 2013]
To obtain the functional relationship among the terminal electrical variables of the device
that is to be modeled.
2. Define Short Channel devices? [AUC NOV 2011]
Transistors with Channel length less than 3- 5 microns are termed as Short channel
devices. With short channel devices the ratio between the lateral & vertical dimensions
are reduced.
3. Why NMOS technology is preferred more than PMOS technology?
N- channel transistors has greater switching speed when compared tp PMOS
transistors.
4. What are the different operating regions foe an MOS transistor? [AUC NOV 2008]
Cutoff region
Non- Saturated Region
Saturated Region
5. What are the different MOS layers?
n-diffusion
p-diffusion
Polysilicon
Metal
6. What is Stick Diagram? [AUC NOV 2013]
It is used to convey information through the use of color code. Also it is the cartoon of a
chip layout.
7. What are the uses of Stick diagram? [AUC NOV 2012]
It can be drawn much easier and faster than a complex layout.
8. These are especially important tools for layout built from large cells. Give the
various color coding used in stick diagram?
Green – n-diffusion
Red- polysilicon
Blue –metal
Yellow- implant
Black-contact areas.
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9. Compare between CMOS and bipolar technologies.
10. Define Threshold voltage in CMOS? [AUC NOV 2009 .APR 2013]
The Threshold voltage, VT for a MOS transistor can be defined as the voltage applied
between the gate and the source of the MOS transistor below which the drain to source
current, IDS effectively drops to zero.
11. What is Body effect? [AUC NOV 2013]
The threshold volatge VT is not a constant w. r. to the voltage difference between the
substrate and the source of MOS transistor. This effect is called substrate-bias effect or
body effect.
12. What is Channel-length modulation? [AUC NOV 2010,NOV 2013]
The current between drain and source terminals is constant and independent of the
applied voltage over the terminals. This is not entirely correct. The effective length of the
conductive channel is actually modulated by the applied VDS, increasing VDS causes
the depletion region at the drain junction to grow, reducing the length of the effective
channel.
13. ,What is Latch – up? [AUC NOV 2007,NOV 2008, APR2010,NOV 2012]
Latch up is a condition in which the parasitic components give rise to the establishment
of low resistance conducting paths between VDD and VSS with disastrous results.
Careful control during fabrication is necessary to avoid this problem.
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14. Give the basic inverter circuit. [AUC NOV 2013]
15. Give the CMOS inverter DC transfer characteristics and operating regions
16. Define Rise time
Rise time, tr is the time taken for a waveform to rise from 10% to 90% of its steady-state
value.
17. Define Fall time
Fall time, tf is the time taken for a waveform to fall from 90% to 10% of its steady-state
value.
18. Define Delay time
Delay time, td is the time difference between input transition (50%) and the 50% output
level. This is the time taken for a logic transition to pass from input to output.
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19. What are two components of Power dissipation.
There are two components that establish the amount of power dissipated in a CMOS
circuit. These are:
i)Static dissipation due to leakage current or other current drawn continuously from the
power supply.
ii) Dynamic dissipation due to Switching transient current Charging and discharging of
load capacitances.
20. Give some of the important CAD tools. [AUC NOV 2013]
Some of the important CAD tools are:
Layout editors
Design Rule checkers (DRC)
Circuit extraction
PART –B (16 MARKS)
1. Write a brief note on Device Models . [ AUC NOV 2011,2012]
Level 1 Models
The SPICE Level 1, or Shichman-Hodges Model [Shichman68] is closely related to the
Shockley model described in EQ (2.10), enhanced with channel length modulation and
the body effect. The basic current model is:
The threshold voltage is modulated by the source-to-body voltage Vsb through the
body effect (see Section 2.4.3.1). For nonnegative Vsb , the threshold voltage is
Level 1 models are useful for teaching because they are easy to correlate with hand
analysis, but are too simplistic for modern design.
Level 2 and 3 Models
The SPICE Level 2 and 3 models add effects of velocity saturation, mobility degradation,
sub threshold conduction, and drain-induced barrier lowering. The Level 2 model is
based on the Grove-Frohman equations [Frohman69], while the Level 3 model is based
on empirical equations that provide similar accuracy, faster simulation times, and better
convergence.
However, these models still do not provide good fits to the measured I-V characteristics
of modern transistors.
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BSIM Models
The Berkeley Short-Channel IGFET1 Model (BSIM) is a very elaborate model that is
now widely used in circuit simulation. The models are derived from the underlying device
physics but use an enormous number of parameters to fit the behavior of modern
transistors.
BSIM versions 1, 2, 3v3, and 4 are implemented as SPICE levels 13, 39, 49, and
54,respectively.
BSIM is quite good for digital circuit simulation.
Features of the model include:
Continuous and differentiable I-V characteristics across sub threshold, linear, and
saturation regions for good convergence
Sensitivity of parameters such as Vt to transistor length and width
Detailed threshold voltage model including body effect and drain-induced barrier
lowering
Velocity saturation, mobility degradation, and other short-channel effects
Multiple gate capacitance models
Diffusion capacitance and resistance models
Gate leakage models (in BSIM 4)
Diffusion Capacitance Models
The p–n junction between the source or drain diffusion and the body forms a diode. We
have seen that the diffusion capacitance determines the parasitic delay of a gate and
depends on the area and perimeter of the diffusion.
The SPICE models also should contain parameters CJ, CJSW, PB, PHP, MJ, and
MJSW.
The diffusion area and perimeter are also used to compute the junction leakage current.
However, this current is generally negligible compared to sub threshold leakage in
modern devices.
2. Explain briefly about analysis techniques using Spice Tutorial.
Transistor DC Analysis
One of the first steps in becoming familiar with a new CMOS process is to look at the I-V
characteristics of the transistors.
Figure shows test circuits for a unit (4/2 ) nMOS transistor in a 65 nm process at
VDD 1.0 V.
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Eg : .dc Vds 0 1.0 0.05
Inverter Transient Analysis
Figure 8.7 shows the step response of an unloaded unit inverter, annotated with
propagation delay and 20–80% rise and fall times. This is convenient for chips designed
using scalable rules, but is not normally done in commercial processes with micron-
based rules.
Eg : .tran 0.1ps 80ps
Reliability
Designing reliable CMOS chips involves understanding and addressing the potential
failure modes. reliability (hard errors) that causes integrated circuits to fail permanently
includes.
o Oxide wearout
o Interconnect wearout
o Overvoltage failure
o Latchup
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Oxide Wearout
As gate oxides are subjected to stress, they gradually wear out, causing the
threshold voltage to shift and the gate leakage to increase.
The circuit fails because transistors become too slow, mismatches become too
large, or leakage currents become too great.
Processes generally specify a maximum operating voltage to ensure oxide wear
out effects
i) Hot Carriers
As transistors switch, high-energy (“hot”) carriers are occasionally injected into
the gate oxide and become trapped there.
Electrons have higher mobility and account for most of the hot carriers.
The damaged oxide changes the I-V characteristics of the device, reducing
current in nMOS transistors and increasing current in pMOS transistors.
Damage is maximized when the substrate current Isub is large, which typically
occurs when nMOS transistors see a large Vds while ON. Therefore, the problem
is worst for inverters and NOR gates with fast rising inputs and heavily loaded
outputs and for high power supply voltages.
Hot carriers cause circuit wear out as nMOS transistors become too slow. They
can also cause failures of sense amplifiers and other matched circuits .
ii) Negative Bias Temperature Instability
When an electric field is applied across a gate oxide, traps ar develop at the Si-
SiO2 interface.
The threshold voltage increases as more traps form, reducing the drive current
until the circuit fails
iii) Time-Dependent Dielectric Breakdown
As an electric field is applied across the gate oxide, the gate current gradually
increases. This phenomenon is called time-dependent dielectric breakdown
(TDDB) and the elevated gate current is called stress-induced leakage current
(SILC). 7.3.3
Interconnect Wearout
High currents flowing through wires eventually can damage the wires. For wires carrying
unidirectional (DC) currents, electromigration is the main failure mode. For wires carrying
bidirectional (AC) currents, self-heating is the primary concern.
Electromigration
High current densities lead to an “electron wind” that causes metal atoms to
migrate over time. Such electromigration causes wearout of metal interconnect
through the formation of voids
The electromigration properties also depend on the grain structure of the metal
film.
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Electromigration depends on the current density.
It is more likely to occur for wires carrying a DC current where the electron wind
blows
in a constant direction than for those with bidirectional currents.
Electromigration current limits are usually expressed as a maximum Jdc.
Ea is the activation energy
Self-Heating
While bidirectional wires are less prone to electromigration, their current density is still
limited by self-heating. High currents dissipate power in the wire.
Because the surrounding oxide or low-k dielectric is a thermal insulator, the wire
temperature can become significantly greater than the underlying substrate.
Hot wires exhibit greater resistance and delay.
self-heating may cause temperature-induced electromigration problems in the
bidirectional wires.
Self-heating is dependent on the root-mean-square (RMS) current density. This can be
measured with a circuit simulator or calculated as
To avoid excessive self-heating, the wire and load capacitance should be less than
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3. Write a brief note on Soft Errors.
Soft errors are random nonrecurring errors triggered by radiation striking a chip. Alpha
particles, emitted by the decay of trace uranium and thorium impurities in packaging
materials.
They have been greatly reduced by using highly purified materials.
High-energy neutrons from cosmic radiation account for most soft errors in many
systems
When a neutron strikes a silicon atom, it can induce fission, shattering the atom into
charged fragments that continue traveling through the substrate. These ions leave a trail
of electron-hole pairs behind as they travel through the lattice.
Figure shows the effect of an ion striking a reverse-biased p-n junction .
The ion leaves a cylindrical trail of electrons and holes in its wake, with a radius of less
than a micron.
Within tens of picoseconds, the electric field at the junction collects the carriers into a
funnel-shaped depletion region.
Over the subsequent nanoseconds, electrons diffuse into the depletion region.
Depending on the type of ion, its energy, its trajectory, and the geometry of the p-n
junction, up to several hundred femtocoulombs of charge may be collected onto the
junction.
The spike of current is called a single-event transient (SET).
If the collected charge exceeds a critical amount, Qcrit, it may flip the state of the node,
causing a fault called a single-event upset (SEU). Failures caused by such faults are
called soft errors.
Overvoltage Failure
Tiny transistors can be easily damaged by relatively low voltages. Overvoltage may be triggered
by excessive power supply transients or by electrostatic discharge (ESD) from static electricity
entering the I/O pads, which can cause very large voltage and current transients Overvoltage at
the gate node accelerates the oxide wearout. In extreme cases, it can cause breakdown and
arcing across the thin dielectric, destroying the device.
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4. How Latchup occurs ? Explain about latchup prevention technique
The phenomenon, called latchup, occurs when parasitic bipolar transistors formed by the
substrate, well, and diffusion turn ON. With process advances and proper layout procedures,
latchup problems can be easily avoided.
In addition to the expected nMOS and pMOS transistors, the schematic depicts a circuit
composed of an npn-transistor, a pnp-transistor, and two resistors connected between the
power and ground rails
The npn transistor is formed between the grounded n-diffusion source of the nMOS transistor,
the p-type substrate, and the n-well. The resistors are due to the resistance through the
substrate or well to the nearest substrate and well taps. The cross-coupled transistors form a
bistable silicon-controlled rectifier (SCR).
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latchup prevention is easily accomplished by
minimizing Rsub and Rwell.
Placing substrate and well taps close to each transistor.
Placing a tap adjacent to every source connected to VDD or GND. voltages can ring
below GND or above VDD, forward biasing the
guard rings should be used to collect the current . Also, processes with VDD –2 V
are immune to latchup because the two parasitic transistors.
Supply Voltage
Systems are designed to operate at a nominal supply voltage, but this voltage may vary for
many reasons including tolerances of the voltage regulator, IR drops along supply rails, and
di/dt noise.
Temperature
As temperature increases, drain current decreases.
The junction temperature of a transistor is the sum of the ambient temperature and the
temperature rise caused by power dissipation in the package.
5. Write a note on Process Variation [AUC NOV 2007]
Devices and interconnect have variations in film thickness, lateral dimensions, and doping
concentrations .
Process variations can be classified as follows:
Lot-to-lot (L2L)
Wafer-to-wafer (W2W)
Die-to-die (D2D), inter-die, or within-wafer (WIW)
Within-die (WID) or intra-die
Wafers are processed in batches called lots. A lot processed after a furnace has been shut
down and cleaned may behave slightly differently than the lot processed earlier. One wafer may
be exposed to an ion implanter for a slightly different amount of time than another,causing W2W
threshold voltage variation. A die near the edge of the wafer may etch slightly differently than a
die in the center, causing D2D channel length variations.
6. Explain briefly about Design Corners involved in CMOS Process. [AUC NOV 2010
,2011]
From the designer’s point of view, the collective effects of process and environmental variation
can be lumped into their effect on transistors: typical (also called nominal), fast, or slow.
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Table 7.2 lists a number of design corners.
The wires linking transistors together are called interconnect and play a major role in the performance of modern systems. 7. Write short notes on Line Parasitics. This is representative of an interconnect line that is described by a width w, and has a distance of d. The material layer itself has a height (or thickness) h. Parasitic electrical elements include resistance and capacitance; although the wire also
has inductance associated with it, we usually do not encounter magnetic effects at local circuit level.1 Our program at this point is two-fold. First, we want to determine the values of the parasitic elements that are introduced by the interconnect. Once these have been calculated, we can then proceed to evaluate their effects on the performance.
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Line Resistance
The resistance of the line from one end to the other is given by the standard equation
Where ρ is the resistivity in units [Ω –cm] and h w is the cross sectional area of the line.
The sheet resistance Rs is defined by
Once Rs is known , the total resistance of a line that has a width W and spans a distance d is given by
Where n is the number of squares of dimensions (w *w)
Line Capacitance The capacitance of an interconnect line can be the limiting factor in high-
speed signal transmission. Consider the cross-sectional geometry shown in Figure 10.3(a).
Most formulations are based on the capacitance per unit length c’ with units of farads per
centimeter such that the total capacitance of the line in farads is given by
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8. Explain briefly about Interconnect Modeling technique. [ AUC APR 2010 , Nov
2012]
The simplest expression for ‘c’ is obtained from the parallel –plate capacitor as
in units of F/cm.
A more accurate empirical expression is given by
To analyze the effects of the line parasitic , we assume that v2(t) can be approximated as an exponential and use the elmore formula to calculate the time constants . For a high to low transition
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9. Describe the RC ladder netwok analysis used in interconnect modeling.
RC Ladder Network
The next level of modeling for the interconnect is to replace the single RC lumped
element model by a multistage RC ladder that has m rungs. Defining the individual
element values by
makes us to construct the desired ladder network.
The equivalent circuits are as shown
With m=3 ,the delay time constant is
With m=4 ,the delay time constant is
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With m=5 ,the delay time constant is
From the series ,the ladder with m-rungs has a time constant of
that represents time delay due to line parasitic.
Substituting Rm and Cm into the equation we get
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11. Explain briefly about Coupling Capacitors and Crosstalk [AUC NOV 2013]
An empirical formula that provides a reasonable estimate for the coupling capacitance Cc per unit length is given by
in units of F/cm which can be applied directly to the geometry. The total coupling capacitance in farads of a line that has a length d is calculated from
this shows that Cc increases as the separation distance S decreases.
12. Write a note on circuit –level modeling [ AUC NOV 2009 , APR 2012]
Let us analyze the network by writing the time –domain node equation as follows
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13. Explain briefly about Crosstalk that occurs in CMOS process