UNIT-I NUMBER SYSTEM AND CODES

• A continuous varying signal is called Analog signal. Whereas which can

have only to discrete value i.e., [0,1] called Digital signal.

• An electronic circuit that is designed for two state of operation is called

digital circuit.The two states are ON state (1), OFF state (0)

• Number Systems: The study of number system is required to understand the

way digital computers are operated.

Types of Number Systems

Some of the important types of number system are 1) Decimal Number System,

2) Binary Number System, 3) Octal Number System, 4) Hexa decimal Number

System

1. Decimal Number Systems

The number system is having digit 0, 1, 2, 3, 4, 5, 6, 7, 8, 9; this number

system is known as a decimal number system because total ten digits are

involved. The base of the decimal number system is 10.

2. Binary Number Systems

The modern computers do not process decimal number; they work with another

number system known as a binary number system which uses only two digits 0

and1.The base of binary number system is 2 because it has only two digit 0 and

1.The digital electronic equipment’s are works on the binary number system and

hence the decimal number system is converted into binary system.

3. Octal Numbers

The number system is having digit 0, 1, 2, 3, 4, 5, 6, 7; this number system is

known as an octal number system because total eight digits are involved. The

base of the octal number system is 8.

4. Hexadecimal Numbers

These numbers are used extensively in microprocessor work. The hexadecimal

number system has a base of 16, and hence it consists of the following sixteen number of digits0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, F.

The size of the hexadecimal is much shorter than the binary number which makes them easy to write and remember. Let 0000 to 000F representing hexadecimal

numbers from zero to fifteen, then 0010, 0011, 0012, etc. Will represent sixteen, seventeen, eighteen, etc. till 001F which represent thirty open and so on.

Decimal Binary Octal Hexadecimal

0 0000 0 0

1 0001 1 1

2 0010 2 2

3 0011 3 3

4 0100 4 4

5 0101 5 5

6 0110 6 6

7 0111 7 7

8 1000 10 8

9 1001 11 9

10 1010 12 A

11 1011 13 B

12 1100 14 C

13 1101 15 D

14 1110 16 E

15 1111 17 F

Binary Number Conversion

• Binary to Octal

An easy way to convert from binary to octal is to group binary digits into sets of

three, starting with the least significant (rightmost) digits.

Binary: 11100101 = (11 100 101 )2

011 100 101 ← the most significant digits with

zeros if necessary, to complete a

group of three.

Binary = 011 100 101

Octal = 3 4 5 = 345 oct

• Binary to Hexadecimal

An equally easy way to convert from binary to hexadecimal is to group binary

digits into sets of four, starting with the least significant (rightmost) digits.

Binary: 11100101 = 1110 0101

Then, look up each group in a table:

Binary: 0000 0001 0010 0011 0100 0101 0110 0111

Hexadecimal: 0 1 2 3 4 5 6 7

Binary: 1000 1001 1010 1011 1100 1101 1110 1111

Hexadecimal: 8 9 A B C D E F

Binary = 1110 0101

Hexadecimal = E 5 = E5 hex

• Binary to Decimal

Example-1 − Convert binary number 11001010 into decimal number. Since there is no binary point here and no fractional part. So,

Binary to decimal is,

= (11001010)2

= 1x27+1x26+0x25+0x24+1x23+0x22+1x21+0x20

= 128+64+0+0+8+0+2+0

= (202)10

Example-2 − Convert binary number 1010.1011 into decimal number. Since there is a binary point here with fractional part. So,

Binary to decimal is,

= (1010.1011)2

= 1x23+0x22+1x21+0x20+1x2-1+0x2-2+1x2-3+1x2-4

= 8+0+2+0+0.5+0+0.125+0.0625

= (10.6875)10

Octal Number Conversion

• Octal to Binary: -Converting from octal to binary is as easy as converting

from binary to octal. Simply look up each octal digit to obtain the equivalent

group of three binary digits.

Octal: 0 1 2 3 4 5 6 7

Binary: 000 001 010 011 100 101 110 111

• Octal to Hexadecimal: - When converting from octal to hexadecimal, it is

often easier to first convert the octal number into binary and then from

binary into hexadecimal. For example, to convert 345 octal into hex:

Octal = 3 4 5

Binary = 011 100 101 = (011100101)2

Drop any leading zeros or pad with leading zeros to get groups of four binary digits

(bits):

Binary 011100101 = 1110 0101→→

• Octal to Decimal

The conversion can also be performed in the conventional mathematical way, by

showing each digit place as an increasing power of 8.

Example 1: (345)8 = (229)10

(345)8 = (3 * 82) + (4 * 81) + (5 * 80) = (3 * 64) + (4 * 8) + (5 * 1) = (229)10

Octal = 3 4 5

Binary = 011 100 101 = 011100101 binary

Binary = (1110 0101)2

Hexadecimal = E 5 = (E5)16

Hexadecimal Number Conversion

• Hexadecimal to Binary

Converting from hexadecimal to binary is as easy as converting from binary to

hexadecimal. Simply look up each hexadecimal digit to obtain the equivalent

group of four binary digits.

Hexadecimal: 0 1 2 3 4 5 6 7

Binary: 0000 0001 0010 0011 0100 0101 0110 0111

Hexadecimal: 8 9 A B C D E F

Binary: 1000 1001 1010 1011 1100 1101 1110 1111

Hexadecimal = (A 2 D E )16

Binary = 1010 0010 1101 1110 = (1010001011011110)2

• Hexadecimal to Octal

When converting from hexadecimal to octal, it is often easier to first convert the

hexadecimal number into binary and then from binary into octal. For example, to

convert A2DE hex into octal:

Hexadecimal = (A 2 D E )16

Binary = 1010 0010 1101 1110 = (1010001011011110)2

Add leading zeros or remove leading zeros to group into sets of three binary digits.

Binary: 1010001011011110 = 001 010 001 011 011 110

Binary = 001 010 001 011 011 110

Octal = 1 2 1 3 3 6 = (121336)8

Hexadecimal to Decimal: -

Converting hexadecimal to decimal can be performed in the conventional

mathematical way, by showing each digit place as an increasing power of 16.

Hexadecimal: 0 1 2 3 4 5 6 7

Decimal: 0 1 2 3 4 5 6 7

Hexadecimal: 8 9 A B C D E F

Decimal: 8 9 10 11 12 13 14 15

A2DE hexadecimal:

= ((A) * 163) + (2 * 162) + ((D) * 161) + ((E) * 160)

= (10 * 163) + (2 * 162) + (13 * 161) + (14 * 160)

= (10 * 4096) + (2 * 256) + (13 * 16) + (14 * 1)

= 40960 + 512 + 208 + 14

= 41694 decimal

• Number System Relationship

The following table depicts the relationship between decimal, binary, octal and

hexadecimal number systems.

HEXADECIMAL DECIMAL OCTAL BINARY

0 0 0 0000

1 1 1 0001

2 2 2 0010

3 3 3 0011

4 4 4 0100

5 5 5 0101

6 6 6 0110

7 7 7 0111

8 8 10 1000

9 9 11 1001

A 10 12 1010

B 11 13 1011

C 12 14 1100

D 13 15 1101

E 14 16 1110

F 15 17 1111

DECIMALNumber Conversion

• Decimal to Binary:-

The remainders are to be read from bottom to top to obtain the binary equivalent.

4310 = 1010112

• Decimal to Octal:-

Reading the remainders from bottom to top,

47310 = 7318

Decimal to Hexadecimal:-

Reading the remainders from bottom to top we get,

42310 = 1A716

Binary Addition

It is a key for binary subtraction, multiplication, division. There are four rules of

binary addition.

In fourth case, a binary addition is creating a sum of (1 + 1 = 10) i.e. 0 is written in

the given column and a carry of 1 over to the next column.

Example − Addition

Binary Subtraction

Subtraction and Borrow, these two words will be used very frequently for the

binary subtraction. There are four rules of binary subtraction.

Example − Subtraction

Binary system complements

As the binary system has base r = 2. So, the two types of complements for the binary

system are 2's complement and 1's complement.

1's complement

The 1's complement of a number is found by changing all 1's to 0's and all 0's to 1's.

This is called as taking complement or 1's complement. Example of 1's Complement

is as follows.

2's complement

The 2's complement of binary number is obtained by adding 1 to the Least

Significant Bit (LSB) of 1's complement of the number.

2's complement = 1's complement + 1

Example of 2's Complement is as follows.

CODES:-

1. Binary Coded Decimal (BCD) code

In this code each decimal digit is represented by a 4-bit binary number. BCD is a

way to express each of the decimal digits with a binary code. In the BCD, with four

bits we can represent sixteen numbers (0000 to 1111). But in BCD code only first

ten of these are used (0000 to 1001). The remaining six code combinations i.e. 1010

to 1111 are invalid in BCD.

Advantages of BCD Codes

• It is very similar to decimal system.

• We need to remember binary equivalent of decimal numbers 0 to 9 only.

Disadvantages of BCD Codes

• The addition and subtraction of BCD have different rules.

• The BCD arithmetic is little more complicated.

• BCD needs a greater number of bits than binary to represent the decimal

number. So, BCD is less efficient than binary.

Binary to BCD Conversion

• Example − convert (11101)2 to BCD.

Binary Number − 111012

Calculating Decimal Equivalent −

Step Binary Number Decimal Number

Step 1 111012 ((1 × 24) + (1 × 23) + (1 × 22) + (0 × 21) + (1 × 20))10

Step 2 111012 (16 + 8 + 4 + 0 + 1)10

Step 3 111012 2910

Binary Number − 111012 = Decimal Number − 2910

→Calculating BCD Equivalent. Convert each digit into groups of four binary

digits equivalent.

Step Decimal

Number

Conversion

Step 1 2910 00102 10012

Step 2 2910 00101001BCD

Result

(11101)2 = (00101001)BCD

BCD to Binary Conversion

Example − convert (00101001)BCD to Binary.

BCD Number − (00101001)BCD

Step BCD Number Conversion

Step 1 (00101001)BCD 00102 10012

Step 2 (00101001)BCD 210 910

Step 3 (00101001)BCD 2910

BCD Number − (00101001)BCD = Decimal Number − 2910

2. Gray Code: -

It is the non-weighted code and it is not arithmetic codes. That means there are no

specific weights assigned to the bit position. It has a very special feature that, only

one bit will change each time the decimal number is incremented as shown in fig.

As only one-bit changes at a time, the gray code is called as a unit distance code.The

gray code is a cyclic code. Gray code cannot be used for arithmetic operation.

Application of Gray code

• Gray code is popularly used in the shaft position encoders.

• A shaft position encoder produces a code word which represents the angular

position of the shaft.

3. Excess-3 code

The Excess-3 code is also called as XS-3 code. It is non-weighted code used to

express decimal numbers. The Excess-3 code words are derived from the 8421 BCD

code words adding (0011)2 or (3)10 to each code word in 8421. The excess-3 codes

are obtained as follows −

ExampleBCD to Excess-3

Steps

• Step 1 -- Convert BCD to decimal.

• Step 2 -- Add (3)10 to this decimal number.

• Step 3 -- Convert into binary to get excess-3 code.

Example − convert (0110) BCD to Excess-3.

Step 1 − Convert to decimal

(0110)BCD = 610

Step 2 − Add 3 to decimal

(6)10 + (3)10 = (9)10

Step 3 − Convert to Excess-3

(9)10 = (1001)2

Result

(0110)BCD = (1001)XS-3

Excess-3 to BCD Conversion

Steps

• Step 1 -- Subtract (0011)2 from each 4 bit of excess-3 digit to obtain the

corresponding BCD code.

Example − convert (10011010) XS-3 to BCD.

EXS-3 number = 1 0 0 1 1 0 1 0

Subtract (0011)2 = 1 0 0 1 0 1 1 1

--------------------

BCD = 0 1 1 0 0 1 1 1

Result

(10011010) XS-3 = (01100111) BCD

UNIT -II BOOLEAN ALGEBRA AND THEOREMS

Boolean Laws

There are six types of Boolean Laws.

Commutative law

Any binary operation which satisfies the following expression is referred to as

commutative operation.

Commutative law states that changing the sequence of the variables does not have

any effect on the output of a logic circuit.

Associative law

This law states that the order in which the logic operations are performed is

irrelevant as their effect is the same.

Distributive law

Distributive law states the following condition.

AND law

These laws use the AND operation. Therefore they are called as AND laws.

OR law

These laws use the OR operation. Therefore, they are called as OR laws.

INVERSION law :- This law uses the NOT operation. The inversion law states that

double inversion of variable results in the original variable itself.

BASIC LOGIC GATES:-

Logic gates are the basic building blocks of any digital system. It is an electronic

circuit having one or more than one input and only one output. The relationship

between the input and the output is based on a certain logic. Based on this, logic

gates are named as AND gate, OR gate, NOT gate etc.

AND Gate

A circuit which performs an AND operation is shown in figure. It has n input (n >=

2) and one output.

Logic diagram & Truth Table

OR Gate

A circuit which performs an OR operation is shown in figure. It has n input (n >=

2) and one output.

Logic diagram & Truth Table

NOT Gate

NOT gate is also known as Inverter. It has one input A and one output Y.

Logic diagram & Truth Table

NAND Gate

A NOT-AND operation is known as NAND operation. It has n input (n >= 2) and

one output.

Logic diagram & Truth Table

NOR Gate

A NOT-OR operation is known as NOR operation. It has n input (n >= 2) and one

output.

Logic diagram & Truth Table

XOR Gate

XOR or Ex-OR gate is a special type of gate. It can be used in the half adder, full

adder and subtractor. The exclusive-OR gate is abbreviated as EX-OR gate or

sometime as X-OR gate. It has n input (n >= 2) and one output.

Logic diagram & Truth Table

XNOR Gate

XNOR gate is a special type of gate. It can be used in the half adder, full adder and

subtractor. The exclusive-NOR gate is abbreviated as EX-NOR gate or sometime

as X-NOR gate. It has n input (n >= 2) and one output.

Logic diagram & Truth Table

UNIT-III COMBINATIONAL LOGIC CIRCUITS

The combinational logic circuits can be classified into various types

based on

Thepurpose of u sage, such as arithmetic & logical functions, data transmission,

and code converters. To solve the arithmetic and logical functions we generally use

adders, subtractors, and comparators which are generally realized by combining

various logic gates called as combinational logic circuits. Similarly, for data

transmission, we use multiplexers, demultiplexers, encoders, and decoders which

are also realized using combinational logic

Half Adder

So, by using one XOR gate and one AND gate we can easily design a half adder,

as shown below.

Fig 4.1.1 The Half Adder

Truth Table for Half Adder

K-map for Half Adder

Now from this truth table we can draw K-map for carries and sums separately.

For above K-maps we get,

Hence, the logical design of Half Adder would be

Although from truth table it is clearly seen that carry (C) column signifies AND

operation and sum (S) column signifies XOR operation between input variables

but till we went through K-map as it is general practice to do so for more

complex binary logic operations.

Full Adder

Full adder is a conditional circuit which performs full binary addition that means

it adds two bits and a carry and outputs a sum bit and a carry bit.

Any bit of augend can either be 1 or 0 and we can represent with variable A,

similarly any bit of addend we represent with variable B. The carry after addition

of same significant bit of augend and addend can represent by C. Hence true table

for all combinations of A, B and C is as follows,

From the above table, we can draw K-map for sum (s) and final carry (Cout).

Hence, from K-maps,

Binary Parallel Adder:-

A full binary adder performs addition of any single bit of one binary number,

same significant or same position bit of another binary numbers and carry comes

from result of addition of previous right side bits of both binary numbers. But a

single full adder cannot add more than one bits binary number instantly. This

can be done only by connecting as many full adders as the number of bits of the

binary numbers whose addition is to be performed. This parallel combination of

full adders which performs addition of specific bits binary numbers is called

binary parallel adder. For adding two 4 bit binary numbers we have to connect 4

full adders to make 4 bit parallel adder.

The inter connection of 4 full adder in 4bit parallel adder is shown below,

Let us examine the justification of the above circuit by taking an example of

addition of two 4 bit binary numbers.

Let us add 1011 with 1101.

As there is no previous carry C0 = 0.

Therefore, final result of the addition would be

MULTIPLEXERS:

The term multiplex means “many into one”. A digital multiplexer is a

combinational circuit that selects binary information from one of the many

input channels and transmits to a single output line. That is why the

multiplexers are also called data selectors. Fig (a) shows the block diagram of a

multiplexer.

2:1 MULTIPLEXER:A 2:1 multiplexer has two input lines (I0, I1), one

selects line (S) and one output line(Y).

Truth table for 2:1 Multiplexer:

Select

line

(S)

Output

(Y)

0 I2

1 I1

The Boolean expression for the output is Y = Io𝑆̅+I1S

From the truth table,

• When S=0, the input I0 is selected and is transmitted through the output

line (Y),

Y = I0.1+I1.0 = I0

• When S=1, the input I1 is selected and is transmitted through the output

line (Y),

Y = I0.0+I1.1 = I1

4:1 MULTIPLEXER: A 4:1 multiplexer has four input lines (I0, I1, I2, and I3), one

output line(Y) and two select lines (S0, S1).

Truth table for 4:1 Multiplexer:

Select lines Out put

S1 S0 (Y)

0 0 I0

0 1 I1

1 0 I2

1 1 I3

The Boolean expression for the output is

𝑌 = 𝑆0̅𝑆1̅𝐼0 + 𝑆0𝑆1̅𝐼1 + 𝑆1𝑆0̅𝐼2+ 𝑆0𝑆1𝐼3

From the truth table,

• When S1=0 and S0=0, the input I0 will be selected and is transmitted

through the output line (Y).

• When S1=0 and S0=1, the input I1 will be selected and is transmitted

through the output line (Y).

• When S1=1 and S0=0, the input I2 will be selected and is transmitted

through the output line (Y).

• When S1=1 and S0=1, the input I3 will be selected and is transmitted

through the output line (Y).

Circuit Diagram:

De-multiplexer: (DATA DISTRIBUTOR)

A De-multiplexer is a combinational circuit with one input and many outputs. It is

abbreviated as DEMUX. The selection of a particular output line is controlled by a

set of selection lines. De-multiplexer is also called as a data distributor. The block

diagram of de-multiplexer is shown in the figure.

1:2 De- multiplexer:

The term De-multiplexer means “one into many”. A 1:2 de- multiplexer has one

input lines (I), one select line (S) and two output lines (Y0, Y1).

Truth table for 1:2 De Multiplexer:

Select line

Output lines

(S) Y1 Y0

0 0 I

1 I 0

From the truth table,

• When S=0, the input Iis connected to output line Y0.

• When S=1, the input Iis connected to output line Y1.

The Boolean expression for the output is Y0 = I 𝑆̅

Y1 = I S

1:4 Demultiplexer

The 1:4 Demultiplexer has one input line (I), two select lines (S0 , S1) and four

output lines (Y0, Y1, Y2, and Y3 ). The 1:4 demultiplexers are shown in figure.

Truth table for 4:1 Multiplexer:

From the above Truth table, we can directly write the Boolean functions for each

output as

Y3=𝑆1𝑆0𝐼

Y2=𝑆1𝑆0̅𝐼

Y1=𝑆1̅𝑆0𝐼

Y0=𝑆1̅𝑆0̅𝐼

Selection

Inputs

Outputs

S1 S0 Y3 Y2 Y1 Y0

0 0 0 0 0 I

0 1 0 0 I 0

1 0 0 I 0 0

1 1 I 0 0 0

The circuit diagram of 1x4 De-Multiplexer is shown in the following figure.

From the truth table,

• When S1=0 and S0=0 the input Iis connected to output Y0.

• When S1=0 and S0=1 the input Iis connected to output Y1.

• When S1=1 and S0=0 the input Iis connected to output Y2.

• When S1=1 and S0=1 the input Iis connected to output Y3.

ENCODER: An encoder has 2n input data lines into an ‘n’ output data lines. The

block diagram of encoder is shown in fig.

8 line to 3 line Encoder:

An 8line to 3line Encoder has eight inputs, Y7 to Y0 and three outputs A2, A1 & A0.

An 8 to 3 encoder is also called Octal to binary encoder.

The Truth table of octal to binary encoder is shown below.

Inputs Outputs

Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 A2 A1 A0

0 0 0 0 0 0 0 1 0 0 0

0 0 0 0 0 0 1 0 0 0 1

0 0 0 0 0 1 0 0 0 1 0

0 0 0 0 1 0 0 0 0 1 1

0 0 0 1 0 0 0 0 1 0 0

0 0 1 0 0 0 0 0 1 0 1

0 1 0 0 0 0 0 0 1 1 0

1 0 0 0 0 0 0 0 1 1 1

From Truth table, we can write the Boolean functions for each output as

A2=Y7+Y6+Y5+Y4

A1=Y7+Y6+Y3+Y2

A0=Y7+Y5+Y3+Y1

The circuit diagram of octal to binary encoder is shown in the following figure.

DECODER: A decoder is a logic device that converts an n bit binary input code

into 2n output lines such that only one output line is activated for each one of the

possible combinations of inputs. Figure shows the block diagram of a decoder.

3line to 8 line Decoder:

An 3-to-8 line decoder has three input lines A, B & Cand eight output lines Y0, Y1,

Y2, Y3, Y4, Y5, Y6 & Y7.

When the inputs A=0, B=0 and C=0, the output Y0 will be selected and the

expression is

Y0 = �̅��̅�𝐶̅, Y1 = �̅��̅� C,

Y2 = �̅� B 𝐶̅ Y3 = �̅� B C,

Y4 = 𝐴 �̅��̅� Y5 = �̅��̅� C,

Y6 = 𝐴 𝐵𝐶̅ Y7 = 𝐴 𝐵 𝐶,

I C LOGIC FAMILIES

Based on the technology used, we can have four basic logic families.

They are:

1. RTL – Resistor transistor logic family.

2. DTL – Diode transistor logic family.

3. TTL – Transistor Transistor logic family.

4. CMOS – Complementary metal oxide semiconductor logic family.

Characteristics of Logic Families

The main characteristics of Logic families include:

• Speed

• Fan-in

• Fan-out

• Noise Immunity

• Power Dissipation

Speed: Speed of a logic circuit is determined by the time between the application

of input and change in the output of the circuit.

Fan-in: It determines the number of inputs the logic gate can handle.

Fan-out: Determines the number of circuits that a gate can drive.

Noise Immunity: Maximum noise that a circuit can withstand without affecting the

output.

Power: When a circuit switches from one state to the other, power dissipates.

RTL FAMILY:

RTL is a type of digital circuit built using resistors as the input network and bipolar

junction transistors (BJTs) as switching devices. The circuit consists of four

resistors and one transistor. Here the transistor acts as an inverter.

WORKING:

1. When both inputs are zero (A=0, B=0) the input to the transistor is zero.

2. Similarly when one of the inputs is high (logic 1) the input to the transistor is

high. So, the output Q is low or logic 0.

3. On the same lines when both the inputs are high the input to the transistor is

high (logic 1). So, the output of the transistor is low or logic 0.

4. This the working of the two input NOR gate which is also shown in the truth

table 1.

ADVANTAGES:

1. Less number of transistors.

DISADVANTAGES:

1. High power dissipation,

2. Low fan in.

DIODE TRANSISTOR LOGIC: DTL is somewhat more complex than RTL

but because of greater fan out and improved noise margins it has replaced RTL. Its

main drawback is slower speed, because of this it was modified and emerged as

TTL, which is the most popular logic family today.

WORKING:

1. When the inputs A =0 and B=0 (low), the current through the resistor to the

R3 is 0. i.e., the input to the transistor T is 0.The transistor is in off state and

the output at Q is high (logic 1).

2. When A= 1 and B=0, the current through the resistor to the R3 is 0.i.e., the

input to the transistor is zero or the transistor is in cut-off state. So the

output at Q is high or at logic 1.

3. When the inputs A =1 and B=1, the current through the resistor to the R3 is

1. i.e., the input of the transistor will be at logic 1. i.e., the transistor is in

conducting state. Hence the output at Q is low or at logic 0. This working of

NAND gate is shown in truth table.

Transistor – Transistor Logic (TTL).

In transistor-transistor logic (TTL) or T2L logic family, logic gates and other

digital circuits are made using bipolar junction transistors and resistors. This logic

family is the most commonly used logic family because high speed capability. It is

the basic extension of the DTL logic family, but has higher noise immunity and

output current capability.fig shows the two input TTL NAND gates.

A two input TTL NAND is shown above. A and B are two inputs while Y is

the output.

Operation:

1. When A =0 and B =0, Transistor T1 is saturated, T2 and T4 are cut off. Then

the transistor T3 will start conducting. Hence the output is high (Q =1).

2. When A =1 and B =1, then T1 & T3 are cut off (off state), T2 and T4 are ON

state (saturation region). Hence the output is low (Q =0).

3. The working of the NAND gate is in accordance with the truth table.

ADVANTAGES:

1. Fastest saturated logic family.

2. Good noise immunity.

1. Compatible with other logic families.

2. Commercial and military versions are available.

3. Good fan out.

4. Low output impedance.

5. Almost all functions are available.

Disadvantages of TTL logic families:

1. Because of isolation problem, VLSI circuits are not possible.

2. Power dissipation is much higher.

CMOS NAND gate:-

The circuit of CMOS NAND gate is shown in figure.

T1 and T2 are n-channel MOSFETs while T3 and T4 are p-channel MOSFETs.

When both inputs A & B are HIGH, then T1 & T2 are ON while T3 & T4 are OFF.

Hence, output is connected to GND i.e. LOW.

If either input is LOW, then either T3 or T4 is ON, connecting output is +Vcc i.e.

HIGH.

FLIP FLOPS

• Flip-On, Flop-Off

• It is a sequential device which stores 1-bit binary (information) data (0 or

1).

• It is the smallest memory element.

• It has two different outputs- Normal and complemented output.

• The various types of Flip Flops are

• 1)Basic S-R flip flop (Set Reset flip flop),

2) Clocked S-R flip flop,

3) D- flip flop (Delay)

4) J-K flip flop

5) T- flip flop (Toggle),

6) Master-Slave flip flop.

If we apply input signal and clock pulse to the present state of a flip flop, the output

will be the next state of the flip flop.

I/P Normal O/p

Com complemented O/p

Clock pulse

Flip flop are generally designed using NAND & NOR gates.

Basic S-R flip flop (Set Reset flip flop):

The S and R in SR flip – flop means ‘SET’ and ‘RESET’ respectively. Hence it is

also called Set – Reset flip – flop. SR flip flop can be designed by cross coupling

of two NAND gates. The circuits of SR flip – flop using NAND gates is shown in

below figure.

Circuit Diagram:

Truth Table:

Operation

S.N. Condition Operation

1 S = 0, R = 0 If S = 0, R = 0 ,

It is an invalid state because the values of both Q

and �̅� are 1.This state must be avoided.

2 S = 0, R = 1 If S = 0, R = 1 → Q = 0 ,�̅�=1

This state is known as the RESET state.

3 S = 1, R = 0 S = 1, R = 0 → Q = 1 , �̅�=0

This state is also called the SET state.

4 S = 1, R = 1 When both the SET and RESET inputs are high,

then the output remains in previous state i.e. it

holds the previous data.

Invalid or RACING or forbidden

Clocked SR Flip – Flops

The circuit of clocked SR flip – flop using NAND gates is shown below

This circuit is formed by adding two NAND gates to NAND based SR flip – flop.

A clock pulse is given as input to both the extra NAND gates. the truth table for

this flip – flop is shown below.

1. In SR flip flop S = 1, R = 0 → Q = 1, �̅�=0

This state is also called the SET state.

2. If S = 0, R = 1 → Q = 0, �̅�=1

This state is known as the RESET state. .

3. If R=1, S=1→ Q = 1, �̅�=1

Is a forbidden condition which must be avoided. Since SR flip flop is modify

the design to eliminate the possibility of RACE condition. The result is new

flip flop know as D-flip flop

Delay Flip Flop / D Flip Flop

D flip – flops are also called as “Delay flip – flop” or “Data flip – flop”. They are

used to store 1 – bit binary data. They are one of the widely used flip – flops in

digital electronics. A D flip – flop is constructed by modifying an SR flip – flop.

The S input is given with D input and the R input is given with inverted D input.

D flip – flop has two inputs , a clock (CLK) input and a data (D) input and two

outputs; one is main output represented by Q and the other is complement of Q

represented by Q’.The major drawback of SR flip – flop is the race around

condition which in D flip – flop is eliminated. The circuit diagram of D flip – flop

is shown in below figure.

Truth Table for the D-type Flip Flop

Operation:

S.N. Condition Operation

1 Clock = 0 No change in output.

2 Clock = 1 and D = 0 If CLK= 1 and D = 0, This is the reset

condition.

3 Clock = 1 and D = 1 If CLK = 1 and D = 1, This is the set condition.

J-K FLIP FLOP:

JK flip – flop is a modified version of SR flip – flop. The design of the JK flip –

flop is such that the three inputs to one NAND gate are J, clock signal along with a

feedback signal from Q’ and the three inputs to the other NAND are K, clock

signal along with a feedback signal from Q. This arrangement eliminates the

indeterminate state in SR flip – flop.

Truth Table: The truth table of JK flip – flop is shown below.

Operation

• Case 1: When both the inputs J and K are LOW, then Q returns its previous

state value i.e. it holds the previous data.

When we apply a clock pulse to the J K flip flop and the J input is low then

irrespective of the other NAND gates, the NAND gate-1 output becomes HIGH. In

the same manner, if the K input is low then output of NAND gate-2 is also HIGH.

So thus the output remains in the same state i.e. no change in the state of flip flop.

• Case 2: When J is LOW and K is HIGH, then flip flop will be in Reset state

i.e. Q = 0, Q’ = 1.

When we apply a clock pulse to the J K flip flop and the inputs are J is low and K

is high the output of the NAND gate connected to J input becomes 1. Then Q

becomes 0. This will reset the flip flop again to its previous state. So the Flip flop

will be in RESET state.

• Case 3 : When J is HIGH and K is LOW, then flip – flop will be in Set state

i.e. Q = 1, Q’ = 0

When we apply a clock pulse to the J K flip flop and the inputs are J is high and K

is low the output of the NAND gate connected to K input becomes 1. Then Q’

becomes 0. This will set the flip flop with the high clock input. So the Flip flop

will be in SET state.

• Case 4 : When both the inputs J and K are HIGH, then flip – flop is in Toggle

state. This means that the output will complement of the previous state.

Toggle Flip Flop / T Flip Flop

Toggle flip flop is basically a JK flip flop with J and K terminals permanently

connected together. It has only input denoted by T as shown in diagram. When

clock pulse is given to the flip flop, the output begins to toggle.

Truth Table of T Flip Flop:

Clock INPUT OUTPUT

Status T Q �̅�

1 0 Q �̅� No Change

1 1 �̅� Q Toggle

Operation:

The T Flip Flop has only the Toggle and hold operation. If toggle mode operation

the output will toggle from 1 to 0 or Vice-versa.

The Master-Slave JK Flip Flop:

Master-slave flip flop is designed using two separate flip flops. Out of these, one

acts as the master and the other as a slave. The figure of a master-slave J-K flip flop

is shown below.

Master Slave Flip Flop

From the above figure you can see that both the J-K flip flops are presented in a

series connection. The output of the master J-K flip flop is fed to the input of the

slave J-K flip flop. The output of the slave J-K flip flop is given as a feedback to

the input of the master J-K flip flop. The clock pulse [Clock] is given to the master

J-K flip flop and it is sent through a NOT Gate and thus inverted before passing it

to the slave J-K flip flop.

When the clock input is low, and the two inputs of master flip flop i.e. J and K

inputs will have no effect on the output of Master Slave flip flop.

When the clock input is high

• If J is low & K is low: No change in state.

• If J is low & K is high: Master Slave flip flop will be in reset state.

• If J is high & K is low: Master Slave flip flop will be in set state.

• If J is high & K is high: Toggled state.

REGISTERS

SHIFT REGISTER:

A register is a temporary storage device of data. It is a group of cascaded flip flops

which stores binary word. register are widely found in microprocessors, micro

computers and digital systems with the names accumulators instruction registers

and program counters etc. a register cannot only store a binary data, but also shifts

the data to its left or right depending upon the user requirements such registers are

known as shift registers.

There are two types of shift registers are namely

1. Shift left register

2. Shift right register

SHIFT LEFT REGISTER:

The shift register that shifts the data by one bit to the left is known as ‘Shift left

Register’. In this the bits are moved from lower significant position to higher

significant position. The below figure shows a shift left register using positive edge

triggered D flip-flops.

SHIFT RIGHT REGISTER:

The shift register that shifts the data by one bit to the right is known as ‘Shift right

Register’. In this the bits are moved from higher significant position to lower

significant position. The below figure shows a shift right register using positive

edge triggered D flip-flops.

2MARKS:

COUNTERS:

Counter is a sequential circuit. A digital circuit which is used for counting pulses is

known counter. Counter is the widest application of flip-flops. It is a group of flip-

flops with a clock signal applied. Counters are of two types.

• Asynchronous or ripple counters.

• Synchronous counters.

Asynchronous Decade Counters :

A binary coded decimal (BCD) is a serial digital counter that counts ten digits .And

it resets for every new clock input. As it can go through 10 unique combinations of

output, it is also called as “Decade counter”.

Asynchronous counters

Fig (1): Asynchronous decade counter.

The count from 1010 to 1111 are skipped through suitable feedback NAND gate.

COUTING ACTION :

Initially 𝐶𝐿𝑅̅̅ ̅̅ ̅̅ is made low and the counter clears to 0000.so the counter word is

0000 and 𝐶𝐿𝑅̅̅ ̅̅ ̅̅ is made high now the counter is ready to go count .

since FFA receives each clock pulse QA toggles for each negative clock edge.the

remaing flipflops will toggle less often because they receive their negative clock

edges from the preceeding flipflops.

For example when QA toggles from 1 to 0 FFB receives negative clock edge and

toggles.like wise when QB toggles from 1 to 0 FFC will toggle and so on.the

output of feedback NAND gate is high for the first 9 states notice that only QB &

QD are connected to NAND gate inputs.

Fig (2): Truth table for asynchronous decade counter.

Fig (3): Asynchronous decade counter timing diagram.

A simple implementation of a 4-bit counter is shown in Figure 1, which consists of

4 stages of cascaded J-K flip-flops. This is a binary counter, since the output is in

binary system format, i.e., only two digits are used to represent the count, i.e., '1'

and '0'. With only 4 bits, it can only count up to '1111', or decimal number 00 to

decimal number 15.

For example when QA toggles from 1 to 0 FFB receives negative clock edge and

toggles.like wise when QB toggles from 1 to 0 FFC will toggle and so on.this

process is continued from 0000 to 1111.

CLOCK

COUNT

Q3 Q2 Q1 Q0 DECIMAL

VALUE

1 0 0 0 0 0

1 0 0 0 1 1

1 0 0 1 0 2

1 0 0 1 1 3

1 0 1 0 0 4

1 0 1 0 1 5

1 0 1 1 0 6

1 0 1 1 1 7

1 1 0 0 0 8

1 1 0 0 1 9

1 1 0 1 0 10

1 1 0 1 1 11

1 1 1 0 0 12

1 1 1 0 1 13

1 1 1 1 0 14

1 1 1 1 1 15

Distinguish between combinational circuits and sequential circuit

Combinational circuits Sequential circuits

1. It is a logic circuit which generates

output based upon present inputs is

known as combinational circuit.

1. It is logic circuit which generates

output based on present input as well

as past output is known as sequential

circuit.

2.this type of circuit has no memory

unit

2. This type of circuit has memory unit

for store past output.

3. Examples of combinational

circuits are half adder, full adder,

multiplexer and demultiplexers etc.

3. Examples of sequential circuits are

flip flop, register, counter etc.

4.faster in speed 4. slower compare to combinational

circuit

5. donot have the ability to store data 5. have memory to store the data

6.Feed backloop is not present 6. feedback loop is present

7. Memory element is not present 7. memory element is present

Distinguish between Synchronous and asynchronous

Synchronous Asynchronous

1. All flip flops are triggered with

same clock

1.Different clock is applied to different

flip flops

2.It is faster 2. It is slower

3. Design is complex 3.Design is easy

4.Decoding errors not present 4. Decoding errors present

5. Any required sequence can be

designed

5. Only fixed sequence can be

designed

6. A clocked flip flop acts as memory

element.

6. An unlocked flip flops or time delay

elements are used as memory element.

7. As number of states increases

designing becomes complex

7. logic circuit is simple even for more

number of states

8. It is called a parallel counter. 8. It is also called a serial counter or

ripple counter

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