Simplification of Logic Circuits using Karnaugh Mapping

Digital Electronic Systems Unit 8

Simplification of Logic Circuits using Karnaugh Mapping

A Karnaugh map provides a systematic method for simplifying a Boolean expression to produce the simplest SOP form possible. Like a truth table, it presents all possible values of input variables and the resulting output for each.

A Karnaugh map is composed of adjacent cells. Each cell represents one particular combination of variable values. The total number of possible combinations of n variables is 2n. Therefore, there are 2n cells in the Karnaugh map, which is the same as the number of rows in the corresponding truth table.

Shown below are the truth tables and the corresponding Karnaugh maps for two variables A and B, for three variables A, B and C and for four variables A,B,C and D.

2-Variable Truth Table

Input

AInput

BMinterms

00m0=

01m1=

10m2=

11m3=

3-Variable Truth Table

Input

AInput

BInput

CMinterms

000m0=

001m1=

010m2=

011m3=

100m4=

101m5=

110m6=

111m7=

4-Variable Truth Table

Input

AInput

BInput

CInput

DMinterms

0000m0=

0001m1=

0010m2=

0011m3=

0100m4=

0101m5=

0110m6=

0111m7=

1000m8=

1001m9=

1010m10=

1011m11=

1100m12=

1101m13=

1110m14=

1111m15=

The cells in the Karnaugh map are arranged so that there is only a single variable change between the minterms in adjacent cells.

For example, for a four variable function (with inputs A, B, C and D), m0 and m1 are adjacent. This is because the only change between and is replaced by D. In a similar fashion, m5 and m13 are adjacent . Note that m12 and m14 are also adjacent .

It can be concluded that each cell in a Karnaugh map is adjacent to cells that are immediately next to it on any of its four sides. Cells on the top row are adjacent to the corresponding cells on the bottom row and cells in the left-most column are adjacent to the corresponding cells on the right-most column (This is called wrap-around). However a cell is not adjacent to the cells that diagonally touch any of its corners.

Once a Boolean expression is in the SOP form it can be plotted by placing 1s in the cells corresponding to the minterms that make up the function.

Now draw a Karnaugh Map for the Boolean Functions of Ex. 1 to Ex. 5.

Grouping the cells

The 1s on a Karnaugh map are grouped according to the following rules by enclosing those adjacent cells containing 1s. The goal is to maximise the size of the groups and to minimise the number of groups.

(1) Cells may be combined in groups of 1s, 2s, 4s, 8s 16s, i.e. in groups of 2n. (2) Cells may combine horizontally and vertically, but NOT diagonally. Each cell in the group must be adjacent to one or more cells in that same group.

(3) As many maximum-sized groups as possible should be formed, until all cells containing 1s are included in at least one group.

(4) Each 1 on the map should be contained in at least one group. The 1s already in a group can be included in another group as long as the overlapping groups include the 1s that are not common.

Now group the cells on the Karnaugh maps of Ex. 1 to Ex. 5.

Simplifying the Boolean expression

This is very easy to do once the cells have been grouped.

(1) Each group of 1s that appears in the table creates a minimised product term. Variables that occur both uncomplemented and complemented within the group have been eliminated for that product term.

(2) The final expression is composed of all the product groupings ORed together. This produces the minimum SOP form.

Now write down the minimised product terms of the functions of Ex. 1 to Ex. 5.

Ex 1: Minimise the following function using Karnaugh Mapping. Verify your result using Boolean Algebra.

Ex 2: Minimise the following function using Karnaugh Mapping. Verify your result using Boolean Algebra.

Ex 3: Minimise the following function using Karnaugh Mapping. Verify your result using Boolean Algebra.

Ex 4: Minimise the following function using Karnaugh Mapping. Verify your result using Boolean Algebra.

Ex 5: Minimise the following function using Karnaugh Mapping. Verify your result using Boolean Algebra.

Dont Care combinations

In certain cases, some combinations of the inputs can never occur, or if they do it does not matter what function the output is. This may allow us to further minimise the Boolean function. However, great care should be taken when using this as part of the minimisation process. When grouping the 1s, the Xs can be treated as 1s to make a larger grouping, or as 0s if they cannot be used to advantage. Remember, the larger the grouping, the simpler the resulting Boolean expression.

Ex 6:

Truth Table

Input

AInput

BInput

CInput

DMintermsOutput

F

0000m00

0001m10

0010m20

0011m30

0100m40

0101m50

0110m61

0111m70

1000m81

1001m90

1010m101

1011m110

1100m121

1101m130

1110m141

1111m150

Now say that this function had some dont care states denoted by X. The resulting Boolean function can be minimised further.

Truth Table

Input

AInput

BInput

CInput

DMintermsOutput

F

0000m0X

0001m10

0010m2X

0011m30

0100m4X

0101m50

0110m61

0111m70

1000m81

1001m90

1010m101

1011m110

1100m121

1101m130

1110m141

1111m150

It can be seen that the output function has been reduced to contain just one variable. The output function is

Further Exercises

Minimise the following Boolean expressions using Karnaugh Mapping:

Ex. 7:

Ex. 8:

Ex. 9:

Ex. 10:

Ex. 11: and there are six disallowed combinations (i.e. they never occur) as follows

Ex. 12:

Ex. 13: The function of Ex. 12, in which minterms m10 to m15 are not allowed.

Ex. 14:

Ex. 15:

Ex. 16:

Ex. 17:

Ex. 18:

Ex. 19:

Ex. 20:

Ex. 21:

Ex. 22:

Ex. 23:

Ex. 24:

Ex. 25:

Building Functions using NAND gates only

Building an Inverter using a NAND gate

To build a NAND inverter, connect the inputs of a 2-input NAND gate together.

This may also be verified using a truth table. When both inputs are the same, that is A=B, then the 01 and 10 conditions dont exist.

INPUT AINPUT B

001

011

101

110

Building an AND gate using NAND gates

To build an AND gate using NAND gates, simply attach a NAND inverter to the output of a NAND gate.

Building an OR gate using NAND gates

To build an OR gate using NAND gates, one of De Morgans Theorems must be applied in conjunction with rule 9.

Building a NOR gate using NAND gates

To build a NOR gate using NAND gates, simply attach a NAND inverter to the output of the OR gate built using NAND gates.

Building Functions using NOR gates only

Building an Inverter using a NOR gate

To build a NOR inverter, connect the inputs of a 2-input NOR gate together.

This may also be verified using a truth table. When both inputs are the same, that is A=B, then the 01 and 10 conditions dont exist.

INPUT AINPUT B

001

010

100

110

Building an OR gate using NOR gates

To build an OR gate using NOR gates, simply attach a NOR inverter to the output of an OR gate.

Building an AND gate using NOR gates

To build an AND gate using NOR gates, one of De Morgans Theorems must be applied in conjunction with rule 9.

Building a NAND gate using NOR gates

To build a NAND gate using NOR gates, simply attach a NOR inverter to the output of the AND gate built using NOR gates.

Ex. 26: Implement the minimised expression using

(a) NAND gates only

(b) NOR gates only

Solution to Ex 26

26(a)Implement the function using NAND gates only

To build a function using NAND gates only

Reduce the function to its minimised Sum of Products format.

Apply rule 9 to the whole function.

Apply De Morgans Theorem .

The function is in its minimised sum of products format. Therefore

26(b)Implement the function using NOR gates only

To build a function using NOR gates only

Reduce the function to its minimised Sum of Products format.

Apply rule 9 to each product term (minterm).

Apply De Morgans Theorem .

The function is in its minimised sum of products format. Therefore

Alternatively, the logic diagram for the minimised function can be built using AND, OR and NOT gates and the NAND (or NOR) equivalents of each gate can be substituted. Removal of superfluous inverter pairs will result in the same circuits as obtained above. However, the gate substitution method takes significantly longer to implement.

Further Exercises

Ex. 27: Minimise the following Boolean Expression using Boolean algebra:

Implement in the minimised form (a) using NAND gates only; and (b) using NOR gates only.

Ex. 28: Minimise the following Boolean Expression using Boolean algebra:

Implement in the minimised form (a) using NAND gates only; and (b) using NOR gates only.

Ex. 29: Minimise the following Boolean Expression using Boolean algebra:

Implement in the minimised form (a) using NAND gates only; and (b) using NOR gates only.

Ex. 30: Minimise the following Boolean Expression using Boolean algebra:

Implement in the minimised form (a) using NAND gates only; and (b) using NOR gates only.

2

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Karnaugh Map

CD

AB

1 0

1 1

0 1

10

11

0 0

1

0

1

1

0

0

0

0

0

0

0

0

1

0

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1

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0

00

01

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D

C

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F

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C

B

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B

A

F

C

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D

A

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B

A

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A

A

B

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B

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A

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B

A

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B

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B

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A

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B

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A

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A

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Karnaugh Map

CD

AB

1 0

1 1

0 1

10

11

0 0

1

0

1

1

X

0

0

0

0

0

X

X

1

0

EMBED Equation.3

1

0

00

01

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m3

m1

m2

m0

m6

m5

m4

m7

0 0

0

1

0 1

1 1

1 0

AB

C

3-Variable Karnaugh Map

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4-Variable Karnaugh Map

CD

AB

1 0

1 1

0 1

10

11

0 0

m14

m11

m10

m6

m2

m7

m3

m15

m5

m1

m4

m0

m12

m9

m8

m13

00

01

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2-Variable Karnaugh Map

m0

m2

m1

m3

B

A

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(0)

(1)

(0)

(1)

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A

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