UNIT 7 - INTRODUCTION TO I/O INTERFACING

TWO MAJOR TYPES OF I/O INTERFACING

• ISOLATED I/O

- DEDICATED I/O INSTRUCTIONS ARE USED TO ACCESS I/O DEVICES (TYPICALLY “IN” AND “OUT” INSTRUCTIONS)

- SEPARATE CONTROL SIGNALS FOR MEMORY AND I/O, TYPICALLY:

- MEMR IOR

- MEMW IOW

• MEMORY-MAPPED I/O

SOME OF THE AVAILABLE MEMORY SPACE IS ASSIGNED TO I/O DEVICES. THE I/O DEVICES ARE THEN ACCESSED USING MEMORY-REFERENCE INSTRUCTIONS.

- SAME CONTROL SIGNALS FOR MEMORY AND I/O, SUCH AS:

- R/W OR - MEMR

- ECLK - MEMW

• A MORE EXTENSIVE INSTRUCTIONS SET CAN BE USED TO ACCESS I/O DEVICES.

• MORE ADDRESSING MODES ARE AVAILABLE.

• SOME OF MEMORY SPACE MUST BE GIVEN TAKEN AWAY FROM MEMORY TO GIVE TO I/O.

• MEMORY MAPPED I/O INSTRUCTIONS GENERALLY TAKE LONGER TO EXECUTE.

ADVANTAGES OF MEMORY-MAPPED I/O

DISADVANTAGES OF MEMORY I/O

“LINEAR SELECT” I/O ADDRESSING

(CAN BE USED TO ADDRESS A NUMBER OF DEVICES EQUAL TO OR LESS THAN THE NUMBER OF ADDRESS LINES)

A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1

0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0

0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0

0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0

1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

decoder

Latch

Latch

Data Bus

Addr. Bus

Device

IOR

INTERFACE OF INPUT PORT TO DATA BUS WITH NO HANDSHAKING SIGNALS USED

Typically Switches

CLK

OE

Ox(373)

G

+5VOR

decoder

Latch

Latch

Data Bus

Addr. Bus

Device

IOW

INTERFACE OF OUTPUT PORT TO DATA BUS WITH NO HANDSHAKING SIGNALS USED

Typically Lights

CLK

CP

Ox(374)

GND

NOR

OE

decoder

Latch

Latch

Data Bus

Addr. Bus

Printer

INTERFACE OF OUTPUT PORT TO DATA BUS WITH HANDSHAKING SIGNALS GENERATED BY SOFTWARE

CLK

OE

NOROx

(374)

CPGND

IOW

busystb

Latch

Latch

IOR

cpoegnd

oeG+5v

Oz

Oy

OR

NOR

USING I/O PORTS

ON THE

MC9S12DP256B MICROCONTROLLER

Port Interface Module – Block Diagram

Register x Descriptions

• Data Direction Register (DDRx)• I/O Register (PTx)• Input Register (PTIx)• Reduced Drive Register (RDRx)• Pull Enable Register (PERx)• Polarity Select Register (PPSx)• Port Interrupt Enable Register (PIEPx)• Port Interrupt Flag Register (PIFx)• Port Wired-Or Mode Register (WOMx)

x: Register Name, e.g., T, S, M, P, H, J

Data Direction Register xx: T, S, M, P, H, J

DDRx7 DDRx6 DDRx5 DDRx4 DDRx3 DDRx2 DDRx1 DDRx0

DDRx[7:0] – Data Direction Port I1 = Associated Pin is Configured as Output0 = Associated Pin is Configured as Input

Port x I/O Register x: T, S, M, P, H, J

PTx7 PTx6 PTx5 PTx4 PTx3 PTx2 PTx1 PTx0

PTx[7:0] – Port I I/O RegisterRead Port If Direction is Input, Read State of Pin If Direction is Output, Read State of BufferWrite Port If Direction is Input, Data is Ignored If Direction is Output, Write Buffer

Port x Input Register x: T, S, M, P, H, J

PTIx7 PTIx6 PTIx5 PTIx4 PTIx3 PTIx2 PTIx1 PTIx0

PTIx[7:0] – Port x Input RegisterReads State of Pins of Port x

If Port x is output, can detect overloads by readingthe actual state of the pin.

Reduced Drive Register Port xDirection is Output

x: T, S, M, P, H, J

RDRx7 RDRx6 RDRx5 RDRx4 RDRx3 RDRx2 RDRx1 RDRx0

RDRx[7:0] – Reduced Drive Register Port x1 = 1/3 Full Output Drive0 = Full Output Drive

Port x Pull Device Enable RegisterDirection is Input

x: T, S, M, P, H, J

PERx7 PERx6 PERx5 PERx4 PERx3 PERx2 PERx1 PERx0

PERx[7:0] – Pull Device Enable Register - Port x1 = Enable Pull Device if Input0 = Disable Pull Device if Input

Pull Device – Direction is Input

• Pull Up – Resistor to +5 Volts

• Pull Down – Resistor to Ground

cpu

cpu

gndinput

input

Pull up Pull down

+5v

Port x Polarity Select RegisterDirection is Input

x: T, S, M, P, H, J

PPSx7 PPSx6 PPSx5 PPSx4 PPSx3 PPSx2 PPSx1 PPSx0

PPSx[7:0] – Port x Polarity Select Register 1 = Enable Pull Down Rising Edge Sets Interrupt Flag – Ports P, H, J0 = Enable Pull UP Falling Edge Sets Interrupt Flag – Ports P, H, J

Dual Purpose for Ports P, H, J

Port x Interrupt Enable Register x: P, H, J (Input)

PIEx7 PIEx6 PIEx5 PIEx4 PIEx3 PIEx2 PIEx1 PIEx0

PIEx[7:0] – Port x Interrupt Enable Register 1 = Enable Interrupt = Unmask Interrupt0 = Disable Interrupt = Mask Interrupt

Port x Interrupt Flag Register x: P, H, J (Input)

PIFx7 PIFx6 PIFx5 PIFx4 PIFx3 PIFx2 PIFx1 PIFx0

PIFx[7:0] – Port x Interrupt Flag Register 1 = Interrupt Pending (Write “1” to Clear Flag)0 = No Interrupt Pending

Port x Wired-OR Mode Register x: S, M

WOMx7 WOMx6 WOMx5 WOMx4 WOMx3 WOMx2 WOMx1 WOMx0

WOMx[7:0] – Port x Wired-OR Mode Register Output Only1 = Output is Open Drain0 = Output is Push-Pull

Example

Sample Application

• Use Port H[3:0] to Read Inputs from Four Switches with Pull Ups

• Use Port H[7:4] to Send Out Four Bits Read from the Switches to a 374 Latch (which is connected to four LEDs)

• Use Port J[0] to Provide a Software-Initiated Clock Pulse to the 374 Latch

Example Components

374 LatchOE = 0Enable Outputs

“0”->”1” CPLatch Input

Fig. 5.7

Port H Port Definitions(One Method)

#define PTH _P(0x260) // port H data register#define PTIH _P(0x261) // port H input register#define DDRH _P(0x262) // port H direction register#define RDRH _P(0x263) // port H reduced drive register#define PERH _P(0x264) // port H pull device enable#define PPSH _P(0x265) // port H pull polarity select#define PIEH _P(0x266) // port H interrupt enable register#define PIFH _P(0x267) // port H interrupt flag register

Port H Port Definitions (Another Method)

/* Port H Port Definitions */#define PTH *(volatile unsigned char *) 0x260#define PTIH *(volatile unsigned char *) 0x261#define DDRH *(volatile unsigned char *) 0x262#define RDRH *(volatile unsigned char *) 0x263#define PERH *(volatile unsigned char *) 0x264#define PPSH *(volatile unsigned char *) 0x265#define PIEH *(volatile unsigned char *) 0x266#define PIFH *(volatile unsigned char *) 0x267

Port H Initialization

/* Initialize Port H */DDRH = 0xF0; // 7:4 Out, 3:0 InRDRH = 0x00; // Full Drive on OutputPERH = 0x00; // Disable Pull Devices on Input//PERH = 0x0F; // Enable Pull DEvices//PPSH = 0x00; // Pull Ups on Inputs (Not Required) PIEH = 0x00; // Disable InterruptsPIFH = 0xFF; // Clear Interrupt Flag Register

/* The switches have pull ups and thus microcontrolleris not required to supply */

Port J Port Definitions

#define PTJ _P(0x268) // port J data register#define PTIJ _P(0x269) // port J input register#define DDRJ _P(0x26A) // port J direction register#define RDRJ _P(0x26B) // port J reduced drive register#define PERJ _P(0x26C) // port J pull device enable#define PPSJ _P(0x26D) // port J pull polarity select#define PIEJ _P(0x26E) // port J interrupt enable register#define PIFJ _P(0x26F) // port J interrupt flag register

Port J Initialization

/* Initialize Port J *//* Set Data Direction Register – Port J Set Bit 0 of Port J to Output Do not change direction of Bits 1 through 7 Read state of Port J Data Direction Register Bitwise Or State with 0x01 Write Data Direction Register – Port J */

DDRJ = DDRJ | 0x01; // Bit 0 is Out

Port J Initialization/* Read State of Reduced Drive Register – Port J Bitwise AND State with 0xFE Write Reduced Drive Register - Port J*/RDRJ = RDRJ & 0xFE; // Bit 0 is Full Output

/* Read State of Interrupt Enable Register – Port J Bitwise AND Value Read Write Interrupt Enable Register – Port J */PIEJ = PIEJ & 0xFE; // Disable Bit 0 Interrupt

/* Init Bit 0 of Port J to 0 */PTJ = PTJ & 0xFE;

Read Port H

Shift Input BitsLeft 4 Places

Write Port H

Latch StrobePTJ0 = 1PTJ0 = 0

Application Flow Diagram

Application Code

/* Read Inputs, Output, Strobe Output into Latches */PTH = PTH<<4; // Read input, shift 4 left and OutputPTJ = PTJ | 0x01; // Set Strobe = 1PTJ = PTJ & 0xFE; // Set Strobe = 0

Parallel Printer Port Example

Parallel Printer Interface

Printer

/Strobe

Busy

Data[7:0]

Busy

WriteData

Strobe

Yes

No

Printer

J[1]

J[0]

68HC12

H[7:0]

Latch

Busy

Data

/Strobe

Parallel Printer Interface

Busy

Data

/Strobe

Printer Waveforms

PC Parallel Printer Port Definitionwww.fapo.com/ieee1284.htm

/* initialize Port H to Output, Full Drive, Printer Data */DDRH = 0xFF; // Output DirectionRDRH = 0x00; // Full Drive

/* Bit 0 Port J - /Strobe Output Bit 1 Port J – Busy Input */DDRJ = (DDRJ & 0xFC)| 0x01;

/* Full Drive for Bit 0 Port J */RDRJ = RDRJ & 0xFE;

/* Enable Pull for Input */PERJ = PERJ | 0x2;

/* Use Pull Up on Input */PPSJ = PPSJ | 0xFD;

/* Strobe Initially High */PTJ = PTJ | 0x01;

Print a Character on Printer

void printc(unsigned char c){ /* Wait while Printer is Busy */ while((PTJ&0x02)!=0);

/* Printer not Busy, Output Data */ PTH = c;

/* Generate Strobe * PTJ = PTJ & 0xFE; // Bit 0 Low PTJ = PTJ | 0x01; // Bit 0 High}

Example – Parallel Interface of 2 Computers

(Send Byte from A to B)

Port H Out

Port J[0]Out

Port J[1]In

Port H Input

Port J[0]In

Port J[1]Out

Computer A Computer B

Port H

J[0]

J[1]

Timing Diagrams

Valid Data

Strobe Data

Acknowledge Data

(Sent by Computer A)

(Sent by Computer A)

(Sent by Computer B)

1

2

3

5

2

4

6

Computer Software(Pseudo Code)

Computer AInitialize: Port H Direction Out Port J[0] Out Port J[1] Input Port J[0] = 0;

Write a byte: Wait until Compute B is Ready Present Data to Comp. B Begin Strobe Pulse Wait for Acknowledge End Strobe Pulse

Computer BInitialize: Port H Direction In Port J[0] In Port J[1] Output Port J[1] = 0;

Read a byte: Wait for Strobe from Computer A Read Port H; Begin Acknowledge Pulse Wait for Strobe to End End Acknowledge Pulse

Computer A// Initialize Port H and Port JDDRH = 0xFF //Port H is Output PortDDRJ = (DDRJ &0xFC) | 0x1; //xxxxx01, J[1] = input, J[0] is outputPTJ = PTJ & 0xFE; //xxxxxxx0, send 0 from J[0]

//Write a byte while ((PTJ&0x02)!=0); //Wait until Compute B is ReadyPTH = data; //Send data out on Port H, to Computer B PTJ = PTJ | 0x01; //Begin strobe pulse to Computer Bwhile ((PTJ&0x2)==0); //Wait until Comp. B has acknowledged dataPTJ = PTJ &0xFE; //End strobe pulse to Computer B

Computer B// Initialize Computer BDDRH = 0x00; // //Port H is Input PortDDRJ = (DDRJ & 0xFC) | 0x02; //xxxxxx10, J[1] = output, J[0] is input PTJ = PTJ & 0xFD; //xxxxxx0x, initialize J[1] to 0

// Read a bytewhile((PTJ&0x01)==0); //Wait until Computer A has sent dataData = PTH; //Read data from Computer APTJ = PTJ | 0x02; //Begin Acknowledge pulse, sent to Computer Awhile((PTJ&0x01)!=0); //Wait for Strobe Pulse from Computer A to endPTJ = PTJ & 0xFD; // End Acknowledge pulse, sent to Computer A

ANOTHER EXAMPLE

Digital Lock

5Switches

CPU Port H[7]Port H[4:0] Unlock

5 Switches -> Port H[4:0]Port H switches are marked as: A, B, C, D, E

5 Momentary Contact Switches

5 Switches -> Port HPort H switches are marked as: A, B, C, D, EPort H [0] =“A”, Port H[1]=“B”, Port H[2]=“C”Port H[3]=“D’, Port H[4]=“E”Switches are normally open – “1” in InputPress Switch - “0” in Input

Digital Code is Sequence to Unlock DoorB, D, E, C, A

Detect Sequence to UnlockPort H[7] -- Unlock

Initialize Interface/* Push Button Codes */#define A 0x1E // 11110#define B 0x1D // 11101#define C 0x1B // 11011#define D 0x17 // 10111#define E 0x0F // 01111/* Port H Symbol Definitions */#define PTH _P(0x260) // port H data register#define PTIH _P(0x261) // port H input register#define DDRH _P(0x262) // port H direction register#define RDRH _P(0x263) // port H reduced drive register#define PERH _P(0x264) // port H pull device enable#define PPSH _P(0x265) // port H pull polarity select#define PIEH _P(0x266) // port H interrupt enable register#define PIFH _P(0x267) // port H interrupt flag register

int main(void){unsigned char state=0,insw,flag=0;/* initialize the Port H Interface */ DDRH = 0x80; // Bit 7 is Output, Bits 0-6 are input RDRH = 0x00; // Full Drive PERH = 0x7f; // Enable Pull Device (Not Required) PPSH = 0x00; // Enable Pull Up PTH = 0x00; // Bit 7=0 // forever loopwhile(flag==0) {while((PTH&0x1F)==0x1F); // wait while not pressed // switch was pressed, go process insw = PTH & 0x1F; // read switches

switch (state) { case 0: if(insw==B) state=1; break; case 1: if(insw==D) state=2 else state=0; break; case 2: if(insw==E) state=3 else state=0; break; case 3: if(insw==C) state=4 else state=0; break; case 4: if(insw==A) {PTH=0x80; // unlock door PTH = 0x00; state=0;} } while((PTH&0x1F)!=0x1F); //Wait until not pressed }}