Unit-4 Microprocessor Based System Development...

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Unit-4 Microprocessor Based System Development Aids

ADC Interfacing with 8085 Microprocessor

The ADC 0808/0809 is an 8-bit analog to digital converter. It has 8 channel multiplexer to interface with the microprocessor.

The ADC0809 is available as a 28 pin IC in DIP (Dual Inline Package). The ADC0808 is also same as ADC0809 except the

error. The total unadjusted error in ADC0808 is ± 1/2 LSD (Least Significant Digit).

This chip is popular and widely used ADC. ADC 0808/0809 is a monolithic CMOS device. This device uses successive

approximation technique to convert analog signal to digital form. One of the main advantage of this chip is that it does not

require any external zero and full-scale adjustment, only +5V DC supply is sufficient.

Let us see some good features of ADC 0808/0809

• The conversion speed is much higher

• The accuracy is also high

• It has minimal temperature dependence

• Excellent long-term accuracy and repeatability

• Less power consumption

Signal Description

Sl No. Signals Description

1 IN0-IN7 This is an 8-bit Analog Input line used to input analog data to ADC Chip.

2 D0-D7

This is an 8bit Digital Output line used to generate output data from ADC Chip. D7 is MSB &

D0 is LSB. 3

CLOCK It is used provide clock frequency to Chip.

4 VCC, VREF (+/-),

GND

VCC supply input voltage of +5v. GND is Ground supply. Vref+ is the input reference voltage of

+5v maximum & Vref- is negative reference voltage of 0v minimum. 5

START (SOC) It is used to provide Start of Conversion (SOC) signal to the ADC.

6 OE It is Output latch Enable (OE) pin, it set as High (1) to enable Output.

7 EOC It is used to Check End of Conversion (EOC) signal to the ADC.

8 ALE It is Address Latch Enable line used to select Address to Data for Input lines.

9 ADD A, B, C It is used for selecting Input Analog Lines (IN0-IN7).

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Procedures for Interfacing

Follow the initial 3 steps of interfacing of 8255 with 8085 that are given before.

The ADC 0808 is 8-channel 8-bit ADC chip. It has 8 analog inputs i.e. IN0-IN7.

One of these channels is selected by sending address to a address line of ADC. The logic level and selected channel is as

shown:

The analog signal is connected to channel 3.

➢ The digital equivalent data D0-D7 is connected to PA0-PA7 of Port A. ➢ The PC0, PC1 and PC2 lines of Port C are connected to channel select address lines of 8255. ➢ PC3 is connected to SOC (Start of conversion) and ALE signal (Input signal). EOC (End of conversion) which is an output

signal of 8255 connected to PC7 of Port C.

➢ The PB0 of Port B is connected to OE (Output Enable) input signal of ADC. ➢ The control word format for above interface Is given as:

=98H

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Data from channel selection: A high to low signal is applied for obtaining data from ADC.

=0BH (SOC= HIGH)

Step 1

=03H (SOC= LOW)

Step 2

OE (Output Enable):

=01H

Program/Code

ADDRESS MNEMONICS COMMENT

2000 MVI A,98H Initialize 8255

2002 OUT 83H Write control word 8255-I to control Word register

2004 MVI A,0BH Selects channel IN3 and get High to Low SOC and ALE signal

2006 OUT 82H Send the content of Accumulator to Port CLOWER to select IN3 (PORT C)

2008 MVI A,03H Load the accumulator with 08H

200A OUT 82H ALE and SOC will be 0 (PORT C)

200C IN 82H Checks EOC (PORT C)

200E RAL Is conversion complete? If no then jump to 200C

2010 JNC 200C

2013 MVI A,01H Is conversion complete? If yes then enable Output

2015 OUT 81H PORT B

2017 IN 80H Read data from PORT A

2019 STA 2050H Store Data

201C HLT Stop

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NOTE

Video Lecture to understand Working Procedure = Interfacing of ADC(Analog to Digital Converter)- OPEN BOX Education

(https://www.youtube.com/watch?v=GYotCX3N0OU&t=818s) (Don’t follow the Program of this Video as it is using interfacing with 8086)

Website

1. Interfacing ADC(Analog to Digital Converter) with 8085

(https://www.zseries.in/embedded%20lab/8085%20microprocessor/adc%20interfacing.php#.XoRxIYgzaMo)

2. Interfacing ADC with 8085 Microprocessor

(https://www.tutorialspoint.com/interfacing-adc-with-8085-microprocessor)

3. ADC Interfacing with 8085 Microprocessor (https://www.brainkart.com/article/ADC-Interfacing-with-8085-Microprocessor_7827/)

https://www.youtube.com/watch?v=GYotCX3N0OU&t=818shttps://www.zseries.in/embedded%20lab/8085%20microprocessor/adc%20interfacing.php#.XoRxIYgzaMohttps://www.tutorialspoint.com/interfacing-adc-with-8085-microprocessorhttps://www.brainkart.com/article/ADC-Interfacing-with-8085-Microprocessor_7827/

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DAC Interfacing with 8085 Microprocessor

To convert the digital signal to analog signal a Digital-to-Analog Converter (DAC) has to be employed. The DAC will accept

a digital (binary) input and convert to analog voltage or current. Every DAC will have "n" input lines and an analog output.

The DAC require a reference analog voltage (Vref) or current (Iref) source. The smallest possible analog value that can be

represented by the n-bit binary code is called resolution.

The resolution of DAC with n-bit binary input is 1/2nof reference analog value.

The DAC0800 is an 8-bit, high speed, current output DAC with a typical settling time (conversion time) of 100 ns. It produces

complementary current output, which can be converted to voltage by using simple resistor load. The DAC0800 require a

positive and a negative supply voltage in the range of ± 5V to ±18V.

Procedure for Interfacing

➢ Follow the initial 3 steps of interfacing of 8255 with 8085 that are given before.

➢ The DAC 0808 is 8-bit digital to analog convertor IC. It converts digital data into equivalent analog current.

➢ Therefore, I to V converter is used to convert analog output current of DAC to equivalent analog voltage.

➢ PA0-PA7 pins of Port A are connected to D0-D7 pins of DAC.

➢ In above DAC dual power supply of +/- 10V is applied with reference voltage 10V as shown in diagram.

➢ According to theory of DAC Equivalent analog output is given as: V0=Vref Ex:

1. If data =00H [00000000], Vref= 10V

V0= 0 Volts.

2. If data is 80H [10000000], Vref= 10V V0=10

V0= 5 Volts.

SL NO. SIGNAL DESCRIPTION

1 NC No connection

2 VEE Negative power supply

3 IO Analog Output signal pin

4 A1-A8 Digital input bit 1 (Most Significant Bit) to Digital input bit 8 (Least Significant

Bit)

5 VCC, GND Positive power supply & Ground

6 VREF+, VREF- Positive reference voltage & Negative reference voltage

7 COMPENSATION Compensation capacitor pin

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➢ The control word format of 8255 for above interfacing is given as:

=80H

Program:

Interfacing Diagram of DAC

NOTE: -

Video Lecture to understand Working Procedure = Interfacing of DAC (Digital to Analog Converter)- OPEN BOX Education

(https://www.youtube.com/watch?v=SdLfnmvprEE&t=98s) (Don’t follow the Program of this Video as it is using interfacing with 8086)

Website

1. Interfacing DAC(Digital to Analog Converter) with 8085

(https://www.zseries.in/embedded%20lab/8085%20microprocessor/dac%20interfacing.php#.XoP_z4gzaMo)

2. DAC0808 – 8 Bit D/A Converter

(https://components101.com/ics/dac0808-8-bit-da-converter)

ADDRESS MNEMONICS COMMENTS

2000 MVI A,80H Initialize 8255 with PORT A as Output

2002 OUT 83H

2004 MVI A,80H Send Digital Data for Conversion

2006 OUT 80H

2008 HLT Stop

https://www.youtube.com/watch?v=SdLfnmvprEE&t=98shttps://www.zseries.in/embedded%20lab/8085%20microprocessor/dac%20interfacing.php#.XoP_z4gzaMohttps://components101.com/ics/dac0808-8-bit-da-converter

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Unit-5: - 8086 Microprocessor (Architecture and Programming-16 bit)

Intel 8086 microprocessor is the enhanced version of Intel 8085 microprocessor. It was designed by Intel in 1976. The 8086

microprocessor is a16-bit, N-channel, HMOS microprocessor. Where the HMOS is used for "High-speed Metal Oxide

Semiconductor". Intel 8086 is built on a single semiconductor chip and packaged in a 40-pin IC package. The type of package is DIP

(Dual Inline Package). Intel 8086 uses 20 address lines and 16 data- lines. It can directly address up to 220 = 1 Mbyte of memory.

It consists of a powerful instruction set, which provides operation like division and multiplication very quickly. 8086 is designed to

operate in two modes, i.e., Minimum and Maximum mode.

Difference between 8085 and 8086 Microprocessor

Features

➢ It is a 16-bit µp.

➢ It can support up to 64K I/O ports.

➢ 8086 has a 20-bit address bus can access up to 220 memory locations (1 MB).

➢ It provides 14, 16 -bit registers.

➢ It has multiplexed address and data bus AD0- AD15 and A16 – A19 are used only as address bus.

➢ It is operating at Clock Rates: 5 MHz

➢ It requires single phase clock with 33% duty cycle to provide internal timing.

➢ 8086 is designed to operate in two modes, Minimum and Maximum.

➢ It requires +5V power supply.

8086 Microprocessor Architecture

The 8086 CPU is organized as two separate processors, called the Bus Interface Unit (BIU) and the Execution Unit (EU). The BIU

provides H/W functions, including generation of the memory and I/O addresses for the transfer of data between the outside world -

outside the CPU, that is- and the EU.

The EU receives program instruction codes and data from the BIU, executes these instructions, and store the results in the general

registers. By passing the data back to the BIU, data can also be stored in a memory location or written to an output device. Note that

the EU has no connection to the system buses. It receives and outputs all its data thru the BIU.

8085 Microprocessor 8086 Microprocessor

It is an 8-bit microprocessor. It is a 16-bit microprocessor.

It has a 16-bit address line. It has a 20-bit address line.

It has a 8-bit data bus. It has a 16-bit data bus.

The memory capacity is 64 KB. The memory capacity is 1 MB.

The Clock speed of this microprocessor is 3 MHz The Clock speed of this microprocessor varies

between 5, 8 and 10 MHz for different versions.

It has five flags. It has nine flags.

8085 microprocessor does not support memory

segmentation.

8086 microprocessor supports memory segmentation.

It does not support pipelining. It supports pipelining.

It is accumulator based processor. It is general purpose register based processor.

It has no minimum or maximum mode. It has minimum and maximum modes.

In 8085, only one processor is used. In 8086, more than one processor is used. An

additional external processor can also be employed.

It contains less number of transistors compare to 8086

microprocessor. It contains about 6500 transistors.

It contains more number of transistors compare to

8085 microprocessor. It contains about 29000 in size.

The cost of 8085 is low. The cost of 8086 is high.

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Functional units of 8086

1. The Bus Interface Unit (BIU):

It provides the interface of 8086 to external memory and I/O devices via the System Bus. It performs various machine cycles such as

memory read, I/O read etc. to transfer data between memory and I/O devices.

BIU performs the following functions-

• It generates the 20-bit physical address for memory access.

• It fetches instructions from the memory.

• It transfers data to and from the memory and I/O.

• Maintains the 6-byte prefetch instruction queue (supports pipelining).

BIU mainly contains the 4 Segment registers, the Instruction Pointer, a prefetch queue and an Address Generation Circuit.

Instruction Pointer (IP):

• It is a 16-bit register. It holds offset of the next instructions in the Code Segment.

• IP is incremented after every instruction byte is fetched.

• IP gets a new value whenever a branch instruction occurs.

• CS is multiplied by 10H to give the 20-bit physical address of the Code Segment.

• Address of the next instruction is calculated as CS x 10H + IP.

Example:

CS = 4321H IP = 1000H

then CS x 10H = 43210H + offset = 44210H (This is the address of the instruction)

Code Segment register: CS holds the base address for the Code Segment. All programs are stored in the Code Segment and accessed

via the IP.

Data Segment register: DS holds the base address for the Data Segment.

Stack Segment register: SS holds the base address for the Stack Segment.

Extra Segment register: ES holds the base address for the Extra Segment.

Address Generation Circuit:

• The BIU has a Physical Address Generation Circuit.

• It generates the 20-bit physical address using Segment and Offset addresses using the formula:

Physical Address = Segment Address x 10H + Offset Address

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Instruction Queue: When EU executes instructions, the BIU gets 6-bytes of the next instruction and stores them in the instruction

queue and this process is known as instruction pre fetch. This process increases the speed of the processor.

2. The Execution Unit (EU):

The main components of the EU are General purpose registers, the ALU, Special purpose registers, Instruction Register and Instruction

Decoder and the Flag/Status Register.

1. Fetches instructions from the Queue in BIU, decodes and executes arithmetic and logic operations using the ALU.

2. Sends control signals for internal data transfer operations within the microprocessor.

3. Sends request signals to the BIU to access the external module.

4. It operates with respect to T-states (clock cycles) and not machine cycles.

8086 has four 16 bit general purpose registers AX, BX, CX and DX. Store intermediate values during execution. Each of these have

two 8 bit parts (higher and lower).

• AX register: It holds operands and results during multiplication and division operations. Also, an accumulator during String

operations.

• BX register: It holds the memory address (offset address) in indirect addressing modes.

• CX register: It holds count for instructions like loop, rotate, shift and string operations.

• DX register: It is used with AX to hold 32 bit values during multiplication and division.

Arithmetic Logic Unit (16 bit): Performs 8 and 16 bit arithmetic and logic operations.

Special purpose registers (16-bit):

• Stack Pointer: Points to Stack top. Stack is in Stack Segment, used during instructions like PUSH, POP, CALL, RET etc.

• Base Pointer: BP can hold offset address of any location in the stack segment. It is used to access random locations of the stack.

• Source Index: It holds offset address in Data Segment during string operations.

• Destination Index: It holds offset address in Extra Segment during string operations.

Instruction Register and Instruction Decoder: The EU fetches an opcode from the queue into the instruction register. The instruction

decoder decodes it and sends the information to the control circuit for execution.

Flag/Status register (16 bits):

It has 9 flags that help change or recognize the state of the microprocessor.

6 Status flags:

1. Carry Flag (CF)

2. Parity Flag (PF)

3. Auxiliary Carry Flag (AF)

4. Zero Flag (Z)

5. Sign Flag (S)

6. Overflow Flag (O)

Status flags are updated after every arithmetic and logic operation.

3 Control flags:

1. Trap Flag (TF)

2. Interrupt Flag (IF)

3. Direction Flag (DF)

These flags can be set or reset using control instructions like CLC, STC, CLD, STD, CLI, STI, etc. The Control flags are used to control

certain operations.

Steps to execute an instruction and concept of Pipelining in 8086 Microprocessors

In the 8086 microprocessors, the instructions are executed in 4 steps which are listed as follows:

1. Fetch the instruction 2. Decode the instruction 3. Fetch the operands 4. Execution of the instruction

https://www.geeksforgeeks.org/general-purpose-registers-8086-microprocessor/https://www.geeksforgeeks.org/flag-register-8086-microprocessor/

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Any instruction that is provided to the 8086 microprocessor is executed by following the above-mentioned steps. For each instruction,

all these steps are performed, i.e. if there are 3 instructions to be executed, then all these steps will be performed 3 times each.

Suppose, these instructions are executed sequentially, and it takes the 1-time unit for each step to run. So, it would take 12-time units

(3 X 4) to execute these instructions.

It seems less as the number of instructions is less, but a processor has o deal with a very large number of instructions, and so it should

process fast to be efficient. In the 8086 microprocessor, this problem was solved by the method of pipelining.

As we know that there are two separate units in 8086 microprocessors:

1. The BIU (Bus Interface Unit) 2. The EU (Execution unit)

Both these units work mutually exclusive to each other. Due to this, the parallel processing of instructions can be implied in the 8086

microprocessor, because these units are responsible for alternate steps of instruction execution. That is,

• Fetch instruction: Done by BIU

• Decode Instruction: Done by EU

• Fetch Operands: Done by BIU

• Execution: Done by EU

So, while the instruction completes its first step and goes to the second step that is handled by the EU, the BIU is idle, and in that time,

the next instruction is sent to BIU. By doing so, the parallel processing of instructions is implemented, and this concept is known as

pipelining.

So, it can be observed that the instructions which were taking 12-time units for execution while being processed in a sequential way

are now taking only 6 clock cycles through pipelining.

Register organization of 8086

8086 has a powerful set of registers known as general purpose registers and special purpose registers. All of them are 16-bit registers.

1. General purpose registers:

• These registers can be used as either 8-bit registers or 16-bit registers.

• They may be either used for holding data, variables and intermediate results temporarily or for other purposes like a counter or for storing offset address for some particular addressing modes etc.

2. Special purpose registers:

• These registers are used as segment registers, pointers, index registers or as offset storage registers for particular

addressing modes.

✓ The 8086 registers are classified into the following types:

➢ General Data Registers

➢ Segment Registers

➢ Pointers and Index Registers

➢ Flag Register

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General Data Registers:

The registers AX, BX, CX and DX are the general purpose 16-bit registers.

1. AX – This is the accumulator. It is of 16 bits and is divided into two 8-bit registers AH and AL to also perform 8-bit instructions.

It is generally used for arithmetical and logical instructions but in 8086 microprocessor it is not mandatory to have accumulator as

the destination operand.

Example:

ADD AX, AX (AX = AX + AX)

2. BX – This is the base register. It is of 16 bits and is divided into two 8-bit registers BH and BL to also perform 8-bit instructions. It is used to store the value of the offset.

Example:

MOV BL, [500] (BL = 500H)

3. CX – This is the counter register. It is of 16 bits and is divided into two 8-bit registers CH and CL to also perform 8-bit instructions. It is used in looping and rotation.

Example:

MOV CX, 0005

LOOP

4. DX – This is the data register. It is of 16 bits and is divided into two 8-bit registers DH and DL to also perform 8-bit instructions. It is used in multiplication an input/output port addressing.

Example:

MUL BX (DX, AX = AX * BX)

Segment Registers:

There are 4 segment registers. They are:

1. Code Segment Register (CS)

2. Data Segment Register (DS)

3. Extra Segment Register (ES)

4. Stack Segment Register (SS)

✓ The 8086 architecture uses the concept of segmented memory. 8086 able to address a memory capacity of 1 megabyte and it is byte organized. This 1-megabyte memory is divided into 16 logical segments. Each segment contains 64 kb of memory.

1. Code segment register (CS): is used for addressing memory location in the code segment of the memory, where the

executable program is stored.

2. Data segment register (DS): points to the data segment of the memory where the data is stored.

3. Extra Segment Register (ES): also refers to a segment in the memory which is another data segment in the memory.

4. Stack Segment Register (SS): is used for addressing stack segment of the memory. The stack segment is that segment of

memory which is used to store stack data.

✓ While addressing any location in the memory bank, the physical address is calculated from two parts:

Physical address= segment address + offset address

✓ The first is segment address, the segment registers contain 16-bit segment base addresses, related to different segment.

✓ The second part is the offset value in that segment.

Pointers and Index Registers:

✓ The index and pointer registers are given below:

1. IP - Instruction pointer-store memory location of next instruction to be executed

2. BP - Base pointer

3. SP - Stack pointer

4. SI - Source index

5. DI - Destination index

✓ The pointers registers contain offset within the particular segments.

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1. The pointer register IP contains offset within the code segment.

2. The pointer register BP contains offset within the data segment.

3. Thee pointer register SP contains offset within the stack segment.

✓ The index registers are used as general purpose registers as well as for offset storage in case of indexed, base indexed and relative base indexed addressing modes.

✓ The register SI is used to store the offset of source data in data segment.

✓ The register DI is used to store the offset of destination in data or extra segment.

✓ The index registers are particularly useful for string manipulation.

8086 Flag register and its functions:

The Flag register is a Special Purpose Register. Depending upon the value of result after any arithmetic and logical operation the flag

bits become set (1) or reset (0).

There are total 9 flags in 8086 and the flag register is divided into two types:

(a) Status Flags – There are 6 flag registers in 8086 microprocessor which become set(1) or reset(0) depending upon condition after

either 8-bit or 16-bit operation. These flags are conditional/status flags. 5 of these flags are same as in case of 8085 microprocessor and

their working is also same as in 8085 microprocessor. The sixth one is the overflow flag.

The 6 status flags are:

1. Sign Flag (S) - This flag is set, when the result of any computation is negative. For signed computations the sign flag equals the

MSB of the result.

2. Zero Flag (Z) - This flag is set, if the result of the computation or comparison performed by the previous instruction is zero.

3. Auxiliary Cary Flag (AC) - This is set, if there is a carry from the lowest nibble, i.e., bit three during addition, or borrow for the

lowest nibble, i.e., bit three, during subtraction. (nibble = 4bit)

4. Parity Flag (P) - This flag is set to 1, if the lower byte of the result contains even number of 1’s.

5. Carry Flag (CY) - This flag is set, when there is a carry out of MSB in case of addition or a borrow in case of subtraction.

6. Overflow Flag (O) – This flag will be set (1) if the result of a signed operation is too large to fit in the number of bits available

to represent it, otherwise reset (0). After any operation, if D[6] generates any carry and passes to D[7] OR if D[6] does not generates

carry but D[7] generates, overflow flag becomes set, i.e., 1. If D[6] and D[7] both generate carry or both do not generate any carry,

then overflow flag becomes reset, i.e., 0.

Example: On adding bytes 100 + 50 (result is not in range -128…127), so overflow flag will set.

MOV AL, 50 (50 is 01010000 which is positive)

MOV BL, 32 (32 is 00110010 which is positive)

ADD AL, BL (82 is 10000010 which is negative)

Overflow flag became set as we added 2 +ve numbers and we got a -ve number.

(b) Control Flags – The control flags enable or disable certain operations of the microprocessor. There are 3 control flags in 8086

microprocessor and these are:

1. Directional Flag (D) – This flag is specifically used in string instructions. If directional flag is set (1), then access the string data

from higher memory location towards lower memory location. If directional flag is reset (0), then access the string data from lower

memory location towards higher memory location.

2. Interrupt Flag (I) – This flag is for interrupts. If interrupt flag is set (1), the microprocessor will recognize interrupt requests from

the peripherals. If interrupt flag is reset (0), the microprocessor will not recognize any interrupt requests and will ignore them.

3. Trap Flag (T) – This flag is used for on-chip debugging. Setting trap flag puts the microprocessor into single step mode for

debugging. In single stepping, the microprocessor executes an instruction and enters into single step ISR.

If trap flag is set (1), the CPU automatically generates an internal interrupt after each instruction, allowing a program to be

inspected as it executes instruction by instruction. If trap flag is reset (0), no function is performed.

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8086 Pins Diagram

8086 Signal Description

The description of the pins of 8086 is as follows:

AD0-AD15 (Address Data Bus): Bidirectional address/data lines. These are low order address bus. They are multiplexed with data.

When these lines are used to transmit memory address, the symbol A is used instead of AD, for example, A0- A15.

A16 - A19 (Output): High order address lines. These are multiplexed with status signals.

A16/S3, A17/S4: A16 and A17 are multiplexed with segment identifier signals S3 and S4.

A18/S5: A18 is multiplexed with interrupt status S5.

A19/S6: A19 is multiplexed with status signal S6.

BHE/S7 (Output): Bus High Enable/Status. During T1, it is low. It enables the data onto the most significant half of data bus, D8-

D15. 8-bit device connected to upper half of the data bus use BHE signal. It is multiplexed with status signal S7. S7 signal is available

during T3 and T4.

RD (Read): For read operation. It is an output signal. It is active when LOW.

Ready (Input): The addressed memory or I/O sends acknowledgment through this pin. When HIGH, it denotes that the peripheral is

ready to transfer data.

RESET (Input): System reset. The signal is active HIGH.

CLK (input): Clock 5, 8 or 10 MHz.

INTR: Interrupt Request.

NMI (Input): Non-maskable interrupt request.

TEST (Input): Wait for test control. When LOW the microprocessor continues execution otherwise waits.

VCC: Power supply +5V dc.

GND: Ground.

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Operating Modes of 8086

There are two operating modes of operation for Intel 8086, namely the minimum mode and the maximum mode.

When only one 8086 CPU is to be used in a microprocessor system, the 8086 is used in the Minimum mode of operation.

In a multiprocessor system 8086 operates in the Maximum mode.

Signal Description for Minimum Mode

In this minimum mode of operation, the pin MN/MX is connected to 5V D.C. supply i.e. MN/MX = VCC.

The description about the pins from 24 to 31 for the minimum mode is as follows:

INTA (Output): Pin number 24 interrupts acknowledgement. On receiving interrupt signal, the processor issues an interrupt

acknowledgment signal. It is active LOW.

ALE (Output): Pin no. 25. Address latch enable. It goes HIGH during T1. The microprocessor 8086 sends this signal to latch the

address into the Intel 8282/8283 latch.

DEN (Output): Pin no. 26. Data Enable. When Intel 8287/8286 octal bus transceiver is used this signal. It is active LOW.

DT/R (output): Pin No. 27 data Transmit/Receives. When Intel 8287/8286 octal bus transceiver is used this signal controls the direction

of data flow through the transceiver. When it is HIGH, data is sent out. When it is LOW, data is received.

M/IO (Output): Pin no. 28, Memory or I/O access. When this signal is HIGH, the CPU wants to access memory. When this signal is

LOW, the CPU wants to access I/O device.

WR (Output): Pin no. 29, Write. When this signal is LOW, the CPU performs memory or I/O write operation.

HLDA (Output): Pin no. 30, Hold Acknowledgment. It is sent by the processor when it receives HOLD signal. It is active HIGH

signal. When HOLD is removed HLDA goes LOW.

HOLD (Input): Pin no. 31, Hold. When another device in microcomputer system wants to use the address and data bus, it sends HOLD

request to CPU through this pin. It is an active HIGH signal.

Signal Description for Maximum Mode

In the maximum mode of operation, the pin MN/MX’ is made LOW. It is grounded. The description about the pins from 24 to 31 is as

follows:

QS1, QS0 (Output): Pin numbers 24, 25, Instruction Queue Status. Logics are given below:

QS1 QS0 Operation

0 0 No operation

0 1 1st byte of opcode from queue.

1 0 Empty the queue

1 1 Subsequent byte from queue

S0, S1, S2 (Output): Pin numbers 26, 27, 28 Status Signals. These signals are connected to the bus controller of Intel 8288. This bus

controller generates memory and I/O access control signals. Logics for status signal are given below:

S2 S1 S0 Operation

0 0 0 Interrupt acknowledgement

0 0 1 Read data from I/O port

0 1 0 Write data from I/O port

0 1 1 Halt

1 0 0 Opcode fetch

1 0 1 Memory read

1 1 0 Memory write

1 1 1 Passive state

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LOCK (Output): Pin no. 29. It is an active LOW signal. When this signal is LOW, all interrupts are masked and no HOLD request

is granted. In a multiprocessor system all other processors are informed through this signal that they should not ask the CPU for

relinquishing the bus control.

RG/GT1, RQ/GT0 (Bidirectional): Pin numbers 30, 31, Local Bus Priority Control. Other processors ask the CPU by these lines to

release the local bus.

In the maximum mode of operation signals WR, ALE, DEN, DT/R etc. are not available directly from the processor. These signals

are available from the controller 8288.

Memory Organization in the 8086 Microprocessor

There are 20 address lines in the 8086 microprocessor. This gives us 220 different memory locations. Hence the total size is 220 Bytes

(as each memory location is Byte Addressable, i.e. one byte of data can be stored at every single location), which is equal to 1MB.

Even the memory is byte-addressable, yet the 8086 microprocessor an easily handle up to 16 bits of data at a time through its 16 data

lines. So, to organize the memory efficiently, the entire memory in 8086 is divided into two memory banks: odd bank and the even

bank.

The way in which data is read or written is decided by the value of BHE, and the last address bit, that is the A0 line. It is done in the

following way:

BHE' A0 Operation performed on memory

0 0 16 bits of data will be read or written into the memory

0 1 8 bits of data will be read/written into the odd memory bank

1 0 8 bits of data will be read/written into the even memory bank

1 1 No operation is performed

To read or write 8 bits of data, it would require only 1 CPU cycle, no matter the data is stored in any of the memory banks, but to read

or write 16 bits of data, the BIU of the 8086 may require either 1 or 2 memory cycles depending upon whether the lower byte of word

is located at even or odd memory address.

1. If the lower byte of the word is stored at even memory bank and the upper byte is stored at odd memory bank then the CPU will

require only 1 memory cycle. So, it is better to store data in this way.

2. If the lower byte of the word is located at an odd memory address, then the CPU will require 2 memory cycles. The first memory

cycle is required for accessing the lower byte of the word through the higher data bus, i.e. D15 to D8, and the second memory

cycle is required for accessing the upper byte of the word through the lower data bus, i.e. D7 to D0.

General bus operation of 8086

• The 8086 has a combined address and data bus commonly referred as a time multiplexed address and data bus.

• The main reason behind multiplexing address and data over the same pins is the maximum utilisation of processor pins and it

facilitates the use of 40 pin standard DIP package.

• The bus can be demultiplexed using a few latches and transreceivers, when ever required.

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• Basically, all the processor bus cycles consist of at least four clock cycles. These are referred to as T1, T2, T3, T4. The address

is transmitted by the processor during T1. It is present on the bus only for one cycle.

• The negative edge of this ALE pulse is used to separate the address and the data or status information. In maximum mode, the

status lines S0, S1 and S2 are used to indicate the type of operation.

• Status bits S3 to S7 are multiplexed with higher order address bits and the BHE signal. Address is valid during T1 while status

bits S3 to S7 are valid during T2 through T4.

Maximum mode

• In the maximum mode, the 8086 is operated by strapping the MN/MX pin to ground.

• In this mode, the processor derives the status signal S2, S1, S0. Another chip called bus controller derives the control signal

using this status information.

• In the maximum mode, there may be more than one microprocessor in the system configuration.

Minimum mode

• In a minimum mode 8086 system, the microprocessor 8086 is operated in minimum mode by strapping its MN/MX pin to logic

1.

• In this mode, all the control signals are given out by the microprocessor chip itself.

• There is a single microprocessor in the minimum mode system.

Timing Diagram of Minimum and Maximum Mode 8086

TIMING DIAGRAM of MINIMUM MODE 8086

The HOLD pin is checked at the end of each bus cycle.

If it is received active by the processor before T4 of the previous cycle of during T1 state of the current cycles, the CPU activates HLDA

in the next clock cycle and for the succeeding bus cycles; the bus will be given to another requesting master.

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The control of the bus is not regained by the processor until the requesting master does not drop the HLDA pin low.

When the request is dropped by the requesting master, the HLDA is dropped by the processor at the trailing edge of the next clock, as

shown in Fig

The other conditions have already been discussed in the signal description section for the HOLD and HLDA signals.

TIMING DIAGRAM of MAXIMUM MODE 8086

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Difference between minimum and maximum mode of operation of 8086 microprocessor.

Minimum mode Maximum mode

In minimum mode there can be only one processor i.e. 8086. In maximum mode there can be multiple processors with 8086,

like 8087 and 8089.

MN/MX’ is 1 to indicate minimum mode. MN/MX’ is 0 to indicate maximum mode.

ALE for the latch is given by 8086 as it is the only processor in the

circuit.

ALE for the latch is given by 8288 bus controller as there can

be multiple processors in the circuit.

DEN’ and DT/R’ for the trans-receivers are given by 8086 itself. DEN’ and DT/R’ for the trans-receivers are given by 8288 bus

controller.

Direct control signals M/IO’, RD’ and WR’ are given by 8086. Instead of control signals, each processor generates status signals called S2’, S1’, S0’.

Control signals M/IO’, RD’ and WR’ are decoded by a 3:8 decoder

like 74138.

Status signals S2’, S1’, S0’ are decoded by a bus controller like

8288 to produce control signals.

INTA’ is given by 8086 in response to an interrupt on INTR line. INTA’ is given by 8288 bus controller in response to an

interrupt on INTR line.

HOLD and HLDA signals are used for bus request with a DMA

controller like 8237.

RQ’/GT’, lines are used for bus requests by other processors

like 8087 or 8089.

The circuit is simpler. The circuit is more complex.

Multiprocessing cannot be performed hence performance is lower. As multiprocessing can be performed, it can give very high

performance.

https://2.bp.blogspot.com/-IGW_LriRF9c/Vw0uQ5ufMTI/AAAAAAAAAMs/7xPFuHwnaRc0IzwIRyUsnf9_JegP0WgygCLcB/s1600/Maximum%2Bmode%2Bmemory%2Bread.jpg

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8086 Interrupts

Interrupt is the method of creating a temporary halt during program execution and allows peripheral devices to access the

microprocessor. The microprocessor responds to that interrupt with an ISR (Interrupt Service Routine), which is a short program to

instruct the microprocessor on how to handle the interrupt.

The following image shows the types of interrupts we have in an 8086 microprocessor −

Hardware Interrupts

Hardware interrupt is caused by any peripheral device by sending a signal through a specified pin to the microprocessor.

The 8086 has two hardware interrupt pins, i.e. NMI and INTR. NMI is a non-maskable interrupt and INTR is a maskable interrupt

having lower priority. One more interrupt pin associated is INTA called interrupt acknowledge.

NMI

It is a single non-maskable interrupt pin (NMI) having higher priority than the maskable interrupt request pin (INTR)and it is of type 2

interrupt.

When this interrupt is activated, these actions take place −

• Completes the current instruction that is in progress.

• Pushes the Flag register values on to the stack.

• Pushes the CS (code segment) value and IP (instruction pointer) value of the return address on to the stack.

• IP is loaded from the contents of the word location 00008H.

• CS is loaded from the contents of the next word location 0000AH.

• Interrupt flag and trap flag are reset to 0.

INTR

The INTR is a maskable interrupt because the microprocessor will be interrupted only if interrupts are enabled using set interrupt flag

instruction. It should not be enabled using clear interrupt Flag instruction.

The INTR interrupt is activated by an I/O port. If the interrupt is enabled and NMI is disabled, then the microprocessor first completes

the current execution and sends ‘0’ on INTA pin twice. The first ‘0’ means INTA informs the external device to get ready and during

the second ‘0’ the microprocessor receives the 8 bit, say X, from the programmable interrupt controller.

These actions are taken by the microprocessor −

• First completes the current instruction.

• Activates INTA output and receives the interrupt type, say X.

• Flag register value, CS value of the return address and IP value of the return address are pushed on to the stack.

• IP value is loaded from the contents of word location X × 4

• CS is loaded from the contents of the next word location.

• Interrupt flag and trap flag is reset to 0

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Software Interrupts

Some instructions are inserted at the desired position into the program to create interrupts. These interrupt instructions can be used to

test the working of various interrupt handlers. It includes −

INT- Interrupt instruction with type number

It is 2-byte instruction. First byte provides the op-code and the second byte provides the interrupt type number. There are 256

interrupt types under this group.

Its execution includes the following steps −

• Flag register value is pushed on to the stack.

• CS value of the return address and IP value of the return address are pushed on to the stack.

• IP is loaded from the contents of the word location ‘type number’ × 4


• Interrupt Flag and Trap Flag are reset to 0

The starting address for type0 interrupt is 000000H, for type1 interrupt is 00004H similarly for type2 is 00008H and ……so on. The

first five pointers are dedicated interrupt pointers. i.e. −

• TYPE 0 interrupt represents division by zero situation.

• TYPE 1 interrupt represents single-step execution during the debugging of a program.

• TYPE 2 interrupt represents non-maskable NMI interrupt.

• TYPE 3 interrupt represents break-point interrupt.

• TYPE 4 interrupt represents overflow interrupt.

The interrupts from Type 5 to Type 31 are reserved for other advanced microprocessors, and interrupts from 32 to Type 255 are

available for hardware and software interrupts.

INT 3-Break Point Interrupt Instruction

It is a 1-byte instruction having op-code is CCH. These instructions are inserted into the program so that when the processor reaches

there, then it stops the normal execution of program and follows the break-point procedure.


• Flag register value is pushed on to the stack.


• IP is loaded from the contents of the word location 3×4 = 0000CH


• Interrupt Flag and Trap Flag are reset to 0

INTO - Interrupt on overflow instruction

It is a 1-byte instruction and their mnemonic INTO. The op-code for this instruction is CEH. As the name suggests it is a conditional

interrupt instruction, i.e. it is active only when the overflow flag is set to 1 and branches to the interrupt handler whose interrupt type

number is 4. If the overflow flag is reset then, the execution continues to the next instruction.


• Flag register values are pushed on to the stack.


• IP is loaded from the contents of word location 4×4 = 00010H


• Interrupt flag and Trap flag are reset to 0

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8086 Addressing Modes

The different ways in which a source operand is denoted in an instruction is known as addressing modes. There are 8 different

addressing modes in 8086 programming −

1. Immediate addressing mode

The addressing mode in which the data operand is a part of the instruction itself is known as immediate addressing mode.

Example: -

MOV CX, 4929 H

ADD AX, 2387 H

MOV AL, FFH

2. Register addressing mode

It means that the register is the source of an operand for an instruction.

Example: -

MOV CX, AX; Moves the contents of the 16-bit AX register into the 16-bit CX register),

ADD BX, AX

3. Direct addressing mode

The addressing mode in which the effective address of the memory location is written directly in the instruction.

Example: -

MOV AX, [1592H]

MOV AL, [0300H]

4. Register indirect addressing mode

This addressing mode allows data to be addressed at any memory location through an offset address held in any of the following

registers: BP, BX, DI & SI.

Example: -

MOV AX, [BX]; Suppose the register BX contains 4895H, then the contents 4895H are moved to AX

ADD CX, {BX}

5. Based addressing mode

In this addressing mode, the offset address of the operand is given by the sum of contents of the BX/BP registers and 8-bit/16-bit

displacement.

Example: -

MOV DX, [BX+04]

ADD CL, [BX+08]

6. Indexed addressing mode

In this addressing mode, the operands offset address is found by adding the contents of SI or DI register and 8-bit/16-bit

displacements.

Example: -

MOV BX, [SI+16]

ADD AL, [DI+16]

7. Based-index addressing mode

In this addressing mode, the offset address of the operand is computed by summing the base register to the contents of an Index

register.

Example: -

ADD CX, [AX+SI]

MOV AX, [AX+DI]

8. Based indexed with displacement mode

In this addressing mode, the operands offset is computed by adding the base register contents. An Index registers contents and 8

or 16-bit displacement.

Example: -

MOV AX, [BX+DI+08]

ADD CX, [BX+SI+16]

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8086 Instruction Sets

The 8086 microprocessor supports 8 types of instructions −

• Data Transfer Instructions

• Arithmetic Instructions

• Bit Manipulation Instructions

• String Instructions

• Program Execution Transfer Instructions (Branch & Loop Instructions)

• Processor Control Instructions

• Iteration Control Instructions

• Interrupt Instructions

Let us now discuss these instruction sets in detail.

1. Data Transfer Instructions

These instructions are used to transfer the data from the source operand to the destination operand. Following are the list of

instructions under this group −

Instruction to transfer a word

• MOV − Used to copy the byte or word from the provided source to the provided destination.

• PPUSH − Used to put a word at the top of the stack.

• POP − Used to get a word from the top of the stack to the provided location.

• PUSHA − Used to put all the registers into the stack.

• POPA − Used to get words from the stack to all registers.

• XCHG − Used to exchange the data from two locations.

• XLAT − Used to translate a byte in AL using a table in the memory.

Instructions for input and output port transfer

• IN − Used to read a byte or word from the provided port to the accumulator.

• OUT − Used to send out a byte or word from the accumulator to the provided port.

Instructions to transfer the address

• LEA − Used to load the address of operand into the provided register.

• LDS − Used to load DS register and other provided register from the memory

• LES − Used to load ES register and other provided register from the memory.

Instructions to transfer flag registers

• LAHF − Used to load AH with the low byte of the flag register.

• SAHF − Used to store AH register to low byte of the flag register.

• PUSHF − Used to copy the flag register at the top of the stack.

• POPF − Used to copy a word at the top of the stack to the flag register.

2. Arithmetic Instructions

These instructions are used to perform arithmetic operations like addition, subtraction, multiplication, division, etc.

Following is the list of instructions under this group −

Instructions to perform addition

• ADD − Used to add the provided byte to byte/word to word.

• ADC − Used to add with carry.

• INC − Used to increment the provided byte/word by 1.

• AAA − Used to adjust ASCII after addition.

• DAA − Used to adjust the decimal after the addition/subtraction operation.

Instructions to perform subtraction

• SUB − Used to subtract the byte from byte/word from word.

• SBB − Used to perform subtraction with borrow.

• DEC − Used to decrement the provided byte/word by 1.

• NPG − Used to negate each bit of the provided byte/word and add 1/2’s complement.

• CMP − Used to compare 2 provided byte/word.

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• AAS − Used to adjust ASCII codes after subtraction.

• DAS − Used to adjust decimal after subtraction.

Instruction to perform multiplication

• MUL − Used to multiply unsigned byte by byte/word by word.

• IMUL − Used to multiply signed byte by byte/word by word.

• AAM − Used to adjust ASCII codes after multiplication.

Instructions to perform division

• DIV − Used to divide the unsigned word by byte or unsigned double word by word.

• IDIV − Used to divide the signed word by byte or signed double word by word.

• AAD − Used to adjust ASCII codes after division.

• CBW − Used to fill the upper byte of the word with the copies of sign bit of the lower byte.

• CWD − Used to fill the upper word of the double word with the sign bit of the lower word.

3. Bit Manipulation Instructions

These instructions are used to perform operations where data bits are involved, i.e. operations like logical, shift, etc.


Instructions to perform logical operation

• NOT − Used to invert each bit of a byte or word.

• AND − Used for adding each bit in a byte/word with the corresponding bit in another byte/word.

• OR − Used to multiply each bit in a byte/word with the corresponding bit in another byte/word.

• XOR − Used to perform Exclusive-OR operation over each bit in a byte/word with the corresponding bit in another

byte/word.

• TEST − Used to add operands to update flags, without affecting operands.

Instructions to perform shift operations

• SHL/SAL − Used to shift bits of a byte/word towards left and put zero(S) in LSBs.

• SHR − Used to shift bits of a byte/word towards the right and put zero(S) in MSBs.

• SAR − Used to shift bits of a byte/word towards the right and copy the old MSB into the new MSB.

Instructions to perform rotate operations

• ROL − Used to rotate bits of byte/word towards the left, i.e. MSB to LSB and to Carry Flag [CF].

• ROR − Used to rotate bits of byte/word towards the right, i.e. LSB to MSB and to Carry Flag [CF].

• RCR − Used to rotate bits of byte/word towards the right, i.e. LSB to CF and CF to MSB.

• RCL − Used to rotate bits of byte/word towards the left, i.e. MSB to CF and CF to LSB.

4. String Instructions

String is a group of bytes/words and their memory is always allocated in a sequential order.


• REP − Used to repeat the given instruction till CX ≠ 0.

• REPE/REPZ − Used to repeat the given instruction until CX = 0 or zero flag ZF = 1.

• REPNE/REPNZ − Used to repeat the given instruction until CX = 0 or zero flag ZF = 1.

• MOVS/MOVSB/MOVSW − Used to move the byte/word from one string to another.

• COMS/COMPSB/COMPSW − Used to compare two string bytes/words.

• INS/INSB/INSW − Used as an input string/byte/word from the I/O port to the provided memory location.

• OUTS/OUTSB/OUTSW − Used as an output string/byte/word from the provided memory location to the I/O port.

• SCAS/SCASB/SCASW − Used to scan a string and compare its byte with a byte in AL or string word with a word in AX.

• LODS/LODSB/LODSW − Used to store the string byte into AL or string word into AX.

5. Program Execution Transfer Instructions (Branch and Loop Instructions)

These instructions are used to transfer/branch the instructions during an execution. It includes the following instructions −

Instructions to transfer the instruction during an execution without any condition −

• CALL − Used to call a procedure and save their return address to the stack.

• RET − Used to return from the procedure to the main program.

• JMP − Used to jump to the provided address to proceed to the next instruction.

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Instructions to transfer the instruction during an execution with some conditions −

• JA/JNBE − Used to jump if above/not below/equal instruction satisfies.

• JAE/JNB − Used to jump if above/not below instruction satisfies.

• JBE/JNA − Used to jump if below/equal/ not above instruction satisfies.

• JC − Used to jump if carry flag CF = 1

• JE/JZ − Used to jump if equal/zero flag ZF = 1

• JG/JNLE − Used to jump if greater/not less than/equal instruction satisfies.

• JGE/JNL − Used to jump if greater than/equal/not less than instruction satisfies.

• JL/JNGE − Used to jump if less than/not greater than/equal instruction satisfies.

• JLE/JNG − Used to jump if less than/equal/if not greater than instruction satisfies.

• JNC − Used to jump if no carry flag (CF = 0)

• JNE/JNZ − Used to jump if not equal/zero flag ZF = 0

• JNO − Used to jump if no overflow flag OF = 0

• JNP/JPO − Used to jump if not parity/parity odd PF = 0

• JNS − Used to jump if not sign SF = 0

• JO − Used to jump if overflow flag OF = 1

• JP/JPE − Used to jump if parity/parity even PF = 1

• JS − Used to jump if sign flag SF = 1

6. Processor Control Instructions

These instructions are used to control the processor action by setting/resetting the flag values.

Following are the instructions under this group −

• STC − Used to set carry flag CF to 1

• CLC − Used to clear/reset carry flag CF to 0

• CMC − Used to put complement at the state of carry flag CF.

• STD − Used to set the direction flag DF to 1

• CLD − Used to clear/reset the direction flag DF to 0

• STI − Used to set the interrupt enable flag to 1, i.e., enable INTR input.

• CLI − Used to clear the interrupt enable flag to 0, i.e., disable INTR input.

7. Iteration Control Instructions

These instructions are used to execute the given instructions for number of times. Following is the list of instructions under this

group

• LOOP − Used to loop a group of instructions until the condition satisfies, i.e., CX = 0

• LOOPE/LOOPZ − Used to loop a group of instructions till it satisfies ZF = 1 & CX = 0

• LOOPNE/LOOPNZ − Used to loop a group of instructions till it satisfies ZF = 0 & CX = 0

• JCXZ − Used to jump to the provided address if CX = 0

8. Interrupt Instructions

These instructions are used to call the interrupt during program execution.

• INT − Used to interrupt the program during execution and calling service specified.

• INTO − Used to interrupt the program during execution if OF = 1

• IRET − Used to return from interrupt service to the main program

NOTE: -

Video Lecture-8086 Microprocessor Lecture Series

(https://www.youtube.com/watch?v=0KZzpGsIAgQ&list=PLiQ6yyBxf5MqT1ggQ1u1Te3b2Y4KZKumg)

https://www.youtube.com/watch?v=0KZzpGsIAgQ&list=PLiQ6yyBxf5MqT1ggQ1u1Te3b2Y4KZKumg

25 | P a g e

Unit-6 Microcontroller (Architecture and Programming-8 bit)

What is Microcontroller?

A microcontroller is a chip optimized to control electronic devices. It is stored in a single integrated circuit which is dedicated to

performing a particular task and execute one specific application.

It is specially designed circuits for embedded applications and is widely used in automatically controlled electronic devices. It contains

memory, processor, and programmable I/O.

Types of Microcontroller

Here are important types of Microcontroller:

• 8-bit microcontroller − This type of microcontroller is used to execute arithmetic and logical operations like addition, subtraction, multiplication division, etc. For example, Intel 8031 and 8051 are 8 bits microcontroller.

• 16-bit microcontroller − This type of microcontroller is used to perform arithmetic and logical operations where higher accuracy and performance is required. For example, Intel 8096 is a 16-bit microcontroller.

• 32-bit microcontroller − This type of microcontroller is generally used in automatically controlled appliances like automatic operational machines, medical appliances, etc.

• Embedded Microcontroller

• External memory Microcontroller

History of Microcontroller

Here, are important landmarks from the history of Microcontroller:

• First used in 1975(Intel 8048)

• The introduction of EEPROM in 1993

• The same year, Atmel introduced the first microcontroller using Flash memory.

Features of Microcontroller

Here are some important features of Microcontroller:

• Processor reset

• Program and Variable Memory (RAM) I/O pins

• Device clocking central processor

• Instruction cycle timers

Applications of Microcontrollers

Microcontrollers are widely used in various different devices such as −

• Light sensing and controlling devices like LED.

• Temperature sensing and controlling devices like microwave oven, chimneys.

• Fire detection and safety devices like Fire alarm.

• Measuring devices like Volt Meter.

KEY DIFFERENCES:

• Microprocessor consists of only a Central Processing Unit, whereas Micro Controller contains a CPU, Memory, I/O all integrated

into one chip.

• Microprocessor is used in Personal Computers whereas Micro Controller is used in an embedded system.

• Microprocessor uses an external bus to interface to RAM, ROM, and other peripherals, on the other hand, Microcontroller uses

an internal controlling bus.

• Microprocessors are based on Von Neumann model Micro controllers are based on Harvard architecture

• Microprocessor is complicated and expensive, with a large number of instructions to process but Microcontroller is inexpensive

and straightforward with fewer instructions to process.

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Difference between Microprocessor & Microcontroller

Microprocessor Microcontroller

Microprocessor is the heart of Computer system. Micro Controller is the heart of an embedded system.

It is only a processor, so memory and I/O components need to be

connected externally

Micro Controller has a processor along with internal memory and

I/O components.

Memory and I/O has to be connected externally, so the circuit

becomes large. Memory and I/O are already present, and the internal circuit is small.

You can't use it in compact systems You can use it in compact systems.

Cost of the entire system is high Cost of the entire system is low

Due to external components, the total power consumption is high.

Therefore, it is not ideal for the devices running on stored power like

batteries.

As external components are low, total power consumption is less. So

it can be used with devices running on stored power like batteries.

Most of the microprocessors do not have power saving features. Most of the microcontrollers offer power-saving mode.

It is mainly used in personal computers. It is used mainly in a washing machine, MP3 players, and embedded

systems.

Microprocessor has a smaller number of registers, so more

operations are memory-based.

Microcontroller has more register. Hence the programs are easier to

write.

Microprocessors are based on Von Neumann model Micro controllers arc based on Harvard architecture

It is a central processing unit on a single silicon-based integrated

chip.

It is a byproduct of the development of microprocessors with a CPU

along with other peripherals.

It has no RAM, ROM, Input-Output units, timers, and other

peripherals on the chip.

It has a CPU along with RAM, ROM, and other peripherals

embedded on a single chip.

It uses an external bus to interface to RAM, ROM, and other

peripherals. It uses an internal controlling bus.

Microprocessor-based systems can run at a very high speed because

of the technology involved.

Microcontroller based systems run up to 200MHz or more depending

on the architecture.

It's used for general purpose applications that allow you to handle

loads of data. It's used for application-specific systems.

It's complex and expensive, with a large number of instructions to

process.

It's simple and inexpensive with less number of instructions to

process.

Difference Between 8bit Microcontroller and 16bit Microcontroller

What is 8bit Microcontroller?

8bit microcontroller is type of microcontroller having all traits of microcontroller and its information gadgets are largely 8 bits big. 8

bits big means your CPU can use 8bit information bus or pipe and can entry the similar dimension information by a single machine

instruction. For every cycle of instruction, it fluctuate is zero to 255. It requires 20mA current to work. Intel 8008 was the first model

having 8bit micro-controller.

What is 16bit Microcontroller?

16bit microcontroller is additional superior than 8bit microcontroller. It is additional right and precise in performing mathematical and

technical duties. Unlike 8bit microcontroller it makes use of 16 bits information bus or pipe for a single instruction. For every cycle of

instruction its bit fluctuate is extended from zero to 65,535. As 16bit controller is 2 time better than 8bit controller, it would probably

work on two 16bit numbers. It requires 10mA current to hold out.

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Key Differences

1. First is on worth. Although as a consequence of enhancement in design worth comparability between two has been lowered

nevertheless nonetheless 8bit microcontroller is cheaper than 16bit microcontroller.

2. Having 16bit microcontroller means 16 bus or pipe to carry on information which is 2 time better than 8bit microcontroller.

3. Due to large bus 16bit can perform additional successfully and fast as consider to 16bit microcontroller.

4. In performing mathematical capabilities, 16bit microcontroller is additional right and reliable than 8bit microcontroller.

5. For every cycle of instruction, 8bit fluctuate is zero to 255 whereas 16bit has fluctuate of zero to 65535 for every cycle.

6. Although 16bit microcontroller reveals double cycle or clock time than 8bit nevertheless having fast time clock means additional

energy and vitality will seemingly be required to hold out.

7. 8bit microcontroller requires 20 mA current to work, which is 2 time better than the current requirement of 16bit microcontroller,

which requires 10 mA.

8. Input and Output peripherals of 16 bit are additional advance than 8bit microcontroller.

9. 8bit microcontroller reveals velocity of 12 MIPS at 48 MHz whereas 16 bit reveals most 16 MIPS at 32 MHz, two time better

than 8bit microcontroller.

Difference between RISC and CISC processor

A microprocessor is a processing unit on a single chip. It is an integrated circuit which performs the core functions of a computer

CPU. It is a multipurpose programmable silicon chip constructed using Metal Oxide Semiconductor (MOS) technology which is clock

driven and register based. It accepts binary data as input and provides output after processing it as per the specification of instructions

stored in the memory. These microprocessors are capable of processing 128 bits at a time at the speed of one billion instructions per

second.

Characteristics of a microprocessor:

• Instruction Set – Set of complete instructions that the microprocessor executes is termed as the instruction set.

• Word Length – The number of bits processed in a single instruction is called word length or word size. Greater the word size,

larger the processing power of the CPU.

• System Clock Speed – Clock speed determines how fast a single instruction can be executed in a processor. The

microprocessor’s pace is controlled by the System Clock. Clock speeds are generally measured in million of cycles per second

(MHz) and thousand millions of cycles per second (GHz). Clock speed is considered to be a very important aspect of predicting

the performance of a processor.

Classification of Microprocessors:

Besides the classification based on the word length, the classification is also based on the architecture i.e. Instruction Set of the

microprocessor. These are categorised into RISC and CISC.

1. RISC:

It stands for Reduced Instruction Set Computer. It is a type of microprocessor architecture that uses a small set of instructions

of uniform length. These are simple instructions which are generally executed in one clock cycle. RISC chips are relatively

simple to design and inexpensive.The setback of this design is that the computer has to repeatedly perform simple operations to

execute a larger program having a large number of processing operations.

Examples: SPARC, POWER PC etc.

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2. CISC:

It stands for Complex Instruction Set Computer. These processors offer the users, hundreds of instructions of variable sizes.

CISC architecture includes a complete set of special purpose circuits that carry out these instructions at a very high speed. These

instructions interact with memory by using complex addressing modes. CISC processors reduce the program size and hence

lesser number of memory cycles are required to execute the programs. This increases the overall speed of execution.

Examples: Intel architecture, AMD

3. EPIC:

It stands for Explicitly Parallel Instruction Computing. The best features of RISC and CISC processors are combined in the

architecture. It implements parallel processing of instructions rather than using fixed length instructions. The working of EPIC

processors are supported by using a set of complex instructions that contain both basic instructions as well as the information of

execution of parallel instructions. It substantially increases the efficiency of these processors.

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Below are few differences between RISC and CISC:

CISC RISC

A large number of instructions are present in the

architecture.

Very fewer instructions are present. The number of instructions are

generally less than 100.

Some instructions with long execution times. These include

instructions that copy an entire block from one part of

memory to another and others that copy multiple registers to

and from memory.

No instruction with a long execution time due to very simple

instruction set. Some early RISC machines did not even have an

integer multiply instruction, requiring compilers to implement

multiplication as a sequence of additions.

Variable-length encodings of the instructions.

Example: IA32 instruction size can range from 1 to 15

bytes.

Fixed-length encodings of the instructions are used.

Example: In IA32, generally all instructions are encoded as 4 bytes.

Multiple formats are supported for specifying operands. A

memory operand specifier can have many different

combinations of displacement, base and index registers.

Simple addressing formats are supported. Only base and

displacement addressing is allowed.

CISC supports array. RISC does not support array.

Arithmetic and logical operations can be applied to both

memory and register operands.

Arithmetic and logical operations only use register operands.

Memory referencing is only allowed by load and store instructions,

i.e. reading from memory into a register and writing from a register

to memory respectively.

Implementation programs are hidden from machine level

programs. The ISA provides a clean abstraction between

programs and how they get executed.

Implementation programs exposed to machine level programs. Few

RISC machines do not allow specific instruction sequences.

Condition codes are used. No condition codes are used.

The stack is being used for procedure arguments and return

addresses.

Registers are being used for procedure arguments and return

addresses. Memory references can be avoided by some procedures.

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8051 Microcontroller Architecture

Oscillator and clock generator:

All operations in a microcontroller are synchronized by the help of an oscillator clock. The oscillator clock generates the clock pulses

by which all internal operations are synchronized. A resonant network connected through pins XTAL1 and XTAL2 forms up an

oscillator. For this purpose, a quartz crystal and capacitors are employed. The crystal run at specified maximum and minimum

frequencies typically at 1 MHz to 16 MHz.

ALU:

It is 8bit unit. It performs arithmetic operation as addition, subtraction, multiplication, division, increment and decrement. It performs

logical operations like AND, OR and EX-OR. It manipulates 8bit and 16bit data. It calculates address of jump locations in relative

branch instruction. It performs compare, rotate and compliment operations. It consists of Boolean processor which performs bit, set,

test, clear and compliment. 8051 micro controller contains 34 general purpose registers or working registers.2 of them are called math

registers A & B and 32 are bank of registers.

a. Accumulator(A-reg):

It is 8 bit register. Its address is E0H and it is bit and byte accessible. Result of arithmetic & logic operations performed by ALU is

accumulated by this register. Therefore, it is called accumulator register. It is used to store 8-bit data and to hold one of operand of

ALU units during arithmetical and logical operations. Most of the instructions are carried out on accumulator data. It is most versatile

of 2 CPU registers.

b. B-register:

It is special 8-bit math register. It is bit and byte accessible. It is used in conjunction with A register as I/P operand for ALU. It is used

as general purpose register to store 8-bit data.

c. PSW:

It is 8-bit register. Its address is D0H and It is bit and byte accessible. It has 4 conditional flags or math flags which sets or resets

according to condition of result. It has 3 control flags, by setting or resetting bit required operation or function can be achieved. The

format of flag register is as shown below:

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i. MATH FLAG:

1. Carry Flag (CY): During addition and subtraction any carry or borrow is generated then carry flag is set otherwise carry flag

resets. It is used in arithmetic, logical, jump, rotate and Boolean operations.

2. Auxiliary carry flag (AC): If during addition and subtraction any carry or borrow is generated from lower 4 bit to higher 4 bit

then AC sets else it resets. It is used in BCD arithmetic operations.

3. Overflow flag (OV): If in signed arithmetic operations result exceeds more than 7 bits than OV flag sets else resets. It is used

in signed arithmetic operations only.

4. Parity flag(P): If in result, even no. Of ones "1" are present than it is called even parity and parity flag sets. In result odd no. Of

ones "1"are present than it is called odd parity and parity flag resets.

ii. CONTROL FLAGS:

1. FO: It is user defined flag. The user defines the function of this flag. The user can set, test n clears this flag through software.

2. RS1 and RS0: These flags are used to select bank of register by resetting those flags.

3. Program counter (PC): The Program Counter (PC) is a 2-byte address which tells the 8051 where the next instruction to execute

is found in memory. It is used to hold 16-bit address of internal RAM, external RAM or external ROM locations. When the 8051

is initialized PC always starts at 0000h and is incremented each time an instruction is executed. It is important to note that PC is

not always incremented by one and never decremented.

4. Data pointer register (DTPR): It is a 16-bit register used to hold address of external or internal RAM where data is stored or

result is to be stored. It is used to store 16-bit data. It is divided into2- 8bit registers, DPH-data pointer higher order (83H) and

DPL-data pointer lower order (82H). Each register can be used as general purpose register to store 8-bit data and can also be

used as memory location. DPTR does not have single internal address. It functions as Base register in base relative addressing

mode and in-direct jump.

5. Stack pointer (SP): It is 8-bit register. It is byte addressable. Its address is 81H. It is used to hold the internal RAM memory

location addresses which are used as stack memory. When the data is to be placed on stack by push instruction, the content of

stack pointer is incremented by 1, and when data is retrieved from stack, content of stack of stack pointer is decremented by 1.

iii. Special function Registers (SFR): The 8051 microcontroller has 11 SFR divided in 4 groups:

A. Timer/Counter register: 8051 microcontroller has 2-16-bit Timer/counter registers called Timer-reg-T0 And Timer/counter

Reg-T1. Each register is 16-bit register divide into lower and higher byte register as shown below: These registers are used to

hold initial no. of count. All of the 4 register are byte addressable.

1. Timer control register: 8051 microcontroller has two 8-bit timer control register i.e. TMOD and TCON register. TMOD

Register: it is 8-bit register. Its address is 89H. It is byte addressable. It used to select mode and control operation of time by

writing control word.

2. TCON register: It is 8-bit register. Its address is 88H. It is byte addressable. Its MSB 4-bit are used to control operation of

timer/ counter and LSB 4-bit are used for external interrupt control.

B. Serial data register: 8051 micro controller has 2 serial data register viz. SBUF and SCON.

1. Serial buffer register (SBUF): it is 8-bit register. It is byte addressable. Its address is 99H. It is used to hold data which is

to be transferred serially.

2. Serial control register (SCON): it is 8-bit register. It is bit/byte addressable. Its address is 98H. The 8-bit loaded into this

register controls the operation of serial communication.

C. Interrupt register: 8051 µC has 2 8-bit interrupt register.

1. Interrupt enable register (IE): it is 8-bit register. It is bit/byte addressable. Its address is A8H.it is used to enable and

disable function of interrupt.

2. Interrupt priority register (IP): It is 8-bit register. It is bit/byte addressable. Its address is B8H. it is used to select low- or

high-level priority of each individual interrupts.

D. Power control register (PCON): it is 8-bit register. It is byte addressable. Its address is 87H. its bits are used to control mode

of power saving circuit, either idle or power down mode and also one bit is used to modify baud rate of serial communication.

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Internal RAM

Internal RAM has memory 128-byte. See 8051 hardware for further internal RAM design. Internal RAM is organized into three distinct

areas: 32 bytes working registers from address 00h to 1Fh 16 bytes bit addressable occupies RAM byte address 20h to 2Fh, altogether

128 addressable bits General purpose RAM from 30h to 7Fh.

Internal ROM

Data memory and program code memory both are in different physical memory but both have the same addresses. An internal ROM

occupied addresses from 0000h to 0FFFh. PC addresses program codes from 0000h to 0FFFh. Program addresses higher than 0FFFh

that exceed the internal ROM capacity will cause 8051 architecture to fetch codes bytes from external program memory.

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8051 Pin Description

The pin diagram of 8051 microcontroller looks as follows –

• Pins 1 to 8 − These pins are known as Port 1. This port doesn’t serve any other functions. It is internally pulled up, bi-directional

I/O port.

• Pin 9 − It is a RESET pin, which is used to reset the microcontroller to its initial values.

• Pins 10 to 17 − These pins are known as Port 3. This port serves some functions like interrupts, timer input, control signals,

serial communication signals RxD and TxD, etc.

• Pins 18 & 19 − These pins are used for interfacing an external crystal to get the system clock.

• Pin 20 − This pin provides the power supply to the circuit.

• Pins 21 to 28 − These pins are known as Port 2. It serves as I/O port. Higher order address bus signals are also multiplexed

using this port.

• Pin 29 − This is PSEN pin which stands for Program Store Enable. It is used to read a signal from the external program memory.

• Pin 30 − This is EA pin which stands for External Access input. It is used to enable/disable the external memory interfacing.

• Pin 31 − This is ALE pin which stands for Address Latch Enable. It is used to demultiplex the address-data signal of port.

• Pins 32 to 39 − These pins are known as Port 0. It serves as I/O port. Lower order address and data bus signals are multiplexed

using this port.

• Pin 40 − This pin is used to provide power supply to the circuit.

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Internal Data Memory Organization of Intel 8051

The internal data memory of 8051 is divided into two groups. These are a set of eight registers and a scratch pad memory. These eight

registers are R0 toR7. The address range 00H to 07H is used to access the registers, and the rest are scratch pad memory.

8051 Provides four register bank, but only one register bank can be used at any point in time. To select the register bank, two bits of

PSW (Program Status Word) are used.

So, the following addressing can be used to select register banks.

Address Range Register Bank

00H to 07H Register Bank 0

08H to 0FH Register Bank 1

10H to 17H Register Bank 2

18H to 1FH Register Bank 3

The concept of four register banks is very useful. For servicing the interrupts, this feature is very good. The interrupt program can use

one bank, and the interrupt Service Subroutine (ISS) can access another bank for better performance. As there are four banks, so for

nested interrupts these can be used

When all of the register banks are being used, the scratch pad area will be 20H to 7FH. But from 20H to 2FH (16 bytes or 128 bits) can

be used as bit addressable RAM. By using some simple instructions with 8-bit memory address we can check the bit addressing. For

an example the instruction CLR 6FH, using this instruction it clears the location 6FH. As we know the8-bit address can locate 256

different locations, but here only128-bits are addressable. Another section of bit addressable locations is 80H to FFH. The remaining

locations (30H to 7EH) of the RAM can be used to store variable data and stack.

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Stack Area

The stack area in 8051always can be implemented in the internal data memory. Here the stack pointer (SP) is an only 8-bit register,

because the internal RAM area is only in range 00H to 7FH, and when all register banks are being used, the stack location will be in

range 30H to 7FH. So in such a case, the SP will be initialized with 2FH.

The stack pointer SP increases before each PUSH operation and decreases after each pop instruction.

When the 8051 is reset, the Stack Pointer will point to 07H. It means the location 08H to 7FHcan be used as a stack. We are assuming

that the register bank 0 is in use and 20H to 27H are not like bit-addressable area.

Register Bank in the 8051

Manufacturer allotted 32 bytes for Register Banks. These 32 bytes are divided into 4 banks of registers in which each bank has 8

registers, named as RO-R7. Each register it takes 1 byte. So, each bank occupies 8 bytes.

Bank 1 uses the same ram space as the stack. Register bank 0 is the default when the 8051 is powered up. We can switch to other banks

by use of the PSW (Program status word) register. PSW is one of the SFR (Special Function Register) and also this one is bit addressable

register. So, we can access bit addressable instructions SETB and CLR. In this register PSW.3 and PSW.4 bits are used to select the

desired register bank as shown in below table.

If we are using CLR PSW.x instruction then it makes zero value in that particular bit, and if we are using SETB PSW.x instruction then

one (1) value passes in that particular bit. Where ‘x’ represents either 3 (or) 4

Special Function Registers (SFRS) Memory Organization Of 8051

1) Special Function Registers (SFRs) are areas of memory that control specific functionality of the 8051 processor. SFRs are accessed

as if they were normal Internal RAM. The only difference is that Internal RAM is from address 00H through 7FH whereas SFR registers

exist in the address range of 80H through FFH. Each SFR has an address (80H through FFH) and a name.

2) SFRs related to the I/O ports. The 8051 has four I/O ports of 8 bits, for a total of 32 I/O lines. Whether a given I/O line is high or

low and the value read from the line are controlled by these SFRs.

3)Total SFR memory is 128 bytes in that manufacturer allotted 21 bytes for 21 register Each and every register is used for some specific

application. That’s why these registers called as a Special Function Registers.

4)In total 21 SFRs only 11 SFRs are Bit — Addressable SFRs and these SFRs also Byte Addressable SFRs

5)Total 21 SFRs are Byte Addressable Registers.

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6)SFRs which in some way control the operation or the configuration of some aspect of the 8051.For example, TCON controls the

timers, SCON controls the serial port. The remaining SFRs are that they don't directly configure the 8051 but obviously the 8051 cannot

operate without them. For example, once the serial port has been configured using SCON, the program may read or write to the serial

port using the SBUF register.

PORT 0, PORT1, PORT2, PORT3 (BIT-ADDRESSABLE Registers)

PORT O is input/output port 0. Each bit of this SFR corresponds to one of the pins on the microcontroller. For example, bit 0 of port 0

is pin PO0.0, bit’ 7 is pin PO.7. Writing a value of 1 to a bit of this SFR will send a high level on the corresponding I/O pin whereas a

value of 0 will bring it to a low level like PORT1(P1),PORT2(P2),PORT3(P3) also having same operation, addresses are different those

are available in above table.

SP (STACK POINTER, ADDRESS 81H)

SP means Stack Pointer used to access the stack. This SFR indicates where the next value to be taken from the stack will be read from

in Internal RAM. If we push a value onto the stack, the value will be written to the address of SP + 1. chat is to say, if SP holds the

value 07H, a PUSH instruction will push the value onto the stack at address 08H. This SFR is modified by all instructions, which

modify the stack, such as PUSH, POP, and LCALL, RET, RETI, and whenever interrupts are provoked by the micro controller.

DPL/DPH (DATA POINTER LOW/HIGH, ADDRESS 82H/83H)

The SFRs DPL and DPH work together to represent a 16-bit value called the Data Pointer. The data pointer is used in operations

regarding external RAM and some instructions involving code memory. Since it is an unsigned two-byte integer value, it can represent

values from 0000H to FFFFH (0 through 65,535 decimal).

PCON (POWER CONTROL, ADDRESS 87H)

The Power Control SFR is used to control the 8051's power control modes. Additionally, one of the bits in PCON is used to double the

effective baud rate of the 8051's serial port.

TCON (TIMER CONTROL, ADDRESS 88H, BIT-ADDRESSABLE) of 8051

The Timer Control SFR is used to configure and modify the way in which the 8051's two timers operate. This SFR controls whether

each of the two timers is running or stopped and contains a flag to indicate that each timer has overflowed. Additionally, some non-

timer related bits are located in the TCON SFR. These bits are used to configure the way in which the external interrupts are activated

and also contain the external interrupt flags which are set when an externa

Unit-4 Microprocessor Based System Development...

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