Digital ElectronicsDigital Electronics

Flip-Flops

Objectives

• Draw the symbol for the D-Latch and D Flip Flop.

• Given a D flip flop and input waveforms, draw the

output waveform for Q.

• Given a J-K flip flop and input waveforms, draw

the output waveform for Q.

• Define “Asynchronous” and “Synchronous”.

• Given a J-K flip flop, identify the synchronous

and asynchronous inputs.

FLIP-FLOP TYPESRS FLIP FLOP (Reset/Set) a.k.a. Set/Clear

•Most basic flip flop can be made by cross coupling NAND or NOR gates

•Activating Set and Reset is invalid

T Flip Flop (Toggle)

•Output toggles on each clock pulse

•Q output divides clock frequency in half

D Flip Flop (Data or Delay)

•Has only a single data input and clock input

•Input transfers to output on clock pulse

J-K Flip Flop

•Universal, can make all other flip flops

•Has no prohibited states

S

R

CLK

Q

Q

CLK

D Q

Q

T

Q

Q

J

K

CLK

Q

Q

POSITIVE LEVEL TRIGGEREDD FLIP-FLOP

Q

Q NOT

D

CLK

D

CLK

Symbol:

Truth Table:

POSITIVE LEVEL TRIGGEREDD FLIP-FLOP

TIMING DIAGRAMS

POSITIVE EDGE TRIGGEREDD FLIP-FLOP

TIMING DIAGRAMS

NEGATIVE EDGE TRIGGEREDT FLIP-FLOP Symbol:

Truth Table:

•Output toggles on each clock pulse

•Q output divides clock frequency in half

•Usually made with JK Flip Flop

CLK Q

Q O

MEANS THAT THE NEW VALUE OF Q WILL BE THEINVERSE OF THE VALUE IT HAD PRIOR TO THE NGT

Q OQ=

NEGATIVE EDGE TRIGGEREDT FLIP-FLOP

Timing Diagrams

T

Q

T

Q

J-K FLIP-FLOP

•UNIVERSAL Flip Flop can make all others from JK (T, D and RS)

•The “J” input acts like SET, K acts like RESET

•No illegal state, activating both inputs causes Q to TOGGLE

J-K FLIP-FLOPSymbol:

Truth Table:

Q

QNOT

J

K

CLOCK

CLK J K

0

Q

X X

1

NO CHG

X X

0

X

0

NO CHG

X NO CHG

0 NO CHG

1

1 0

1 1

SET

RESET

TOGGLE

MODE

HOLD

HOLD

HOLD

HOLD

0

1

Q O

NEGATIVE EDGE TRIGGEREDJ-K FLIP-FLOP

Timing Diagrams

CLK J K Q0

0

0 NO CHG

1

1 0

1 1

0

1

QO

C

J

K

Q

C

J

K

Q

POSITIVE EDGE TRIGGEREDJ-K FLIP-FLOP

Timing Diagrams

CLK J K Q0

0

0 NO CHG

1

1 0

1 1

0

1

QO

C

J

K

Q

C

J

K

Q

C

J

K

Q

ASYNCHRONOUS OVERRIDES

Asynchronous Inputs a.k.a. Overide Inputs operate independent of the control and clock inputs

PRESET

Active-low override Q=1

overrides all other inputs

PRE

CLR CLEAR

Active-low override Q=0

overrides all other inputs

J-K FLIP-FLOPASYNCHRONOUS OVERRIDES

0

1 0

PRE1

0 Ambiguous (not used)

Q=0 independent of synchronous inputs

Q*

No effect; FF can respond to J, K, and CLK

Q=1 independent of synchronous inputs

*CLK can be in any state

CLR1

0 1

J-K FLIP-FLOP

Symbol:

Mode of Operation Inputs Outputs

PS Clr Clk J K Q Q’

Asynchronous set 0 1 x x x 1 0

Asynchronous reset 1 0 x x x 0 1Prohibited 0 0 x x x 1 1-------------------------------------------------------------------------Hold 1 1 0 0 no changeReset 1 1 0 1 0 1Set 1 1 1 0 1 0Toggle 1 1 1 1 opposite

x = Irrelevant = H-to-L transition of clock pulse

Truth Table:

J QK Q

Clk

__

J-K FLIP-FLOPASYNCHRONOUS OVERRIDES

Timing Diagrams

1. The “D” in “D flip flop” stands for _________ or _________ .

2. With a D flip flop, Q follows _____ when triggered by the clock.

3. The “J” input on a J-K flip flop acts like what input on an RS Latch?

4. The “K” input on a J-K flip flop acts like what input on an RS Latch?

5. What inputs on a J-K flip flop are the Asynchronous inputs?

6. What inputs on a J-K flip flop are the Synchronous inputs?

TEST

Data

Delay

D

Set

Reset

Preset/Set

Clear/Reset

J & K