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Transcript of Unit 3rd Processor Design
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Unit-3rd
Processor Design
Text Books: (1) Computer Systems Architecture
by M. Morris Mano
Processor Design
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Central Processing Unit
The Part of computer that performs the bulk data-
processing operations is called the central processing
unit (CPU)
The CPU is made up of three major parts.
Register Set
ALU
Control Unit
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Central Processing Unit Register Set: Stores the intermediate data used during the
execution of the instruction.
Arithmetic Logic Unit: Performs the required micro operationfor executing the instructions.
Control Unit: The Control unit supervises the transfer of
information among the register and instruct the ALU as towhich operation to perform
Computer Architecture is sometimes defined as the computer
structure and behavior as seen by the programmer that usesmachine language instruction.
This includes the instruction formats , addressing modes, theinstruction set , and the general organization of the CPU
register.
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General Register Organization
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General Register Organization The Control unit that operates the CPU bus system directs the
information flow through the registers and ALU by selecting
the various components in the system. For example , to perform the operation
Thecontrol must provide binary selection variables to the
following selection inputs1. MUX A selector (SEL A): To place the content of R2 into bus A.
2. MUX B selector (SEL B): To place the content of R3 into bus B.
3. ALU operation selector (OPR): To provide the arithmetic
addition A+B4. Decoder destination selector (SEL D): To transfer the content
of the output bus into R1.
R1 R2 +R3
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General Register Organization Control Word: There are 14 binary selection inputs in the
unit, and their combined value specifies a control word.
The 14-bit control word is defined or consists of four
fields.
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General Register Organization The encoding of the register selection is specified in Table
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General Register Organization The encoding of the ALU operations for the CPU is
specified in table. The OPR fields has 5 bits and each
operation is designated with a symbolic name.
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General Register Organization For example, The subtract micro-operations given by the
statement
Control word for this micro-operation
R1 R2 +R1
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General Register Organization
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Stack Organization A useful feature that is included in the CPU of most
computers is a stack or last-in, first-out(LIFO) list.
A stack is a storage device that stores information insuch a manner that the item stored last is the first item
retrieved. The operation of a stack can be compared to a
stack of trays.
The stack in digital computer is essentially a memory
unit with an address register that can count only(after an
initial value is loaded into it). The register that holds the
address for the stack is called a stack pointer(SP)because its value always points at the top item in the
stack.
Two operation of a stack are the insertion and
deletion
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Stack Organization Insertion: The operation of insertion is called push because
it can be thought of as the result ofpushing a new item on
top.
Deletion: Theoperation of deletion is called pop because it
can be thought of as the result of removing one item so
that the stack pops up.
Register Stack: A stack can be placed in a portion of a large
memory or it can be organized as a collection of an finite
number of memory words or registers.
The SP register contains a binary number whose value
equal to the address of the words that is currently on the
top of the stack.
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Stack Organization Three items are placed in the stack A,B, & C. Item C is on
the top of the stack so that the content of SP = 3. To
remove the top item, the stack is popped by reading thememory word at address 3 and decrementing the
content of SP.
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tac rgan zat on Now, item B on top SP = 2 . To insert a new item , the
item is pushed by incrementing SP and writing a word in
the next - higher location in the stack. In a 64 word stack, the SP contains 6 bits (26 = 64). It
cannot exceed 63(111111 in binary). When 63 is
incremented by 1 , the result is 0 since 111111 + 1
=(1000000) . Similarly when 000000 is decremented by 1,the result is ( ? ).
The one - bit register FULL = 1 , when the stack is full
The one bit register EMTY = 1 , When the stack is emptyof items.
DR is the data register that holds the binary data to be
written into or read out of the stack.
S k O i i
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Stack Organization Push: Initially, SP is cleared to 0 , EMTY = 1 and FULL = 0 ,
so that SP points to the word at address 0 and stack is
marked empty and not full. If stack is not full (if FULL = 0) ,new item is inserted with push operation.
SP SP + 1 Increment stack pointer
M[SP] DR Write item on top of the stack
If (SP = 0) then (FULL 1) Check if stack is full
EMTY 0 Mark the stack not empty
Note that SP holds the address of the top of the stack and
that M[SP] denotes the memory word specified by theaddress presently available in SP.
The first item stored at address 1. And the last item is
stored at address 0. If SP reaches 0, the stack is full. Sofull is set = 1 FULL = 1 and EMTY = 0
St k O i ti
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Stack Organization POP: A new item is deleted from the stack if the stack is
not empty(if EMTY =0). The micro-operation for the POP
are following: DRM[SP] Read item from the top of the stack
SP SP-1 Decrement stack pointer
If (SP = 0) then (EMTY
1) Check the stack is empty FULL 0 Mark the stack not full.
Note that if a POP operation reads the item form location
0 and then SP is decremented , SP changes to 111111 (63).
Note that erroneous operation will result if the stack is
pushed when FULL =1 or popped when EMTY =1
k i i
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Stack Organization Memory Stack: A stack can exist as a stand - along unit
can be implemented in a random access memory
attached to a CPU. The implementation of a stack in theCPU is done by assigning a portion of memory to a stack
operation and using a processor register as a stack pointer.
A portion computer memory partitioned into three
segments: program , data, and stack.
The PC (program counter) points at the address of the
next instruction in the program. PC is used during the
fetch phase to read an instruction. The address register (AR) points at an array of data. AR is
used during the execute phase to read an operand
The stack pointer (SP) points at the top of the stack. SP is
used to push or pop items into or form the stack .
S k O i i
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Stack Organization The initial value of SP is 4001 and the stack grows with
decreasing address. Thus the first item stored in the stack
is at address 4000, the 2nd item at 3999 and the lastaddress that can be use for the stack is 3000.
A new item is inserted with the push operation as
follows SP SP 1
M[SP] DR
A memory write operationinserts the word from DR into
the top of the stack. A new item is deleted with a pop
operation as follows:
DRM [SP]
SPSP + 1
S k O i i
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Stack Organization
S k O i i
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Stack Organization Stack Limits: The stack limits can be checked by using two
processor register : one to hold the upper limit (3000 in
this case) , and the other to hold the lower limit (4001 inthis case). After a push operation is compared with upper
limit and after a pop operation , SP is compared with
lower limit register .
The two micro-operation needed for either the push or
pop are
1. An access to memory through SP
2. Updating SP
St k O i ti
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Stack Organization Reverse polish Notation:
A Stack organization is very effective for evaluating
arithmetic expression.
(A + B) Infix notation
(+AB) Prefix or Polish notation
(AB+) Postfix or reverse Polish notation
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I t ti F t
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Instruction Formats An instruction is a command given to a computer to perform a
specified operation on some given data and the format in which
the instruction is specified is known as instruction format.
The bits of the instruction are divided into groups called fields.
The most common fields founds in instruction formats are:
An operation code field that specifies the operation to be
performed. (such as add, subtract, complement shift etc.)
An address fields that designate a memory address or a
processor register
A mode field that specifies the way the operand or the
effective address is determined. (bits specify a variety of
alternative for choosing the operands form the given address)
t t t
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nstruct on ormats A register address is a binary number of k bits that defines
one of 2K register in the CPU. A CPU with 16 processor
register R0 through R15. Thus the binary number 0101(means R5).
Computer may have instruction of several different
lengths containing varying number of address. Most
computer fall into one of three types of CPU organizations:
1. Single accumulator organization
2. General register organization
3. Stack organization
Accumulator: All operations are performed with an implied
accumulator register. The instruction format in this type
ofcom uter uses one address field.
Instr ction Formats
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Instruction Formats For ex: Assembly language instruction as
ADD X where X is the address of the operand.
AC AC + M[X]. AC is the accumulator register and M[X]
symbolizes the memory word located at address X.
General Register: In this format computer needs 3 or 2
register address fields.
For ex:Assembly language instruction as
ADD R1,R2,R3 to denote the operation R1 R2 + R3
If the destination register is same as one of the source
register . Thus the instruction
ADD R1, R2 to denote the operation R1 R1 + R2
Instruction Formats
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Instruction Formats For ex: Register use the move instruction with a mnemonic
MOV to symbolize a transfer instruction. Thus the
instruction are
MOV R1 R2 denotes the transfer R1 R2 transferinstruction need two address fields source & destination
For ex:
ADD R1 , X denotes R1 R1 + M[X] . It has 2addressfields one for R1 & other for memory address X
Stack Organization: Stack oriented machine do not contain
any accumulator or general purpose register. Stack have
PUSH & POP instruction which require an address fields.
Instruction Formats
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Instruction Formats For ex:
PUSH X
push the word at address X to the top of stack. The SP isupdate automatically.
Operationtype instruction do not need an address fieldin stack organized computers. Because operation is
performed on two top most operands of the stack
For ex: ADD
The instruction consists of an operation code only with no
address field. To perform this pops the two operands and
add the numbers and then PUSH the result into stack.
Instruction Formats
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Instruction Formats Evaluate the arithmetic statement using zero, one,
two or three address instructions.
X = (A + B) * (C + D)
We will use the symbols ADD,SUB,MUL and DIV for
the four arithmetic operations, MOV for transfer
type and LOAD and STORE for transfer to and
from memory and AC register.
We assume that the operands are in memory
address A,B,C & D and the result must be stored in
memory at address X.
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Number of Addresses (a)
3 addresses
Operand 1, Operand 2, Result
a = b + c;
Not common
Needs very long words to hold everything
I t ti F t
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Instruction Formats Three address Instruction
Advantages: It result in short programs when evaluating
arithmetic expression Disadvantage: The binary coded instructions require
too many bits to specify 3-address
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Number of Addresses (b)
2 addresses
One address doubles as operand and result
a = a + b
Reduces length of instruction
Requires some extra work
Temporary storage to hold some results
I t ti F t
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Instruction Formats Two Address Instruction:
Most common in commercial computers
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Number of Addresses (c)
1 address
Implicit second address
Usually a register (accumulator)
Common on early machines
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Instruction Formats One Address Instruction:
One address instruction use an accumulator (AC)register for all data manipulations
T is the address of a temporary memory location required
for storing the intermediate result
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Number of Addresses (d)
0 (zero) addresses
All addresses implicit
Uses a stack
e.g. push a push b
add
pop c
c = a + b
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Instruction Formats Zero Address Instructions: It is necessary to convert the
expression into RPN .
X = (A + B) * (C + D) = RPN = AB + CD + *
Addressing Modes
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Addressing Modes
The technique for specifying the address of the operands
are known as addressing modes. The address of an
operand is known as effective address.
Each instruction needs data on which it has to perform
the specified operation. The operand may be inaccumulator, general purpose register or at some
specified memory location. Thus , there are various ways
of specifying the address of the data known as
addressing modes.
Addressing Modes
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Addressing Modes Mode Field:The mode field is used to locate the
operands needed for the operation. The instruction may
have more than one address filed and each address fieldmay be associated with its own particular addressing
mode.
Although most addressing modes modify the addressfield of the instruction, there are two modes that need
no address field at all. These are the implied and
immediate modes.
Instruction format with mode field
Opcode Mode Address
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Stack/ Implied Addressing
Operand is (implicitly) on top of stack
e.g.
ADD Pop top two items from stack
and add
Addressing Modes
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Addressing Modes Implied Mode: In this mode the operands are
specified implicitly in the definition of the
instruction . For ex: The instruction "Complement
accumulator is an implied mode instruction
because the operand in the accumulator register isimplied in the definition of the instruction.
All register reference instruction that anaccumulator are implied mode instruction.
Zero address instruction are implied mode
instruction since the operand to be on top of the stack
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Immediate Addressing
Operand is part of instruction
Operand = address field
e.g. ADD 5
Add 5 to contents of accumulator
5 is operand
No memory reference to fetch data
Fast
Limited range
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Immediate Addressing Diagram
OperandOpcode
Instruction
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Direct Addressing
Address field contains address of operand
Effective address (EA) = address field [A]
e.g. ADD A
Add contents of cell A to accumulator
Look in memory at address A for operand
Single memory reference to access data
No additional calculations to work out
effective address
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Direct Addressing Diagram
Address of Operand AOpcode
Instruction
Memory
Operand
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Indirect Addressing (1)
Memory cell pointed to by address field
contains the address of (pointer to) the
operand
EA = [A]
Look in A, find address [A] and look there for
operand
e.g. ADD [A]
Add contents of cell pointed to by contents of A to
accumulator
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Indirect Addressing (2)
May be nested, multilevel, cascaded
e.g. EA = [[[A]]]
E.A. = Address part of the instruction + Content of CPU
Multiple memory accesses to find operand
Hence slower
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Indirect Addressing Diagram
Address of Operand AOpcodeInstruction
Memory
Operand
Pointer to operand
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Register Direct Addressing (1)
Operand is held in register named in address
field
EA = R
Limited number of registers
Very small address field needed
Shorter instructions
Faster instruction fetch
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Register Direct Addressing(2)
No memory access
Very fast execution
Very limited address space
Multiple registers helps performance
Requires good assembly programming
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Register Direct Addressing Diagram
Register Address ROpcode
Instruction
Registers
Operand
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Register Indirect Addressing
Similar to indirect addressing
EA = [R]
Operand is in memory cell pointed to by
contents of register R
R i I di Add i Di
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Register Indirect Addressing Diagram
Register Address ROpcode
Instruction
Memory
OperandPointer to Operand
Registers
Indexed/Displacement /Based
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Indexed/Displacement /Based
Addressing
EA = X + [R]
Address field hold two values
X = base value
R = register that holds displacement
or vice versa
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Displacement Addressing Diagram
Register ROpcode
Instruction
Memory
OperandPointer to Operand
Registers
Address X
+
Relative Addressing
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Relative Addressing A version of displacement addressing
R = Program counter, PC
EA = A + [PC]
i.e. get operand from A cells from current
location pointed to by PC
Ex: Assume that the program counter contains
the number 825 and the address part of the
instruction contains the number 24 .
The instruction at 825 is read form memoryduring fetch phase & PC is then incremented(826)
EA = 826 + 24 = 850
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Base-Register Addressing
A holds displacement
R holds pointer to base address
R may be explicit or implicit
e.g. segment registers in 80x86
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Indexed Addressing
A = base
R = displacement
EA = A + R
Good for accessing arrays
EA = A + R
R++
E l f Add i M d
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Example of Addressing Mode The two word instruction at address 200 and 201 is a
load to AC instruction with an address field equal to500.The first word of the instruction specifies theoperation code and mode, and the second wordspecifies the address part. PC has the value 200 forfetching this instruction. The contents of processor
register R1 is 400, and the content of an index registerXR is 100.AC receives the operand after the instructionis executed. The Mode field of the instruction canspecify any one of a number of modes. For eachpossible mode calculate the effective address and the
operand that must be loaded into AC
Example of Addressing Mode
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Example of Addressing Mode
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Solutions
Data Transfer & Manipulation
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Data Transfer & Manipulation The symbolic name given to the instruction in the
assemblylanguage notation instruction is different for
different computers, even for the same instruction. Thereis a set of basic operations that most , if not all computer
include in their instruction collection. The basic set of
operations available in a typical computer.
Most computer instruction can be classified into three
categories.
1. Data transfer instructions
2. Data manipulation instructions
3. Program control instructions
Data Transfer & Manipulation
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Data Transfer & Manipulation Data Transfer Instruction: Data transfer instruction cause
transfer of data form one location to another without
changing the binary information content.
Data manipulation Instruction: Data manipulation
instruction are those that perform arithmetic, logic, andshift operations.
Program Control instruction: Program control instructions
provide decisions making capabilities and change the pathtaken by the program when executed in the computer.
Data Transfer & Manipulation
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Data Transfer & Manipulation Data transfer Instruction: Data transfer instruction move
data form one place in the computer to another without
changing the data content. The most common transfer arebetween memory and processor register, between
processor register and input or output , and between the
processor register themselves.
Below gives the list of eight data transfer instruction usedin many computers.
Mnemonic (Designed to help the memory)
Data Transfer & Manipulation
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ata a s e & a pu at o Load: It is used to transfer from memory to a processor
register (usually an accumulator).
Store: It designates a transfer from a processor registerinto memory .
Move: Itdesignates a transfer from one register to
another. Exchange: These instruction swaps information between
two register or a register and a memory word.
I/P & O/P: These instruction transfer data among
processor register and input or output terminals.
Push & Pop: These instruction transfer data between
processor register and a memory stack.
Data Transfer & ManipulationT bl h th bl l ti d th
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p Table shows the assembly language convention and the
actual transfer in each case.(load to accumulator instr.)
ADR stands for an address , NBR is number or operand , X isan index register , R1 is processor register , AC is
accumulator register.
@ symbolized an indirect address , $ character before an
address makes the address relative to the PC. # character precedes the operand in an immediate-mode
instruction.
Data Transfer & Manipulation
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p Data Manipulation Instructions: Data manipulation
instructions perform operation on data and provide the
computation capabilities for the computer. The datamanipulation instructions in a typical computer are usually
divided into three into three basic types:
1. Arithmetic instruction
2. Logical and bit manipulation instruction
3. Shift instructions
Data Transfer & ManipulationA ith ti I t ti
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p Arithmetic Instructions:
Logical and Bit Manipulation Instructions
Data Transfer & Manipulation
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p Shift Instructions
Program Control
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g
Data Transfer & Manipulation
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p
Data Transfer & Manipulation
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p
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How Many Addresses
More addresses
More complex (powerful?) instructions
More registers
Inter-register operations are quicker
Fewer instructions per program
Fewer addresses
Less complex (powerful?) instructions More instructions per program
Faster fetch/execution of instructions
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Design Decisions (1)
Operation repertoire
How many ops?
What can they do?
How complex are they?
Data types
Instruction formats
Length of op code field
Number of addresses
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Design Decisions (2)
Registers
Number of CPU registers available
Which operations can be performed on which
registers?
Addressing modes (later)
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Types of Operand
Addresses
Numbers
Integer/floating point
Characters
ASCII etc.
Logical Data
Bits or flags
f
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Types of Operation
Data Transfer
Arithmetic
Logical
Conversion
I/O
System Control Transfer of Control
f
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Data Transfer
Specify
Source
Destination
Amount of data
h
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Arithmetic
Add, Subtract, Multiply, Divide
Signed Integer
Floating point ?
May include
Increment (a++)
Decrement (a--)
Negate (-a)
Shif d O i
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Shift and Rotate Operations
L i l
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Logical
Bitwise operations
AND, OR, NOT
C i
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Conversion
E.g. Binary to Decimal
I /O
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Input/Output
May be specific instructions
May be done using data movement
instructions (memory mapped)
May be done by a separate controller (DMA)
T f f C t l
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Transfer of Control
Branch
e.g. branch to x if result is zero
Skip
e.g. increment and skip if zero
ISZ Register1
Branch xxxx
ADD A
Subroutine call
c.f. interrupt call
B h I t ti
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Branch Instruction
N t d P d C ll
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Nested Procedure Calls
U f St k
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Use of Stack
Addressing Modes The basic operation cycle of the computer to go through
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The basic operation cycle of the computer to go through
an instruction cycle that is divided into three major
phases
1. Fetch the instruction from memory
2. Decode the instruction
3. Execute the instruction
Program Counter(PC) : PC holds the address of
instructions to be executed next and is incremented each
time an instruction is fetched from memory.