Digital Electronic Systems Unit 13

SHIFT REGISTERS

Shift registers are very important devices in applications that involve the storage and the transfer of data in a digital system. The difference between a register and a counter is that the register has no specified series of states. A register is solely used for storing and shifting data (that is 1s and 0s) that have been entered from an external source.The storage capacity of a register is the number of bits (of digital data) it can retain. Each stage of a shift register represents the one bit of information it can store, so the number of stages in a shift register represents the total storage capacity of a register. Shown below is how a Flip-Flop is used as a storage device.

QC

D1 1Q

C

D00

It can be seen that when the clock is going HIGH, that is on a rising edge, the input on the D becomes the output.

There are various type of shift register, and shown below are simplified diagrams of the most commonly used.

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Digital Electronic Systems Unit 13

Serial in, Serial out Shift RegistersThis type of shift register accepts data serially, that is, one bit at a time on a single line. It produces the stored information on its output also in serial form.

Q

C

D Q

C

D Q

C

D Q

C

DSerial input

Clock

Serial Output

The diagram above shows a shift register that will hold four bits at any one time. On the rising edge of a clock pulse, the data is fed into the register. After four clock pulses the register is full and the next pulse will start to release the data in the order in which it entered.

Shown below is a 5-bit shift register and the corresponding timing diagram.

The timing diagram is shown below. The main point to note is the data shifting through the registers.

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Digital Electronic Systems Unit 13

Shown above are the values contained in each Flip-Flop after five clock pulses.

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Digital Electronic Systems Unit 13

Serial in, Parallel out Shift RegistersData is entered serially into this type of register as was described in the last section. The difference is the way in which the Data bits are taken out of the register. In a parallel output register, the output of each stage is available. Once the data bits are stored, each bit appears on its respective output line, and all bits are available simultaneously, rather than on a bit by bit basis as was the case for the serial output. Shown below is a 4-bit serial input parallel output register.

Q

C

D Q

C

D Q

C

D Q

C

D

Clock

FF0 FF1 FF2 FF3

SerialData Input

Q0 Q1Q2 Q3

Parallel Data Output

The above Serial Input Parallel Output (SIPO) shift register has the summarised symbol shown below.

SRG 4D

Ck

Q0

Q1

Q2

Q3

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Digital Electronic Systems Unit 13

Below is shown the timing diagram for this 4-bit serial input parallel output shift register.

This looks very similar to the serial-input serial-output timing diagram, but in this timing diagram the clock pulse signifies that the serial data is on the output.

Parallel-in, Serial-out Shift RegisterHere the data is entered simultaneously into the respective stages on parallel lines rather than on a bit by bit basis as is the case with the serial input shift register. The serial output appears at the output terminal one bit at a time with each new bit coinciding with another clock pulse. The diagram below shows a 4-bit parallel-in serial-out shift register.

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Digital Electronic Systems Unit 13

Notice that there are four input Lines. The key feature of this shift register is the SHIFT / LOAD line. When this line is LOW then the AND gates on the right hand side of each grouping is enabled and thus any parallel data can get through to the Flip-Flops. When this line is HIGH then the AND gate on the left hand side of each grouping is enabled and the data can flow through the Flip-Flops to be seen as a serial data output. Like before this gate is summarised into a more convenient logic symbol as shown below.

SRG 4Ck

D0 D1 D2 D3

SERIAL DATA OUTCLOCK

SHIFT / LOAD

Shown below is the corresponding timing diagram.

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Digital Electronic Systems Unit 13

Parallel in, Parallel out Shift RegistersPreviously described was the parallel inputting and outputting of data. What happens with this register is that immediately following the simultaneous entry of all the data bits, the bits appear on the parallel outputs. A diagram for this shift register is shown below.

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