IEEE TRANSACTIONS ON COMPUTERS, VOL. C-29, NO. 1, JANUARY 1980

Undetectability of Bridging Faults andValidity of Stuck-At Fault Test Sets

K. L. KODANDAPANI AND DHIRAJ K. PRADHAN

Abstract-The study ofbridging faults (or short circuits that occurbetween conducting paths) has become increasingly important withthe advent of LSI technology. To date, only a very few papers havebeen published on this topic. Specifically, little is known regardingundetectable bridging faults. More importantly, what has yet to beexplored are the effects of undetectable bridging faults on the testsdesigned to detect stuck-at faults.

In this correspondence, we exhibit the importance of undetectablebridging faults by showing how they can cause significant practicalproblems. First, we derive necessary and sufficient conditions forbridging faults to be undetectable. Using these conditions, weconstruct an example of a circuit which has an undetectable bridgingfault between two irredundant gate-input leads, with fanout. Then weshow that all intragate faults in two-level networks, as well as those incertain types of unate networks, are always detectable.

Next, we study the intergate bridging faults. We show that anundetectable bridging fault in an irredundant network can invalidatea test set designed to detect stuck-at faults. This, in our opinion, raisesa serious concern; i.e., finding test sets which remain valid in the eventof an undetectable bridging fault.A solution to this problem, that applies for a restricted class of

networks, is presented. A procedure is developed to derive test setswhich are not invalidated by undetectable bridging faults.

Index Terms-Boolean difference, bridging faults, intergatebridging faults, intragate bridging faults, irredundant networks,redundancy, short circuits, two-level networks, undetectability, unatenetworks, undetectability.

I. INTRODUCTIONMost of the research in the area of fault diagnosis is based on

the stuck-at fault model [1], [2]. This model represents many typesof faults that occur in practice. (Such an example would be an

open diode.) However, there are some commonly occurring typesof faults which cannot be easily modeled by the stuck-at faultmodel. One of these is the class of bridging faults [3]-[8] whichoccurs frequently in integrated circuits. An example is the recentlyobserved fact that many faults MOS-LSI circuits are actuallyshorts between [13].A bridging fault in a digital circuit causes a short circuit be-

tween two or more conducting paths of the circuit. These bridgingfaults may arise due to failure of insulation between adjacentlayers of metallization on a chip, or they can be due to a shortbetween two conductors in the same layer, which could be a resultof improper masking or etching. The bridging faults lead to a

different logical behavior of the circuit than that caused by thestuck-at faults.

It is known that for ECL, RTL, and DTL, the bridging fault canbe modeled as wired-AND or wired-OR. The bridging fault has theeffect of an AND (OR) function for positive (negative) logic. Also, itis known that for TTL gates, the bridging fault will cause an ANDfunction. This is because for most of the present-day TTL gates,the totem-pole drivers are not symmetrical. Therefore, 0-outputdominates in the bridging fault.

Manuscript received August 3, 1977; revised June 25, 1979. This research was

supported in part by AFOSR Contract F 49620-79-C-0119.K. L. Kodandapani is with the Department of Computer Science, Wichita State

University, Wichita, KS 67208.D. K. Pradhar was with the University of Regina, Regina, Sask., Canada. He is

now with the School of Engineering, Oakland University, Rochester, MI 48063.

Compared to the stuck-at faults, bridging faults pose moredifficulties. These are as follows:

1) As shown in this paper, the occurrence of an undetectablebridging fault in an irredundant network can invalidate a test setthat is designed to detect stuck-at faults. This, therefore, poses apractical problem.

2) Bridging faults may introduce a feedback loop in a combina-tional logic circuit, causing the circuit to behave as an asynch-ronous sequential circuit. This violates the usual assumption thata fault does not change a combinational circuit into a sequentialcircuit. Also, since a bridging fault can occur between any twolines in the circuit, the analysis of the fault behavior can be quitecomplex, especially when the fault results in a sequential network.

3) In the case of stuck-at faults, if there are n lines in the circuit,then there are 2n possible single stuck-at faults, and 3n _ 1 poS-sible multiple stuck-at faults. Whereas in the case of bridgingfaults, if we have to consider bridging faults between any two linesin a circuit, then the number of single bridge faults, alone, will be(2) and the number of multiple bridging faults will be very muchlarger [5].

However, it may be noted that in the case of bridging faults, iftest generation is carried out after the layout of the circuit on thechip, then the tests need to be generated only for bridging faultsbetween conduction paths that are adjacent on the same layer, oracross different layers of metallization. This results in a reductionin the number of faults to be considered. Therefore, it is alsopossible to plan the layout in such a way that certain types ofbridging faults which are hard to detect can be made unlikely.To date, only limited results are available regarding bridging

faults [4]-[8]. Several outstanding questions remain to beanswered.Redundancy in relation to bridging faults, and its effect on test

sets, has not yet been explored. In this paper, we specifically in-vestigate this aspect of bridging faults, and present several results.Here we consider both intragate bridging fault (between inputleads of the same gate) and intergate bridging fault (between inputleads of two different gates).

First, certain results are presented which are used to formulatean example of a circuit which has an undetectable bridging faultbetween two irredundant leads of a gate. Next, it is shown thatthere cannot exist undetectable bridging faults in certain restrictedclasses of networks. These results are related to a question ori-ginally posed by Friedman [4], that would establish theexistence/nonexistence of undetectable bridging faults in irredun-dant circuits.A class of bridging faults that differs from those considered by

previous researchers is investigated next. It is shown that anundetectable bridging fault from this class can invalidate a test setdesigned to detect stuck-at faults in an irredundant circuit. This,therefore, poses a practical problem: the design of stuck-at faulttest sets which are not invalidated by undetectable bridging faults.

Finally, a solution to this problem is presented for a restrictedclass of networks.

This paper is organized into two main sections. In Section II,we present necessary and sufficient conditions for the occurrenceof undetectable bridging faults. Then, using this, we construct anexample of an undetectable bridging fault between two irredun-dant input leads of a gate, where both of the input leads havefanout. Also, it is shown that there cannot exist an undetectablebridging fault in certain two-level and unate networks. Next, inSection III, we study undetectable intergate bridging faults. We

0018-9340/80/0100-0055$00.75 ©) 1980 IEEE

55

IEEE TRANSACTIONS ON COMPUTERS, VOL. c-29, NO. 1, JANUARY 1980

Fig. 1. Undetectable AND type bridging faults at the inputs of AND gate.

exhibit the possibility of an undetectable bridging fault invalidat-ing a stuck-at fault detection test set; i.e., the test devised to detecta stuck-at fault fails to detect it in the presence of the undetectablebridging fault. A procedure to generate test sets for certain unatenetworks is then presented. These test sets have the interestingproperty of not becoming invalid in the presence of any undetect-able bridging fault of either the intragate or intergate type.

III. REDUNDANCY AND INTRAGATE FAULTSThe conventional definition of redundancy is based on undetec-

tability of stuck-at faults. A lead in a network is said to be redun-dant if no test exists for a stuck-at fault on the lead. A network issaid to be irredundant if there are no redundant leads in the net-work. Redundancy can be a serious problem in test generationand hence, it has been one of the important areas of research[10]-[12]. Friedman [10] showed that a stuck-at fault on a re-

dundant lead of network may invalidate a test set which was

designed to detect stuck-at faults on the irredundant leads. There-fore, redundancy in general is undesirable from the point of viewof test generation.A fault is said to be undetectable if the faulty function is the

same as the fault-free function.One obvious class of undetectable bridging faults is the AND

(OR) type of bridging fault on the input leads of an AND (OR) gate,where the input leads do not have fanout. On the other hand, itcan be easily seen that these types of faults may be detectable if theinput leads have fanout. Having fanout does not always guaranteedetectability.

In Fig. 1, we show an example of a circuit in which an AND-typebridging fault on two leads with fanout is not detectable.However, the question of AND-(OR)-type bridging faults on theinput leads of OR (AND) gates is partially answered in [4]. It hasbeen shown in [4] that if, at most, one of the leads has fanout, thenan AND-(OR)-type bridging fault between two input leads of an OR(AND) gate is always detectable by single stuck-at fault detectiontest set. However, it is not known if there can exist an undetectablebridging fault between the input leads, where both of the leadshave fanout. Also, if we consider bridging faults on two leadsthat are not inputs to the same gate, this problem becomes more

complex. In the following paragraphs, we provide some insightinto undetectability of bridging faults on two arbitrary leads, withthe only restriction that they do not cause feedback loops.

Here, we assume that h and m are two arbitrary leads (lines) in acombinational network. The only constraint on these leads, h and

m, is that a bridging fault between them does not produce a feed-back loop. The function realized by the fault-free network isdenoted by F, and those functions realized by the leads, h and m,arefh and fi, respectively. Due to the above constraint on the linesh and m, we can state that fh(fm) cannot be expressed as a functionoffn(fSh).

Definition 1: Given a functionfof n variables: x0, x1, x, - 1the Boolean difference [9] of f, with respect to a variable xi isdenoted by df/dxi and is evaluated as follows:

dx= f (Xi = °) 3f (xi = 1).

The following results are derived by using principles of Booleandifference, and the proofs are omitted for the sake of brevity.

In the sequel, we denote an OR type bridging fault as + (h/m),and an AND type as *(h/m).

Theorem 1: The bridging fault + (h/m) between h and m is notdetectable if and only if

- dF - dF

fhfm d = fh fm df

Theorem 2: The bridging fault *(h/m) is not detectable if andonly if

- dF - dF

fhfr df =ffm .

The following corollaries are immediate consequences of theabove theorems.

Corollary 1: The bridging fault + (h/m) is not detectable if andonly if

- dF -dFfh fm df = fh fmd. =0.

Corollary 2: The bridging fault *(h/m) is not detectable if andonly if

-dF - dFfh fm d = fh fm 0.=

f dm~fhfdfmCorollary 3: If s-a-i (s-a-0) faults on both the leads h and m are

not detectable, then + (h/m)(*(h/m)) is not detectable.Corollary 4: If h s-a-I (s-a-0) is not distinguishable from m s-a-1

(s-a-0), then + (h/m)(*(h/m)) is not detectable.Corollary 5: If h and m are any leads other than the fanout

branches, then h s-a-1 (s-a-0) is not distinguishable from m s-a-i(s-a-0) if and only if + (h/m)(*(h/m)) is not detectable.Using the above results in the following example, we will syn-

thesize a circuit which has an undetectable bridging fault betweentwo irredundant input leads of a gate.Example 1:Let Fij = F(fh = i, fm =J)The conditions given in Theorem 1 can be written as

fhfm(Fol eF,1) =fhfm(Flo G) F 1) = 0

or

fh fmFo I ®Jfh fm F 10 = (fh efm)F 1 1. (8)Let F(x1, x2, X3, X4) be a 4 variable function. Let

fh = Xl X2 + X3 X4 andfm = X1 X3 + X2 X4. We will now try to finda set of functions, Fo1, F1o, and F1l, satisfying (8).

Consider the Karnaugh maps offh fm,fh fm andfh efm shown inFig. 2. One possible choice of the three functions, F01, F10, andF1 which satisfies (8) for the above selection of fh and fm isFol = X4, Flo = 1, and F1l = x1 + x2. Using these functions, we

56

IEEE TRANSACTIONS ON COMPUTERS, VOL. C-29, NO. 1, JANUARY 1980

++00 01 11 .10

00 0 0 0 0

01 0 0 0

II 0 0 0 0

1o 0 0 0o

fh fm

+X00

01

10

+\+Y 0oo 11 10

00 0 0 0

01 0 0 0 0

0 0 0

10 0 0 0 0

00 01 11

1

i- ooIL

ZL212J

o o- l

fh fm

Fig. 2. Karnaugh maps for Example 1.

can construct the circuit shown in Fig. 3, which realizes the func-tion F.

In this circuit the input leads h and m are irredundant withrespect to stuck-at faults, but the bridging fault +(h/m) is notdetectable. However, the circuit shown in Fig. 3 is redundant, e.g.,line p is redundant. Removing redundant lines in the circuit makes+ (h/m) detectable.Thus, this does not constitute a conclusive answer to the

question originally posed in [4]. However, this does establish thatan undetectable bridging fault can exist between two irredundantleads of a gate.

In the following, it is shown that for certain classes of networks,undetectable bridging faults cannot exist.

Theorem 3: In an irredundant two-level AND-OR or OR-ANDnetwork, all intragate bridging faults are detectable.

Proof: First it may be observed that bridging faults at theinputs of the second-level gate (i.e., the gate for generating theoutput) are detectable, provided they are OR type at the inputs ofAND gate, and AND type at the inputs of OR gate.Now consider the first-level gates. We shall assume that they

are AND gates for this proof. Let x* and xJ be two inputs to anAND gate, realizing a prime implicant P where x4 denotes Xk, orXk. Thus, one has P = x*x*P'. Under the fault + (x*'/x,7), theoutput of the AND gate realizing P assumes the value (x4 + x )P'.Thus FBR = 1 for all input combinations for which x* or x4 equals1, and P'= 1. But F cannot be equal to 1 for all these inputcombinations, since the prime implicant P subsumes x*P' andx*P'. Thus F * FBR and hence, the fault is detectable. Q.E.D.

Theorem 4: An irredundant network, where any two reconver-gent paths have equal numbers of parity inversions, cannot havean undetectable intragate bridging fault.

Proof: Without loss of generality, the proof will be given forthe case of OR-type bridging faults at the inputs of AND gates.

Consider the fault + (h/m) at the inputs of an AND gate G1, asshown in Fig. 4. Since the network is irredundant, a test for h s-a-iexists. Let this test be t. In the following, it is shown that t alsodetects + (h/m).

Fig. 3. A realization of the network in Example 1.

g

h

F

Fig. 4. Network in the proof of Theorem 4.

The test t applies a 0 to h, and l's to all other inputs of G1. Thefault + (h/m) will result in a 0 to 1 change in h. Thus, if h does nothave any fanout, then t obviously detects + (h/m).On the other hand, let h have a fanout g. Thus, the fault + (h/m)

will cause a 0 to 1 change in both h and g.It will now be shown that this change in g does not affect

detection of the fault + (h/m) by the test t.Let a path through g reconverge at the inputs of some gate G2

which is on the sensitized path from G1 to the network output F.For t to detect + (h/m), this path must remain sensitized, in spiteof the 0 to 1 change in g. The two reconvergent paths, one throughh and the other through g, have the same number of parity inver-sions. Thus, the path from G1 to the network output F cannot bedesensitized at G2 due to the change in g. Q.E.D.

It may be added that for any unate function, there exists arealization in which any two reconvergent paths have equal num-bers of parity inversions. Given the input variables and their com-plements as independent inputs, any function can be realized as anunate function. This, thus, constitutes a realization in which allintragate bridging faults are detectable.

IV. UNDETECTABILITY OF INTERGATE BRIDGING FAULTS ANDTHEIR EFFECT ON STUCK-AT FAULT DETECTION TEST SETS

In the previous section, we have been primarily concerned withintragate bridging faults; i.e., faults at the input leads of the samegate. (However, Theorems 1 and 2, Corollaries 1-4 are true for

57

IEEE TRANSACTIONS ON COMPUTERS, VOL. c-29, NO. 1, JANUARY 1980

Fig. 5. Undetectable bridging fault.

bridging faults on any two arbitrary leads, as long as they do notproduce a feedback loop.)

In this section, we shall consider intergate bridging faults; i.e.,faults between input leads of two different gates. We shall studythe effect of undetectability of such bridging faults on the validityof test sets devised to detect stuck-at faults.

First, we show some interesting examples in order to reveal theimportance of the problem. Then, for certain unate networks, weexhibit a technique to generate stuck-at test sets which cannot beinvalidated by any undetectable bridging fault (both intragate andintergate).The circuit shown in Fig. 5 is an example of an irredundant

circuit with respect to stuck-type faults. Consider the OR-typebridging fault between leads x and y, as shown in the Fig. 5. Thisfault is undetectable, since the faulty function produced is thesame as the fault-free function. However, this undetectable faultdoes not create any problem: any test set designed to detect singlestuck-at faults will continue to detect these faults, in spite of thepresence of this undetectable bridging fault.Now, consider a different network shown in Fig. 6. This net-

work realizes the function xy + zx. The set

T.YZ= {010,001,101,111}

is a minimal single fault detection test set. Consider the OR-typebridging fault between y and x, as shown in the figure. This fault isundetectable since the faulty function produced is equal toxy + yz + zx, which is also equal to xy + zx.

Consider the fault q stuck-at 0, as shown in Fig. 6. In thepresence of the above bridging fault, this above-described test set,T,YZ9 will fail to detect this stuck-at 0 fault. This fault can still bedetected by applying x = y = 1 and z = 0, but this input combina-tion is not in the test set Tlyz- Hence, Txyz now becomes invalidbecause of the undetectable bridging fault + (x/y).The above discussion gives rise to the following two important

practical problems:Pl: Generation of stuck-at fault detection test sets which are

not invalidated by undetectable bridging faults.P2: Devising techniques for designing networks so that tests for

stuck-type faults are not invalidated by undetectable bridgingfaults.

In the following, we present a solution to the first problem (P1)for two-level unate networks.

Theorem 5: For an unate two-level irredundant AND-OR net-work, the minimal true vertices, along with any set of tests fors-a-1 faults, form a complete stuck-at fault detection test set andthis test set is not invalidated by any undetectable bridging fault(intergate, intragate, AND-type, OR-type).

Fig. 6. Undetectable bridging fault invalidating the test set.

Proof:Case 1 Intragate Faults: First, it may be observed from

Theorem 3 that the only type of intragate bridging faults that arenot detectable are the AND-types, and the OR-types which are atthe inputs of the AND gates, and the OR gate, respectively.However, these faults cannot invalidate any stuck-at fault test set.

Case 2-Intergate Faults: The intergate bridging faults occuronly at the first level of the network. Of the two possible types offaults, first we consider the AND-type in the following: Considertwo AND gates realizing the prime implicants, Pi-= Qixi, andPj= Qjxj. Let the inputs xi and xj be shortened by a bridgingfault. This will change the outputs of these two AND gates toQi xi xj and Qj xi xj.Consider the following two possible cases. First, let xj 0 Qi or

xi 0 Qj. In this, it is obvious that the fault-free function F is notequal to the faulty function FBR and hence, the fault is detectable.On the other hand, if xj E Qi, and xi E Qj, then F = FBR, and

thus, the fault is undetectable. But it can be easily seen that in thiscase, this undetectable fault cannot invalidate stuck-at fault tests.Now we consider the OR-type, which is the only other case when

there is an undetectable OR-type intergate bridging fault at theinputs of the AND gates. As before, let this OR-type bridging faultoccur between the leads xi and xj which are at the inputs of theAND gates computing Pi= Qixi, and Pj= Qjxj. The faulty func-tion will then be equal to FBR = F + Qi xj + Qj xi.We observe that F = FBR, since the fault is undetectable. In the

following, we consider the two types of stuck-at faults.a) s-a-I Faults: The addition of an AND term can only pro-

duce a 0 to 1 change. Hence, the tests for s-a-i faults cannot beinvalidated by the extra terms Qi xj and Qj xi.

b) s-a-O Faults: First, it may be observed that all the primeimplicants are essential prime implicants for a unate function.Thus, if Qi xj or Qj xi is a prime implicant, then it must be identicalto the term realized by some AND gate. Thus, if Qixj or Qjxi is aprime implicant, then it does not have any effect on the test fors-a-0 fault. Therefore, the case when Qixj or Qjxi is not a primeimplicant is of concern. Consider the following test for a s-a-0fault on some AND gate computing a prime implicant, say, Pk. Letthis test be the minimal true vertex which applies l's to only thosevariables which are included in the term Pk and 0's to all othervariables. For this test, neither Qixj nor Qjxi can be equal to 1,because if they are equal to 1, then they must be included in Pk,which in turn will imply that Pk cannot be a prime implicant.Hence, this test cannot be invalidated by the presence of the addi-tional terms Qixj and Qj xi. Q.E.D.The following procedure may be used for generating test sets for

58

IEEE TRANSACTIONS ON COMPUTERS, VOL. c-29, NO. 1, JANUARY 1980

BRIDGING

Fig. 7. Bridging fault in an unate network invalidating a stuck-at fault detection testset.

two-level unate networks, as indicated by the above theorem.

TEST GENERATION PROCEDURE

AND-OR Networks:1) Generate the tests for s-a-i faults, using any conventional

technique.2) For s-a-0 faults, select the tests that correspond to minimal

true vertices.OR-AND Networks:1) Generate the tests for s-a-0 faults, using any conventional

technique.2) For s-a-i faults, select the tests that correspond to maximal

false vertices.A possible solution to the second problem (P2) may be realized

by finding a class of networks, or a class of functions, for which theundetectable bridging faults cannot invalidate any stuck-at faulttest set. This could lead to the design of networks for any arbitraryfunction where one need not be concerned about undetectablebridging faults while generating tests for stuck-at faults.The following example shows that the conventional two-level

designs do not provide such protection, even for unate functions.Example 2:Consider the network shown in Fig. 7. This network realizes the

unate function F = abc + def + bd + fc. The faulty functionproduced by the bridging fault, shown in the figure, is equal to

FBR= abc + def+ bd +fc + abd + efc.Now, consider the faults v s-a-0 and u s-a-0, as shown in the

figure. These can be tested by tabcdef= 110100 andtabcdef = 001011, respectively. In the presence of the undetectablebridging fault, these tests will fail to detect the above s-a-0 faultsdue to the additional terms abd and efc.

Thus, if the solution exists, it may require more sophisticateddesigns, possibly using three or more levels.

VI. CONCLUSIONS

In this correspondence, we have presented several results onbridging faults. First, we have derived necessary and sufficientconditions for undetectability of bridging faults. Using these re-sults, we have considered an example of a circuit which has anundetectable bridging fault between two irredundant input leadsof a gate, where both of these input leads have fanout. Further-

more, we were able to establish that in certain classes ofcombina-tional networks, there cannot exist an undetectable intragatebridging fault. Thus, we have provided a partial answer to aquestion raised by Friedman [4].We then studied the intergate bridging faults, and established

that it is possible for an undetectable bridgingfault to invalidate astuck-at fault detection test set. A procedure was presented fordesigning test sets for unate networks, such that the test set is notinvalidated by undetectable bridging faults.Two of the important points of this correspondence, then are,

first, the identification of the problem of generating stuck-at faulttest sets which are not invalidated by undetectable bridging faults,and second, the solution to the problem, for a restricted class ofnetworks.

REFERENCES[1] H. Y. Chang, G. Metze, and E. Manning, Fault Diagnosis of Digital Systems.

New York: Wiley-Interscience, 1970.[2] A. D. Friedman and P. R. Menon, Fault Detection in Digital Circuits. Englew-

ood Cliffs, NJ: Prentice-Hall, 1971.[3] M. A. Breuer and A. D. Friedman, Diagnosis and Reliable Design of Digital

Systems. Los Angeles, CA. Computer Science Press, 1976.[4] A. D. Friedman, "Diagnosis of short circuit faults in combinational circuits,"

IEEE Trans. Comput., vol. C-23, pp. 746-752, July 1974.[5] K. C. Y. Mei, "Bridging and stuck-at-faults," IEEE Trans. Comput., vol. C-23,

pp. 720-727, July 1974.[6] M. J. Y. Williams and J. B. Angell, "Enhancing testability of large-scale in-

tegrated circuits via test points and additional logic." IEEE Trans. Comput., vol.C-22, pp. 46-60, Jan. 1973.

[7] S. M. Reddy, "On the detection of bridge and shorted diode faults," in Proc.Allerton Conf., Urbana, IL, Oct. 1974.

[8] A. Isoupvicz, "Optimal detection of bridge faults and stuck-at faults in two-levellogic," IEEE Trans. on Computers, vol. C-27, pp. 452-55, May 1978.

[9] F. F. Sellers, M. Y. Hsiao, and C. L. Bearnson, "Analyzing errors with theBoolean difference," IEEE Trans. Comput., vol. C-17, pp. 676-683, July 1968.

[10] A. D. Friedman, "Fault detection in redundant circuits," IEEE Trans. Electron.Comput., vol. EC-16, pp. 99-100, Feb. 1967.

[11] R. Dandapani and S. M. Reddy, "On the design of logic networks with redun-dancy and testability considerations," IEEE Trans. Computers, vol. C-23, pp.1139-1149, Nov. 1974.

[12] J. P. Hayes, "On properties of irredundant logic networks," IEEE Trans.Comput., vol. C-25, pp. 884-492, Sept. 1976.

[13] Y. Crouzet and C. Landrault, "Design of self-checking MOS-LSI circuits,application to a four-bit microprocessor," in Proc. FTC-9, Madison, WI, pp.189-192, June 1979.

Comments on "Modular Replacement of CombinationalSwitching Networks"

R. M. M. OBERMAN

Abstract-The result of the "modular replacement of combina-tional switching networks method" by Schmidt and Metze' isdiscussed in this correspondence. It shows that the switching functionof the last example used to demonstrate the power of the developedcomputer programs, can be implemented in "library modules" at lessthan half the cost of the best computer result. With other "non-library" modules being ordinary integrated circuits, an even betterresult can be obtained.

Index Terms-Combinational logic, decomposition, design auto-mation, dynamic programming, modules, replacement.

The example used by Schmidt and Metze1 to demonstrate thepower of their computer-aided design of logic circuits using aconstrained library of logic modules shows the weakness of such

Manuscript received October 19, 1979.The author is with the Department of Electrical Engineering, Technical Univer-

sity, Delft, The Netherlands.1 D. C. Schmidt and G. Metze, IEEE Trans. Comput., vol. C-24, pp. 29-48, Jan.

1975.

0018-9340/80/0100-0059$00.75 ©) 1980 IEEE

59