UM10211LPC23XX User manualRev. 4.1 5 September 2012 User manual

Document informationInfo ContentKeywords LPC2300, LPC2361, LPC2362, LPC2364, LPC2365, LPC2366, LPC2367,

LPC2368, LPC2377, LPC2378, LPC2387, LPC2388, ARM, ARM7, 32-bit, USB, Ethernet, CAN, I2S, Microcontroller

Abstract LPC23XX User manual revision

NXP Semiconductors UM10211LPC23XX User manual

Revision historyRev Date Description

4.1 20120905 LPC23XX User manual

Modifications: Corrected cross references throughout.

4 20120726 LPC23XX User manual

Modifications: Updated numbering for CAN interfaces: CAN1 uses SCC = 0, CAN2 uses SCC = 1.

See Section 12.14 ID look-up table RAM and Section 12.16 Configuration and search algorithm.

Registers CANWAKEFLAGS and CANSLEEPCLR added. See Table 220 CAN Wake and Sleep registers.

CCR register bit description updated. See Table 505 Clock Control Register (CCR - address 0xE002 4008) bit description.

Flash erase time corrected in Section 1.3 Features. Reset value of the SCS register changed to 0x8 in Table 31. Write restriction for RTC register appended in Section 26.8 RTC usage notes. ADC self-test pin set-up removed. See Table 520 A/D pin description. Update RTC usage notes: Do not ground VBAT. See Table 501 and Section 26.8. Description of Ethernet initialization updated in Section 11.9. Glitch filter constant for EINTx pins changed to 10 ns in Table 97 to Table 100. Editorial updates.

3 20090825 LPC23XX User manual

Modifications: Deep power-down mode functionality added (see Section 48 Power control and

Section 2626.7 RTC Usage Notes). Register containing device revision added (implemented starting with revision D, see

Section 297.11). Part id for part LPC2387 updated (Table 29542). XTAL1 input selection and PCB layout guidelines added (see Section 44.2). Editorial updates throughout the user manual. LPC2361 flash sectors added in Table 29526. ISP1301 replaced by ISP1302 in Section 157. Fractional baud rate generator disabled in UART0/1/2/3 auto baud mode.

UM10211 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved.

User manual Rev. 4.1 5 September 2012 2 of 708

NXP Semiconductors UM10211LPC23XX User manual

2 20090211 LPC23XX User manual

Modifications: Parts LPC2361 and LPC2362 added. Numerous editorial updates. AHB configuration registers AHBCFG1 and AHBCFG2 added. UARTs: minimum setting for DLL value updated.

1 20080311 LPC2364/65/66/67/68/77/78/87/88 User manual

Revision history continuedRev Date Description

UM10211 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved.

User manual Rev. 4.1 5 September 2012 3 of 708

Contact informationFor more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

1.1 Introduction

LPC23xx series are ARM-based microcontrollers for applications requiring serial communications for a variety of purposes. These microcontrollers typically incorporate a 10/100 Ethernet MAC, USB 2.0 Full Speed interface, four UARTs, two CAN channels, an SPI interface, two Synchronous Serial Ports (SSP), three I2C interfaces, an I2S interface, and a MiniBus (8-bit data/16-bit address parallel bus).

1.2 How to read this manual

The term LPC23xx in the following text will be used as a generic name for all parts covered in this user manual:

LPC2361/62 LPC2364/65/66/67/68 LPC2377/78 LPC2387 LPC2388

Only when needed, a specific device name will be used to distinguish the part. See Table 1 to find information about a particular part.

1.3 Features

1.3.1 General features

ARM7TDMI-S processor, running at up to 72 MHz. Up to 512 kB on-chip Flash Program Memory with In-System Programming (ISP) and

In-Application Programming (IAP) capabilities. Single Flash sector or full-chip erase in 100 ms. Flash program memory is on the ARM local bus for high performance CPU access.

Up to 64 kB of SRAM on the ARM local bus for high performance CPU access.

UM10211Chapter 1: LPC23xx Introductory informationRev. 4.1 5 September 2012 User manual

Table 1. LPC23xx overviewPart Features Ordering info Ordering options Block diagramLPC2361/62 Section 1.3.1,

Section 1.3.2Table 3 Table 4 Figure 1

LPC2364/65/66/67/68 Section 1.3.1 Table 3 Table 5 Figure 2

LPC2377/78 Section 1.3.1, Section 1.3.3

Table 3 Table 6 Figure 3

LPC2387 Section 1.3.1, Section 1.3.4

Table 3 Table 7 Figure 4

LPC2388 Section 1.3.1,Section 1.3.4

Table 3 Table 8 Figure 5

UM10211 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved.

User manual Rev. 4.1 5 September 2012 3 of 708

NXP Semiconductors UM10211Chapter 1: LPC23xx Introductory information

16 kB Static RAM for Ethernet interface. Can also be used as general purpose SRAM. 8 kB Static RAM for general purpose or USB interface. Dual AHB system that provides for simultaneous Ethernet DMA, USB DMA, and

program execution from on-chip flash with no contention between those functions. A bus bridge allows the Ethernet DMA to access the other AHB subsystem.

Advanced Vectored Interrupt Controller, supporting up to 32 vectored interrupts. General Purpose DMA controller (GPDMA) on AHB that can be used with the SSP

serial interfaces, the I2S port, and the SD/MMC card port, as well as for memory-to-memory transfers.

Serial Interfaces: Ethernet MAC with associated DMA controller. These functions reside on an

independent AHB bus. On LPC2364/66/68, LPC2378, LPC2387, LPC2388: USB 2.0 device controller

with on-chip PHY and associated DMA controller. On LPC2388: USB Host/OTG controller. Four UARTs with fractional baud rate generation, one with modem control I/O, one

with IrDA support, all with FIFO. These reside on the APB bus. SPI controller, residing on the APB bus. Two SSP controllers with FIFO and multi-protocol capabilities. One is an alternate

for the SPI port, sharing its interrupt. The SSP controllers can be used with the GPDMA controller and reside on the APB bus.

Three I2C interfaces reside on the APB bus. The second and third I2C interfaces are expansion I2C interfaces with standard port pins rather than special open-drain I2C pins.

I2S (Inter-IC Sound) interface for digital audio input or output, residing on the APB bus. The I2S interface can be used with the GPDMA.

On LPC2364/66/68, LPC2378, LPC2387, LPC2388: Two CAN channels with Acceptance Filter/FullCAN mode residing on the APB bus.

Other APB Peripherals: On LPC2367/68, LPC2377/78, LPC2387, LPC2388: Secure Digital (SD) /

MultiMediaCard (MMC) memory card interface. Up to 70 (100 pin packages) or 104 (144 pin packages) general purpose I/O pins. 10 bit A/D converter with input multiplexing among 6 pins (100 pin packages) or 8

pins (144 pin packages). 10 bit D/A converter. Four general purpose timers with two capture inputs each and up to four compare

output pins each. Each timer block has an external count input. One PWM/Timer block with support for three-phase motor control. The PWM has

two external count inputs. Real-Time Clock (RTC) with separate power pin; clock source can be the RTC

oscillator or the APB clock. 2 kB Static RAM powered from the RTC power pin, allowing data to be stored

when the rest of the chip is powered off.

UM10211 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved.

User manual Rev. 4.1 5 September 2012 4 of 708

NXP Semiconductors UM10211Chapter 1: LPC23xx Introductory information

Watchdog Timer. The watchdog timer can be clocked from the internal RC oscillator, the RTC oscillator, or the APB clock.

Standard ARM Test/Debug interface for compatibility with existing tools. Emulation Trace Module. Support for real-time trace. Single 3.3 V power supply (3.0 V to 3.6 V). Four reduced power modes: Idle, Sleep, Power-down, and Deep power-down modes. Four external interrupt inputs. In addition every PORT0/2 pin can be configured as an

edge sensing interrupt. Processor wake-up from Power-down mode via any interrupt able to operate during

Power-down mode (includes external interrupts, RTC interrupt, and Ethernet walk-up interrupt).

Two independent power domains allow fine tuning of power consumption based on needed features.

Brownout detect with separate thresholds for interrupt and forced reset. On-chip Power On Reset (POR). On-chip crystal oscillator with an operating range of 1 MHz to 24 MHz. 4 MHz internal RC oscillator that can optionally be used as the system clock. For USB

and CAN application, the use of an external clock source is suggested. On-chip PLL allows CPU operation up to the maximum CPU rate without the need for

a high-frequency crystal. May be run from the main oscillator, the internal RC oscillator, or the RTC oscillator.

Boundary scan for simplified board testing is available in LPC2364FET100, LPC2368FET100 (TFBGA packages), LPC2377/78, and LPC2388.

Versatile pin function selections allow more possibilities for using on-chip peripheral functions.

1.3.2 Features available on LPC2361/62

Device/Host/OTG controller available. No Ethernet on LPC2361.

1.3.3 Features available in LPC2377/78 and LPC2388External memory controller that supports static devices such as Flash and SRAM. An 8-bit data/16-bit address parallel bus is available.

1.3.4 Features available in LPC2387 and LPC2388

64 kB of SRAM on the ARM local bus for