Ultra-low power model-based ASIC design for implantable ... · Title: Ultra-low power model-based...
27
Ultra-low power model-based ASIC design for implantable medical products using HDL Coder MATLAB EXPO 2017 Dean Andersen Abbott (formerly St. Jude Medical)
Transcript of Ultra-low power model-based ASIC design for implantable ... · Title: Ultra-low power model-based...
Ultra-low power model-based ASIC design for implantable medical products using HDL Coder
MATLAB EXPO 2017
Dean Andersen
Abbott (formerly St. Jude Medical)
Abstract
Model-based design is a path from algorithm to hardware implementation, in this case a full custom mixed-signal integrated circuit for class III implantable medical
products. For applications like these, custom integrated circuit die area and power consumption are critical for circuit performance as these parameters translate directly
to device size and device longevity. The model is used for design exploration and algorithm validation. The model is transformed to an RTL description using HDL Coder. The model is refined to meet power and area constraints while iterating
between HDL simulation results and model parameters to create the lowest possible power design. This presentation shows a typical design flow of modelling, validating
and implementing an algorithm into a custom ASIC. The steps in taking the design into an ASIC simulation environment to validate power and area are also presented.
MATLAB Expo 2017 2
Overview
About Abbott Motivation for ASIC design Model-based design Translation to HDL HDL verification Model validation
MATLAB Expo 2017 3
About Abbott
MEDICAL DEVICES*
38% of sales
ESTABLISHED PHARMACEUTICALS
15% of sales
DIAGNOSTICS
18% of sales
NUTRITION
26% of sales
MATLAB Expo 2017 4 * Based on 1 half 2017 results
About Abbott
Deep Brain Stimulation • Parkinson’s Disease
Spinal Cord Stimulation • Chronic pain
Cardiac Rhythm Management • Cardiac resynchronization
(CRT) • Cardiac pacemakers • Implantable cardioverters
defibrillators (ICD)
Insertable Cardiac Monitoring (ICM) • AF detection
Left Ventricle Assist Device (LVAD) • Heart failure
MATLAB Expo 2017 5
Overview
About Abbott Motivation for ASIC design Model-based design Translation to HDL HDL verification Model validation
MATLAB Expo 2017 6
Motivation for ASIC design
Why custom integrated circuits? • First implantable pacemaker in 1958
– Two-transistor blocking oscillator
– 55 mm in diameter, 16 mm depth
– Power from 2 rechargeable NiCad batteries
• Modern pacemaker – Millions of transistors
– Sophisticated embedded systems
– Offering responsive therapy based on individual patient’s needs
– Storing heart electrical activity for retrieval
– Wireless communication
– Hundreds of parameters programmable to adjust to patient
LARSSON, B., ELMQVIST, H., RYDÉN, L. and SCHÜLLER, H. (2003), Lessons From the First Patient with an Implanted Pacemaker:. Pacing and Clinical Electrophysiology, 26: 114–124. doi:10.1046/j.1460-9592.2003.00162.x
MATLAB Expo 2017 7
Motivation for ASIC design
Today – large scale of integration driven by small size and longevity • Longevity has been offset by device sophistication and technology • Most devices last 7 – 15 years • Features and algorithms are driving next generation devices Small size has opened new therapy opportunities • Leadless pacemakers • Pulmonary artery pressure • Insertable cardiac monitors
MATLAB Expo 2017 8
Motivation for ASIC design
Power budgets of pacemakers are extreme! • Typical implantable device has a primary cell at 2.8V • Average current of system: 10 – 20 µA • Peak current 2 – 5 mA • An 11 year device with a 1 A*hr battery • Miniature package
Analog 2
Digital 2
Therapy 6
Current (µA)
1 cm3 • 6mm diameter • 40 mm length
10 cm3 • 6mm thick,
MATLAB Expo 2017 9
Overview
About Abbott Motivation for ASIC design Model-based design Translation to HDL HDL verification Model validation
MATLAB Expo 2017 10
Model-based Design
Mixed signal designs • Analog design
– Schematic design
– Simulation
– Layout
• Digital design – HDL (hardware design language)
– Simulation
– Synthesis
– Automated place and route
Mixed Signal
Simulation
MATLAB Expo 2017 11
Model-based Design
Simulink® is a mixed-signal simulation environment • A bridge between analog and digital design • Familiarity to both analog and digital designers • Dynamic simulation environment
– Similar to transient simulation in SPICE
– Cycle by cycle event modeling similar to digital simulation
• Particularly strong in DSP applications
MATLAB Expo 2017 12
Model-based Design
Example: Sigma-Delta ADC • Cardiac electrogram sensing • 60 dB SNR • 3rd Order modulator • 150 nW power dissipation
MATLAB Expo 2017 13
SpectrumAnalyzer
DSP
Sine Wave Scope
3
3rd OrderSigma-Delta
To WorkspaceAnalog Reconstruction
Add
0
Constant
To Workspace1
Saturation
Data Type Conversion
0 200 400 600 800 1000 1200 1400 1600 1800 2000
Frequency (Hz)
-150
-100
-50
0
Pow
er s
pect
rum
(dB
W)
Periodogram
Ideal
Measured
Model-based Design
Example complete analog front end model
MATLAB Expo 2017 14
Input Stimulus
Amplifier & ADC
Highpass and Offset Compensation
Programmable Filters
Decimation Filters
Gain
Model-based Design
Example output
MATLAB Expo 2017 15
Overview
About Abbott Motivation for ASIC design Model-based design Translation to HDL HDL verification Model validation
MATLAB Expo 2017 16
Translation to HDL
Power vs Configurability • Trade-off between power and configurability • General purpose vs. application specific
MATLAB Expo 2017 17
• Application Specific • Low Configurability • Low Power
• General Purpose • High
Configurability • High Power
MCU DSP FPGA ASIC
Translation to HDL
Power Triangle • Most power benefits are at system and architecture levels
MATLAB Expo 2017 18
Circuit Level
Logic Level
Architecture Level
System Level
Translation to HDL
MATLAB Expo 2017 19
HDL models optimized for power • Minimum data paths
– Sizing and scaling of adders and multipliers
– Minimized area which minimizes power
– Parameterizing an RTL model for data path is difficult and requires extensive verification
• Choosing rounding methods – Parameterizing an RTL model for data path is difficult and requires extensive
verification
Translation to HDL
MATLAB Expo 2017 20
Architecture exploration • Quickly explore various topologies and architectures • Use MATLAB/Simulink to evaluate performance • Generate RTL and use simulation tools to evaluate power
HDL Coder
Power Analysis
Translation to HDL
Example: Bandpass filter • Approximately 10 – 30 Hz • 1000 Hz sample rate • Three implementations
– 2nd order Biquad IIR
– Two 1st order IIR
– Two 1st order integer IIR
MATLAB Expo 2017 21
10 20 30 40 50 60
Frequency, Hz
-45
-40
-35
-30
-25
-20
-15
-10
-5
0
Mag
nitu
de, d
B
Frequency Response of Filtering
10 20 30 40 50 60
Frequency (Hz)
-60
-50
-40
-30
-20
-10
0
Mag
nitu
de (d
B) (
norm
aliz
ed to
0 d
B)
Magnitude Response (dB)
0 10 20 30 40 50
Frequency, Hz
-60
-50
-40
-30
-20
-10
Mag
nitu
de, d
B
Frequency Response of Filtering
Translation to HDL
Power simulation results • Technology dependent on ASIC library • Power estimation using an EDA simulation tool
MATLAB Expo 2017 22
0
200
400
600
800
1000
1200
Biquad IIR 2 1st OrderIIR
2 1st OrderInteger
Energy (nW/MHz)
0
0.2
0.4
0.6
0.8
1
1.2
Biquad IIR 2 1st OrderIIR
2 1st OrderInteger
Relative Area
HDL verification
MATLAB Expo 2017 23
Verification steps • Block-level verification
– Output testbench from HDL coder provides a quick stand-alone verification
• Use HDL model along with data input and expected output – This is used to conform to existing testbench environment
– Can be ported to ASIC top level verification environment
• FPGA rapid prototyping for co-verification
Simulation
?
Overview
About Abbott Motivation for ASIC design Model-based design Translation to HDL HDL verification Model validation
MATLAB Expo 2017 24
HDL validation
MATLAB Expo 2017 25
Validation methodology • Post-silicon
– Vectors from simulation are run on actual silicon
– Power is verified
– Design is tested across parameters such as voltage and temperature
• Model for algorithm development – A MATLAB model(s) are created
• Usually both fixed point and non-fixed point
– Used by Research and System Engineering to validate behavior • For example for CRM devices tested against an extensive library of cardiac arrhythmias
• Animal and human testing
HDL validation
MATLAB Expo 2017 26
Lifecycle
Clinical or Marketing
Idea
Research
Development
Fabrication
Verification
Validation
Conclusion
MATLAB Expo 2017 27
HDL Coder in IC design flow • Rapid development from architecture to RTL
– Cuts significant amount of design time
– Very straightforward datapath optimization for power and performance
– Making parameterized RTL models is very time consuming and a verification challenge
• Intuitive signal flow centric • HDL hierarchy is equivalent to model
– This is necessary for proper evaluation of power
• Simulink model becomes the golden source for verification and validation
http://www.abbott.com/abbott-stjudemedical-en.html
![Ultra Low-Power Algorithm Design for Implantable Devices ... · from results of their human clinical study, published in 2005 [9]. ... consumption pie-chart of implantable medical](https://static.fdocuments.us/doc/165x107/5f48b2a1e9c4aa18062c41c4/ultra-low-power-algorithm-design-for-implantable-devices-from-results-of-their.jpg)
