IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 56, NO. 6, JUNE 2009 1277

Ultra High-Stress Liner Comprising Diamond-LikeCarbon for Performance Enhancement of

p-Channel Multiple-Gate TransistorsKian-Ming Tan, Student Member, IEEE, Mingchu Yang, Tsung-Yang Liow, Student Member, IEEE,

Rinus Tek Po Lee, Student Member, IEEE, and Yee-Chia Yeo, Member, IEEE

Abstract—We report the demonstration of strained p-channelmultiple-gate transistors or FinFETs with a novel liner-stressormaterial comprising diamond-like carbon (DLC). In this work,a DLC film with very high intrinsic compressive stress up to6 GPa was employed. For FinFET devices having a 20 nm thinDLC liner stressor, more than 30% enhancement in saturationdrain current IDsat is observed over FinFETs without a DLCliner. The performance enhancement is attributed to the couplingof compressive stress from the DLC liner to the channel, leadingto hole mobility improvement. Due to its extremely high intrinsicstress value, significant IDsat enhancement is observed even whenthe thickness of the DLC film deposited is less than 40 nm. TheDLC liner stressor is a promising stressor material for perfor-mance enhancement of p-channel transistors in future technologynodes.

Index Terms—Contact etch stop layer (CESL), diamond-likecarbon (DLC), FinFET, multiple-gate, strain.

I. INTRODUCTION

MULTIPLE-GATE transistors or FinFETs demonstratebetter control of short-channel effects and scalability

than planar transistors and show promise for possible adoptionbeyond the 22-nm technology generation [1]–[6]. To achievegood electrical performance, various strain engineering ormobility enhancement techniques could be employed on themultiple-gate transistor. A high-stress silicon nitride (SiN) lineror a contact etch stop layer with an intrinsic compressiveor tensile stress enhances the hole or electron mobility en-

Manuscript received November 19, 2008. Current version published May 20,2009. This work was supported by the National Research Foundation (NRF)under Research Grant NRF-RF2008-09.

K.-M. Tan is with the Logic Device Technology Team, Chartered Semi-conductor Manufacturing, Singapore 738406, and also with the Departmentof Electrical and Computer Engineering, National University of Singapore,Singapore 119260.

M. Yang is with the Data Storage Institute, Agency for Science, Technologyand Research (A∗STAR), Singapore 117608.

T.-Y. Liow is with the Institute of Microelectronics, Agency for Science,Technology and Research (A∗STAR), Singapore 117685, and also with theDepartment of Electrical and Computer Engineering, National University ofSingapore, Singapore 119260.

R. T. P. Lee is with the Silicon Nano Device Laboratory, Departmentof Electrical and Computer Engineering, National University of Singapore,Singapore 119260.

Y.-C. Yeo is with the Department of Electrical and Computer Engineering,National University of Singapore, Singapore 119260, and also with the Instituteof Microelectronics, Agency for Science, Technology and Research (A∗STAR),Singapore 117685 (e-mail: yeo@ieee.org; eleyeoyc@nus.edu.sg).

Digital Object Identifier 10.1109/TED.2009.2019388

Fig. 1. Comparison of reported intrinsic compressive-stress levels in high-stress liners employed in transistor demonstrations. (Open symbols) Integrationof such high-stress liners on planar transistors. (Closed symbols) Integration ofhigh-stress liners on multiple-gate transistors or FinFETs. (Circles) SiN high-stress liners. (Diamonds) DLC liners. Intrinsic compressive stress of the DLCis much higher than that of SiN.

hancement, respectively, and has already been adopted in themanufacturing of planar transistors. The SiN liner stressor hasalso been demonstrated to improve the saturation drain currentIDsat in multiple-gate device structures [6]–[9]. Nevertheless,the intrinsic stress of SiN is not high. p-Channel FinFETsintegrated with a SiN liner employed intrinsic compressivestress values in the range of ∼0.8–2 GPa (Fig. 1). A highermagnitude of stress has to be induced in the transistor channelregion to give further boost in device performance. This canbe achieved either by further increasing the intrinsic stressof SiN and/or its thickness, as the stress–thickness producthas been considered as a first-order figure of merit for linerstressors. Process tuning to increase the intrinsic stress in a SiNliner is challenging, and alternative materials with much higherintrinsic stresses would be required. For FinFETs, interactionsbetween the liner stressor and the fin sidewalls are importantcontributors to the channel stress as well. To increase thecompactness of circuits employing FinFETs with multiple fins,the fin pitch has to be reduced. Fin pitch reduction, however,will reduce the amount of the liner stressor material foundbetween the fins, as shown in Fig. 2, and could decreasethe stress effects. This is similar to the decline in the channelstress due to a reduced gate pitch [10]. Increasing the intrinsicstress rather than the thickness of the liner stressor is expectedto be beneficial. Therefore, there is a need to discover new

0018-9383/$25.00 © 2009 IEEE

1278 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 56, NO. 6, JUNE 2009

Fig. 2. Schematic of a FinFET device with a liner stressor and multiple semiconductor fins with a fin pitch pfin. Cross sections through the fin and the linerstressor on the right illustrate that fin-pitch reduction leads to reduced spacing between fins, and the volume of the liner stressor material found between fins willbe reduced, leading to reduced stress effects.

materials with a higher stress for possible adoption as a linerstressor in CMOS technology. We have recently demonstratedthe use of a diamond-like carbon (DLC) film having an intrinsiccompressive stress value that is significantly greater than thatof SiN [11], [12]. The DLC film has a very high intrinsiccompressive stress. Compressive stress values of 6 GPa orhigher can be achieved. We exploited this property of the DLCand integrated it as a liner stressor on p-channel field-effecttransistors [11], [12], demonstrating significant drive currentenhancement using a DLC liner-stressor thickness of less than40 nm. In addition, as the dielectric constant of the DLC canbe tuned to be lower than that of SiN, parasitic capacitance canbe reduced for achieving faster circuit speed. The integration ofthe DLC as a new liner-stressor material was first reported onplanar transistors [11]. Very recently, we have briefly reportedthe first demonstration of a DLC liner stressor on multiple-gatetransistors [13]. Details of the process integration of the DLCon FinFETs have not yet been reported. In addition, extensiveelectrical characterization on FinFETs with a DLC liner stressorhas recently been performed, but the results have not beenreported.

In this paper, we provide a detailed account of the process in-tegration of a DLC liner stressor on p-channel multiple-gatetransistors or FinFETs and also report on the extensive elec-trical characterization that was performed on the first strainedFinFETs with a DLC liner. Extensive measurement was doneto study the impact of a compressive stress from the DLC liner.Performance enhancement due to the DLC liner stressor will bediscussed.

II. MATERIAL CHARACTERIZATION

In this section, material characterization is discussed, and keyfactors considered in the deployment of the DLC as a linerstressor in CMOS technology are highlighted. The DLC is adense form of carbon. Its chemical, electrical, and mechanicalproperties are affected by the bonding configuration of carbon

in the film. Carbon atoms in the DLC can be sp3- or sp2-hybridized. A film having a high sp3 carbon content will haveproperties very close to those of diamond and will possess prop-erties such as extreme hardness, high resistivity, and chemicalinertness. The DLC film with a high sp3 content can still beetched using either a pure O2 plasma or a mixture of Ar and O2

plasma [14]. High sp2 carbon content, however, gives graphite-like properties, including high electrical conductivity. For liner-stressor application in which the DLC is to be formed overa p-channel transistor, the sp2 content has to be sufficientlylow so that there are no undesirable leakage paths in theDLC layer. A high sp2 content in the DLC liner would leadto intradevice leakage, e.g., between source and drain, andinterdevice leakage. Fig. 3(a) shows an X-ray photoelectronspectroscopy spectrum obtained from the DLC film used inthis work, showing the carbon 1s core level. The spectrumis deconvoluted into three peaks corresponding to sp3, sp2,and C–O bonds. In this work, the DLC film employed forintegration in FinFETs has an sp3 content of ∼60%, which wasestimated by taking the ratio of the area under the curve due tosp3-hybridized C to the total area under the C 1s curve. This sp3

content is acceptable for device realization in this experiment.If a larger resistivity is required, a DLC film with a highersp3 content can be employed. Alternatively, hydrogenation ofthe DLC can also be employed to increase its resistivity [15],[16]. In addition to sp3 content and resistivity, the intrinsicstress of the DLC is of particular importance for liner stressorapplication. Fig. 3(b) plots the magnitude of the compressivestress versus the sp3 content for DLC films deposited usingvarious techniques. Whereas a higher intrinsic compressivestress would be desirable for increased stress effects, the like-lihood of film delamination is also increased. Managing andpreventing the high-stress DLC film from delaminating are vitalfor its integration on transistors. For a given compressive stress,e.g., ∼6 GPa, the DLC film formed on transistors can locallydelaminate and buckle, as illustrated in the optical image ofFig. 4(a). “Phone-cord-like” delamination occurred in the DLC

TAN et al.: LINER COMPRISING DIAMOND-LIKE CARBON FOR PERFORMANCE ENHANCEMENT OF TRANSISTORS 1279

Fig. 3. (a) X-ray photoelectron spectra of the DLC film used in this work, showing the carbon 1s core level. The spectrum is fitted with curves having peakscorresponding to sp3, sp2, and C–O bonds. The DLC film exhibits a high sp3 content. (b) Comparison of the compressive-stress magnitude and the sp3 contentfrom DLC films deposited using various deposition techniques. This work shows the first demonstration of the DLC as a liner stressor on a multiple-gate transistor.

Fig. 4. (a) Optical microscopy image of a DLC film on a wafer with FinFET devices, in which film delamination and buckling occur due to the large intrinsiccompressive stress. A schematic showing the buckling of the film to relieve the high compressive stress is shown below. (b) Optical image of a thinner DLC film(∼20 nm) adhering well to the substrate when the DLC thickness is reduced.

film of Fig. 4(a). Films under compressive stress are susceptibleto buckling delamination when the elastic energy per unit areastored in the film exceeds the energy per area that is requiredto decohere the interface. Such buckling delamination is com-monly observed in thin films with a high compressive stress,films that are too thick, or with inadequate interfacial adhesion[17]. By reducing the deposition time and, therefore, the thick-ness of the DLC film deposited, good adhesion was achieved.We were able to avoid buckling of the DLC film, as shown in

Fig. 4(b), while achieving a substantial stress–thickness productfor device application.

III. DEVICE FABRICATION

Eight-inch silicon-on-insulator substrates with 35-nm-thickSi were used for the fabrication of p-channel FinFET devices.After threshold voltage Vth adjust implant, patterning using248-nm lithography and dry etching were performed to define

1280 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 56, NO. 6, JUNE 2009

the active regions comprising silicon fins with a fin width WFin

of down to 40 nm. The fin height HFin is 35 nm. The Si fins arealigned in the 〈110〉 direction. A gate stack consisting of SiO2

gate dielectric (∼3 nm) and a poly-Si gate was subsequentlyformed. The poly-Si gate was pre-doped with boron. A SiO2

hardmask was formed on the poly-Si gate. Gate lengths LG

down to 70 nm were defined with 248-nm lithography andhardmask trimming. This was followed by p+ S/D extensionimplant, SiO2 spacer liner deposition, SiN spacer deposition,and dry etching to form gate spacers. Poly-Si and SiN/SiO2

spacer stringers, which are also formed by the sides of thefins, were removed with an optimized dry-etching process [18].To reduce series resistance, slightly elevated Si source/drainregions were formed using an ultrahigh vacuum chemical vapordeposition. The thickness of Si that was selectively grown inthe S/D is ∼15 nm. After deep S/D implantation and dopantactivation, the SiO2 hardmask on the poly-Si gate was removed.Ni (5 nm) was then sputter-deposited and annealed to formNiSi on the gate and S/D regions. A thin NiSi was used, andthe fin was not completely silicided. A liftoff process was usedfor contact definition by patterning photoresist on the contactregions, followed by deposition of ∼10 nm SiO2 and ∼20 nm ofthe DLC. The SiO2 underlayer provides good adhesion betweenthe DLC and the NiSi region. To ensure a fair comparison,deposition of 10 nm SiO2 was similarly performed on thecontrol device (without the DLC). Eliminating or reducingthe thickness of the SiO2 underlayer is expected to improve thestress transfer from the DLC to the transistor channel, and thiswould be a good direction for continual improvement of theliner-stressor design.

For DLC deposition, we used a filtered cathodic vacuum arc(FCVA) system. In the FCVA system, carbon ions are generatedby an arc discharge and are introduced into the process chamberthrough a magnetic filter duct. Therefore, only ions with awell-defined energy can reach the substrate for deposition.The control of the carbon ion energy is important since ionbombardment contributes to the buildup of high stress in theDLC film [19]. DLC films with a compressive stress as largeas 7.5–10 GPa have also been reported using the FCVA system[11], [20]. The deposition of the DLC in this paper was done atarc and filter currents of 50 and 11 A, respectively. The thick-ness of the DLC deposited on the devices was around 20 nm,as measured from the transmission electron microscopy (TEM)image in Fig. 5. Scanning electron microscopy (SEM) imagesof the FinFET device after DLC deposition are also shown inFig. 5. A compressive stress as high as 6 GPa was obtained fromwafer-curvature measurement, separately done on a blanketwafer with about the same DLC thickness as that used fordevice demonstration. The intrinsic stress in the DLC is afunction of film thickness, and it is important that the sameDLC thickness is deposited on the blanket wafers for wafer-curvature measurement. The DLC in the contact regions wasremoved together with the resist using acetone, followed bythe removal of SiO2 using dilute HF. For the control FinFETdevices, the step of depositing the DLC was skipped, whereasother process steps are identical. Electrical characterization wasperformed by direct probing on the NiSi source, drain, and gatecontact regions.

Fig. 5. (a) Tilt view and (b) plan view SEM images of a p-channel FinFETwith a DLC liner. (c) TEM image taken in the nickel-silicided source/drainregion clearly showing the DLC film formed on a SiO2 liner.

IV. ELECTRICAL CHARACTERIZATION

The electrical characteristics of FinFETs with and withouta DLC liner stressor are compared next. Fig. 6(a) showsthe ID–VG plot of a pair of FinFETs with a gate length of80 nm and a fin width of 40 nm. The subthreshold swing(SS) and the drain-induced barrier lowering (DIBL) are around110 mV/dec and ∼0.05 V/V, respectively. Both devices havecomparable short-channel effects. The ID–VD characteristicsfor the matched pair of FinFETs are shown in Fig. 6(b). Thedrain current is normalized based on a tri-gate structure, witha device width given by (2HFin + WFin). At a gate overdrive(VG − Vth) of −1.2 V and a drain voltage VD of −1.2 V, thestrained FinFET having a DLC liner shows an ∼38% enhance-ment of saturation drain current IDsat over the control device.Since the process flows for the control FinFET and the strainedFinFET are identical except for the DLC deposition step, theenhancement in IDsat is attributed to the presence of the highlycompressive-stressed DLC liner. Compressive strain is inducedin the Si channel, which leads to hole mobility and drive currentenhancement. Fig. 7 compares the transconductance of thedevices shown in Fig. 6. A 54% higher peak transconductanceis observed for the strained FinFET over the control FinFET,indicating hole mobility enhancement. This is consistent withthe enhancement observed in the drain current shown in theID–VD plot.

A large number of devices were characterized to comparethe OFF-state leakage current Ioff versus the drain–current(Fig. 8). Gate lengths of the devices characterized range from

TAN et al.: LINER COMPRISING DIAMOND-LIKE CARBON FOR PERFORMANCE ENHANCEMENT OF TRANSISTORS 1281

Fig. 6. Comparison of (a) ID–VG and (b) ID–VD characteristics for FinFETs with and without a DLC liner at a gate length of 80 nm. Similar SS and DIBL areobserved. ID–VD curves with gate overdrive VG − Vth from 0 to −1.2 V in steps of −0.2 V are shown. A 38% enhancement in the saturation drain–current isobserved for the FinFET with a DLC liner stressor over the control FinFET.

Fig. 7. Transconductance as a function of the gate voltage, showing 54%improvement in the peak transconductance for the strained FinFET with a DLCliner over the control FinFET. The gate length is 80 nm, and the fin widthis 40 nm.

50 to 80 nm. The DLC liner stressor increased IDlin by 66%at an Ioff of 100 nA/μm. At an Ioff of 100 nA/μm, a 50%enhancement in IDsat was observed for the strained FinFETs[13]. The drive-current performance of the devices can befurther improved with the use of a thinner gate dielectric andfurther optimization of the S/D doping and activation condi-tions. In general, the coupling of stress from the DLC film tothe channel is also influenced by the source/drain topology.With a reduced S/D elevation for a FinFET structure, a betterstress transfer can be achieved, but higher series resistance mayreduce the strain-induced mobility enhancement. We also plotthe drive current performance as a function of indicators ofshort-channel effects such as the DIBL and the SS in Figs. 9 and10, respectively. Data points in Figs. 9 and 10 are obtained fromFinFETs with LG ranging from 50 to 80 nm. At a fixed DIBL of0.1 V/V, the IDsat enhancement is 42%, and at a fixed SS of

Fig. 8. Plot of OFF-state leakage current Ioff (VG = −0.5 V) versusdrain–current in the linear regime (VG = −1.7 V) for strained FinFETs andcontrol FinFETs. VD was fixed at −0.1 V. For each device split, about50 FinFETs or data points were measured.

120 mV/dec, the IDsat enhancement is 39%. Thus, for givencontrollability of short-channel effects, the DLC liner stressorprovides significant performance enhancement for FinFETs.

V. CONCLUSION

We have developed a liner stressor comprising DLC withan ultrahigh intrinsic compressive stress of ∼6 GPa. The firstp-channel multiple-gate transistor with a DLC liner stressorwas demonstrated. At a fixed Ioff , FinFETs with a DLC linerstressor show a very significant IDsat enhancement over controlFinFETs without a DLC liner stressor. The intrinsic com-pressive stress in the DLC film is effectively coupled to the

1282 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 56, NO. 6, JUNE 2009

Fig. 9. DLC liner stressor significantly enhances the drive current IDsat ofFinFETs at various values of the DIBL. Devices with gate lengths rangingfrom 50 to 80 nm were characterized. IDsat was measured at gate overdrive(VG − Vth) = −1.2 V and VD = −1.2 V. At a fixed DIBL of 0.1 V/V, thestress from the DLC liner contributed to a 42% IDsat enhancement.

Fig. 10. At a fixed SS of 120 mV/dec, the DLC liner stressor contributes toa significant IDsat enhancement of 39%. IDsat was measured at VG − Vth =−1.2 V and VD = −1.2 V.

FinFET channel, leading to the increase in hole mobility anddrive current. Due to the large intrinsic stress in the DLC, arelatively small thickness of ∼20 nm was sufficient to providea significant performance enhancement.

ACKNOWLEDGMENT

The authors would like to thank C.-H. Tung of the Instituteof Microelectronics for TEM analysis and H.-C. Chin of theNational University of Singapore (NUS) for SEM analysis.K.-M. Tan would like to thank the NUS and Chartered

Semiconductor Manufacturing, Singapore, for a graduatescholarship.

REFERENCES

[1] F.-L. Yang, D.-H. Lee, H.-Y. Chen, C.-Y. Chang, S.-D. Liu, C.-C. Huang,T.-X. Chung, H.-W. Chen, C.-C. Huang, Y.-H. Liu, C.-C. Wu, C.-C. Chen,S.-C. Chen, Y.-T. Chen, Y.-H. Chen, C.-J. Chen, B.-W. Chan, P.-F. Hsu,J.-H. Shieh, H.-J. Tao, Y.-C. Yeo, Y. Li, J.-W. Lee, P. Chen, M.-S. Liang,and C. Hu, “5 nm-gate nanowire FinFETs,” in VLSI Symp. Tech. Dig.,Honolulu, HI, Jun. 2004, pp. 196–197.

[2] Y.-K. Choi, N. Lindert, P. Xuan, S. Tang, D. Ha, E. Anderson, T.-J. King,J. Bokor, and C. Hu, “Sub-20 nm CMOS FinFET technologies,” in IEDMTech. Dig., Washington, DC, Dec. 2–5, 2001, pp. 421–424.

[3] J. Kedzierski, E. Nowak, T. Kararsky, Y. Zhang, D. Boyd, R. Carruthers,C. Cabral, R. Amos, C. Lavoie, R. Roy, J. Newbury, E. Sullivan,J. Benedict, P. Sanders, K. Wong, D. Canaperi, M. Krishnan,K.-L. Lee, B. A. Rainey, D. Fried, P. Cottrell, H.-S. P. Wong, M. Ieong,and W. Haensch, “Metal-gate FinFET and fully-depleted SOI devicesusing total gate silicidation,” in IEDM Tech. Dig., San Francisco, CA,Dec. 8–11, 2002, pp. 247–250.

[4] B. Yu, L. Chang, S. Ahmed, H. Wang, S. Bell, C.-Y. Yang, C. Tabery,C. Ho, Q. Xiang, T.-J. King, J. Bokor, C. Hu, M.-R. Lin, andD. Kyser, “FinFET scaling to 10 nm gate length,” in IEDM Tech. Dig., SanFrancisco, CA, Dec. 8–11, 2002, pp. 251–254.

[5] T.-Y. Liow, K.-M. Tan, R. T. P. Lee, M. Zhu, B. L.-H. Tan,N. Balasubramanian, and Y.-C. Yeo, “Germanium source and drainstressors for ultra-thin-body and nanowire field-effect transistors,” IEEEElectron Device Lett., vol. 29, no. 7, pp. 808–810, Jul. 2008.

[6] N. Collaert, A. De Keersgieter, K. G. Anil, R. Rooyackers, G. Eneman,M. Goodwin, B. Eyckens, E. Sleeckx, J.-F. de Marneffe, K. De Meyer,P. Absil, M. Jurczak, and S. Biesemans, “Performance improvement oftall triple gate devices with strained SiN layers,” IEEE Electron DeviceLett., vol. 26, no. 11, pp. 820–822, Nov. 2005.

[7] T.-Y. Liow, K.-M. Tan, R. T. P. Lee, A. Du, C.-H. Tung, G. S. Samudra,W.-J. Yoo, N. Balasubramanian, and Y.-C. Yeo, “Strained N-channel Fin-FETs with 25 nm gate length and silicon–carbon source/drain regions forperformance enhancement,” in VLSI Symp. Tech. Dig., 2006, pp. 68–69.

[8] T.-Y. Liow, K.-M. Tan, R. T. P. Lee, C.-H. Tung, G. S. Samudra,N. Balasubramanian, and Y.-C. Yeo, “N-channel (110)-sidewall strainedFinFETs with silicon–carbon source and drain stressors and tensile cap-ping layer,” IEEE Electron Device Lett., vol. 28, no. 11, pp. 1014–1017,Nov. 2007.

[9] J. Kavalieros, B. Doyle, S. Datta, G. Dewey, M. Doczy, B. Jin,D. Lionberger, M. Metz, W. Rachmady, M. Radosavljevic, U. Shah,N. Zelick, and R. Chau, “Tri-gate transistor architecture with high-k gatedielectrics, metal gates and strain engineering,” in VLSI Symp. Tech. Dig.,2006, pp. 50–51.

[10] A. Oishi, O. Fujii, T. Yokoyama, K. Ota, T. Sanuki, H. Inokuma, K. Eda,T. Idaka, H. Miyajima, S. Iwasa, H. Yamasaki, K. Oouchi, K. Matsuo,H. Nagano, T. Komoda, Y. Okayama, T. Matsumoto, K. Fukasaku,T. Shimizu, K. Miyano, T. Suzuki, K. Yahashi, A. Horiuchi, Y. Takegawa,K. Saki, S. Mori, K. Ohno, I. Mizushima, M. Saito, M. Iwai, S. Yamada,N. Nagashima, and F. Matsuoka, “High performance CMOSFET tech-nology for 45 nm generation and scalability of stress-induced mobilityenhancement technique,” in IEDM Tech. Dig., Washington, DC, Dec. 5–7,2005, pp. 229–232.

[11] K.-M. Tan, M. Zhu, W.-W. Fang, M. Yang, T.-Y. Liow, R. T. P. Lee,K. M. Hoe, C.-H. Tung, N. Balasubramanian, G. S. Samudra, andY.-C. Yeo, “A new liner stressor with very high intrinsic stress (> 6 GPa)and low permittivity comprising diamond-like carbon (DLC) forstrained p-channel transistors,” in IEDM Tech. Dig., Washington, DC,Dec. 10–12, 2007, pp. 127–130.

[12] K.-M. Tan, M. Zhu, W.-W. Fang, M. Yang, T.-Y. Liow, R. T. P. Lee,K. M. Hoe, C.-H. Tung, N. Balasubramanian, G. S. Samudra, andY.-C. Yeo, “A high stress liner comprising diamond-like carbon (DLC)for strained p-channel MOSFET,” IEEE Electron Device Lett., vol. 29,no. 2, pp. 192–194, Feb. 2008.

[13] K.-M. Tan, W.-W. Fang, M. Yang, T.-Y. Liow, R. T.-P. Lee,N. Balasubramanian, and Y.-C. Yeo, “Diamond-like carbon (DLC) liner:A new stressor for p-channel multiple-gate field-effect transistors,” IEEEElectron Device Lett., vol. 29, no. 7, pp. 750–752, Jul. 2008.

[14] M. Massi, J. M. J. Ocampo, H. S. Maciel, K. Grigorov, C. Otani,L. V. Santos, and R. D. Mansano, “Plasma etching of DLC films formicrofluidic channels,” Microelectron. J., vol. 34, no. 5–8, pp. 635–638,May–Aug. 2003.

TAN et al.: LINER COMPRISING DIAMOND-LIKE CARBON FOR PERFORMANCE ENHANCEMENT OF TRANSISTORS 1283

[15] M. K. Hassan, B. K. Pramanik, and A. Hatta, “Comparative study onchemical vapor deposition of diamond-like carbon films from methaneand acetylene using RF plasma,” Jpn. J. Appl. Phys., vol. 45, no. 10B,pp. 8398–8400, Oct. 2006.

[16] M. Massi, H. S. Maciel, C. Otani, R. D. Mansano, and P. Verdonck, “Elec-trical and structural characterization of DLC films deposited by magnetronsputtering,” J. Mater. Sci.: Mater. Electron., vol. 12, no. 4–6, pp. 343–346,Jun. 2001.

[17] M. W. Moon, H. M. Jensen, J. W. Hutchinson, K. H. Oh, and A. G. Evans,“The characterization of telephone cord buckling of compressed thin filmson substrates,” J. Mech. Phys. Solids, vol. 50, no. 11, pp. 2355–2377,Nov. 2002.

[18] K.-M. Tan, T.-Y. Liow, R. T. P. Lee, K. M. Hoe, C.-H. Tung,N. Balasubramanian, G. S. Samudra, and Y.-C. Yeo, “Strained p-channelFinFETs with extended Π-shaped silicon-germanium source and drainstressors,” IEEE Electron Device Lett., vol. 28, no. 10, pp. 905–908,Oct. 2007.

[19] A. C. Ferrari, S. E. Rodil, J. Robertson, W. I. Milne, “Is stress necessaryto stabilise sp3 bonding in diamond-like carbon?” Diamond Relat. Mater.,vol. 11, no. 3–6, pp. 994–999, Mar.–Jun. 2002.

[20] R. Pastorelli, A. C. Ferrari, M. G. Beghi, C. E. Bottani, andJ. Robertson, “Elastic constants of ultrathin diamond-like carbon films,”Diamond Relat. Mater., vol. 9, no. 3–6, pp. 825–830, Apr./May 2000.

Kian-Ming Tan (S’08) received the B.Eng.,M.Eng., and Ph.D. degrees in electrical and com-puter engineering from the National University ofSingapore (NUS), Singapore, where he worked onplasma-etching technologies, multiple-gate transis-tors, strained-silicon-device technologies, and ad-vanced stressor technologies.

He is currently with the Department of Electricaland Computer Engineering, NUS, and also with theLogic Device Technology Team, Chartered Semi-conductor Manufacturing, Singapore.

Mingchu Yang received the Ph.D. degree fromTsinghua University, Beijing, China, in 2001.

He is currently a Senior Research Fellow with theData Storage Institute, Agency for Science, Technol-ogy and Research, Singapore. His research interestsinclude thin-film deposition, carbon overcoat, andtribology at the head–disk interface of the computerhard-disk drive.

Tsung-Yang Liow (S’06) received the B.Eng. andPh.D. degrees in electrical and computer engineeringfrom the National University of Singapore (NUS),Singapore, in 2003 and 2008, respectively.

He is currently with the Institute of Microelectron-ics, Agency for Science, Technology and Research(A∗STAR), Singapore, working on silicon photoniccomponents and circuits. He is also with the De-partment of Electrical and Computer Engineering,NUS. His research interests include the design andthe fabrication of sub-10-nm multiple-gate FDSOI

and nanowire transistors, as well as performance-enhancement techniques suchas channel-strain engineering.

Dr. Liow received the NUS Faculty of Engineering Innovation Award in 2003and the A∗STAR Graduate Scholarship in 2004–2007.

Rinus Tek Po Lee (S’06) received the B.S. degree inelectrical engineering and the M.S. degree in appliedphysics from the National University of Singapore(NUS), Singapore, where he is currently workingtoward the Ph.D. degree in electrical engineering,with the research focus of parasitic resistance scalingin multiple-gate nanoscale transistors.

He was with the Institute of Materials Researchand Engineering, Agency of Science, Technologyand Research, Singapore, where he worked on thedevelopment of advanced process technologies for

contact metallization. Since 2005, he has been with the Silicon Nano DeviceLaboratory, Department of Electrical and Computer Engineering, NUS. Afterreceiving his Ph.D. degree, he will join the Bosch Asia Pacific Research andTechnology Center, Singapore. His current research interests include devicephysics and process technology integration for the multiple-gate transistorarchitecture.

Mr. Lee was the recipient of the Marubun Research Promotion FoundationGrant for the 2006 Solid State Devices and Materials Conference, Yokohama,Japan, the 2007 Gold Award at the Taiwan Semiconductor ManufacturingCompany (TSMC) Outstanding Student Research Award Ceremony, and theFirst Prize for Outstanding Performance in the 2008 TSMC Internship Program.

Yee-Chia Yeo (S’98–M’02) received the B.Eng.(with first class honors) and M.Eng. degrees inelectrical engineering from the National Universityof Singapore (NUS), Singapore, and the M.S. andPh.D. degrees in electrical engineering and computersciences from the University of California, Berkeley.

He had worked on optoelectronic devices withthe British Telecommunications Laboratories, U.K.,and on CMOS technology with the University ofCalifornia. In 2001–2003, he worked on exploratorytransistor technologies with Taiwan Semiconductor

Manufacturing Company (TSMC). He is currently an Assistant Professor inelectrical and computer engineering with the Department of Electrical andComputer Engineering, NUS. He is also a Research Program Manager withthe Agency for Science, Technology and Research, Singapore. He has authoredor coauthored 300 journal and conference papers and a book chapter. He isthe holder of 76 U.S. patents. His research interests include strained-channeltransistors, high-mobility devices, contact-resistance reduction technologies,and devices with reduced SS.

Dr. Yeo was the recipient of the 1995 IEE Prize from the Institution ofElectrical Engineers, U.K., the 1996 Lee Kuan Yew Gold Medal, the 1996Institution of Engineers Singapore Gold Medal, the 1997–2001 NUS Over-seas Graduate Scholarship Award, the 2001 IEEE Electron Devices SocietyGraduate Student Fellowship Award, the 2002 IEEE Paul Rappaport Award,and the 2003 TSMC Invention Awards. He was also the recipient of the 2006Singapore Young Scientist Award and the Singapore Youth Award in Scienceand Technology, and of the 2008 National Research Foundation Fellowship andthe NUS Young Researcher Award. In 2005 and 2006, he served on the IEDMSubcommittee on CMOS Devices.