UIC_Thesis_Defense_Vinella

A study of using STT-MRAM as Memory PUF: design, modeling and quality evaluation

Paolo Vinella

– Thesis Defense –

Academic Committee:Wenjing RaoZhichun ZhuFabrizio Bonani

Chicago, Turin - May 7, 2015

Master of Science in Electrical and Computer Engineering

SummaryCONTENTS:

• Introduction on the relevant topics

• Thesis goals & Workflow organization

2

Introduction on the relevant topics

3

• Preliminary work on MRAM to realize “binary signature”

• Low-cost, secure, reliable and tampering-resistant

• Applications: chip signature + secure authentication

New memory device: MAGNETIC MEMORY

(STT-MRAM)

New application for Hardware Security: PHYSICALLY UNCLONABLE FUNCTION

(PUF)

Summary

Thesis goals & Workflow organization

4

STT-MRAM tech PUF

Tunneling Magnetoresistance

Previous Work: MRAM as PUF

MY

WO

RK 2 – Verify and re-implement previous work+

Augment previous work

4 – Propose a new “Strong PUF”

1 – Study process variation effect on MRAM cell

3 – Evaluate PUF Quality

Summary

MRAM Technology

CONTENTS:

• ITRS: need of new memory tech

• MRAM a good new memory candidate

• STT-MRAM working principles

• Magnetoresistance effect

• MRAM Memory Array

• Applications

5

ITRS: need of new memory tech

6MRAM Technology

• International Technology Roadmap for Semiconductors, 2013 Issue

• Need to solve ICs scale-down limits & limitations

• NEAR TERM (2013-2020):o CMOS scalingo Enduranceo Noise margin reductiono Solve memory latency gap

• LONG TERM (2021-2028):o New memory structures: replace DRAM/SRAMo Non-volatile memories (NVM) possible candidateo Implement non-charge-storage type of NVM cost effectivelyo Keep it smart: “low-cost, high-density, low-power, low-latency”

MRAM a new good memory candidate

7MRAM Technology

• Current memory technologies: none is the best!• Advanced MRAM (p-STT-MRAM) a solution

DREAM-MEMORY:ü unique, universal, fast memoryü only advantages of current memoriesü little cost / extra design effort

DREAM MEMORY

LATENCY

CAPACITY

1ns

10ns

100ns

1 ms

MB GB TB

Hard Disk drives

Flash (NOR)

Flash(NAND)

T R E N D

Field MRAM

CPU Registers

Cache (SRAM)

Main mem. (DRAM)

STT-MRAM

STT-MRAM working principles

8MRAM Technology

• Magnetic memory: based on ELECTROMAGNETISM

• M (magnetic dipole moment): natural magnetization of a material

• Based on MTJ: Magnetic Tunneling Junction

(Ferromagnet + Oxide + Ferromagnet)

FREE layerMgO

PINNED layer

• MRAM use = control M direction of ferromagnetic layer (“SWITCHING”)

o Field MRAM: use external magnetic field

o STT-MRAM: more clever, uses current flowing through

Magnetoresistance effect

9MRAM Technology

FerroMagnet

Tunneling Oxide

FerroMagnet

Rp

Rap

bit ‘0’

bit ‘1’

PARALLEL STATE (P):

ANTIPARALLEL STATE (AP):

MRAM Memory Array

10MRAM Technology

WL

BL

SL

Ip Iap

RMTJFREE layer

MgO

PINNED layer

RMTJ

R P

R APVMTJ

VMTJ

Source Drain

Gate

MTJ

G

D

S

(a) (b) (c)

BL j SL j

WL i

WL i+1

BL j-1 SL j-1 BL j+1 SL j+1

10 1WL i

BL j BL j+1BL j-1

APP APPROGRAMMING PATTERN:

+ V cell j-1 – – V cell j + – V cell j+1 +

I P I AP I AP

Applications

11MRAM Technology

NANO-ELECTRONICS• MTJ-based BJT• Pseudo-spin-MOSFET *

AS PROPER MEMORY

• Universal memory: p-STT-MRAM by Toshiba *

DIGITAL BLOCKS

• Unbalanced MTJ flip-flop à FPGA• Logic in Memory (runtime reconfig. LUT) *• Associative Computing

MICROARCHITECTURES• Normally-Off Processor with p-STT-MRAM (cache)• Resistive Computation: entire non-volatile CPU

à Hardware Security and PUF: the newest and less mature use ß

HW Security& PUF

CONTENTS:

• Chips Piracy

• Hardware Security

• Physically Unclonable Function (PUF)

12

Chips Piracy

13HW Security & PUF

• Engineering products = result of clever insights and breakthroughs

• Every idea should be protected against theft and plagiarism

• Fab-less company à chip design shared with manufacturer(s)

• Untrusted parties may access, steal, re-use design illegally

Company A(Fab-less Designer)

Company B(Manufacturer)

Unprotected Chip Design



Protected Chip Design

Hardware Security

14HW Security & PUF

• Fight design thefts: add some sort of extra “layer of security”

• Rules + protocols + implementations embedded at design stage of a chip

• New research area: HARDWARE SECURITY

• Identify a given chip: “ID, UNIQUE SIGNATURE”



Unprotected Chip Design



Protected Chip Design

Physically Unclonable Function (PUF) (1)

15HW Security & PUF

NEW BUT… OLD!

Identification of nuclear weapons during the Cold War:

1. “CHALLENGE”: spray thin coating light-reflecting particles on nuclear weapon

2. Particles are randomly distributed

3. “RESPONSE”: illuminate weapons from different

angles à get different interference patterns

UNIQUE/UNCLONABLE SIGNATURE STORED IN A SECURE DATABASE!


16HW Security & PUF

• Physical: rely on a feature of materials constituting an electronic chip

• Unclonable: unique and tampering-resistant

• Function: generate useful information for identification purposes

• Exploit manufacturing process inaccuracies (rather fought at the digital level!)

• Challenge: let analog and digital domains coexist + using process variation

PROCESS VARIATION(oxide thickness, doping fluctuations,

feature size, trapped charges,…)

MANIFACTURING PROCESS STEPS

Chip#1

CHIPS LOTVariation in physical features of each chip

PUFyi = f x i

i=1…N

SIGNATURES

Easy to generate !

Difficult to invert "

Signature#1

Signature#2

Signature#i

Signature#N

…

…

x1

x2

xi

x N

y 1y 2

yi

yN

Chip#2

Chip#i

Chip#N

OXIDE

DOPING

FEAT. SIZE

TRAPPED

CHARGES


17HW Security & PUF

• Totally random, easy to generate, hard to invert

• Analog PUF: laser on 3D token à unique interference pattern

• Popular digital PUFs: “Ring Oscillator ” and “SRAM initialization”

• Current practice for HW authentication: secret key in NVM

(EEPROM), and use hardware cryptographic operations

• PUF avoids to use EEPROM / other expensive HW: nothing

stored in a memory, but derives a signature “on the fly”

Previous WorkMRAM as PUF

CONTENTS:

• MRAM Resistance dispersion as PUF

• Previous Work ideas

• Sensing schemes

• Results

18

Ref: Zhang L. et al. , Feasibility study of emerging non-volatile memory based physical unclonable functions. In Memory Workshop (IMW) 2014 IEEE

MRAM Resistance dispersion as PUF

19Previous WorkMRAM as PUF

R [Ω]μ Rp

σ Rp

σ Rap

R [Ω]Rpnom Rapnom μ Rap

bit ‘0’ bit ‘1’bit ‘0’ bit ‘1’

IDEAL REALPROCESS'VARIATION

n"# $ Rp

Engineer resistance dispersion:

random physical phenomena à source of a robust signature generation

Previous Work ideas


For each WORD, process each BIT exploiting MTJ resistance variation

generating a PUF response bit

Response is a binary string

STT-MRAM

chip

WLi

BLj SLjRMTJ

B I T L I N E S ( B L + S L )

W O

R D

L

I N

E S

b0 b1 … … … … bL

… … … …

PUFyi = f x i

i=1…L

TO THE INSIDE …

PUF Signature String 0PUF Signature String 1

…………

PUF Signature String M

B I T L I N E S ( B L + S L )

W O

R D

L

I N

E S

L - bits

M -

word

s

Sensing schemes


+

–

Ref_CellData_Cell

ΔIsens,min

IDATA

IREF+

–

Data_Cell_2Data_Cell_1

ΔIsens,min

IDATA1

IDATA2

WLi WLi

WLi WLi

PUF_bit PUF_bit

CASE 1 CASE 2

• Ideally, two identical currents (nominal RP or RAP)

• Process variation à resistance dispersion leads to different actual values

• Same read voltage à to two different currents!

• Sense amplifier detects mismatch and produces output PUF bit

Results


AS A PUF

• STT-MRAM can generate a “good quality” PUF

• Best results with differential schemes (no reference)

• STT-MRAM the best NVM as PUF (BER)

AS A MEMORY

• “Dream Memory”

• MTJs have high endurance à higher signature reliability

• Resistant to external disturbances

23

MY WORK1. Study on process variation effects on

MRAM cell

2. Verify + Augment previous work

3. Evaluate PUF Quality

4. Outlook: upgrading to a “strong PUF”

The complete simulation framework, overview

24

MAIN_RpRap_analysis.m

MTJ_Rp_Rap_populations.m

tox_var_effect_on_RpRap.m

MAIN_PUF_simulation.m

case1_1T1MTJ_with_reference.m

case2_2T2MTJ_no_reference.m

case3_2T2MTJ_with_reference.m

Case4_2T2MTJ_no_reference.m

BER_for_various_deltaI_PvsAP.m

case1_UniquenessEval.m




sense_amplifier.m

plot_BER.m

1N=5000tox_nom=0.85nm, σ=1%RA=10Ωμm2

A=B=65nm, σ=3%TMR0=120%Vbias_nom=0.1V, σ=1%

AB

tox0.1V

N, tox_nom, tox_dev,RA, A, B, size_dev, TMR0,Vbias_nom, Vbias_dev

N, Rp_pop, Rap_pop,Vbias_pop, tox_nom, RA, A, B, TMR0

N, RA, A, B, TMR0, Vbias_nom

Rp_pop, Rp_pop,Vbias_pop

FIVE PLOTS ONPOPULATION PERFORMANCES

@ tox = 0.85 ; 1 ; 1.15 nmPLOT : σRp , σRap = f ( σtox )

μRp , μRap = f ( σtox )Given : Vbias, A, B constant and varying

MTJ_pop_param_eval.m

used by

used by

used by

2choose: !

σtox=1%σFeatSize=3%

then:Nchips=100PUF size: (m=32) x (l=32)

other param. exactly as

CHIPS_STT_MRAM

L

M

Nchips

1

error,Iplus, Iminus resp_bit

used by

used by

used by

used by

used by

N, m, l, state,CHIPS_STT_MRAM,sense_ampl_err

same as case1

same as case1

same as case1

Menu, N, m, l, CHIPS_STT_MRAM,tox_nom, A, B, TMR0

flag=1

flag=1

flag=1

flag=1

flag=0

IF flag=1 && sense_ampl_err=0




err_bit_percentage

err_bit_percentage

err_bit_percentage

err_bit_percentage

FOR THE SELECTED CASE, let sense ampl. error varythen compute and plot the associated BER.

PLOT: Hamming Distance, Hamming Weight, Bit Aliasing




PLOT the BER for Case 1, 2, 3 and 4

o Implemented in Matlabo Made versatile

Study on process variation

effects on MRAM cell

CONTENTS:

• Memory cells MTJ resistance model

• RP/RAP interesting results

• Oxide thickness effects on RP/RAP

populations

25

Memory cells MTJ resistance model

26Process variation effects on MRAM cell

• MRAM as PUF à RP and RAP

• Nominal values with equation models, most accurate found (*):

R#,R%# = f (t+, ,RA , Area , ϕ , V3456)

(*) Ref: Zhao W. et al. , Macro-model of spin-transfer torque based magnetic tunnel junction device for hybrid magnetic-CMOS design. In Behavioral Modeling and Simulation Workshop 2006, IEEE

• So far, dispersion of RP / RAP found producing sample devices

• Bond the two approaches to check suitability as a PUF

• Simulation based on Monte Carlo to emulate process variation effects on RP/AP

−0.5 −0.4 −0.3 −0.2 −0.1 0 0.1 0.2 0.3 0.4 0.52000

2500

3000

3500

4000

4500

5000

5500

6000

6500

7000

Rp and Rap vs Bias Voltage of MTJ, with no variations in device geometrytox = 0.85 nm − Feat.size = 65 nm − TMR = 120 %

Vbias [mV]

Rp

and

Rap

[Ω]

Rp=f(VMTJ)Rap=f(VMTJ)

RP/RAP interesting results


2000 3000 4000 5000 6000 7000 8000 90000

50

100

150

200

250

300

350

400

450

500

Rp and Rap MTJ simulated distribution − Sample size = 5000tox = 0.85 nm − Feat.size = 65 nm − TMR = 120 %

Resistance [Ω]

Co

un

ts [

# d

evi

ces

with

th

at

Re

sist

an

ce]

Rp distributionRap distribution

INPU

TSN=5000 cells, elliptic shape

PARAMETER μ σtOX 0.85 nm 1 %

A , B 65 nm 3 %Vbias 100 mV 1 %TMR0 120 %

RA 10 Ωμm2

Oxide thickness effects on RP/RAP populations


• Understand how far to push resistance dispersion of MTJs

• PROCESS VARIATION à the base for for PUF

• At same time, need reliable memory cells for classic applications: data storage!

Oxide thickness the center of gravity

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 50

5

10

15

20

25

30

35

40

45

50

STT−MTJs σRap

and σRap

, (% over mean value) − Sample size = 5000

TMR = 120%V

read = 0.1V , Feat.size = 65nm (both w/ 5% variation)

For different oxide thicknesses

σtox

[%]

σR

p ,

σR

ap

[%]

σRp

@ tox

= 0.85nm

σRap

@ tox

= 0.85nm

σRp

@ tox

= 1nm

σRap

@ tox

= 1nm

σRp

@ tox

= 1.15nm

σRap

@ tox

= 1.15nm

• tOX ↑ and σtox ↑à RP/RAP dispersion ↑

• No variability whatsoever à back to

nominal case

• But when tOX<1nm also variability of other

physical quantities matters

• Strong influence of tOX on RP/RAP: makes

sense (e- tunneling)

Verify + Augment previous work

CONTENTS:

• Augment MRAM PUF Signature

• Design schemes variation

• Simulation details

29

Augment MRAM PUF Signature

30Verify+Augment previous work

STT-MRAM

STT-MRAM

STT-MRAM

STT-MRAM

STT-MRAM

B I T L I N E S ( B L + S L )L - bits

PUF Signature for chip i

(entire memory matrix used) W

O R

D

L I N

E S

M -w

ords

MRAM_CHIP_N

MRAM_CHIP_1

MRAM_CHIP_2

MRAM_CHIP_i

MRAM_CHIP_N-1P

R O D

U C

T I O

N

L O

T

STT-MRAM

STT-MRAM

STT-MRAM

STT-MRAM

STT-MRAM

STT-MRAM

N devices in theproduction lot

N chips of STT-MRAM used for a par ticular memory-

related purposeM

A N

I F

A C

T.

Design schemes variation


WLi WLi

CASE 1 CASE 2

+–

ΔIsens,min

PUF_bit

AP or PAP or P

+ –

ΔIsens,min

PUF_bit

AP or PAP or P

IDATA IREF IDATA1 IDATA2

\WLi WLi

+ –

ΔIsens,min

PUF_bit

CASE 3

AP P

Δ I 1

AP P

Δ I 2

CASE 4

IDATA1 IDATA2 IREF2IREF1

+ –

ΔIsens,min

PUF_bit

AP P

Δ I 1

AP P

Δ I 2

IDATA1 IDATA2 IDATA4IDATA3

• Trend for MRAM to store data: differential approach

• Memory size (number of MTJs) increases

Simulation details


• Generate a PUF Signature of (32x32) bits for each chip

• Production lot: N=100 different chips

• Simulator steps:

1. Generate population of STT-MRAM chips à a 3D matrix

2. Generate PUF response string for each Case 1-2-3-4

3. Evaluate PUF Quality: “Uniqueness” and “Reliability”

L

M 0 1 1 0 0 0 0 0 0 1 0 … … … … 1 0 0 0 1 1 1

M x L = Z

PUF binary response string R i=r 1∥r 2∥...∥r j∥...∥r Z in vectored form:

0 0 1 1 0 1 10 0 1 0 0 1 10 0 1 0 0 1 01 1 1 0 1 1 11 1 0 0 1 0 10 1 1 1 1 0 11 0 0 0 1 1 1

1 1 0 1 1 0 10 0 1 0 0 1 10 0 1 0 0 1 11 1 1 0 1 1 11 1 0 0 1 0 10 1 1 1 1 0 01 0 0 0 1 1 1

1 1 1 1 0 1 00 0 1 0 0 1 10 0 1 0 0 1 01 1 1 0 1 1 01 1 0 0 1 0 00 1 1 1 1 0 01 0 0 0 1 1 0

0 0 1 0 1 0 10 0 1 0 0 1 00 0 1 0 0 1 11 1 1 0 1 1 11 1 0 0 1 0 00 1 1 1 1 0 01 0 0 0 1 1 1

1 0 0 0 1 0 10 0 1 0 0 1 00 0 1 0 0 1 01 1 1 0 1 1 01 1 0 0 1 0 10 1 1 1 1 0 11 0 0 0 1 1 0

0 1 1 0 0 0 00 0 1 0 0 1 00 0 1 0 0 1 11 1 1 0 1 1 11 1 0 0 1 0 00 1 1 1 1 0 01 0 0 0 1 1 1

RESHAPE AS A VECTOR

Ni=1÷N

* mem. matrix M x (4 x L) x N

Evaluate PUF Quality

CONTENTS:

• PUF Signature Quality metrics

• Uniqueness Results

• BER (Reliability) Results

• Influence of reading voltage over BER

• Keep increasing reading voltage then?

33

PUF Signature Quality metrics

34Evaluate PUF Quality

• UNIQUENESS: expresses randomness of the signature, how unique it is w.r.t. others

o Hamming Distance

o Hamming Weight

o Bit Aliasing

1 1 0 0 1 0 0 1 … … … … 0 0 1 N0 0 1 1 1 1 1 0 … … … … 1 1 11 1 0 0 0 1 0 1 … … … … 1 0 00 1 1 0 0 0 1 0 … … … … 1 0 1

=?

0 1 1 0 0 0 1 0 … … … … 1 0 1

1 1 0 0 1 0 0 1 … … … … 0 0 1 N0 0 1 1 1 1 1 0 … … … … 1 1 11 1 0 0 0 1 0 1 … … … … 1 0 00 1 1 0 0 0 1 0 … … … … 1 0 1

• RELIABILITY: stability over undesired parameter fluctuations (voltage, temperature)

o BER: Bit-Error Rate, due to sense amplifier quality and reading voltage

Uniqueness Results


• All cases provide nominal HD/HW/BA close to 50% (ideal value)

• Avoiding the use of a reference cell improves Uniqueness (better randomness)

• Although Case 3 (and especially 4) use far more cells, Uniqueness not penalized

BER (Reliability) Results


• P state better! Lower BER (lower R à higher currents à amplifier more relaxed)

• Case 3 & 4 are a “reversed-combo” (P+AP) à BER still better than 1 & 2

• Also, we showed that BER ∝ ΔISENS,MIN

CASE 1 CASE 2 CASE 3 CASE 4 CASE 1 CASE 2 CASE 3 CASE 4

Influence of reading voltage over BER


• PUF stability changes with voltage / temperature fluctuations (high “variations”!)

• Model used does not provide temperature dependence à focus on voltage only

• VBIAS affects RP and RAP à effects on BER

2000 3000 4000 5000 6000 7000 8000 9000 100000

0.5

1

1.5

2

2.5

3

3.5x 10

4

Rp and Rap MTJ simulated distribution − Sample size = 409600

@ READING VOLTAGES: Vbias = 50mV ; 100mV ; 150mV

tox = 0.85 nm − Feat.size = 65 nm − TMR = 120 %

Resistance [Ω]

Counts

[# d

evi

ces

with

that R

esi

stance

]

RpRpRpRapRapRap

BETTER

BETT

ER

Keep increasing reading voltage then?


• Higher reading voltage, lower BER but… there is a limit!

o Power dissipation, especially if PUF response generated multiple times @runtime

o AP and P distributions will start to overlap: BER also as a memory!

o Memory cell MTJs could switch magnetization: unwanted write operation

Outlook: upgrading to

a “Strong PUF”

CONTENTS:• Motivations to enhance a PUF• Weak PUF vs Strong PUF• Re-engineering MRAM as Strong PUF• Memory layout assumptions• A proposed implementation of Strong

MRAM PUF• Complexity for the attacker Φ

39

Motivations to enhance a PUF

40Propose new “Strong PUF”

• Unique signature à single binary stream, can be used as cryptographic processes

• Example: secret key to encrypt/decrypt data on a device

• This information must thus be kept private

• Sometimes we need authentication

• Data exchanged with a device to be identified as valid

• Need of a key that might travel through unsecure media

Weak PUF vs Strong PUF


• Weak PUF: a limited set of challenge-response pairs (CRPs)

o So far, our MRAM PUF in this category. Challenge: WL à Response: binary string

o Application: unique Signature

• Strong PUF: a high number of CRPs

o Back to the origins (cold war)

o Application: authentication (secure server +chip at potential unsecure location)

Re-engineering MRAM as Strong PUF


• Previously studied Case 3 & 4 based on cells grouping

• Idea can be augmented: digital switches connecting MRAM cells to sense amplifier

• Now challenge is WL + a variable “command” driving switches


(ch-resp)1

(ch-resp)2(ch-resp)3

…(ch-resp)C

W O

R D

L

I N E

SM

-wor

ds

FOR EACH ROW: use switches to realize connections, grouping different

memory cells with sense amplifiers:

PUF bit

⇐

Original STT-MRAMmemory matrixin a given chip

Interconnections overhead

Sense Ampl. row

A large enough number of possible (challenge-

response) pairs

Designer chooses differentswitches patterns leading to several (challenge-response) pairs

Memory layout assumptions



W O

R D

L

I N E

SM

-wor

dsELEMENTARY MEMORY CELL

Sense Ampl. row

MEMORY MATRIXBL j SL j

WL i = 1 I cell

V DD

L/2 SENSE AMPLIFIERSserving couples of cells for the i-th rowselected activating its respective WL-i

+ –

ΔIsens,min

A proposed implementation of Strong MRAM PUF


• Decoder bit stream can be stored in unused rows of MRAM à memory + PUF!

L bits

WL i⇒for each memory cell

+ –

log2(L)-to-L DECODER

log2(L)-bits stream

A B each group contains K elements

A DECODER for each memory cell, connecting it to any of the available sense amplifiers’ inputs

S available sense amplifiers (typically S=L/2)

PUF$Response$Binary$String

the word line activates a specific word, thenthe generation of the PUF response starts

The CHALLENGE is now the combination of the word line WLiand of the switches

programming pattern bits stream

The binary RESPONSE string

for the word line “i”

BL j SL j

WL i = 1 I CELL

VDD

+ –

C D

+ –

E F

+ –

… …

Complexity for the attacker Φ


• Resistance to Brute force attacks: how complex trying all combinations of challenges

• Strong PUF à complexity for attacker exponentially increasing with memory size

• Not a closed form à proved to beexponential evaluating up/low bounds

• L: # elementary memory cells per row

• K: # cells grouped to each sense amplifier input

A SEMILOG-Y PLOT!0 5 10 15 20 25 30 35

100

102

104

106

108

1010

1012

1014

1016

1018

1020

Memory matrix word width L

Logarith

mic

plo

ts o

f Φ

, M

IN a

nd M

AX

Semilog plot of attacker complexity Φ as function of memory word width L. Fix M=32 words

MIN

Phi

MAX

Conclusions,Future Work& Remarks

CONTENTS:

• Conclusions

• Future Work

• Acknowledgements

46

Conclusions

47Conclusions, Future Work & Remarks

• Very new memory applied to a new paradigm of Hardware Security

• STT-MRAM both good memory and good PUF

• Simulation framework can be further expanded

CHALLENGES OVERCOME

o Understand previous work, re-implement from scratch

o MRAM very new: unified / comprehensive literature not present yet

o PUF: nanoelectronics + analog + digital domains

o MRAM DC electrical models incomplete, never applied with process variation

MAIN CONTRIBUTIONS

1. Start from scratch to reproduce previous work

2. Twist of ideas, new models

3. Larger departure from original work (land on “Strong PUF”)

Future Work


MRAM

• Overcome IC scale-down issues, speed, non volatile, low power

• Propose/agree on standards and design schemes

• Translate early prototypes in cost-effective innovative logic

• More accurate / comprehensive models and equations

PUF

• Expand Strong PUF (HW overhead vs speed,…)

• Implement real-time complete authentication system based on MRAM as PUF

• Use Fuzzy Extractor to generate a more stable PUF Response

Acknowledgements


• Grateful for this research experience, both as RA and TA at UIC

• Staff and Faculty, from both UIC and PoliTo

• Advisors:

o Prof. Wenjing Rao

o Prof. Fabrizio Bonani

• Committee Members:

o Prof. Zhichun Zhu

• Soroush Khaleghi

Thank you!

Appendix

MRAM vs conventional memories - BENCHMARKS

52

Source: Latest Advances and Future Prospects of STT-RAM, Alexander Driskill-Smith, © 2010 Grandis Corporation

STT-MRAM vs Field MRAM

53

Source: Latest Advances and Future Prospects of STT-RAM, Alexander Driskill-Smith, © 2010 Grandis Corporation

MRAM vs conventional memories - BENCHMARKS

54

• ANISOTROPIC MAGNETORESISTANCE (1856): R = f (θ J,M)

(a) External+field+applied+→+PARALLEL++→+RLOW

(b) No+field+applied++→++ANTIPARALLEL++→+RHI

• (GIANT) TUNNELING MAGNETORESISTANCE (TMR Ratio) (1975):+FM//OXIDE//FM+(“MTJ”)

• GIANT MAGNETORESISTANCE - GMR (1988,+Nobel+in+2007):+FM//NM//FM+layer

FMNMFM

FMNMFM

Nowadays,+near+

TMR=500% at+room+

temperature!

“Pinned layer”+(fixed+direction)+++Oxide +++“Free layer”+(able+to+switch+magnetization)

Use+THIN films+for+abrupt+P/AP+

transition

Spin-Torque Transfer effect

55

• Giant Tunneling Magnetoresistance (1975): MTJ stack exhibits large associated resistance

• Combined with SPINTRONIC (1996): “spin-torque transfer ” effect

• Ferromagnet acts as a “polarization filter ” (alteringelectrons populations)

M1 fixed (pinned): minority-spin electrons

reflected back!

Scheme from Magnetic Memory: Fundamentals and Technology, Cambridge Press.

MTJ resistance model used

56

• Nominal values RP / RAP with equation models

• Most accurate found to be:

• Equations applied to derive the properties of the memory matrix cells (associated

resistances) after letting their physical inputs vary simulating the process variation.

Ref: Zhao W. et al. , Macro-model of spin-transfer torque based magnetic tunnel junction device for hybrid magnetic-CMOS design. In Behavioral Modeling and Simulation Workshop 2006, IEEE

Currents distribution: evaluating the PUF

57

• Good dispersion RP and RAP à better PUF uniqueness

• Normal distribution required (easy to study)

• RP has higher currents à hopefully lower BER

• Differential currents as high as possible to be correctly sensed

−2 −1 0 1 2x 10−5

0

2

4

6

8

10

x 105 Pairs (Rpi , Rpj)

Differential current [A]

Freq

uenc

y [#

cou

ples

dev

ices

gen

erat

ing

that

cur

rent

]

Currents distrib. associated to all possible pairs (Ri,Rj)

−2 −1 0 1 2x 10−5

0

2

4

6

8

10

x 105 Pairs (Rapi , Rapj)

Differential current [A]

Freq

uenc

y [#

cou

ples

dev

ices

gen

erat

ing

that

cur

rent

]

Oxide thickness effects on RP/RAP populations

58

• Understand how far to push resistance dispersion of MTJs

• Play with process variation to get a good base for a PUF implementation

• At same time, need reliable memory cells for classic applications: data storage!

Oxide thickness the center of gravity

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 50

5

10

15

20

25

30

35

40

45

50

STT−MTJs σRap

and σRap


TMR = 120%V

read = 0.1V , Feat.size = 65nm (both w/out variation)


σtox

[%]

σR

p ,

σR

ap

[%]

σRp

@ tox

= 0.85nm

σRap

@ tox

= 0.85nm

σRp

@ tox

= 1nm

σRap

@ tox

= 1nm

σRp

@ tox

= 1.15nm

σRap

@ tox

= 1.15nm

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 50

5

10

15

20

25

30

35

40

45

50

STT−MTJs σRap

and σRap


TMR = 120%V

read = 0.1V , Feat.size = 65nm (both w/ 5% variation)


σtox

[%]

σR

p ,

σR

ap

[%]

σRp

@ tox

= 0.85nm

σRap

@ tox

= 0.85nm

σRp

@ tox

= 1nm

σRap

@ tox

= 1nm

σRp

@ tox

= 1.15nm

σRap

@ tox

= 1.15nm

Results validation (PART II)

59

• Strong influence of tOX on RP/RAP: makes sense (e- tunneling)

• No variability whatsoever à back to ideal case (nom. RP/RAP)

• tOX ↑ and σtox ↑à RP/RAP dispersion ↑

• tox plays a dominant role, but when lower than 1nm also

variability of other physical quantities matters

• Digital application: need separation between

the two populations

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5−14

−12

−10

−8

−6

−4

−2

0

2x 10

4

STT−MTJs Rp and Rap populations DISTANCE amount − Sample size = 5000TMR = 120%

Vread

= 0.1V , Feat.size = 65nm (both w/ 5% variation)


σtox

[%]

Dis

tance

betw

een p

opula

tions

min

(Rap)

− m

ax(

Rp)

[Ω]

min(Rap)−max(Rp) @ tox

= 0.85nm


= 1nm


= 1.15nm

Cases 1-2-3-4 memory size comparison

60

• Trend for MRAM to store data: differential approach à 2 MTJ +2 MOS for cell

• New schemes (3&4) use differential cells (2T2MTJ)

• Memory size?

PUF Quality: Equations

61

• UNIQUENESS: expresses randomness of the signature, how unique it is w.r.t. others

o Hamming Distance

o Hamming Weight

o Bit Aliasing

• RELIABILITY: stability over undesired parameter fluctuations (voltage, temperature)

o BER: Bit-Error Rate, related to sense amplifier quality and cells reading voltage

Uniqueness & Reliability: example for Case 4

62

44 46 48 50 52 54 560

200

400

600

800

1000

1200

1400

UNIQUENESS: Inter−die Hamming Distance distributionCASE 2T2MTJ+2T2MTJ, NO REFERENCE

Average(HD)=49.995916% ; Deviation(HD)=1.573119%

HD [%]

Count [#

]

10 20 30 40 50 60 70 80 90 100

40

45

50

55

60

Hamming WeightCASE 2T2MTJ+2T2MTJ, NO REFERENCE

Average: 50.12% ; Deviation: 1.40%

CHIP#H

am

min

g W

eig

ht [%

]

Hamming Weight of each chipAverage Hamming Weight

100 200 300 400 500 600 700 800 900 1000

30

35

40

45

50

55

60

65

70

75

Bit AliasingCASE 2T2MTJ+2T2MTJ, NO REFERENCE

Average: 50.12% ; Deviation: 5.02%

Bit Position in each CHIP matrix (reorganized by rows)

Bit

Alis

ing [%

]

Bit Alising of each chipAverage Bit Alising

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

x 10−6

0

10

20

30

40

50

60

70

80

Sense amplifier min ∆I detectable [A]

Bit

err

ors

ra

te [

%]

Bit errors rate in (2T2MTJ + 2T2MTJ) config.Couples AntiPar + Par.

min ∆ I range: (0 − 5)µA tox = 0.85 nm − Feat.size = 65 nm − TMR = 120 %

Reversed Combo (AP+P)

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

x 10−8

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

Sense amplifier min ∆I detectable [A]

Bit

err

ors

ra

te [

%]

Bit errors rate in (2T2MTJ + 2T2MTJ) config.Couples AntiPar + Par.

min ∆ I range: (0 − 0.05)µA tox = 0.85 nm − Feat.size = 65 nm − TMR = 120 %

Reversed Combo (AP+P)

Challenges space Ω

63

• The total number of different challenges (combinations)

• Strong PUF à # of possible challenges exponentially increasing with memory size

0 5 10 15 20 25 30 3510

0

105

1010

1015

1020

1025

1030

1035

1040

Growth rate of the challenges space Ω as function of the word size L. Fix M=32 words


Challe

nges

space

Ω

• L: # elementary memory cells per row

• M: memory length (# rows)

• K: # cells grouped to each sense amplifier input

• S: # available sense amplifiersA

SEM

ILOG-

Y PL

OT!

Response space Λ

64

• The number of possible responses depending on the selected challenge

• Sense amplifiers output: either 0 or 1

• S/2 sense amplifiers, M memory rows

0 5 10 15 20 25 30 350

0.5

1

1.5

2

2.5x 10

6

Growth rate of the size of the PUF response as function of the word size L. Fix M=32 words


Siz

e Λ

of th

e b

inary

resp

onse

R

UIC_Thesis_Defense_Vinella

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