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LogiCORE IPSpartan-6 FPGATriple-Rate SDI v1.0

User Guide

UG824 June 22, 2011


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Spartan-6 FPGA Triple-Rate SDI User Guide www.xilinx.com UG824 June 22, 2011

Notice of DisclaimerThe information disclosed to you hereunder (the Materials) is provided solely for the selection and use of Xilinx products. To the maximumextent permitted by applicable law: (1) Materials are made available "AS IS" and with all faults, Xilinx hereby DISCLAIMS ALLWARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OFMERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whetherin contract or tor t, including negligence, or under any other theory of liability) for any loss or damage of any kind or nature related to, arisingunder, or in connection with, the Materials (including your use of the Materials), including for any direct, indirect, special, incidental, orconsequential loss or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of any actionbrought by a third party) even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility of the same.Xilinx assumes no obligation to correct any errors contained in the Materials or to notify you of updates to the Materials or to productspecifications. You may not reproduce, modify, distribute, or publicly display the Materials without prior written consent. Certain products aresubject to the terms and conditions of the Limited Warranties which can be viewed at http://www.xilinx.com/warranty.htm; IP cores may besubject to warranty and support terms contained in a license issued to you by Xilinx. Xilinx products are not designed or intended to befail-safe or for use in any application requiring fail-safe performance; you assume sole risk and liability for use of Xilinx products in CriticalApplications: http://www.xilinx.com/warranty.htm#critapps.

Copyright 2011 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Zynq, and other designated brands included hereinare trademarks of Xilinx in the United States and other countries. All other trademarks are the property of their respective owners.

Revision History

The following table shows the revision history for this document.

Date Version Revision

06/22/11 1.0 Initial Xilinx release.
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Spartan-6 FPGA Triple-Rate SDI User Guide www.xilinx.com 3UG824 June 22, 2011

Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Preface: About This Guide

Additional Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

References. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

List of Acronyms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Chapter 1: Introduction

About the Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Supported Tools and System Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7Operating System Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7Technical Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Feedback. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8Spartan-6 FPGA Triple-Rate SDI Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Chapter 2: Overview

SD-SDI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

HD-SDI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3G-SDI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Video Payload ID. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Ancillary Data Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Complete Triple-Rate SDI Interface Solution. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Chapter 3: Core Architecture

Core Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Spartan-6 FPGA Triple-Rate SDI Core Top-Level Module. . . . . . . . . . . . . . . . . . . . 15

Reference Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

DRP Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Shared DRP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Clock Sharing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Chapter 4: Triple-Rate SDI Receiver Operation

Triple-Rate SDI Receiver Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Bit Rate and Transport Format Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Operation of the Triple-Rate SDI Receiver in the Various SDI Modes . . . . . . . . 39Triple-Rate SDI Receiver Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40SD-SDI RX Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41HD-SDI RX Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Table of Contents
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3G-SDI Level A RX Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423G-SDI Level B RX Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Electrical Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Other Triple-Rate SDI RX Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . 45Dual Link HD-SDI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45Processing Embedded Audio and Other Ancillary Data . . . . . . . . . . . . . . . . . . . . . . . . 45

SMPTE 352 Video Payload ID Packets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45SD-SDI EDH Error Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45SD-SDI Data Recovery Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47SD-SDI Clock Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Chapter 5: Triple-Rate SDI Transmitter Operation

Triple-Rate SDI Transmitter Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Operation of the Triple-Rate SDI Transmitter in the SDI Modes . . . . . . . . . . . . . 49SD-SDI Transmitter Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49HD-SDI Transmitter Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 513G-SDI Transmitter Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Level A Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52Level B Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Dual Link HD-SDI Transmitter Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Summary of Triple-Rate TX Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Triple-Rate TX Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55ST 352 Packet Insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55Line Number Insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56CRC Generation and Insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56EDH Generation and Insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56Ancillary Data Insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57Reference Clocks and Reference Clock Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57Electrical Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Chapter 6: Implementing the Core

Timing Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Other Constraints. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

SD-SDI DRU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

GTP Transceiver Wrapper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60


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Preface

About This Guide

This user guide describes the LogiCORE IP Spartan-6 FPGA Triple-Rate SDI core. Thiscore implements triple-rate serial digital interface (SDI) receivers and transmitters inSpartan-6 devices. It supports SD-SDI, HD-SDI, and 3G-SDI (level A, level B-DL, and levelB-DS) and dual link HD-SDI standards.

Additional Resources

For support resources such as Answers, Documentation, Downloads, and Forums, see theXilinx Support website at:

http://www.xilinx.com/support .

For a glossary of technical terms used in Xilinx documentation, see:

http://www.xilinx.com/support/documentation/sw_manuals/glossary.pdf .

References

For more information, see these documents at http://www.xilinx.com/support :

DS849: LogiCORE IP Spartan-6 FPGA Triple-Rate SDI Data Sheet

UG386: Spartan-6 FPGA GTP Transceivers User Guide

XAPP1014:Audio/Video Connectivity Solutions for Virtex-5 FPGAs

XAPP1075: Implementing Triple-Rate SDI with Virtex-6 FPGA GTX Transceivers

XAPP1076: Implementing Triple-Rate SDI with Spartan-6 FPGA GTP Transceivers

List of Acronyms

The following table defines acronyms used in this document.

Acronym Definition

ANC Ancillary

AP Active Picture

ASSP Application-Specific Standard Product

CDR Clock Data Recovery

CML Current Mode Logic

CRC Cyclic Redundancy Check
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Preface: About This Guide

DRU Data Recovery Unit

EAV End of Active Video

EDH Error Detection and Handling

FF Full Field

HANC Horizontal Ancillary

HD High Definition

HDL Hardware Description Language

LVDS Low-Voltage Differential Signalling

MMCM Mixed-Mode Clock Manager

RX Receiver

SAV Start of Active Video

SD Standard DefinitionSDI Serial Digital Interface

SMPTE Society of Motion Picture and Television Engineers

TRS Timing Reference Signal

TX Transmitter

VPID Video Payload Identifier

Acronym Definition


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Chapter 1

Introduction

The triple-rate serial digital interface (SDI) supports the SMPTE SD-SDI, HD-SDI, and3G-SDI standards. The SDI interface is widely used in professional broadcast videoequipment. SDI interfaces are used in broadcast studios and video production centers tocarry uncompressed digital video along with embedded ancillary data, such as multipleaudio channels.

About the CoreThe LogiCORE IP Spartan-6 FPGA Triple-Rate SDI core implements triple-rate SDIreceivers and transmitters in Spartan-6 devices. It supports SD-SDI, HD-SDI, and 3G-SDI(level A, level B-DL, and level B-DS) and dual-link HD-SDI standards. The Spartan-6FPGA Triple-Rate SDI core is compatible with the GTP transceivers in Spartan-6 devices.SDI interface solutions for other Xilinx FPGAs can be found at www.xilinx.com.

The Spartan-6 FPGA Triple-Rate SDI core is a CORE Generator IP software core. It doesnot require a license. It is provided in source code form in both Verilog and VHDL.

Supported Tools and System Requirements

Operating System Requirements

For a list of system requirements, see the ISE Design Suite 13: Release Notes Guide.

Tools

The tools and their respective versions for the 13.2 release are:

ISE software 13.2

Mentor Graphics ModelSim 6.6d

Technical Support

For technical support, go to www.xilinx.com/support. Questions are routed to a team withexpertise using the Spartan-6 FPGA Triple-Rate SDI core.
http://www.xilinx.com/http://www.xilinx.com/http://www.xilinx.com/support/documentation/sw_manuals/xilinx13_2/irn.pdfhttp://www.xilinx.com/supporthttp://www.xilinx.com/http://www.xilinx.com/http://www.xilinx.com/supporthttp://www.xilinx.com/support/documentation/sw_manuals/xilinx13_2/irn.pdf


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Chapter 1: Introduction

Feedback

Xilinx welcomes comments and suggestions about the Spartan-6 FPGA Triple-Rate SDIcore and the accompanying documentation.

Spartan-6 FPGA Triple-Rate SDI Core

For comments or suggestions about the core, submit a WebCase at www.xilinx.com/support/clearexpress/websupport.htm. Be sure to include this information:

Core name

Core version number

Explanation of your comments

Documentation

For comments or suggestions about the core documentation, submit a WebCase atwww.xilinx.com/support/clearexpress/websupport.htm . Be sure to include thisinformation:

Document title

Document number

Page number(s) to which your comments refer

Explanation of your comments
http://www.xilinx.com/http://www.xilinx.com/support/clearexpress/websupport.htmhttp://www.xilinx.com/support/clearexpress/websupport.htmhttp://www.xilinx.com/support/clearexpress/websupport.htmhttp://www.xilinx.com/http://www.xilinx.com/support/clearexpress/websupport.htmhttp://www.xilinx.com/support/clearexpress/websupport.htmhttp://www.xilinx.com/support/clearexpress/websupport.htm


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Chapter 2

Overview

The LogiCORE IP Spartan-6 FPGA Triple-Rate SDI core implements three mainSMPTE interface standards:

SD-SDI (SMPTE ST 259): SDTV Digital Signal/Data - Serial Digital Interface

HD-SDI (SMPTE ST 292): 1.5 Gb/s Signal/Data Serial Interface

3G-SDI (SMPTE ST 424): 3 Gb/s Signal/Data Serial Interface

In addition, two triple-rate SDI receivers or transmitters can be combined to implement anSMPTE ST 372 dual link 1.5 Gb/s digital interface.

SD-SDI

The Spartan-6 FPGA Triple-Rate SDI core supports the 270 Mb/s bit rate (level C) of theSD-SDI standard. This bit rate is too slow for the RX clock data recovery (CDR) circuit inthe GTP receiver to receive, directly, so the GTP receiver is used to oversample the270 Mb/s data stream, and a data recovery unit (DRU), implemented in the Spartan-6FPGA Triple-Rate SDI core, is used to recover the data with a high degree of jitter tolerance.This DRU supports only 270 Mb/s SD-SDI. However, it is possible to use a moregeneral-purpose DRU to receive any SD-SDI bit rate. Customers needing to do this shouldcontact Xilinx technical support for more information.

The Spartan-6 FPGA Triple-Rate SDI core fully supports the SMPTE RP 165 ErrorDetection and Handling (EDH) standard for the receive and transmit sections.

HD-SDI

Although the HD-SDI standard is called a 1.5 Gb/s interface, the bit rates supported byHD-SDI are 1.485 Gb/s and 1.485/1.001 Gb/s. The Spartan-6 FPGA Triple-Rate SDI corefully supports both bit rates. The Triple-Rate SDI core also fully supports generation (TXside) and checking (RX side) of CRC values for each video line and the insertion (TX side)and capture (RX side) of line number values for each line.

3G-SDIThe 3G-SDI standard is called a 3 Gb/s interface, but the bit rates are 2.97 Gb/s and2.97/1.001 Gb/s. The Spartan-6 FPGA Triple-Rate SDI core fully supports both of these bitrates. 3G-SDI supports several different mapping levels, described in the SMPTE ST 425standard. These levels are called A, B-DL, and B-DS. The Triple-Rate SDI core supports allthree levels. As with the HD-SDI standard, the Triple-Rate SDI core supports CRCgeneration and checking and line number insertion and capture for 3G-SDI.


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Chapter 2: Overview

Video Payload ID

The Spartan-6 FPGA Triple-Rate SDI core implements an SMPTE ST 352 compliant videopayload ID (VPID) ancillary data packet insertion capability for the transmitter that worksin all SDI modes (SD-SDI, HD-SDI, 3G-SDI, and dual link HD-SDI). The receive side alsodetects and captures the four data bytes of ST 352 VPID packets.

Ancillary Data Support

The Spartan-6 FPGA Triple-Rate SDI core allows the application to implement ancillarydata packet insertion prior to transmission. While the core does not provide ancillary datapacket insertion capability, it has the necessary datapaths to allow ancillary data packetinsertion to be implemented by the application. On the receive side, all embedded ancillarydata is preserved by the Triple-Rate SDI cores receiver section and is present in the SDIdata streams output from the core. Applications can process the received SDI data streamsto process the ancillary data as needed.

Complete Triple-Rate SDI Interface Solution

A complete triple-rate SDI interface is comprised of:

A GTP transceiver

The LogiCORE IP Spartan-6 FPGA Triple-Rate SDI core

An industry-standard SDI cable driver (for TX) and SDI cable equalizer (for RX)

GTP reference clock source(s)

Figure 2-1shows a high-level block diagram of an SDI receive/transmit interface using theSpartan-6 FPGA Triple-Rate SDI core. The Triple-Rate SDI core implements one triple-rateSDI receiver and one triple-rate SDI transmitter. If only a receiver or only a transmitter isneeded by the application, the input ports for the unused half of the core can be tied toground, and the output ports can be left unconnected. The synthesis tool optimizes the

unused portion of the core out of the application.

When both the receiver and transmitter sections of the Triple-Rate SDI core are used, thereceiver and transmitter are completely independent. They can operate in different SDImodes and bit rates (receiving 3G-SDI at 2.97/1.001 Gb/s while transmitting SD-SDI at270 Mb/s or HD-SDI at either bit rate, for example).

The Spartan-6 FPGA Triple-Rate SDI core always supports all three SDI modes (SD-SDI,HD-SDI, and 3G-SDI). If only a subset of these modes is required by an application, the fullTriple-Rate SDI core is still used.


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Complete Triple-Rate SDI Interface Solution

Notes relevant to Figure 2-1:

1. The SDI cable equalizer and cable driver are external to the FPGA.

2. The optional ancillary (ANC) packet insertion function is not included with theSpartan-6 FPGA Triple-Rate SDI core.

X-RefTarget - Figure 2-1

Figure 2-1: Overview of Triple-Rate SDI Interface


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Chapter 2: Overview


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Chapter 3

Core Architecture

Core Block Diagram

Figure 3-1shows a detailed top-level block diagram of a complete triple-rate SDIreceive/transmit interface implemented with the LogiCORE IP Spartan-6 FPGATriple-Rate SDI core.


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Spartan-6 FPGA Triple-Rate SDI Core Top-Level Module


The Spartan-6 FPGA Triple-Rate SDI core top-level module implements three mainfunctions:

Triple-rate SDI receiver

Triple-rate SDI transmitter

GTP transceiver control

The GTP transceiver control function provides the necessary resets and other control forthe GTP transceiver to initialize the transceiver and to dynamically change the GTPtransceiver attributes to change the SDI mode in which the receiver and transmitter areoperating.

Table 3-1describes the ports of the Triple-Rate SDI core's top-level module.

Table 3-1: Spartan-6 FPGA Triple-Rate SDI Core Ports

Port Name I/O Width Description

Receive Ports

transceiver_id In 1

Specifies which transceiver in the GTP tile isconnected to this instance of the core. This port isused by the GTP control section to create resetsand control the DRP. It must always be setcorrectly regardless of whether there is asecondary core or if this instance is primary orsecondary.

0= Transceiver 0

1= Transceiver 1

rxpipeclk In 1

This input is the receiver pipeline clock at 1/20ththe serial bit rate. Connect it to rxusrclk2 of thecore instance that sources the RX user clocks to the

GTP transceiver.

rx_rst In 1

This synchronous reset input usually can be tied toground because a reset is not required. AfterFPGA configuration, this module is in a fullyoperational mode and does not require a reset.Both rx_ce_sd and rx_din_rdy_3G must be Highwhen rx_rst is High to completely reset thereceiver.


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rx_mode_HD

rx_mode_SD

rx_mode_3G

Out 1

These three output ports are decoded versions ofthe rx_mode port. They are provided forconvenience. Unlike the rx_mode port, whichchanges continuously as the receiver seeks toidentify and lock to the incoming signal, theseoutputs are all forced Low when the receiver is notlocked. The output matching the current SDImode of the receiver is High whenrx_mode_locked is High.

rx_mode_locked Out 1

When this output is Low, the receiver is activelysearching for the SDI mode that matches the inputdata stream. During this time, the rx_mode outputport changes frequently. When the receiver locksto the correct SDI mode, the rx_mode_lockedoutput goes High.

rx_bit_rate Out 1

This output port indicates which bit rate is beingreceived in HD-SDI and 3G-SDI modes. Thisoutput is only valid when rx_mode_locked isHigh.

HD-SDI mode:

rx_bit_rate = 0: Bit rate = 1.485 Gb/s

rx_bit_rate = 1: Bit rate = 1.485/1.001 Gb/s

3G-SDI mode:

rx_bit_rate = 0: Bit rate = 2.97 Gb/s

rx_bit_rate = 1: Bit rate = 2.97/1.001 Gb/s

rx_t_locked Out 1This output is High when the transport detectionfunction in the receiver has identified the

transport mode of the SDI signal.

rx_t_family Out 4

This output indicates which family of videosignals is being used as the transport on the SDIinterface. This output is only valid whenrx_t_locked is High. This port does not necessarilyidentify the video format of the picture beingtransported. It only identifies the transportcharacteristics. See Table 4-1, page 38for theencoding of this port.

rx_t_rate Out 4

This output indicates the frame rate of thetransport. This is not necessarily the same as theframe rate of the actual picture. See Table 4-2,

page 39for the encoding of this port. This outputis only valid when rx_t_locked is High.

rx_t_scan Out 1

This output indicates whether the transport isinterlaced (Low) or progressive (High). This is notnecessarily the same as the scan mode of the actualpicture. This output is only valid whenrx_t_locked is High.

Table 3-1: Spartan-6 FPGA Triple-Rate SDI Core Ports (Contd)



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rx_b_vpid Out 32

All four user data bytes of the SMPTE 352 packetfrom data stream 2 are output on this port in thisformat: most-significant byte to least-significant

byte: byte4, byte3, byte2, byte1. This output isvalid only in 3G-SDI mode and only whenrx_b_vpid_valid is High. In 3G-SDI level A mode,the output data is the VPID data captured fromdata stream 2 (chroma). In 3G-SDI level B mode,the output data is the VPID data captured fromdata stream 1 of link B (dual link streams) orHD-SDI signal 2 (dual HD-SDI signals).

rx_b_vpid_valid Out 1 This output is High when rx_b_vpid is valid.

rx_crc_err_a Out 1

This output is asserted High for one sampleperiod when a CRC error is detected on theprevious video line. For 3G-SDI level B mode, thisoutput indicates CRC errors on data stream 1 only.There is a second output called rx_crc_err_b thatindicates CRC errors on data stream 2 for 3G-SDIlevel B mode. This output is not valid in SD-SDImode.

rx_ds1a Out 10

The recovered data stream 1 is output on this port.The contents of this data stream are dependent onthe SDI mode:

SD-SDI: Multiplexed Y/C data stream

HD-SDI: Y data stream

3G-SDI level A: Data stream 1

3G-SDI level B-DL: Data stream 1 of link A

3G-SDI level B-DS: Y data stream of HD-SDIsignal 1

rx_ds2a Out 10

The recovered data stream 2 is output on this port.The contents of this data stream are dependent onthe SDI mode:

SD-SDI: Not used

HD-SDI: C data stream

3G-SDI level A: Data stream 2

3G-SDI level B-DL: Data stream 2 of link A

3G-SDI level B-DS: C data stream of HD-SDIsignal 1

rx_eav Out 1 This output is asserted High for one sample timewhen the XYZ word of an EAV is present on thedata stream output ports.

rx_sav Out 1This output is asserted High for one sample timewhen the XYZ word of an SAV is present on thedata stream output ports.




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rx_trs Out 1This output is asserted High for four consecutivesample times when the four words of an EAV orSAV are output on the data stream ports.

rx_line_b Out 11

This output port is only valid in 3G-SDI level Bmode. It outputs the line number for the Y datastream of link B or HD-SDI signal 2. For any casewhere the interface line number is not the same asthe picture line number, the line number output onthis port is the interface line number, not thepicture line number.

rx_dout_rdy_3G Out 2

In 3G-SDI level B mode, the output data rate is74.25 MHz, but the rxpipeclk frequency is148.5 MHz. The rx_dout_rdy_3G output isasserted at a 74.25 MHz rate in 3G-SDI level Bmode. This output is always High in all othermodes, allowing it to be used as a clock enable todownstream modules.

rx_crc_err_b Out 1

This output is the CRC error indicator for link B orHD-SDI signal 2. The rx_crc_err_b output isasserted High for a single clock cycle when a CRCerror is detected.

rx_ds1b Out 10

This output is only used in 3G-SDI level B mode.The data stream output on this port is:

3G-SDI level B-DL: Data stream 1 of link B

3G-SDI level B-DS: Y data stream of HD-SDIsignal 2

rx_ds2b Out 10

This output is only used in 3G-SDI level B mode.The data stream output on this port is:

3G-SDI level B-DL: Data stream 2 of link B

3G-SDI level B-DS: C data stream of HD-SDIsignal 2

rx_edh_errcnt_en In 16This input controls which EDH error conditionsincrement the rx_edh_errcnt counter. SeeTable 4-4, page 46for more details.

rx_edh_clr_errcnt In 1

When High, this input clears the rx_ed_errcntcounter. This input port must be High during thesame clock cycle when rx_ce_sd is also High toclear the error counter.

rx_edh_ap Out 1This output is asserted High when the activepicture CRC calculated for the previous field doesnot match the AP CRC value in the EDH packet.

rx_edh_ff Out 1This output is asserted High when the full fieldCRC calculated for the previous field does notmatch the FF CRC value in the EDH packet.

rx_edh_anc Out 1This output is asserted High when an ancillarydata packet checksum error is detected.




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rx_edh_ap_flags Out 5The active picture error flag bits from the mostrecently received EDH packet are output on thisport. See Table 4-5, page 47for more information.

rx_edh_ff_flags Out 5The full field error flag bits from the most recentlyreceived EDH packet are output on this port. SeeTable 4-5, page 47for more information.

rx_edh_anc_flags Out 5The ancillary error flag bits from the most recentlyreceived EDH packet are output on this port. SeeTable 4-5, page 47for more information.

rx_edh_packet_flags Out 4This port outputs four error flags related to themost recently received EDH packet. See Table 4-6,page 47for more information.

rx_edh_errcnt Out 16

This port is the SD-SDI EDH error counter. Itincrements once per field when any of the error

conditions enabled by the rx_edh_err_en portoccurs during that field.

Transmit Ports

txpipeclk In 1

This input is the transmitter pipeline clock at1/20th the serial bit rate. Connect it to txusrclk2 ofthe core instance that sources the TX user clocks tothe GTP transceiver.

tx_rst In 1

This port is a synchronous reset input. It resets thetransmit section when High. To fully reset thetransmitter, both tx_ce and tx_din_rdy must beHigh when tx_rst is High.

tx_ce In 3

The clock enable must be asserted at a 27 MHz ratefor SD-SDI mode (with a mandatory 5/6/5/6clock cycle cadence). For all other SDI modes, theclock enable is always High. Three identical copiesof the clock enable signal must be provided on thethree bits of this port.

tx_din_rdy In 1

For SD-SDI, HD-SDI, and level A 3G-SDI modes,this input must be kept High at all times. For levelB 3G-SDI mode, this input must be asserted everyother clock cycle.

tx_mode0 In 2

This input port selects the transmitter SDI modefor GTP transceiver 0. If this instance is primary

and there is an associated secondary core, bothtx_mode0 and tx_mode1 must be connected. Ifthis instance is secondary or there is no secondarycore, only the mode for the transceiver to whichthis instance is connected needs to be driven.

00= HD-SDI (including dual link HD-SDI)

01= SD-SDI

10= 3G-SDI

11= Invalid




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tx_mode1 In 2

This input port selects the transmitter SDI modefor GTP transceiver 1. If this instance is primaryand there is an associated secondary core, bothtx_mode0 and tx_mode1 must be connected. Ifthis instance is secondary or there is no secondarycore, only the mode for the transceiver to whichthis instance is connected needs to be driven.

00= HD-SDI (including dual link HD-SDI)

01= SD-SDI

10= 3G-SDI

11= Invalid

tx_bit_rate In 1

This port indicates the bit rate for transmitterclocks.

0= Divide by 1 bit rate

1= Divide by 1.001 bit rate

tx_level_b_3G In 1

In 3G-SDI mode, this input determines whetherthe module is configured for level A (level = Low)or for level B (level = High). In 3G-SDI mode, thisinput must be properly controlled to produce legal3G-SDI data streams.

tx_insert_crc In 1

When this input is High, the transmitter generatesand inserts CRC values on each video line inHD-SDI and 3G-SDI modes. When this input isLow, CRC values are not generated and inserted.This input is ignored in SD-SDI mode.

tx_insert_ln In 1

When this input is High, the transmitter inserts

line numbers after the EAV in each video line. Theline number must be supplied on the tx_line_a andtx_line_b input ports. This input is ignored inSD-SDI mode.

tx_insert_edh In 1

When this input is High, the transmitter generatesand inserts EDH packets in every field in SD-SDImode. When this input is Low, EDH packets arenot inserted. This input is ignored in HD-SDI and3G-SDI modes.

tx_insert_vpid In 1

When this input is High, ST 352 packets areinserted into the data streams, otherwise thepackets are not inserted. ST 352 packets aremandatory in 3G-SDI and dual link HD-SDImodes and optional in HD-SDI and SD-SDImodes.




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tx_overwrite_vpid In 1

If this input is High, ST 352 packets alreadypresent in the data streams are overwritten. If thisinput is Low, existing ST 352 packets are notoverwritten. When transporting ST 372 dual linkdata streams on a 3G-SDI level B interface, existingST 352 packets in the data streams must beupdated to indicate that the interface is 3G-SDIrather than HD-SDI mode. This module updatesthese packets only when overwrite is High. So,unless the ST 352 packets are being updatedexternally to the triple-rate SDI core, this inputmust be High when transmitting in 3G-SDI levelB-DL mode.

tx_video_a_y_in In 10

This is the data stream A Y input. The data on thisport depends on the SDI mode:

SD-SDI: The multiplexed Y/C data stream

enters the module on this port. HD-SDI: The Y data stream enters the module

on this port.

3G-SDI level A: Data stream 1, as defined bySMPTE 425, enters the module on this port.

Dual link HD-SDI or 3G-SDI level B-DL: The Ydata stream of link A enters the module on thisport.

3G-SDI level B-DS: The Y data stream ofHD-SDI signal 1 enters the module on this port.

tx_video_a_c_in In 10

This is the data stream A C input. The data on thisport depends on the SDI mode:

SD-SDI: Unused.

HD-SDI and 3G-SDI level A: The C data streamenters the module on this port.

Dual link HD-SDI or 3G-SDI level B-DL: The Cdata stream of link A enters the module on thisport.

3G-SDI level B-DS: The C data stream ofHD-SDI signal 1 enters the module on this port.

tx_video_b_y_in In 10

This is the data stream B Y input: The data streamon this port depends on the SDI mode:

Dual link HD-SDI or 3G-SDI level B-DL: The Ydata stream of link B enters the module on thisport.

3G-SDI level B-DS: The Y data stream ofHD-SDI signal 2 enters the module on this port.

For other SDI modes, this input port is unused.




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tx_video_b_c_in In 10

This is the data stream B C input: The data streamon this port depends on the SDI mode:

Dual link HD-SDI or 3G-SDI level B-DL: The C

data stream of link B enters the module on thisport.



tx_line_a In 11

The current line number must be provided to themodule through this port if either ST 352 VPIDpacket insertion is enabled (tx_insert_vpid =High) or if HD-SDI and 3G-SDI line numberinsertion is enabled (tx_insert_ln = High).

SD-SDI only uses 10-bit line numbers, so bit 10 ofthe port must be 0 in SD-SDI mode. In SD-SDI

mode, this input is only used for ST 352 VPIDpacket insertion. If tx_insert_vpid is Low, thisinput port is ignored in SD-SDI mode.

The line number must be valid at least one clockcycle before the start of the HANC space (by theXYZ word of the EAV) and must remain validduring the entire HANC interval.

This input is the only line number input used forSD-SDI, HD-SDI, and 3G-SDI level A modes. For3G-SDI level B mode, a second line number inputport, tx_line_b, is also provided.

For video formats where the picture line numberis different from the transport line number, the

value supplied on this port must be the transportline number.

tx_line_b In 11

This second line number input port is used onlyfor 3G-SDI level B mode. This additional linenumber port allows the two separate HD-SDIsignals to be vertically unsynchronized in levelB-DS mode. When using either 3G-SDI level B-DLor B-DS, this port must be given a valid linenumber input. This input port has the same timingand requirements described for tx_line_a.

tx_vpid_byte1 In 8This value is inserted as the first user data word ofthe ST 352 packet. It must be valid during the

entire HANC interval.

tx_vpid_byte2 In 8This value is inserted as the second user data wordof the ST 352 packet. It must be valid during theentire HANC interval.

tx_vpid_byte3 In 8This value is inserted as the third user data wordof the ST 352 packet. It must be valid during theentire HANC interval.




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tx_vpid_byte4a In 8

This value is inserted as the fourth user data wordof the ST 352 packet. This word is used for the ST352 packets inserted into SD-SDI, HD-SDI, and3G-SDI level A data streams. For 3G-SDI level Band dual link HD-SDI modes, this value is usedfor the ST 352 packet inserted into Y channel oflink A only. This input must be valid during theentire HANC interval.

tx_vpid_byte4b In 8

This value is inserted as the fourth user data wordof ST 352 packets inserted in the Y channel of linkB for 3G-SDI level B and dual link HD-SDI modesonly. This input value is not used for SD-SDI,HD-SDI, or 3G-SDI level A modes. This inputmust be valid during the entire HANC interval.

tx_vpid_line_f1 In 11

The ST 352 packet is inserted in the HANC spaceof the line number specified by this input port. Forinterlaced video, this input port specifies a linenumber in field 1. For progressive video, thisspecifies the only line in the frame where thepacket is inserted. The input value must be validduring the entire HANC interval. If tx_insert_vpidis Low, this input is ignored.

tx_vpid_line_f2 In 11

For interlaced video, an ST 352 packet is insertedon the line number in field 2 indicated by thisvalue. For progressive video, this input port must

be disabled by holding the tx_vpid_line_f2_enport Low. The input value must be valid duringthe entire HANC interval. This input is ignored if

either tx_insert_vpid or tx_vpid_line_f2_en isLow.

tx_vpid_line_f2_en In 1

This input controls whether or not ST 352 packetsare inserted on the line indicated by line_f2. Forinterlaced video, this input must be High. Forprogressive video, this input must be Low. Forprogressive video transported on an interlacedtransport, such as 1080p 60 Hz transported byeither 3G-SDI level B-DL or dual link HD-SDI,ST 352 packets must be inserted into both fields ofthe interlaced transport, so this input must beHigh. This input must be valid during the entireHANC interval. This input is ignored if

tx_insert_vpid is Low.




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tx_ds2b_out Out 10

This is the data stream B C input: The data streamon this port depends on the SDI mode:

Dual link HD-SDI or 3G-SDI level B-DL: the C

data stream of link B enters the module on thisport.



tx_use_dsin In 1

This input controls the source of the data streamssent by the transmitter. When this input is High,the sources of the transmitted data streams are thetx_ds1a_in, tx_ds2a_in, tx_ds1b_in, andtx_ds2b_in input ports. When this input is Low,the source of the transmitted data streams areinternal to the core, coming directly from the videopayload ID insertion function. When theapplication needs to insert ancillary data, thetx_use_dsin port is driven High to allow theapplication to modify the data streams andprovide the modified data streams to thetransmitter on the tx_dsxx_in ports. When noancillary data insertion is required, thetx_use_dsin input is driven Low, and thetx_dsxx_in ports are ignored.

tx_ds1a_in In 10

This is the link A data stream 1 input. This port isignored if tx_use_dsin is Low. If tx_use_dsin isHigh, this port supplied a data stream to betransmitted. The data stream supplied on this port

depends on the SDI mode: SD-SDI: Multiplexed Y/C data stream.

HD-SDI: Y data stream.

3G-SDI level A: Data stream 1.

Dual link HD-SDI or 3G-SDI level B-DL: Y datastream of link A.

3G-SDI level B-DS: Y data stream of HD-SDIsignal 1.

tx_ds2a_in In 10

This is the link A data stream 2 input. This port isignored if tx_use_dsin is Low. If tx_use_dsin isHigh, this port supplied a data stream to betransmitted. The data stream supplied on this port

depends on the SDI mode: SD-SDI: Unused.

HD-SDI and 3G-SDI level A: The C data streamenters the module on this port.

Dual link HD-SDI or 3G-SDI level B-DL: C datastream of link A.

3G-SDI level B-DS: C data stream of HD-SDIsignal 1.




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tx_ds1b_in In 10

This is the link B data stream 1 input. This port isignored if tx_use_dsin is Low. If tx_use_dsin isHigh, this port supplied a data stream to betransmitted. The data stream supplied on this portdepends on the SDI mode:

Dual link HD-SDI or 3G-SDI level B-DL: Y datastream of link B.

3G-SDI level B-DS: Y data stream of HD-SDIsignal 2.


tx_ds2b_in In 10

This is the link B data stream 2 input. This port isignored if tx_use_dsin is Low. If tx_use_dsin isHigh, this port supplied a data stream to betransmitted. The data stream supplied on this portdepends on the SDI mode:

Dual link HD-SDI or 3G-SDI level B-DL: C datastream of link B.

3G-SDI level B-DS: C data stream of HD-SDIsignal 2.


tx_ce_align_err Out 1

This output indicates problems with the 5/6/5/6clock cycle cadence on the tx_ce clock enable inSD-SDI mode. In SD-SDI mode, the tx_ce signalmust follow a regular 5/6/5/6 clock cyclecadence. If it does not, the SD-SDI bitstream isformed incorrectly. The tx_ce_align_err signalgoes High if the cadence is incorrect. This port isonly valid in SD-SDI mode.

tx_slew Out 1

This output port can drive the slew rate controlpin of the external SDI cable driver to correctlyswitch it between slow slew rate for SD-SDI andhigh slew rate for HD-SDI and 3G-SDI.

GTP Transceiver Ports

gtp_bufgtpclk In 2

These two inputs carry the output clocks from theGTP transceiver. The source is GTPCLKOUT fromthe GTP transceiver. This must be bufferedthrough BUFIO2 components between the GTPtransceiver and this input port.

Bit 0 is the TX output clock derived by dividing

the GTP REFCLK. It is used to produce TX userclocks.

Bit 1 is the RX recovered clock. It is used toproduce the RX user clocks.




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gtp_gtpreset Out 1Connect this port to the GTPRESET_IN port of theGTP transceiver.

gtp_txbufstatus1 In 1

Connect this port to bit 1 of the

TXBUFSTATUS_OUT port of the GTP transceiver.

gtp_txplllkdet In 1Connect this port to the PLLLKDET_OUT port ofthe GTP transceiver.

gtp_txreset Out 1Connect this port to the TXRESET_IN port of theGTP transceiver.

gtp_txdata Out 20Connect this port to the TXDATA_IN port of theGTP transceiver.

gtp_drpclk In 1

This clock input must be driven by the same clockthat drives the DCLK port of the GTP transceiver.This clock must meet the DRP clock frequencyrequirements listed in DS162, Spartan-6 FPGA Data

Sheet: DC and Switching Characteristics. Because thedrpclk is also used internally by the receiver SDI

bit rate detector, the drpclk frequency must be afixed-frequency clock. It must not changefrequencies when the SDI bit rate changes. Also,the frequency of this clock must match the value ofthe DRPCLK_FREQ parameter/generic of theTriple-Rate SDI core.

gtp_drpdo In 16Connect this port to the DRPDO_OUT port of theGTP transceiver.

gtp_drdy In 1Connect this port to the DRDY_OUT port of theGTP transceiver.

gtp_daddr Out 8Connect this port to the DADDR_IN port of theGTP transceiver.

gtp_di Out 16Connect this port to the DI_IN port of the GTPtransceiver.

gtp_den Out 1Connect this port to the DEN_IN port of the GTPtransceiver.

gtp_dwe Out 1Connect this port to the DWE_IN port of the GTPtransceiver.

rxusrclk_locked Out 1

This output indicates the lock status of the PLLused to create the RX user clocks gtp_rxusrclk and

gtp_rxusrclk2. 0 = Unlocked

1 = Locked

txusrclk_locked Out 1

This output indicates the lock status of the PLLused to create the TX user clocks gtp_txusrclk andgtp_txusrclk2.

0 = Unlocked

1 = Locked




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Reference Clocks

Reference Clocks

A single reference clock is used for both the receive and transmit sides of a GTP transceiver.The frequency of the reference clock is determined by the TX operating frequency.

The GTP transmitter always transmits at an exact multiple of the GTP transmitter referenceclock frequency; thus the reference clock must have a frequency that will work for thetransmitter. So, to support the two bit rates of HD-SDI and 3G-SDI, two different reference

clock frequencies are required. These frequencies are either 74.25/1.001 MHz and74.25 MHz or 148.5/1.001 MHz and 148.5 MHz. To transmit SD-SDI, the GTP transmitterreference clock frequency must be 74.25 MHz or 148.5 MHz.

The receiver, on the other hand, can use either of the reference clock frequencies requiredfor the transmitter to receive 270 Mb/s SD-SDI, both HD-SDI bit rates, and both 3G-SDI bitrates. For the receiver, the reference clock frequency must be between 74.1758 MHz and74.25 MHz or between 148.3516 MHz and 148.5 MHz.

When implementing multiple transmitters, each GTP transceiver might require its own,individual, GTP TX reference clock to allow it to be fully independent of the other SDItransmitters in the FPGA. However, some applications, especially genlocked applications,often can use a single TX reference clock. In this case, the reference clock can be shared, ascan the user clocks. This is discussed in Clock Sharing, page 34.

When implementing multiple SDI interfaces in one FPGA, the same RX reference clocksource is usually provided to all of GTP transceivers implementing SDI receiver interfaces.Because a single reference clock frequency allows reception of any of the supported SDI bitrates, all SDI interfaces clocked by a common RX reference clock frequency areindependent and each can receive different SDI bit rates. However, because both receiverand transmitter sides of a transceiver share a clock, changes to or interruptions of the clockaffect both receiver and transmitter.

The reference clock frequencies used in an application are specified in the Spartan-6 FPGAGTP Transceiver Wizard. When the hd sdiprotocol template is chosen, the line rate isautomatically set to 1.485 Gb/s. The user can set the reference clock frequency to either74.25 MHz or 148.5 MHz. Choosing either of these frequencies still allows the slower74.25/1.001 and 148.5/1.001 MHz reference clock frequencies to be used.

DRP Clock

The DRP clock is used to clock transfers on the DRP interface between the GTP transceiverand the Spartan-6 FPGA Triple-Rate SDI core. The frequency of this clock must, therefore,meet the frequency requirements specified for the GTP transceivers DCLK as specified inDS162, Spartan-6 FPGA Data Sheet: DC and Switching Characteristics.

rx_mode_test In 2This port is used during verification tests of theTriple-Rate SDI core. Always wire both bits of thisport Low.

test In 3This port is used during verification tests of theTriple-Rate SDI core. Always wire all bits of thisport Low.




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The Triple-Rate SDI core also uses the DRP clock for two other purposes. First, theTriple-Rate SDI core uses the DRP clock as a reference clock frequency for the receive bitrate detector. The number of pulses of rxpipeclk are counted for a given number of cyclesof the DRP clock, and the results are used to determine which bit rate is being received.Furthermore, the bit rate detector also determines if rxpipeclk is running at a frequencythat is within normal ranges. If it is not, then the Triple-Rate SDI core periodically asserts

the CDRRESET_IN port of the GTP transceiver.Second, the Triple-Rate SDI core uses the DRP clock as a free-running clock to time andcontrol important initialization and reset sequences for the GTP transmitter. Thesesequences cause the GTPOUTCLK[0] of the GTP transmitter to stop, thus the Triple-RateSDI core cannot use the txpipeclk signal, usually derived from GTPOUTCLK[0], to controlthese initialization and reset sequences. It must use an independent free-running clock, sothe DRP clock is used.

Both applications require that the Triple-Rate SDI core know the frequency of the DRPclock. A parameter called DRPCLK_FREQ is used to tell the Triple-Rate SDI core thefrequency of the DRP clock in Hz. It is essential that this parameter accurately reflects theactual frequency of the DRP clock to within about 100 ppm. The CORE Generatorwizard for the Triple-Rate SDI core allows the user to specify the frequency of the DRP

clock and sets the DRPCLK_FREQ parameter automatically.The frequency of the DRP clock does not have to be related to any video frequency or to thefrequency of rxpipeclk or txpipeclk. To get an acceptable resolution for the bit rate detector,it is recommended that the frequency of the DRP clock be at least 10 MHz. So, any clockfrequency between 10 MHz and the highest supported GTP DCLK frequency is allowedfor the DRP clock. One global DRP clock can be used for all Spartan-6 FPGA Triple-RateSDI cores in the same FPGA.

Shared DRP

Each Spartan-6 FPGA GTP tile contains a pair of transceivers with a single, common DRPinterface. The Spartan-6 FPGA Triple-Rate SDI core contains a DRP controller that can

write parameters for either or both transceivers in a GTP tile. When both transceivers in atile are utilized for SDI, two instances of the core are required; they must be connected in aprimary/secondary fashion to utilize the DRP correctly.

The core instance physically connected to the DRP is the primary core. This core can beconnected to either transceiver. The core instance that has no connection to the DRP isdesignated as the secondary core. It connects to the transceiver of the tile not connected tothe primary core, which likewise can be either of the two transceivers of a GTP tile. Thesecondary tile must have its RX and TX mode outputs connected to the mode inputs of theprimary core so that the primary core can write DRP data on behalf of the secondary core.This is shown in Figure 3-2.


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Shared DRP

In Figure 3-2, the two transceivers operate independently, with separate reference clocksand user clocks. However, the primary core handles the DRP interface for both cores. In


Figure 3-2: Independent Transceivers with Shared DRP


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this example, the primary core interfaces to transceiver 1 and the secondary core totransceiver 0. The primary core must receive mode information for both transmitters, andthe receiver mode of the secondary core must be passed to the primary core.

For the DRP functionality to work for both cores, the same DRP clock (gtp_drpclk) must beused for both cores to guarantee the communication between cores is synchronous.

Clock Sharing

The Spartan-6 FPGA Triple-Rate SDI core contains PLLs for generating synchronized userclocks required by the GTP transceiver. In cases where there are multiple synchronouschannels in a single FPGA, these channels must share user clocks. To facilitate the sharingof user clocks, the core has clock inputs for an RX pipeline clock and a TX pipeline clock,separate from the TX and RX user clocks generated in the core. If it is desired to use thesegenerated clocks, they must be connected to the pipeline clock inputs external to the core.

For synchronous multi-channel systems, the clocks from a single core instance can beconnected to pipeline clock instances of multiple cores to provide synchronization. In suchcases, all GTP transceivers driven by common user clocks must also use the same referenceclock. In the core instances that utilize user clocks from another core instance, the userclock generation logic is not used and is optimized out in synthesis.

Figure 3-3shows an example of a synchronous multi-channel system. In this example, theclocks are provided by the core connected to transceiver 1. This core is also the primarycore for DRP; however, it is not necessary for the primary core to provide the clocks. Asingle reference clock is used for both transceivers, and all the user clocks come from theprimary core. The pipe clocks for the secondary core also utilize these clocks,synchronizing it to the primary core and both transceivers.


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Clock Sharing


Figure 3-3: Synchronous Transceivers with Shared User Clocks and DRP


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Chapter 4

Triple-Rate SDI Receiver Operation

Triple-Rate SDI Receiver Overview

The triple-rate SDI receiver has these features:

A single reference clock frequency is required to receive the five supported bit rates:

270 Mb/s SD-SDI

1.485 Gb/s HD-SDI

1.485/1.001 Gb/s HD-SDI

2.97 Gb/s 3G-SDI

2.97/1.001 Gb/s 3G-SDI

The other SD-SDI bit rates can also be received using the same reference clockfrequency. However, this requires modifications to the triple-rate SDI receiverreference design.

The receiver has a bit rate detector that determines whether the SDI bit rate is1.485 Gb/s or 1.485/1.001 Gb/s in HD-SDI mode, or 2.97 Gb/s and 2.97/1.001 Gb/sin 3G-SDI mode. An output signal from the receiver indicates which bit rate is beingreceived.

The receiver automatically detects the SDI standard of the input signal (3G-SDI,HD-SDI, or SD-SDI) and reports the current SDI mode on an output port.

The receiver detects and reports the video transport format (for example, 1080p 30 Hzor 1080i 50 Hz) for HD-SDI and 3G-SDI modes.

The receiver supports 3G-SDI level A and level B formats, and automatically detectswhether 3G-SDI data streams are level A or B. The 3G-SDI level is reported on anoutput port.

The receiver performs CRC error checking for HD-SDI and 3G-SDI modes.

Optional EDH error checking for the SD-SDI format is available. The optional EDHprocessor also includes an SD-SDI flywheel, an SD-SDI locked detector, and a videoformat (NTSC or PAL) detector.

Line numbers are captured and output from the triple-rate SDI receiver. For the3G-SDI level B format, line numbers are captured for each of the two HD-SDI streamscarried on the 3G-SDI interface.

SMPTE ST 352 video payload ID packets are captured for all SDI modes. The capturedST 352 packet data is available on output ports for one or two data streams (for thoseformats that require ST 352 packets in both streams).

The receiver datapath interfaces with a 20-bit GTP receiver RXDATA port. Thepipeline clock and the GTP user clocks are created in the core.


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All ancillary data embedded in the SDI data streams is preserved and output from thereceiver on the video data stream outputs.

The GTP receiver takes in the serial bitstream from an external SDI cable equalizer. Itautomatically determines whether the SDI signal is HD-SDI, 3G-SDI, or SD-SDI bysequentially trying to lock to the incoming signal in each of these modes until the receiverrecognizes that good data is received. During this search process, the rx_mode_locked

output is Low. When the receiver determines it has locked to the signal, therx_mode_locked output goes High, and the rx_mode and rx_mode_HD, rx_mode_3G, andrx_mode_SD outputs indicate in which SDI mode the receiver is operating.

Bit Rate and Transport Format Detection

The triple-rate SDI receiver has an automatic transport format detector. This functionexamines the timing of the video signals in the SDI data streams and determines whichvideo format they are. The operation of this function is independent of and not dependenton ST 352 video payload ID (VPID) packets. This function determines the transport format,not the picture format. Usually these are the same, but not always. For example, when1080p 60 Hz video is transported on 3G-SDI level B-DL, the video transport is actually

1080i 60 Hzthe transport is interlaced, but the picture is progressive.The rx_t_family output port provides a 4-bit code that indicates to which video formatfamily the transport timing corresponds. Table 4-1shows the encoding of this output port.The transport detection unit also determines whether transport is interlaced or progressiveand reports this information on the rx_t_scan output port.

The transport detector also determines the bit rate of the SDI signal and the frame rate ofthe transport signal. The rx_bit_rate output is valid in HD-SDI and 3G-SDI modes andindicates whether the incoming bit rate is 1.485 Gb/s or 1.485/1.001 Gb/s in HD-SDI modeor 2.97 Gb/s or 2.97/1.001 Gb/s in 3G-SDI mode. The rx_t_rate port indicates the frame ofthe transport signal as shown in Table 4-2. The encoding of the frame rate matches theencoding used in the picture rate field of SMPTE ST 352 VPID packets; however, therx_t_rate shows the transport frame rate, not the picture rate. The rx_t_rate port value isalways the frame rate, even for interlaced transports.

Table 4-1: rx_t_family Encoding

rx_t_family Transport Video Format Active Pixels

0000 SMPTE ST 274 1920 x 1080

0001 SMPTE ST 296 1280 x 720

0010 SMPTE 2048-2 2048 x 1080

0011 SMPTE 295 1920 x 1080

1000 NTSC 720 x 486

1001 PAL 720 x 576

1111 Unknown

Others Reserved


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Operation of the Triple-Rate SDI Receiver in the Various SDI Modes

The transport format detector can take up to two video frames to identify the transportformat after the receiver locks to the SDI signal. It takes even longer for the rx_t_rate portto be correct. The rx_t_rate value is determined by a combination of the transport timingand the rx_bit_rate signal. The rx_bit_rate signal is determined by comparing thefrequency of rxpipeclk to the frequency of drpclk. It takes approximately 0.1 seconds, afterthe SDI receiver is locked to the SDI signal, before the rx_bit_rate and rx_t_rate signals areaccurate. Because the transport format detector reacts faster than the bit rate detector, therx_t_rate port might initially change to a value of 60 Hz, for example, and then within0.1 seconds change to a value of 59.94 Hz as the bit rate detector determines that the SDI bitrate is 1.485/1.001 Gb/s instead of 1.485 Gb/s.

The bit rate detection function that generates the rx_bit_rate signal also serves to verifythat the frequency of rxpipeclk is within expected normal values. If the bit rate detectordetermines that the rxpipeclk frequency is outside of the expected normal values, it assertsthe gtp_cdrreset signal to reset the CDR block of the GTP receiver. This operation dependson the frequency of the reference clock (drpclk) matching the DRPCLK_FREQgeneric/parameter. If the frequency of drpclk does not match the DRPCLK_FREQ value,the bit rate detector does not function correctly and frequently resets the CDR.


The triple-rate SDI receiver automatically determines the standard of the incoming SDImode (SD-SDI, HD-SDI, 3G-SDI level A, or 3G-SDI level B) by sequentially trying to lock toeach SDI mode until it finds the correct SDI mode. When locked to the correct SDI mode,the receiver configures itself for correct operation in that mode. The recovered clockfrequency and the number and data rate of the output data streams depend on the SDImode.

Table 4-2: rx_t_rate Encoding

rx_t_rate Frame Rate

0000 None

0010 23.98 Hz

0011 24 Hz

0100 47.95 Hz

0101 25 Hz

0110 29.97 Hz

0111 30 Hz

1000 48 Hz

1001 50 Hz

1010 59.94 Hz

1011 60 Hz

Others Reserved


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Triple-Rate SDI Receiver Clocking

The GTP receivers CDR block requires a reference clock, which can be either 74.25 MHz or74.25/1.001 MHz. Some integer multiples of these frequencies are also supported. Inparticular, 148.5 MHz and 148.5/1.001 MHz are also commonly used. Only a singlereference clock frequency is required to support SD-SDI at 270 Mb/s, HD-SDI at both bitrates, and 3G-SDI at both bit rates. The frequency of the reference clock should not change.Any change in the reference clock frequency requires that the GTP receiver, including theRX PMA PLL, be reset.

The GTP receiver recovers a clock in 3G-SDI and HD-SDI modes, but not in SD-SDI mode.The recovered clock from the GTP transceiver is output on the GTPCLKOUT[1] port. Thisclock goes to a PLL that produces two phase-aligned user clocks for the GTP receiver,rxusrclk and rxusrclk2. The user clock gtp_rxusrclk has the same frequency asGTPCLKOUT[1], whereas gtp_rxusrclk2 is at half the frequency. The pipeline clock to thecore (rxpipeclk) and downstream logic should be driven by gtp_rxusrclk2, whosefrequency matches that of the 20-bit rx_data bus. The frequency of the recovered clockdepends on the current SDI mode of the receiver. In HD-SDI mode, the clock frequency is148.5 MHz or 148.5/1.001 MHz. In 3G-SDI mode, the clock frequency is 297 MHz or297/1.001 MHz. In SD-SDI mode, the CDR unit is locked to the reference clock, and

GTPCLKOUT[1] is either 148.5 MHz or 148.5/1.001 MHz, depending on the frequency ofthe reference clock. Table 4-3shows the frequencies of the clocks in the different modes.

The GTPOUTCLK[1] output of the GTP receiver must be buffered with a BUFIO2 buffer.The output of this clock buffer should drive the gtp_bufgtpclk[1] of the core as shown inFigure 2-1, page 11. Two synchronous user clocks are produced from the RX recoveredclock by dividing the clock by 1 and 2 using a PLL. These clocks are buffered inside the corewith global clock buffers. The gtp_rxusrclk output is at the recovered clock rate. Thegtp_rxusrclk2 output is at one-half the recovered clock rate. These two clocks are required

by the GTP RX interface. They must be in sync with each other and with the data going intothe GTP receiver. The rxpipeclk should be driven by the gtp_rxusrclk2 at one-half the rateof the recovered clock, and thus can be used to clock the 20-bit RX data pipeline in the core.

gtp_rxusrclk2 can also be used to drive any additional downstream modules that need tobe clocked at the 20-bit recovered clock rate.

Internally, most of the logic in the triple-rate SDI receiver runs at the rxpipeclk frequencyfor HD-SDI and 3G-SDI modes (some portions run at half the rxpipeclk frequency in3G-SDI level B mode). For SD-SDI mode, the internal data rate is 27 MHz. Clock enablesare used in the triple-rate SDI receiver to run the various sections at the proper rates whenthe data rate is different from the clock frequency.

Table 4-3: Receiver Clock Frequencies

SDI ModeGTPCLKOUT[1]

Frequency (MHz)How Derived

gtp_rxusrclk

Frequency (MHz)

gtp_rxusrclk2 /

rxpipeclk

Frequency (MHz)

SD-SDI148.5 or

148.5/1.001

Fixed multipleof GTP reference

clock

148.5 or148.5/1.001

74.25 or74.25/1.001

HD-SDI148.5 or

148.5/1001Recovered fromSDI input data

148.5 or148.5/1001

74.25 or74.25/1.001

3G-SDI297 or

297/1.001Recovered fromSDI input data

297 or297/1.001

148.5 or148.5/1.001


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The Triple-Rate SDI core supplies one SD-SDI clock enable on the rx_ce_sd output port.This clock enable can be used, in conjunction with gtp_usrclk2, to clock logic downstreamfrom the Triple-Rate SDI core at the 27 MHz SD-SDI data rate.

The rx_ce_sd signal is High in all modes except SD-SDI. In SD-SDI mode, this is a 27 MHzclock enable. See SD-SDI RX Operationfor more details.

The Triple-Rate SDI core also outputs an rx_dout_rdy_3G data ready signal. In 3G-SDIlevel B mode, rx_dout_rdy_3G toggles at half the recovered clock frequency because theoutput data rate is 74.25 MHz, while the clock frequency is 148.5 MHz. In all modes except3G-SDI level B, rx_dout_rdy_3G is always High.

The rx_ce_sd clock enable signal can be used as a clock enable to those datapaths that onlyoperate at the SD-SDI data rate. The rx_dout_rdy_3G signal can be used as a clock enableto those datapaths that operate in HD-SDI and 3G-SDI modes, but not in SD-SDI mode. Ifa datapath must operate correctly in all three SDI modes, it should use a clock enable thatis the AND of the rx_ce_sd signal and the rx_dout_rdy_3G signal.

SD-SDI RX Operation

When the triple-rate SDI receiver is operating in SD-SDI mode, the frequency of theRXRECCLKRX recovered clock on rxpipeclk is 74.25 MHz or 74.25/1.001 MHz, dependingon the reference clock frequency. The recovered SD-SDI data stream is output on therx_ds1a port with the Y and C components interleaved at a 27 MHz data rate. The timingsignals rx_trs, rx_eav, and rx_sav are valid.

In SD-SDI mode, the receiver clock GTPCLKOUT[1] is not a recovered clock because theGTP receiver is locked to the reference clock and asynchronously samples the input

bitstream. Therefore, rxpipeclk is a fixed multiple of the reference clock supplied to theGTP receiver.

A data recovery unit (DRU) in the triple-rate SDI receiver recovers the actual data streamfrom the oversampled data. The DRU asserts a data ready signal when it has a 10-bit dataword ready. The Spartan-6 FPGA Triple-Rate SDI core outputs this data ready signal on

the rx_ce_sd output. On average, this output is asserted every 2.75 clock cycles by using a3/3/3/2 clock cycle cadence. The output cadence is occasionally altered when the DRUneeds to catch up to the actual data rate. This occurs because the GTP transceiver referenceclock is a local clock, and is asynchronous to the actual timing of the incoming SD-SDI

bitstream. High amounts of jitter on the SD-SDI can also cause the cadence to vary.

Figure 4-1shows the timing of the SD video and timing signals output by thetriple_sdi_rx_20b_s6gtp module. The outputs only change on the rising edge of rxpipeclk,when rx_ce_sd is High. The timing of the EAV sequence is shown in Figure 4-1. The rx_savoutput signal has the same timing as the rx_eav signal, except that it is asserted during SAVsequences.


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HD-SDI RX Operation

When the triple-rate SDI receiver is operating in HD-SDI mode, RXRECCLK is a truerecovered clock, and runs at 74.25 MHz or 74.25/1.001 MHz, depending on the HD-SDI bitrate. The Y and C data streams of the HD-SDI signal are output on the rx_ds1a and rx_ds2aports, respectively, along with the timing signals rx_trs, rx_eav, and rx_sav. The linenumber is output on the rx_line_a port. In HD-SDI mode, the line number changes duringthe CRC0 word. Figure 4-2shows the timing of the HD-SDI outputs.

3G-SDI Level A RX Operation

When the triple-rate SDI receiver is operating in 3G-SDI level A mode, the frequency ofrxpipeclk is 148.5 MHz or 148.5/1.001 MHz, depending on the 3G-SDI bit rate.

Figure 4-3shows the output timing of the triple-rate SDI receiver when receiving a1080p 50, 59.94, or 60 Hz signal in 3G-SDI level A mode. These video formats do notrequire further unpacking of the data streams, because rx_ds1a carries the lumacomponent, and rx_ds2a carries the multiplexed chroma components.


Figure 4-1: SD-SDI RX Timing Diagram


Figure 4-2: HD-SDI RX Timing Diagram

rxpipeclk(74.25 MHz)

rx_ds1a

rx_ds2a

rx_trs

rx_eav

rx_line_a

UG823_c4_03_042811

3FFY(n) Y(n+1) Y(n+10) Y(n+11)000 XYZ LN0 LN1 CRC0 CRC1

3FFCB(n) CR(n) CB(n+10) CR(n+10)000

line(n) line(n+1)

XYZ LN0 LN1 CRC0 CRC1


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Other video formats, such as 4:4:4 10-bit or 12-bit, have identical timing to that shown inFigure 4-3, but the video samples are packed as specified by the SMPTE 425 so that it takestwo consecutive words on each data stream to carry a single video sample. The Spartan-6FPGA Triple-Rate SDI core does not unpack these other video formats, but outputs the twodata streams exactly as described in the 3G-SDI level A data stream mapping sections ofSMPTE 425.

3G-SDI Level B RX Operation

When the triple-rate SDI receiver is operating in 3G-SDI level B mode, the frequency ofrxpipeclk is 148.5 MHz or 148.5/1.001 MHz, depending on the 3G-SDI bit rate. However,

in this mode, there are four 10-bit data streams output by the triple-rate SDI receiver. Thedata rate of these data streams is half the frequency of RXRECCLK; therefore, therx_dout_rdy_3G signal is asserted every other clock cycle, and acts as a clock enable.

Both line number output ports are active. When the level B signal is transportingSMPTE 372 dual link data streams (level B-DL), the values on both rx_line_a and rx_line_bare identical and indicate the interface line number, not the picture line number. When thelevel B signal is transporting two independent HD-SDI signals, the two line number valuesare not necessarily the same, depending on whether the two HD-SDI signals areframe-locked or not. The rx_line_a and rx_line_b ports, not shown in Figure 4-4, change atthe same relative position as they do for 3G-SDI level A and HD-SDI, as the CRC0 word isoutput on the data streams.

When the 3G-SDI level B signal carries SMPTE 372 dual link data streams, the link A data

streams are output on rx_ds1a and rx_ds2a, and the link B data streams are output onrx_ds1b and rx_ds2b. These four links carry video mapped as required by SMPTE 372. Thetriple-rate SDI receiver does not unpack the data streams into video, but outputs them asSMPTE 372 data streams.

When the 3G-SDI level B signal carries two independent HD-SDI streams (level B-DS), thefirst HD-SDI stream is output with the luma component on rx_ds1a and the multiplexedchroma components on rx_ds2a. The second HD-SDI stream is output with the lumacomponent on rx_ds1b and the multiplexed chroma component on rx_ds2b. These two


Figure 4-3: 3G-SDI Level A RX Timing (1080p 50 Hz or 60 Hz)

rxpipeclk(148.5 MHz)

rx_dout_rdy_3G

rx_ds1a

rx_ds2a

rx_trs

rx_eav

rx_line_a

UG823_c4_04_042811

3FFY(1918) Y(1919) Y(1928) Y(1929)000 XYZ LN0 LN1 CRC0 CRC1

line(n) line(n+1)

3FFCB(1918) CR(1918) CB(1928) CR(1928)000 XYZ LN0 LN1 CRC0 CRC1


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HD-SDI streams are horizontally synchronized such that their EAVs and SAVs always lineup exactly; therefore there is only a single set of rx_eav, rx_sav, and rx_trs timing signals.

Figure 4-4shows the output timing of the triple-rate SDI receiver when receiving a 3G-SDIlevel B signal.

Electrical Interface

The GTP receiver must be connected to the SDI connector through an SDI cable equalizer.

The equalizer serves two purposes. It equalizes the SDI signal to compensate for signaldistortion and attenuation, and it converts the single-ended 75SDI signal to a differentialsignal compatible with the GTP receiver input. Any industry-standard SDI cable equalizercan be used, such as those from National Semiconductor and Gennum.

Most, if not all, SDI cable equalizers currently available do not have a common modeoutput voltage directly compatible with the GTP transceiver inputs. Therefore ACcoupling is required to shift the common mode voltage of the signal as it enters the GTPreceiver. The GTP receiver has built-in AC coupling, but these internal capacitors are notadequate to support the long run lengths of the SDI signals. The internal AC coupling must

be bypassed and external AC coupling capacitors must be used. The value of these externalcapacitors is usually about 4.7 F. Nothing else needs to be done to set the common modevoltage, because the GTP receiver provides a correct termination voltage to set the

common mode voltage on its inputs. The user must follow the recommendations of thecable equalizer manufacturer for interfacing the cable equalizer to the BNC cable.

When a GTP transceiver wrapper is created using the hd sdiprotocol template, the wrapperis configured correctly to bypass the internal AC coupling capacitors and to properlyterminate the receiver inputs for use with external AC coupling capacitors.


Figure 4-4: 3G-SDI Level B RX Timing

rxpipeclk

(148.5 MHz)

Link A

Link B

rx_dout_rdy_3G

rx_ds1a

rx_ds2a

rx_ds1b

rx_ds2b

rx_trs

rx_eav

UG824_c4_05_032811

3FFY(1918) Y(1919) 000 XYZ LN0

3FFCB(1918) CR(1918) 000 XYZ LN0

3FFY(1918) Y(1919) 000 XYZ LN0

3FFCB(1918) CR(1918) 000 XYZ LN0


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Other Triple-Rate SDI RX Design Considerations


Dual Link HD-SDI

To implement a dual link HD-SDI receiver, two triple-rate SDI receivers are paired togetherwith one receiving link A and the other receiving link B. Typically, the received data

streams for the two links are skewed, so the application must remove the skew. The datastreams can then be unpacked into video streams, if desired.

Deskewing the data streams involves watching the EAV or SAV signals from each link, anddelaying the data streams of the link whose EAV becomes asserted first by an appropriateamount to match the timing of the other link. The Spartan-6 FPGA SRLC32E elementsmake perfect delay devices for implementing this deskew function. Prior to 2011, theSMPTE ST 372 specification stated that the maximum skew between the two links at theoutput of the transmitters must not exceed 40 ns. However, it is common in the industryfor dual link HD-SDI transmitters to have much more skew between the two links thanthis. The ST 372 specification now states that the skew between the links can be as high as500 ns.

Processing Embedded Audio and Other Ancillary Data

The output data streams from the triple-rate SDI receiver always have all ancillary data,including embedded audio packets, intact. Modules designed to process ancillary data can

be connected to the data streams, clock enables, and other timing signals output by thetriple-rate SDI receiver.

SMPTE 352 Video Payload ID Packets

The triple-rate SDI receiver module captures SMPTE 352 packets present in the datastreams for all SDI modes. For SD-SDI and HD-SDI modes, the four data bytes of theSMPTE 352 packet are output on the rx_a_vpid port. The rx_a_vpid_valid port indicates

when valid SMPTE 352 packets have been captured. This output has some hysteresis sothat SMPTE 352 packets can be missing from a few fields or frames before the valid signalis negated. During the time that the valid output is asserted and new SMPTE 352 packetsare not found, the data from the last valid SMPTE 352 packet received is output on therx_a_vpid port.

The 3G-SDI standard requires SMPTE 352 packets in both data streams. The triple-rate SDIreceiver captures the SMPTE 352 packets from both streams, outputting the data from thepacket in data stream 1 on rx_a_vpid, and the data from the packet in data stream 2 onrx_b_vpid. The module also supplies individual rx_a_vpid_valid and rx_b_vpid_validoutputs.

SD-SDI EDH Error Detection

The triple-rate SDI receiver contains an EDH processor that checks the SD-SDI signal forerrors. This EDH processor does not update EDH packets in the SD-SDI stream. It simplyreports any errors found and also captures the error flags from each EDH packet.

The EDH processor has a 16-bit counter that counts the number of fields with errors. Thecurrent error count is output on the rx_edh_errcnt port. The counter can be cleared byasserting rx_edh_clr_errcnt High. The user can specify which types of errors are counted

by this counter using the rx_edh_errcnt_en input port. This port has 16 unary bits thatenable and disable 16 different error types. Any bit that is High enables the corresponding


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error. When this type of error is detected, the error counter increments. Any bit that is Lowdisables the corresponding error. Table 4-4shows the encoding of the bits on therx_edh_errcnt_en port.

The ANC error conditions occur when there are errors in the ancillary data packets. The FFerror conditions occur when there are errors in the full field. The AP error conditions occurwhen there are errors in the active portion of the picture. The EDH packet checksum errorindicates a checksum error was found within the EDH packet itself.

Each ANC, FF, and AP error condition set has five individual error flags. All flags areasserted High to indicate an error condition.

EDH error: This error condition occurs when the EDH processor detects a CRC error(checksum error for ANC packets) in a field.

EDA error: This error condition occurs when the EDA or EDH flags of the receivedEDH packet are asserted.

IDH error: This error condition is not supported.

IDA error: This error condition occurs when the IDA or IDH flags of the receivedEDH packet are asserted.

UES error: This error condition occurs when the UES flag in the received EDH packetis asserted.

The actively computed EDH errors for the ANC, AP, and FF are also output on therx_edh_anc, rx_edh_ap, and rx_edh_ff ports, respectively. Thus, the rx_edh_anc port isasserted whenever a checksum error is detected in an ancillary data packet. The rx_edh_apport is asserted when the calculated active picture CRC does not match the AP CRC in the

Table 4-4: Encoding of rx_edh_errcnt_en

Bit # Error

0 ANC EDH error

1 ANC EDA error

2 ANC IDH error

3 ANC IDA error

4 ANC UES error

5 FF EDH error

6 FF EDA error

7 FF IDH error

8 FF IDA error

9 FF UES error

10 AP EDH error

11 AP EDA error

12 AP IDH error

13 AP IDA error

14 AP UES error

15 EDH packet checksum error


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