RISC processor implementation using Bluespec part 1 - final presentation
UEFI Port to RISC-V Processor Architecture
Transcript of UEFI Port to RISC-V Processor Architecture
presented by
UEFI Port to RISC-V Processor Architecture
UEFI Spring Plugfest – March 30, 2016Abner Chang, SW/FW Technologist
UEFI Plugfest – March 2016 www.uefi.org 1
Updated 2011-06-01
Agenda
• Introduction
• RISC-V UEFI port on EDKII
• Spec changes for RISC-V
• Appendix
UEFI Plugfest – March 2016 www.uefi.org 2
RISC and CISC
UEFI Plugfest – March 2016 www.uefi.org 3
RISC Reduced instruction set computer, like ARM, Power PC, SPARC processor
CISC Complex instruction set computer, like Intel processor
Fixed length of instruction, simple instructions to be executed in one CPU clock.
Less instruction sets, RISC-V has around 90+ instructions for example.
Better performance of instruction fetch and pipeline.
Variable length of instructions, multiple clocks instruction
Slightly complex when writing program in assembly language.
Easy to write program in assembly language
Specific instructions for specific purpose
Less code size
To complete a task in few line assembly as possible.
Large code sizeEmphasis on software
Emphasis on hardware
What is RISC-V processor
UEFI Plugfest – March 2016 www.uefi.org 4
- New and open instruction set architecture (ISA) original designed for computer architecture research and education
- Now become a standard open ISA for industrial
- From UC Berkeley, the fifth major RISC ISA design.
- Roman numeral “V” to signify “variations” and “vectors”
What is RISC-V processor
UEFI Plugfest – March 2016 www.uefi.org 5
- 32-bit, 64-bit and 128 bit processor.
- Instruction groups
- Base integer instruction set
- Standard extension for integer multiplication and division
- Standard extension for atomic instructions
- Standard extension for single-precision floating point
- Standard extension for double-precision floating point
- Standard extension for quad-precision floating point
- Standard extension for compressed instructions
- Standard extension for bit manipulation
- Standard extension for SIMD instruction
What is RISC-V processor
UEFI Plugfest – March 2016 www.uefi.org 6
- 4 privileged operation modes
Machine mode
Hypervisor mode
Supervisor mode
User mode
RISC-V UEFI PortEDKII OVMF RISC-V Package on QEMU
Security
SecMain.efi
(SEC)
Pre EFI Initialization
(PEI)
Driver Execution Environment
(DXE)
Boot Dev
Select
(BDS)
Transient
System
Load
(TSL)
Runtime
(RT)
After
Life
(AL)
Reset
Vector
(VTF)
UEFI/PI Execution
Phases
Power on [….Platform initialization..] [….OS boot...] Shutdown
Reset
Vector
CPU Init
Chipset
Init
Board init
SEC to PEI
handoff
PEI Driver Dispatcher
Device,
Bus, or
Service Driver
Device,
Bus, or
Service Driver
Platform
initial Drivers
DXE initial
program
loader
DXE Driver
Dispatcher
Boot Manager
Device,
Bus, or
Service Driver
Device,
Bus, or
Service Driver
Device,
Bus, or
Service Driver
OS-
Absent App
Transient
OS
Environment
Transient OS Loader
Final OS
boot Loader
Final OS
Environ
ment
OS-
Present APP
Security
SecMain.efi
(SEC)
Pre EFI Initialization
(PEI)
Driver Execution Environment
(DXE)
Boot Dev
Select
(BDS)
Transient
System
Load
(TSL)
Runtime
(RT)
After
Life
(AL)
Reset
Vector
(VTF)
UEFI/PI Execution
Phases
Power on [….Platform initialization..] [….OS boot...] Shutdown
FD, Flash Device (ROM)
Vo
lum
e
To
p
Fil
e
FV
FV
FV
FV
FF
S
FF
S
FD
FF
S
FF
S
FF
S
FV
RISC-V Machine Mode
FF
S
FF
S
Generate Reset
Vector VTF for
RISC-V Two standard values
0xF…FFE00 or
0x0…0200
CSR MTVEC Machine Trap Vector Base Address
0xF…FFFFFFFF
RISC-V Reset
Vector
(0xF…FF00)
GenF
w
Security
SecMain.efi
(SEC)
Pre EFI Initialization
(PEI)
Driver Execution Environment
(DXE)
Boot Dev
Select
(BDS)
Transient
System
Load
(TSL)
Runtime
(RT)
After
Life
(AL)
Reset
Vector
(VTF)
UEFI/PI Execution
Phases
FD, Flash Device (ROM)
Vo
lum
e
To
p
Fil
e
FV
FV
FV
FV
FF
S
FF
S
FD
FF
S
FF
S
FF
S
FV
RISC-V Machine Mode
FF
S
FF
S
Generate Reset
Vector VTF for
RISC-V
0xF…FFFFFFFF
RISC-V Reset
Vector
(0xF…FF00)
- Generate EFI
PECOFF
image
-PECOFF RISC-V
relocation type.
- ProcessorBinding
(structure alignment,
variable alignment)
- Prepare Temporary
memory
ELF to PE COFF convertor
- RISC-V ELF to PE COFF
- Handle RISC-V relocation
GenF
W- RISC-V image relocation for
XIP image.
GenF
V
typedef unsigned long long UINT64 __attribute__ ((aligned (8)));
typedef long long INT64 __attribute__ ((aligned (8)));
typedef unsigned int UINT32 __attribute__ ((aligned (4)));
typedef int INT32 __attribute__ ((aligned (4)));
typedef unsigned short UINT16 __attribute__ ((aligned (2)));
typedef unsigned short CHAR16 __attribute__ ((aligned (2)));
typedef short INT16 __attribute__ ((aligned (2)));
ProcessorBinding.h (datatype alignment)
-fpack-struct=8
C Compiler
PECOFF Target Machine
Type
- 0x5032 for RISC-V 32
- 0x5064 for RISC-V 64
ELF to PECOFF
ELF relocation type to EFI IMAGE relocation type (PECOFF)
ELF to
PECOFF
SEC to PEI
handoff
Power on [….Platform initialization..] [….OS boot...] Shutdown
Security
SecMain.efi
(SEC)
Pre EFI Initialization
(PEI)
Driver Execution Environment
(DXE)
Boot Dev
Select
(BDS)
Transient
System
Load
(TSL)
Runtime
(RT)
After
Life
(AL)
Reset
Vector
(VTF)
UEFI/PI Execution
Phases
FD, Flash Device (ROM)
Vo
lum
e
To
p
Fil
e
FV
FV
FV
FV
FF
S
FF
S
FD
FF
S
FF
S
FF
S
FV
RISC-V Machine Mode
FF
S
FF
S
Generate Reset
Vector VTF for
RISC-V
0xF…FFFFFFFF
RISC-V Reset
Vector
(0xF…FF00)
- ProcessorBinding
(structure alignment,
variable alignment)
- Generate EFI image
PECOFF
- PECOFF RISC-V
relocation type.
- Prepare Temporary
memory
- Platform memory
initialization
- CPU HOB to
declare memory
address size
- RISC-V
SET_JUMP/LONGJ
UMP to switch
stack to permanent
- RISC-V memory
map read/write
- RISC-V I/O
read/write (memory
map)
- EDKII BaseLib for
RISC-V
- RISC-V specific PEI
service pointer
retrieval
Memory address :32-bit, I/O
address:32-bit
CPU HOB
SET_JUMP requires return value on
EDKII
SET_JUMP/LONG_J
UMP
Memory map Read/Write and,Memory map I/O
read/write
Memory and I/O
Processor intrinsic function, Ena/Dis
interrupt (CSR) , Stack switch,
Breakpoint (EBREAK), CPU pause
(NOP)
BaseLib
Maintain RISC-V machine trap handler in MSCRATCH CSR
Power on [….Platform initialization..] [….OS boot...] Shutdown
Security
SecMain.efi
(SEC)
Pre EFI Initialization
(PEI)
Driver Execution Environment
(DXE)
Boot Dev
Select
(BDS)
Transient
System
Load
(TSL)
Runtime
(RT)
After
Life
(AL)
Reset
Vector
(VTF)
UEFI/PI Execution
Phases
FD, Flash Device (ROM)
Vo
lum
e
To
p
Fil
e
FV
FV
FV
FV
FF
S
FF
S
FD
FF
S
FF
S
FF
S
FV
RISC-V Machine Mode
FF
S
FF
S
Generate Reset
Vector VTF for
RISC-V
0xF…FFFFFFFF
RISC-V Reset
Vector
(0xF…FF00)
- ProcessorBinding
(structure alignment,
variable alignment)
- Generate EFI image
PECOFF
- PECOFF RISC-V
relocation type.
- Prepare Temporary
memory
- Platform memory
initialization
- CPU HOB to
declare memory
address size
- RISC-V
SET_JUMP/LONGJ
UMP to switch
stack to permanent
- RISC-V memory
map read/write
- RISC-V I/O
read/write (memory
map)
- EDKII BaseLib for
RISC-V
- RISC-V specific PEI
service pointer
retrieval
Maintain RISC-V machine trap handler in MSCRATCH CSR
DXE initial
program
loader
RISC-V DXE
Timer Arch
protocol
RegisterHandler
SetTimerPeriod
GetTimerPeriod
GenerateSoftwareIn
t
mtime CSRmtimecmp CSR
RISC-V DXE CPU arch
protocolCpuFlushDataCache
CpuEnableInterrupt
CpuDisableInterrupt
CpuGetInterruptState
CpuInit
CpuRegisterInterruptHandle
r
CpuGetTimerValue
CpuSetMemoryAttribute
mcause CSR
mip CSRmie CSR
RISC-V
Trap
handler in
VTF
RISC-V Reset
Vector
(0xF…FE00)
Power on [….Platform initialization..] [….OS boot...] Shutdown
Security
SecMain.efi
(SEC)
Pre EFI Initialization
(PEI)
Driver Execution Environment
(DXE)
Boot Dev
Select
(BDS)
Transient
System
Load
(TSL)
Runtime
(RT)
After
Life
(AL)
Reset
Vector
(VTF)
UEFI/PI Execution
Phases
FD, Flash Device (ROM)
Vo
lum
e
To
p
Fil
e
FV
FV
FV
FV
FF
S
FF
S
FD
FF
S
FF
S
FF
S
FV
RISC-V Machine Mode
FF
S
FF
S
Generate Reset
Vector VTF for
RISC-V
0xF…FFFFFFFF
RISC-V Reset
Vector
(0xF…FF00)
- ProcessorBinding
(structure alignment,
variable alignment)
- Generate EFI image
PECOFF
- PECOFF RISC-V
relocation type.
- Prepare Temporary
memory
- Platform memory
initialization
- CPU HOB to
declare memory
address size
- RISC-V
SET_JUMP/LONGJ
UMP to switch
stack to permanent
- RISC-V memory
map read/write
- RISC-V I/O
read/write (memory
map)
- EDKII BaseLib for
RISC-V
- RISC-V specific PEI
service pointer
retrieval
Maintain RISC-V machine trap handler in MSCRATCH CSR
DXE initial
program
loader
RISC-V DXE
Timer Arch
protocol
RegisterHandler
SetTimerPeriod
GetTimerPeriod
GenerateSoftwareIn
t
mtime CSRmtimecmp CSR
RISC-V DXE CPU arch
protocolCpuFlushDataCache
CpuEnableInterrupt
CpuDisableInterrupt
CpuGetInterruptState
CpuInit
CpuRegisterInterruptHandle
r
CpuGetTimerValue
CpuSetMemoryAttribute
mcause CSR
mip CSRmie CSR
RISC-V
Trap
handler in
VTF
RISC-V Reset
Vector
(0xF…FE00)
User Mode Trap
Handler
Supervisor Mode Trap
Handler
Hypervisor Mode Trap
Handler
Machine Mode Trap
Handler
GenF
w
Power on [….Platform initialization..] [….OS boot...] Shutdown
Machine Trap Vector Base Address
Security
SecMain.efi
(SEC)
Pre EFI Initialization
(PEI)
Driver Execution Environment
(DXE)
Boot Dev
Select
(BDS)
Transient
System
Load
(TSL)
Runtime
(RT)
After
Life
(AL)
Reset
Vector
(VTF)
UEFI/PI Execution
Phases
FD, Flash Device (ROM)
Vo
lum
e
To
p
Fil
e
FV
FV
FV
FV
FF
S
FF
S
FD
FF
S
FF
S
FF
S
FV
RISC-V Machine Mode
FF
S
FF
S
Generate Reset
Vector VTF for
RISC-V
0xF…FFFFFFFF
RISC-V Reset
Vector
(0xF…FF00)
- ProcessorBinding
(structure alignment,
variable alignment)
- Generate EFI image
PECOFF
- PECOFF RISC-V
relocation type.
- Prepare Temporary
memory
- Platform memory
initialization
- CPU HOB to
declare memory
address size
- RISC-V
SET_JUMP/LONGJ
UMP to switch
stack to permanent
- RISC-V memory
map read/write
- RISC-V I/O
read/write (memory
map)
- EDKII BaseLib for
RISC-V
- RISC-V specific PEI
service pointer
retrieval
Maintain RISC-V machine trap handler in MSCRATCH CSR
DXE initial
program
loader
RISC-V DXE
Timer Arch
protocol
RegisterHandler
SetTimerPeriod
GetTimerPeriod
GenerateSoftwareIn
t
mtime CSRmtimecmp CSR
RISC-V DXE CPU arch
protocolCpuFlushDataCache
CpuEnableInterrupt
CpuDisableInterrupt
CpuGetInterruptState
CpuInit
CpuRegisterInterruptHandle
r
CpuGetTimerValue
CpuSetMemoryAttribute
mcause CSR
mip CSRmie CSR
RISC-V
Trap
handler in
VTF
RISC-V Reset
Vector
(0xF…FE00)
Power on [….Platform initialization..] [….OS boot...] Shutdown
Security
SecMain.efi
(SEC)
Pre EFI Initialization
(PEI)
Driver Execution Environment
(DXE)
Boot Dev
Select
(BDS)
Transient
System
Load
(TSL)
Runtime
(RT)
After
Life
(AL)
Reset
Vector
(VTF)
UEFI/PI Execution
Phases
FD, Flash Device (ROM)
Vo
lum
e
To
p
Fil
e
FV
FV
FV
FV
FF
S
FF
S
FD
FF
S
FF
S
FF
S
FV
RISC-V Machine Mode
FF
S
FF
S
Generate Reset
Vector VTF for
RISC-V
0xF…FFFFFFFF
RISC-V Reset
Vector
(0xF…FF00)
- ProcessorBinding
(structure alignment,
variable alignment)
- Generate EFI image
PECOFF
- PECOFF RISC-V
relocation type.
- Prepare Temporary
memory
- Platform memory
initialization
- CPU HOB to
declare memory
address size
- RISC-V
SET_JUMP/LONGJ
UMP to switch
stack to permanent
- RISC-V memory
map read/write
- RISC-V I/O
read/write (memory
map)
- EDKII BaseLib for
RISC-V
- RISC-V specific PEI
service pointer
retrieval
Maintain RISC-V machine trap handler in MSCRATCH CSR
DXE initial
program
loader
RISC-V DXE
Timer Arch
protocol
RegisterHandler
SetTimerPeriod
GetTimerPeriod
GenerateSoftwareIn
t
mtime CSRmtimecmp CSR
RISC-V DXE CPU arch
protocolCpuFlushDataCache
CpuEnableInterrupt
CpuDisableInterrupt
CpuGetInterruptState
CpuInit
CpuRegisterInterruptHandle
r
CpuGetTimerValue
CpuSetMemoryAttribute
mcause CSR
mip CSRmie CSR
RISC-V
Trap
handler in
VTF
RISC-V Reset
Vector
(0xF…FE00)
SEC RISC-V Machine mode Trap handler
PEI RISC-V machine mode trap handler DXE RISC-V machine mode trap handler
Power on [….Platform initialization..] [….OS boot...] Shutdown
Security
SecMain.efi
(SEC)
Pre EFI Initialization
(PEI)
Driver Execution Environment
(DXE)
Boot Dev
Select
(BDS)
Transient
System
Load
(TSL)
Runtime
(RT)
After
Life
(AL)
Reset
Vector
(VTF)
UEFI/PI Execution
Phases
FD, Flash Device (ROM)
Vo
lum
e
To
p
Fil
e
FV
FV
FV
FV
FF
S
FF
S
FD
FF
S
FF
S
FF
S
FV
RISC-V Machine Mode
FF
S
FF
S
Generate Reset
Vector VTF for
RISC-V
0xF…FFFFFFFF
RISC-V Reset
Vector
(0xF…FF00)
- ProcessorBinding
(structure alignment,
variable alignment)
- Generate EFI image
PECOFF
- PECOFF RISC-V
relocation type.
- Prepare Temporary
memory
- Platform memory
initialization
- CPU HOB to
declare memory
address size
- RISC-V
SET_JUMP/LONGJ
UMP to switch
stack to permanent
- RISC-V memory
map read/write
- RISC-V I/O
read/write (memory
map)
- EDKII BaseLib for
RISC-V
- RISC-V specific PEI
service pointer
retrieval
Maintain RISC-V machine trap handler in MSCRATCH CSR
DXE initial
program
loader
RISC-V DXE
Timer Arch
protocol
mtime CSRmtimecmp CSR
RISC-V DXE CPU arch
protocol
mcause CSR
mip CSRmie CSR
RISC-V
Trap
handler in
VTF
RISC-V Reset
Vector
(0xF…FE00)
SEC RISC-V Machine mode Trap handler
PEI RISC-V machine mode trap handler DXE RISC-V machine mode trap handler
RISC-V DXE Reset
Arch protocol
RISC-V DXE
Real Time Clock
arch protocol
Stall ()
Metronome DXE Arch Ptotocol
ACPI
EDKII
TimerLib
mtimeCSR
Management
Mode
MP service
Power on [….Platform initialization..] [….OS boot...] Shutdown
Power on [….Platform initialization..] [….OS boot...] Shutdown
Security
SecMain.efi
(SEC)
Pre EFI Initialization
(PEI)
Driver Execution Environment
(DXE)
Boot Dev
Select
(BDS)
Transient
System
Load
(TSL)
Runtime
(RT)
After
Life
(AL)
Reset
Vector
(VTF)
UEFI/PI Execution
Phases
FD, Flash Device (ROM)
Vo
lum
e
To
p
Fil
e
FV
FV
FV
FV
FF
S
FF
S
FD
FF
S
FF
S
FF
S
FV
RISC-V Machine Mode
FF
S
FF
S
Generate Reset
Vector VTF for
RISC-V
0xF…FFFFFFFF
RISC-V Reset
Vector
(0xF…FF00)
- ProcessorBinding
(structure alignment,
variable alignment)
- Generate EFI image
PECOFF
- PECOFF RISC-V
relocation type.
- Prepare Temporary
memory
- Platform memory
initialization
- CPU HOB to
declare memory
address size
- RISC-V
SET_JUMP/LONGJ
UMP to switch
stack to permanent
- RISC-V memory
map read/write
- RISC-V I/O
read/write (memory
map)
- EDKII BaseLib for
RISC-V
- RISC-V specific PEI
service pointer
retrieval
Maintain RISC-V machine trap handler in MSCRATCH CSR
DXE initial
program
loader
RISC-V DXE
Timer Arch
protocol
mtime CSRmtimecmp CSR
RISC-V DXE CPU arch
protocol
mcause CSR
mip CSRmie CSR
RISC-V
Trap
handler in
VTF
RISC-V Reset
Vector
(0xF…FE00)
SEC RISC-V Machine mode Trap handler
PEI RISC-V machine mode trap handler DXE RISC-V machine mode trap handler
RISC-V DXE Reset
Arch protocol
RISC-V DXE
Real Time Clock
arch protocol
ACPI
EDKII
TimerLib
Time CSR
Management
Mode
MP service
RISC-V DXE
Timer Arch
protocol
RISC-V
Trap
handler in
VTF
Security
SecMain.efi
(SEC)
Pre EFI Initialization
(PEI)
Driver Execution Environment
(DXE)
Boot Dev
Select
(BDS)
Transient
System
Load
(TSL)
Runtime
(RT)
After
Life
(AL)
Reset
Vector
(VTF)
UEFI/PI Execution
Phases
FD, Flash Device (ROM)
0xF…FFFFFFFF
RISC-V Reset
Vector
(0xF…FF00)
Vo
lum
e
To
p
Fil
e
Generate Reset
Vector VTF for
RISC-V
- ProcessorBinding
(structure alignment,
variable alignment)
- Generate EFI image
PECOFF
- PECOFF RISC-V
relocation type.
- Prepare Temporary
memory
FV
FV
FV
FV
FF
S
FF
S
FF
S
GenFW
- RISC-V ELF to PE COFF
- Handle RISC-V relocation
GenFV
- RISC-V image
relocation for XIP image.
- Platform memory
initialization
- CPU HOB to
declare memory
address size
- RISC-V
SET_JUMP/LONGJ
UMP to switch
stack to permanent
- RISC-V memory
map read/write
- RISC-V I/O
read/write (memory
map)
- EDKII BaseLib for
RISC-V
- RISC-V specific PEI
service pointer
retrieval
SEC RISC-V Machine mode Trap handler
PEI RISC-V machine mode trap handler DXE RISC-V machine mode trap handler
RISC-V Reset
Vector
(0xF…FE00)
Maintain RISC-V machine trap handler in MSCRATCH CSR
DXE initial
program
loader
RISC-V DXE Reset
Arch protocol
RISC-V DXE
Real Time Clock
arch protocol
RISC-V DXE CPU arch
protocol
ACPI
SEC to PEI
handoff
Management
Mode
FV
FF
S
FF
S
mtime CSRmtimecmp CSR
mcause CSR
mip CSRmie CSR
MP service
EDKII
TimerLib
Time CSR
RISC-V Machine Mode
FV
FF
S
FF
S
Power on [….Platform initialization..] [….OS boot...] Shutdown
UEFI/PI Spec changes for RISC-V (in progress)
UEFI Plugfest – March 2016 www.uefi.org 19
UEFI spec change for RISC-V
• 2.1.1. UEFI Images• 2.3. Calling Conventions• 2.3. RISC-V 32 (64/128) Platforms• 17.2 EFI Debug Support Protocol
PI spec change for RISC-V
• Volume 1 : 5.4 RISC-V PEI Services Table Retrieval• Volume 3 : PI Status code
PE/Coff changes for RISC-V
UEFI Plugfest – March 2016 www.uefi.org 20
PE/COFF image machine type,
• IMAGE_FILE_MACHINE_RISCV32 0x5032
• IMAGE_FILE_MACHINE_RISCV64 0x5064
• IMAGE_FILE_MACHINE_RISCV128 0x5128
RISC-V image relocation types,
• IMAGE_REL_BASED_RISCV_HI20 5
• IMAGE_REL_BASED_RISCV_LO12I 7
• IMAGE_REL_BASED_RISCV_LO12S 8
Microsoft will release RISC-V related definition in next PE/COFF specification.
RISC-V QEMU
UEFI Plugfest – March 2016 www.uefi.org 22
• QEMU RISC-V PC/AT board
• QEMU PC/AT memory map devices (CMOS, PM, PCI and other devices)
Built up RISC-V PC/AT board on QEMU with some PC peripherals.
Changed these PC peripherals to memory map I/O device because RISC-V uses memory map I/O.
RISC-V Interrupt Controller
UEFI Plugfest – March 2016 www.uefi.org 23
• BERI (Bluespec Extensible RISC Implementation) Programmable Interrupt Controller
BERI PIC is attached to BERI processor. BERI PIC supports large number of external interrupts, total up to 1024 interrupt sources.
Need more in RISC-V spec
UEFI Plugfest – March 2016 www.uefi.org 24
• PI Management Mode support
• ACPI support
• Reset mechanism
• MP support
• Bus Interface
RISC-V Implementations
UEFI Plugfest – March 2016 www.uefi.org 25
• RISC-V in AXIOM First Fully Open Source 4K Film Camera
• A 32-bit 100MHz RISC-V Microcontroller with 10-bit SAR ADC
• SoC for a Satellite Navigation Unit based on the RISC-V single-core Rocket chip
• RISC-V-based photonic processor
• lowRisc Rocket chip (RISC-V based SoC)
Thanks for attending the UEFI Spring Plugfest 2016
For more information on the Unified EFI Forum and UEFI Specifications, visit http://www.uefi.org
presented by
UEFI Plugfest – March 2016 www.uefi.org 26