TUTORIAL ON USING XILINX ISE DESIGN SUITE 10.1:Design Entry Using VHDL (Full Adder) for Spartan-II E

(Digilent D2E Board)

Shawki Areibi

September 28, 2009

1 Introduction

The objective of this tutorial is to show the basic concepts of VHDL. VHDL (Very High-Speed-Integrated-Circuit Description Language) is a very powerful digital design language. It allows adesigner to specify a digital circuit at a very high level.

2 Start a new project

We wish to enter our design using a Hardware Description Language specifically VHDL.

1. Load the Project Navigator from the → All Programs → Development → XilinxISE Design Suite 10.1 → ISE → Project Navigator.

2. The Project Navigator window will appear. Select File → New Project

3. The New Project Wizard window will appear.

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• Enter a name for the project.

• Specify the directory in which you want to store it in.

• For Top-Level Source Type select HDL.

• click

4. Another New Project Wizard dialog box will appear prompting you for device, synthesis andsimulation settings for the project.

In this dialog box verify the following settings:

• Device Family → Spartan2E.

• Device → xc2s200e.

• Package → pq208.

• Speed Grade → -6.

• Synthesis Tool → XST (VHDL/Verilog).

• Simulator → ISE Simulator (VHDL/Verilog).

• Generated Simulation Language → VHDL.

If the information is correct click Next.

5. The next dialog box will ask if you wish to add a new source file to the project. Click NewSource.... A new dialog box will appear prompting you for the file type, name and location.Select VHDL module from the list of file types and name the file MyAdder. The defaultlocation should be the project directory and ensure the Add to project box is checked.

6. In the Define VHDL Source dialog box that appears, add ports A, B and CI as inputsand CO and S as outputs. Click Next when this is done.

7. The next dialog box will allow you to confirm the previous choices. Click if they arecorrect.

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8. You will now return to the New Project dialog box and the ”MyAdder.vhd” source templatethat you have created will now be listed. Click Next. The next dialog box is used to addexisting source files to the project. Since we are only using new source files in this project,click Next. Finally, a confirmation dialog box will appear. Click Finish if the information iscorrect.

3 Using the HDL Editor for VHDL

We are now ready to start working with the HDL Editor.

1. The VHDL editor window should show the following code:

library IEEE;use IEEE.STD LOGIC 1164.ALL;use IEEE.STD LOGIC ARITH.ALL;use IEEE.STD LOGIC UNSIGNED.ALL;

– Uncomment the following lines to use the declarations that are– provided for instantiating Xilinx primitive components.–library UNISIM;–use UNISIM.VComponents.all;

entity MyAdder isPort ( A : in std logic;

B : in std logic;CI : in std logic;CO : out std logic;S : out std logic);

end MyAdder;

architecture Behavioral of MyAdder is

begin

end Behavioral;

2. Between begin and end Behavioral add the following lines:

S <= ((A xor B) xor CI);

CO <= ((A and B) or (CI and (A xor B)));

3. We must now check that the syntax of the VHDL code is correct. In the Project Navigator

window highlight the VHDL source in the Sources in Project pane. Expand ifit is not already and double click A process will be spawned to verify the VHDLcode for syntax errors.

• If there are none, a green check mark will appear next to the Check Syntax process.

• If errors where found, A red cross will appear next to the Check Syntax process. Theerrors will be listed in the Errors tab of the transcript window located at the bottom of

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the Project Navigator window. In it you will see a listing of the errors and the lines onwhich they occur. If you double click on an error message a red dot will appear in theVHDL editor pane next to (or close to) the line where the error was found.

4. Once you have eliminated all of the errors, save your work.

5. Next, we will assign the pins in our design to actual pins on the FPGA.

4 Creating a UCF file

A User Constraint File (UCF) is used to assign I/O pins in a design to the actual pins on theFPGA.

Please refer to Appendix B for more information.

1. Highlight and right-click on the VHDL source in the Sources in Project pane of the ProjectNavigator and select New Source... from the floating menu.

2. From the list of file types select Implementation Constraints File. Name the file ”MyAd-der” and click Next.

3. The next dialog box is used to associate the UCF file with a specific source file. There is onlyone source file in the project, ”MyAdder.vhd”, so click Next.

4. The final dialog box is for confirming the information input in the previous dialog boxes. ClickFinish if the information is correct.

5. In the Sources in Project pane ensure ”MyAdder.ucf” is highlighted and in the Processesfor Source pane click on the ”+” in to expand the section and double clickEdit Constraints (Text) in the list.

6. The UCF file has the following format:

NET <pin name in VHDL design> LOC=P<pin number on FPGA>

NOTE: Make sure to use upper case letters for the pin names.

7. Let us assign the inputs to the dips switches on the FPGA and the outputs to the LEDs.Please refer to the DIO1 board schematic for more information about pin connections. Wewill make CI switch 1, A switch 2, B switch 3, S LED 1 and CO LED 2.

—Design pin —FPGA pin —DescriptionCI 126 SW8A 129 SW7B 133 SW6S 154 LED8

CO 161 LED7

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8. Enter the following code:NET CI LOC=P126;NET A LOC=P129;NET B LOC=P133;NET S LOC=P154;NET CO LOC=P161;

5 Compiling the design

1. Now go back to the Project Navigator window. Highlight the VHDL source in the Sources inProject pane and double click in the Processes for Source pane to synthesizethe design

2. When the synthesis stage has completed, double click to implement the design.When the implementation process has completed a yellow exclaimation mark will appear.This can be safely ignored.

3. Finally, double click to generate the programming file that will be downloadedto the FPGA. It is possible to go straight to generating the programming file, and the Project

Navigator will determine which of the previous step need to be run to produce an up to dateprogramming file.

6 Downloading the design to the FPGA

Downloading a file to the FPGA is accomplished through the iMPACT tool.Please check Appendix A for setting up the DE2 and DIO1 boards before downloading the

desing on the FPGA board.

1. Select

2. Double click in the Processes pane to start the iIMPACT tool.

3. In the Configure Devices dialog box that appears verify the Boundary-Scan Mode radiobutton is selected and click Next.

4. In the next dialog box ensure the Automatically connect to cable and identify Boundary-Scan chain radio button is selected and click Finish.

5. A message window titled Boundary-Scan Chain Contents Summary will appear stating iMPACTwill ask for the desired programming file. Click OK.

6. In the Assign New Configuration File dialog box select “MyAdder.bit” and click Open.

7. A message box will appear with a warning that the BIT file is for a different device than wasfound in the boundary scan. This can be safely ignored. Click Yes.

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8. Another warning will appear stating that the Startup Clock has been changed to ’JtagClk’ inthe bitstream. Click OK.

9. Move the cursor over the device that appears in the Boundary-Scan tab and press the leftmouse button and select Program....

10. In the Program Options dialog box that appears verify none of the options are selected andclick OK.

7 Testing the design

Depending on the state of the inputs, you may or may not see some of the LEDs on the bargraphdisplay glowing. We have assigned our Sum bit to LEDs LD1. The carry-out bit (C) is displayedon LED LD2.

We are using the slide switches for our A and B inputs. The A inputs is assigned to SW switch1. The B input is assigned to SW switch 2 Moving a switch to the ON position puts a 1 on theinput. Moving a switch to the OFF position puts a 0 on the input.Try different combinations of inputs and verify that the circuit is working correctly.

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8 Appendix A - Setting up the D2E and DIO1 Boards

This is intended to allow the student to quickly set up the D2E board with the DIO1 board forthis tutorial. It does not attempt to explain the configuration and is in no way a substitute for thedocumentation provided with the two boards. It will allow you to use the slide switches as inputand the LEDs as outputs.

1. Ensure that the slide switch located next to the DB25 connector is in the JTAG position.

2. Connect the parallel cable to the D2E board.

3. Ask your lab instructor to verify your jumper settings before applying power to the board.

4. Plug the 9V DC center positive adapter into the D2E board. A small red LED labeled LED2

should glow.

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9 Appendix B - User Constrained File (UCF)

A User Constraint File (UCF) is used to assign I/O pins in a design to the actual pins on theFPGA.

The UCF file has the following format:

NET <pin name in VHDL design> LOC=P<pin number on FPGA>

9.1 LEDs

The Digilent DIO1 Board provides a series of eight LEDs (LD1–LD8) and four multiplexed 7-segment displays (DSP1) for use by a Digilent 2E FPGA Board. All of these LEDs are Largeactive high meaning that an LED segment will glow when a logic-high is applied to it. Thefollowing tables show the connection from the Digilent 2E Board to the LEDs on the DIO1 Boardexpressed as UCF constraints.

—Description —LocationNET SEGA LOC=P127NET SEGB LOC=P132NET SEGC LOC=P134NET SEGD LOC=P136NET SEGE LOC=P139NET SEGF LOC=P141NET SEGG LOC=P146NET SEGDP LOC=P148

Table 1: Connections between DIO1 7-Segment display and Digilent 2E

—Description —LocationNET LD < 1 > LOC=P154NET LD < 2 > LOC=P161NET LD < 3 > LOC=P163NET LD < 4 > LOC=P165NET LD < 5 > LOC=P167NET LD < 6 > LOC=P169NET LD < 7 > LOC=P174NET LD < 8 > LOC=P176

Table 2: Connections between the DIO1 LEDs and Digilent 2E

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—Description —LocationNET SW < 1 > LOC=P126NET SW < 2 > LOC=P129NET SW < 3 > LOC=P133NET SW < 4 > LOC=P135NET SW < 5 > LOC=P138NET SW < 6 > LOC=P140NET SW < 7 > LOC=P145NET SW < 8 > LOC=P147

Table 3: Connections between the DIO1 slide switches and Digilent 2E

—Description —LocationNET BTN < 1 > LOC=P149NET BTN < 2 > LOC=P150NET BTN < 3 > LOC=P151NET BTN < 4 > LOC=P152NET BTN < 5 > LOC=P178

Table 4: Connections between the DIO1 pushbuttons and Digilent 2E

9.2 Switches

The DIO1 has bank of eight slide switches and five pushbuttons (labeled BTN1 through BTN5)that are accessible from an Digilent 2E Board.

When closed or ON, each DIP switch pulls the connected pin of the D2E Board to ground.When the DIP switch is open or OFF, the pin is pulled high through a 10KΩ resistor.

When pressed, each pushbutton pulls the connected pin of the D2E Board to ground. Otherwise,the pin is pulled high through a 10KΩ resistor. The table below show the connections from theDigilent D2E Board to the switches on the Digilent IO1 Board expressed as UCF constraints.

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