Tutorial at the European Nanoelectronics Applications, Design & Technology Conference 2016

Electronic System Modeling, Analysis and Design beyond Moore’s Law: A proposalDesign beyond Moore s Law: A proposal

Eugenio VillarSchedulablity

Analysis Simulation

VerificationReusability

Embedded Systems LabUniversity of Cantabria

Spain

Performance AnalysisOptimization

Reusability

pDesign-Space

ExplorationArchitectural

Mapping HWSynthesis

SWSynthesis

AgendaAgenda

M ti ti & I t d ti Motivation & Introduction

Contrex Modeling Methodology Contrex Modeling Methodology

Single-Source Design Approach Performance analysis SW Synthesis

System Design beyond Moore’s Law

Conclusions

June 20, 2016 2Nanoelectronics, Applications, Design & Technology Conference

AgendaAgenda





Conclusions


MotivationMotivation

D i d ti it Design productivity gapMore powerful design technologies

I i th b t ti l l Increasing the abstraction level Increasing reusability


MotivationMotivation

D i d ti itH-MPSoC

Design productivity gap??

C/C++OpenCL/MPC/C++

MPSoC

SoC

UMLC/C++

OpenCL/MP

ASIC

pSystemCVerilog

C/C++SystemCVerilogC/C++

Verilog

SoC pSystemCVerilog

Verilog MappingSW SynthesisCompilation

HW/SW CoDesignCompilation

Verilog

CompilationRTLSynthesis…

CompilationBehavioral Synthesis…

CompilationBehavioral Synthesis…

CompilationRTLSynthesis…


IntroductionIntroduction

M d l D i D i (MDD) Model-Driven Design (MDD) High-abstraction levelMature SW engineering methodology

State-of-the-ArtMatlab-Simulink

Proprietary, only one MoC, M languagey y g g

Co-Fluent Proprietary, a few MoCs, C language

Ptolemy II Academic, any MoC, C/C++ inside a Java block

…June 20, 2016 6Nanoelectronics, Applications, Design & Technology Conference


UML UML Standard, any MoC, any language Natural way to capture system architecture

M A

B

M A

Semantics lacks

Domain-specific profiles

N2 BN1

p p

MetaMorph OpenSource any MoC any (skeleton) OpenSource, any MoC, any (skeleton)



UML UML UMLUMLUMLHPC DSLs

UMLDC DSLs

UMLES DSLs

UMLSmartPhone

DSLs

ForTran,…Python,…

MPI,…

Java,…MPI,…

ADA,…C/C++,…MCAPI,…

HTML5,…Java,…

, ,



MARTE MARTE Standard UML profile for real-time embedded

tsystems Platform-Independent Model (PIM) Platform Description Model (PDM) Platform Description Model (PDM) Platform-Specific Model (PSM)

Rich semantics content S h d l bilit Rich semantics content Single-source approach

SchedulabilityAnalysis Simulation

VerificationReusability

Performance Analysis

Design-SpaceArchitectural

Optimization

Design Space Exploration

Architectural Mapping HW

SynthesisSW

Synthesis


AgendaAgenda





Conclusions


CONTREX Modeling MethodologyCONTREX Modeling Methodology

M i f t Main featuresMDD support Component-Based Engineering approach SW centric Standard

MARTE profile

Supporting Mixed-Criticality Modeling Supporting Design-Space Exploration

System Performance Analysis SW Synthesis


CONTREX Modeling Methodology

A hit t l D i

CONTREX Modeling Methodology

Architectural Design

Code reuse and/or developmentp platform independent

HW/SW platform

Architectural mapping Architectural mapping



Mi d C iti lit Cl i l h Mixed-Criticality: Classical approachData Flight

CCameraC t l Logging

Mining

P di t bl P f

Control Control Logging

Platform

Predictable Performance



Mi d C iti lit h Mixed-Criticality approachData Flight

CCameraC t l Logging

Mining Control Control Logging

Predictable Performance

Low-Cost



Mi d C iti lit Mixed-Criticality

Mixed-Criticality Application

Sh dSharedResources



C iti lit Criticality Integer Level of importance

Functional & Extra-Functional Requirements

Implications on analysis and development

In-lined with usual definitions Level of assurance against failure [Burns&Davis, 2015]g Safety Standards

IEC/EN 61508 (SIL) DO-178B ISO 26262 (ASIL)



C iti lit f A li ti C t Criticality of Application Components For imposing conditions on the software development Associate criticality to all the related constraints and sub-

components



C iti lit f Pl tf C t Criticality of Platform Components HW constraints derived from the criticality level

Imposing conditions on the hardware development Coherence of application to platform component mapping



D i S E l ti Design Space Exploration A single model for describing the Design Space DSE parameters: declared as VSL expressions

within an attribute oft d l ti

Through a constraint associateda component declaration to a component instance



D i S E l ti Design Space ExplorationMapping Exploration



D i S Design Space a N-dimensional cube (36 = 729)



DSE l DSE rules Constrain the N-dimensional cube


AgendaAgenda





Conclusions



P bl St t t


Problem Statement Fast Simulation &

Performance Analysisbefore full SWDevelopment

Native Simulation Host-Compiled Host Compiled



N ti Si l ti


Native Simulation…Overflow = 0;

Global variableint Sim_Time = 0;

TB() is a function of# of binary instructionstype of instructions# f h i

;s = 1L;for (i = 0; i < L_subfr; i++) {

Carry = 0; s L macNs(s xn[i] y1[i]);

Sim_Time += TB();# of cache missesfrequency

evens = L_macNs(s, xn[i], y1[i]);if (Overflow != 0) {

break; }}if (Overflow == 0) {

Sim_Time += TB();Sim_Time += TB();

evendata dependencies

( ) {exp_xy = norm_l(s);if (exp_xy<=0)

xy = round(L_shr (s, -exp_xy));else

Sim_Time += TB();

Sim Time += TB();

TSYS() is a function ofpreemptions

elsexy = round(L_shl (s, exp_xy)); }

mutex_lock(mutex_name);…

_ B();

Sim_Time += TB(); wait included

Sim Time += T ();

conflicts in the bus

Sim_Time += TSYS();


SW SynthesisSW Synthesis

F ti l th i Functional synthesis ‘main’ functions DSP

optimized C code

OpenCL/GL code for

GPU

Platform-Independent

C code

Static concurrency Platform-Specific code

C codeGPUC code

Optimized C code for DSPs OpenCL/GL for GPUs C/C++ & OpenMP for SMPs

C3

C/C++ & OpenMP for SMPs…Memory Space

OS GPUGPUSMPnode

DSP

Communication Infrastructure


SW SynthesisSW Synthesis

C i ti th i Communication synthesis Architectural mapping

Memory space OS Processing node Processing node

Benefits / Drawbacks Benefits / Drawbacks Communication Speed Memory protection Memory/cache use Scheduling

P ll li Parallelism…


AgendaAgenda





Conclusions


System Design beyond Moore’s LawSystem Design beyond Moore s Law

M ’ L i i Moore’s Law is passing away Long live to Moore’s Law! No party lasts forever



Th t h ld ti The party should continue Equivalent scaling => Vertical nanowires =>

Graphene =>Quantum computing =>…

Pragmatic position opens competitive advantages in new technologies =>p p g g


System Design beyond Moore’s LawSystem Design beyond Moore s LawDesign Automation Tools

El t i V l Ch i‘Fabless’ Chip DesignIP Provider

Today Electronics Value Chain

Silicon FoundrySemiconductor Equipment Manufacturer

Integrated Device Manufacturer (IDM)

Original Design Manufacturer (ODM)

Electronic Manufacturing Services (EMS) Original Equipment Manufacturer (OEM)

Service ProviderRetail SW Provider

Industrial End User Consumer End User


System Design beyond Moore’s LawSystem Design beyond Moore s LawDesign Automation Tools

El t i V l Ch i‘Fabless’ Chip DesignIP Provider

Electronics Value Chain Tomorrow

Silicon FoundrySemiconductor Equipment Manufacturer

Integrated Device Manufacturer (IDM)

Original Design Manufacturer (ODM)

Electronic Manufacturing Services (EMS) Original Equipment Manufacturer (OEM)

Service ProviderRetail SW Provider

Industrial End User Consumer End User



I t l i t t i li ti Intel investment in applicationsWearables, drones…

Google & Microsoft investing in HWGoogle X CatapultGoogle X, Catapult…

The end of technological obsolescence?



P i th I t t f E thi Programming the Internet of Everything Services provided on computing platforms of many kind




S iUML

HPC DSLsUML

DC DSLsUML

ES DSLs

UMLSmartPhone

DSLs

Service

ForTran J HTML5

DSLs

ForTran,…Python,…

MPI,…

Java,…MPI,…

C/C++,…MCAPI,…

HTML5,…Java,…




Schedulability SForTran,

Python, Java, HTML5

ConcernsPerformance, safety, cost,

security size

SchedulabilityAnalysis Simulation

Verification

P fD i S

Optimization

ServiceUML

CPSoS DSL

HWSW (RT)OSCorba TCT/IP

HTML5, C/C++,…

security, size,… Performance

AnalysisDesign-Space

ExplorationCPSoS DSL

SynthesisSynthesis(RT)OS,

Runtime,…Corba, TCT/IP, MPI, MCAPI,…


AgendaAgenda





Conclusions


ConclusionsConclusions

C t UML/MARTE M d li M th d l Contrex UML/MARTE Modeling Methodology Reusability Component-Based Engineering approach SW centric

DSE-oriented Supporting Mixed-Criticality Design Performance Analysis SW synthesis

Powerful Single-Source approachJune 20, 2016 38Nanoelectronics, Applications, Design & Technology Conference

ConclusionsConclusions

CPS S th i i ti CPSoS as the main innovation area

Holistic, single-source approach to CPSoS Design Services over the IoE

Understanding complex interactions among devices Facing heterogeneity Detecting emergent behaviors

Adapted to the human behavior Adapted to the human behavior

Design framework beyond Moore’s Lawg y


Tutorial at the European Nanoelectronics Applications, Design & Technology Conference 2016

Technology

Transcript of Tutorial at the European Nanoelectronics Applications, Design & Technology Conference 2016