UNIVERSITI TEKNIKAL MALAYSIA MELAKAFAKULTI KEJURUTERAAN ELEKTRONIK & KEJURUTERAAN KOMPUTERBENM 1143: LOGIC CIRCUITTUTORIAL 5 (SOLUTION)

1. The invalid state of an S-R latch occurs when the input of S and R is S =1 and R=1.

2. A J-K flip-flop is in the toggle condition when the input of J and K is J =1 and K=1.

3. Write the truth table of negative edge triggered S-R flip-flop and J-K flip-flop.

S-R Flip-flop Truth TableCSRQQComments00QQHold0101Reset1010Set11XXInvalid

J-K Flip-flop Truth TableCJKQQComments00QQHold0101Reset1010Set1111Toggle

4. If the waveforms in figure 4 are applied to an active-LOW input S-R latch, draw the resulting Q output waveforms in relation to the inputs. Assume that Q starts LOW.

5. For a gated S-R latch, determine the Q and Q outputs for the inputs in figure 5. Assume Q starts LOW.

6. For a gated D latch, the waveforms shown in figure 6 are observed on its inputs. Draw timing diagram showing the output waveform you would expect to see at Q if the latch is initial RESET.

7. For a positive edge-triggered J-K flip-flop with inputs as shown in figure 7 determine the Q output relative to the clock. Assume that Q starts LOW.

8. Two edge triggered S-R flip-flop are shown in figure 7. If the inputs are as shown, draw the Q outputs of each flip-flop relative to the clock, and explain the difference between the two. The flip-flops are initially RESET.

9. The circuit of Figure 9 (a) contains a D latch and two T flip-flop. Complete the timing diagram at Figure 9 (b) by drawing the waveform of signals Q0, Q1 and Q2. Assume that Q0, Q1, and Q2 are initially RESET.

10. The circuit of Figure 10 contains a D latch, a positive-edge-triggered and a negative edge-triggered D flip-flop. Sketch the waveform of signals y1, y2 and y3.

xClocky1y2y3

FKEKK-BENM 1143[11/12]4 | Page2

S

EN

R

Q

EN

D

Q

CLK

J

K

Q

CLK

S

R

Q

Q

Positive edge triggered

Negative edge triggered

CLK

Z

Q0

Q1

Q2

J

Q

Q

K

J

S

R

K

S

R

Q

Q

D

C

J

D

K

S

Q

Q

D

clock

x

y1

y2

y3

C

C

S

R

Q