[TUT] IAR Embedded Workbench.pdf

5/25/2018 [TUT] IAR Embedded Workbench.pdf

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Copyright by [Trc en, virus_lazy, hacker_black_hat] http://dtvt.org/

CHNG TRNH SON THO, BIN DCH V NPCHO MSP430

1. Gii thiu v MSP430FG4618/F2013 Experimenters Board:1.1. MSP430FG4618/F2013 Experimenters Board:

KIT MSP-EXP430FG4618 gm 1 Board MSP430FG4618/F2013 nh hnh div 2 pin AAA 1.5V.

Hnh 1.1: MSP430FG4618/F2013 Experimenters Board


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S khi ca Board MSP430FG4618/F2013 nh sau:

Hnh 1.2: S khi ca MSP430FG4618/F2013 Experimenters Board


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bi th nghim ny chng ta stm hiu 2 thnh phn ca chip MSP430FG4618 lI/O port v LCD_A (module iu khin LCD c tch hp sn trn KIT)

Cc dng chip MSP430 l low power nn n hot ng ngun kh thp t1.8V-3.6V.cc KIT ca TI, thng thng dng ngun 3.5V (c chuyn i tngun 5V tcng

USB)1.2. Cc khi chc nng chnh trn boad:1.2.1. Interfaces:

4mux LCD display:Bhin th4mux SoftBaugh LCD SBLCDA4 giao tip vi driver ngoi vi LCD

ca MSP430FG4618.

MometaryOn Push Buttons:2 nt nhn S1 v S2 c kt ni vi I/O port P1 ca MSP430FG4618.

Light Emitting Diodes (LEDs):MSP430FG4618/F2013 Experimenters Board c tt c 4 LEDs. Trong , 3

LEDs c ni vi MSP430FG4618 v 1 LED ni vi MSP430F2013.

3 led ni vi MSP430FG4618 qua chn P2.1, P2.2 vP5.1


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Buzzer:Buzzer c ni vi digital I/O port ca MSP430FG4618, c thngt kt ni bng

jump JP1.

Capacitive Touch Pad :Touchpad c dng s 4 nm trn board c kt ni n cc I/O port ca

MSP430F2013, gm c 16 segments.

JTAG Interfaces:2 header JTAG c sn trn board gm:

- 4-wire JTAG cho MSP430FG4618- 2-wire Spi-Bi-wire cho MSP430F2013

1.2.2. Communication Peripherals: Wireless:

Module giao tip wireless c kt ni vi ch truyn USART caMSP430FG4618 v c cu hnh bi giao thc SPI, htrcc board CCxxxxEMK caTI. CC2420EMK dng chun 802.15.4/Zigbee. CC1100EMK c cu hnh lm victn ssng mang RF 868 MHz. CC2500EMK/CC2420EMK c cu hnh lm victn ssng mang RF 2.4 GHz.

RS232:MSP430FG4618 htrgiao tip ni tip vi PC dng chun RS232 (9pins),

giao tip thng qua ngoi vi USCI, cu hnh bi chtruyn UART.

I2C/SPI:MSP430FG4618 v MSP430F2013 h trcc giao thc I2C v SPI, sdng cc

ngoi vi USCI v USI.


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1.2.3. Analog Signal Chain:

Hnh 1.3: Analog Signal Chain

Microphone:Microphone c kt ni vi MSP430FG4618, c thenable hoc disable thng

qua 1 port kt ni.

Analog Filter:Blc thng cao tch cc bc 1 (1st-order active High-pass filter HPF) vi tn s

ct khong 340Hz c thlc bcc tn scc thp tmicrophone. Blc thng thp tchcc bc 2 Sallen-Key (2nd-order Sallen-Key active Low-pass filter LPF) vi tn sct c4kHz loi bcc nhiu tn scao ng ra analog ca bchuyn i DAC.


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Hnh 1.4: Active Analog Filter Setup

Analog Output:Sdng jack n 3.5 mm ly tn hiu analog ng ra c kt ni vi Op-Amp

OA2 tch hp trn board. u vo ca Op-Amp c ly tu ra ca bDAC12 caMSP430FG4618.


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2. Cch kt ni bKIT vi mch np v mch np vi my tnh.-Kt ni KIT vi mch np nh hnh (kt ni mch np vi KIT qua cng

JTAG1):


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Thay i cc Jump trn mch:

Trn mch np, led xanh (Power) bo hiu ngun, led (Mode) bo hiu khimch c np.


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3. Trnh son tho v bin dchDownload IAR Embedded Workbench 5.3 ti:

http://www-s.ti.com/sc/techzip/slac050.zip

Sau khi ci t thnh cng ta khi chy chng trnh (y chnh l trnh son tho, bindch, np v ng thi l debugger cho KIT).

Icon trn desktop

3.1. To project:
http://www-s.ti.com/sc/techzip/slac050.ziphttp://www-s.ti.com/sc/techzip/slac050.ziphttp://www-s.ti.com/sc/techzip/slac050.zip


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Nn to 1 th mc mi qun l ton bproject


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Khi to project thnh cng th IDE shin ra nh hnh:


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IAR stng to mt file main.c v add vo project ca ta, ta sson tho code trn .Ta cng c th add thm file (cc header chng hn) vo project bng cch kch chut

phi vo project > Add > Add Files


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3.2. Ty chn cc thng scho project:


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Chn loi chip ang sdng cho mch l MSP430FG4618


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tab Debugger chn Driver l FET Debugger

Cc thng scc tab khc ginguyn.


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3.3. Bin dch v npSau khi code xong ta tin hnh code v bin dch (v np) bng cch bm Ctrl+D hoc

bm vo biu tng tam gic mu xanh nh hnh:


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Khi bin dch v np thnh cng, ta c th tin hnh debugger trc tip trn mch bngcc Step


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Thng thng ta bqua bc trn (Step) m np thng vo mch bng cch chnRun (nh hnh)

(on code n gin bt led sng, gisled c ni vi cng P1.0 ca chip)

Nh vy ta tin hnh code, bin dch v np thnh cng cho KIT. Nu sau khi np mta thy mch vn cha chy nh mun th c th kim tra li code hoc debug tngStep li test li.


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Ch : y chn Debug chko phi Release


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4. Cu trc mt chng trnh C thng thng cho MSP430

Cc phn trong du c thkhng c

Ch :o Trong hm main ta thng thy dng lnh:

WDTCTL = WDTPW + WDTHOLD;

Stop watchdog timer n khi reset chip. Nu khng c lnh ny (v khng cty chn khc con WDTCTL) th mch skhng hot ng.

o Trong C cho MSP430, th c cc hng s c nh ngha trc ( fileheader), ta rt hay dng cc hng sny:BIT0 = 0000 0001


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BIT1 = 0000 0010

BIT2 = 0000 0100

.

.

.

BIT7 = 1000 0000

o Mt chn ca MSP430 thng c nhiu chc nng, ta mun s dng chcnng g th nh ngha cho n.V d:

P1DIR = 0xFF;// ton bport1 l OutputP1DIR = 0x00;//ton bport1 l Input

Nh vy nu mun mt schn ca port1 l Output v mt schn ca port1 lInput th lm thno? Khng ging mt sVK khc, MSP430 khng cho phpta tc ng trc tip n 1 chn no ring l, chc thtc ng ln port (8 chn).

Nh vy mun tc ng ln chn ring lno th ta dng php ton OR, AND vXOR.

V d:P1DIR |= BIT1; //chn P1.1 sl chn Output, cc chn khc ko bnh hng bilnh ny

P1DIR &= ~BIT1;// chn P1.1 sl chn Input (nu ta ko nh ngha th n mcnh l Input)

P2DIR |= BIT0 + BIT1 + BIT3;//chn P2.0, P2.1, P2.3 sl Output

Lnh trn cng c thvit li: P2DIR |= 0x0B;// BIT0 + BIT1 + BIT3 = 11d=0Bh

P2DIR &= ~(BIT4+BIT5);//P2DIR &=~0x30; //chn P2.4, P2.5 l Input

o Xut ra port theo tng bit ring l.Nh vic nh ngha cc chn, MSP430 cng khng cho ta tc ng trc tip ntng chn no, mun xut ra mt bit hay nhiu bit bt kta sdng cch nh dng vi nh ngha chn.


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V dmun cho P1.1=1, P1.3=1, P2.1=0

P1OUT |= BIT1+BIT3 ; //P1.1=1, P1.3=1

P2OUT &=~ BIT1 ;//P2.1=0

Hoc c tho mt bit chn bt kbng ln XOR ^

P1OUT ^= BIT4 ; //chn P1.4 o trng thi

o Kim tra trng thi mt chn.Ngoi ngt ra ta c thkim tra trng thi mt chn no ang mc thp (0V)hay mc cao (1.8V n 3.6V).

V dkim tra chn P1.2

if( (P1IN&BIT2)==0) //nu chn P1.2 bng 0

//do anythi ng

else

//do anythi ng

// nu vit if( P1IN&BIT2==0), thiu 1 ngoc lsai

CHC CC BN HC TT!

[TUT] IAR Embedded Workbench.pdf

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