DIFFERENTIAL IMPLEMENTATIONS OF THRESHOLD LOGIC GATES V. Beiu 1), J.M. Quintana 2), M.J. Avedilo 2), R. Andonie 3)

1) School of Electrical Engineer and Computer Science, Washington State University Pullman, WA 99164-2752, USA 2) Centro National de Microelectrnica (CNM), Universty of Sevilla, Edificio CICA, Avda. Reina Mercedes s/n, 41012Sevilla, Spain

3) Department of Electronics and Computers, Transilvania University of Braov, Braov 2200, Romania

ABSTRACT 2. CAPACITIVE SOLUTIONS This paper reviews differential implementations of threshold logic gates, detailing two classes of solutions: capacitive (switched capacitor and floating gate), and conductance/current.

The concept underlying capacitive TLGs is the use of an array of capacitors to implement the weighted sum of inputs. The idea was introduced as early as 1966 [6]. Capacitive TLGs can be classified into two major groups: Capacitive Threshold Logic (CTL), and Neuron MOS (MOS). Several comparisons draw the following conclusions:

1. INTRODUCTION Research on neural networks (NNs) goes back sixty years ago. The seminal year for the development of the science of mind was 1943 when McCulloch and Pitts published A Logical Calculus of the Ideas Immanent in Nervous Activity [23], introducing the threshold logic (TL) gate (TLG):

the MOS operation is simpler than that of the CTL; the maximum attainable fan-in by MOS is an order of

magnitude less than that of CTL gate; the delay has a logarithmic dependence with respect to

large fan-ins (fan-in 255 in [25], fan-in 64 in [26]), while for small fan-ins (fan-in 20 [7]) the behaviour looks linear: 1+0.35n (where n is the fan-in);

),,( 1 nxxf K ( )sgn 1 = =ni ii xw (1) both solutions have large power consumptions. where wi is the synaptic weight associated to xi, is the

threshold, and n is the fan-in of the TLG. The general belief that a neuron is a TLG, which fires when some variable reaches a threshold, can be questionable. That is why, the TLG model has been tested on a spike train generated by the Hodgkin-Huxley model with a stochastic input [17]. The result was that the threshold model correctly predicts nearly 90% of the spikes, justifying the description of a neuron as a TLG.

2.1 The Switched Capacitor

Originally introduced in 1987 [34], [35], the main idea was to use switched capacitors, switches and inverters, and to take advantage of the inherent saturation of the inverters to implement the perceptron non-linearity. This approach required a somehow complex three-phase clock. It has quickly evolved into a simpler two-phase clock solution [25], known as the Capacitive Threshold Logic (CTL) gate. Experimental results for CTL gates fabricated in standard-CMOS technologies have shown its proper functionality and its large fan-in capability (up to 255). This feature is due to the auto-offset cancellation technique used in chopper-type CMOS comparators. Their main drawbacks are: large delays and area, DC power consumption, and the threshold programming mechanism.

The tremendous impetus of VLSI technology has made neurocomputer design a really lively research topic. Research on hardware implementations of NNs in general, and TL in particular, has been very active (see [4]). Besides, there are many theoretical complexity results showing that TLCs are more powerful/efficient than classical BCs. These have been a motivation to investigate different VLSI implementations. One important aspect of NNs is their adaptive behaviour, but in this paper we shall focus only on the differential approaches that have been tried for implementing TLGs in silicon. We should also mention here several TLG implementations which have been used commercially: MIPS R2010 [15], SUN Sparc V9 [21], a CMOS fingerprint sensor array [16], and very recently the Itanium 2 microprocessor [24] as well as in 0.18 m CMOS asynchronous circuits operating at 3.34.5 GHz [30]. Because there are many different solutions reported in the literature, we shall try to cover representative differential architectures. Section II is dedicated to capacitive differential solutions, while Section III will detail conductance/current differential ones. In conclusions we comment on their potential, and on future directions of research.

A differential version is the Balanced-CTL (B-CTL) [12], shown in Fig. 1. The requirement for a highly precise reference voltage is eliminated by implementing functions with thresholds equal to 0. The basic structure is formed by two banks of capacitors (A and B). Both banks are connected to a differential amplifier that determines which bank has a larger number of inputs at logic one. That bank has a higher voltage on its common line. One additional half-capacitor unbalances the voltage level at the amplifier inputs in case both banks have an identical number of high-level inputs. B-CTL gates are reported to be faster than CIAL gates [29] (to be described in Section III).

V. Beius is partly sponsored by the Air Force Research Laboratory under agreement number F29601-02-2-0299. The U.S. Government is authorized to reproduce and distribute reprints for Governmental purposes notwithstanding any copyright notation thereon. The views and conclusions contained herein are those of the author and should not be interpreted as necessarily representing the official policies or endorsements, either expressed or implied, of the Air Force Research Laboratory or the U.S. Government.

Figure 4. Charge recycling threshold logic (CRTL) from [8], and self-timed threshold logic (STTL), another asynchronous sense amplifier differential logic with self-timed enable signalling from [9]. Figure 1. Balanced capacitive threshold logic (B-CTL) from [12]. Fig. 4a shows the structure of another TLG called Charge Recycling Threshold Logic (CRTL) gate [8], [10]. The inputs are capacitively coupled onto the floating gate of transistor M5, and the gate voltage of transistor M6 sets the threshold. When E=1 the output voltages are equalized. When E=0, the outputs are disconnected and the differential circuit (M5, M6, M7) draws different currents from OUT and OUT. The sense amplifier increases the difference of potential between OUT and OUT, accelerating the transition. It evaluates if the weighted sum of the inputs is greater or less than the threshold. CRTL gates exhibit high speed, and are suitable for high fan-ins, while also having low power consumption. In fact, CRTL gates achieve the highest speed and 15-20% lower power consumption when compared with clocked MOS [19], C3L [14], and LCTL [1] (to be described in Section III).

2.2 The Neuron MOS Transistor

Neuron-MOS (MOS) TLGs are based on an idea introduced in 1966 [6]. Its integration led to the MOS transistor [30], having a buried floating polysilicon gate and a number of input gates capacitively coupled to the floating gate. The voltage of the floating gate becomes a weighted sum of the voltages on the input gates, controling the current in the transistor channel. The static MOS is very simple and compact, but has DC power consumption. This static power can be eliminated and the speed increased by a current comparison between a MOS transistor and a reference device, using a positive feedback circuit. Many different configurations taking advantage of this concept have been reported [18]. One example is the configuration called sense-amplifier MOS TL [19] (Fig. 2a). It applies a current-controlled latch-sense amplifier circuit to the basic MOS TLG. Variations can be found in [36], [37] (Fig. 2b). They use a solution similar to the digital comparator based on the cross-coupled inverters introduced in [22] (to be described in Section III). In [37], significant speed improvements (100 MHz to 500 MHz) and power savings over the static MOS gate are reported.

A Self-Timed Threshold Logic (STTL) has also been proposed [9]. The self-timing idea comes from asynchronous circuits, one goal being to reduce the power consumed at the chip level by eliminating the demanding clock distribution. The gate is based on the cross-coupled nMOS transistor pair: M3 and M4 (Fig. 4b). Precharge and evaluate are specified by an enable signal: E and E. Two current mirrors M8M1 and M9M2 are used. Because the capacitances of node A and B have to be matched, the two buffering inverters have to be identically sized. The enable signals are asynchronously passed to the next stage. This is a low power solution, which eliminates the clock at the expense of a double-rail signalling and the additional enable generate block.

3. CONDUCTANCE SOLUTIONS The differential TLG implementations in the current/conductance category have in common two parallel-connected sets of nMOS transistors implementing the weighting operation, and a current CMOS comparator for the threshold operation. Here again, the main advantage thought after is their low power consumption.

Figure 2. Dynamic latched-sense-amplifier (comparator) neuron MOS from [19].

Another variation, called CMOS Capacitor Coupling Logic (C3L), uses the capacitor coupling technique and a current sense amplifier [14] (Fig. 3). Although these circuits do not have an offset cancellation mechanism, fluctuation in device parameters can be compensated by the differential configuration.

The operation of Cross-coupled Inverters with Asymmetrical Loads (CIAL) was exploited to implement digital (bus) comparators [22], a particular TLG (see Fig. 5a). At the same time, a generic Latch-type TLG (LCTL) was proposed in [1] (Fig. 5b). Its consists of a CMOS current-controlled latch (M2/M5 and M7/M10) providing both the output and its complement, and two input arrays (M41M4n) and (M91M9n) having an equal number of parallel input transistors. Transistor pairs M1/M3 and M6/M8 specify the precharge or evaluate phase, and transistors M4n+1/M9n+1 guarantee correct operation. Precharging occurs when the reset signal R=0. M1 and M6 are on, while M3 and M8 off, and OUT=OUT=1. Evaluation begins when R=1. M1 and M6 are turned off, while M3 and M8

Figure 3. CMOS capacitor coupling logic (C3L) from [14].

Figure 6. Single input current-sensing differential logic (SCSDL) form [32], [33].

Figure 5. Digital comparators based on clocked cross-coupled inverters with asymmetrical load (CIAL) from [22]; latch type low power threshold logic (LCTL) from [1]; (CIAL-TL) from [29]; and the differential implementation from [28].

These TLGs based on current comparisons are relatively sensitive to noise and mismatch of process parameters. Reliability can be improved by known layout and circuits techniques where the devices behaviour is matched: substrate voltage control, shield and isolations, centroid layout of transistors (same orientation and size) for reducing statistical parameter variations, symmetrical layout. Yield analysis for SCSDL in 0.35 m CMOS has showed that fan-in 14 [33].

are turned on, and nodes OUT and OUT begin to be discharged. Depending on inputs, one of the paths will sink more current than the other. This accelerates the falling of its corresponding output voltage. When the output node of the path with the highest current value falls below the threshold voltage (of either M5 or M10), it turns it off, fixing the latch. Supply current only flows during transitions and, consequently this TLG does not consume static power.

Finally, a solution bridging the gap between capacitive and conductance implementations has also been proposed [11] (Fig. 7b). The key computational concept is to use a floating-gate device as a programmable-switched conductance. By storing one analogue value as the threshold of a floating gate device, and applying a second digital value on the gate of the device, the conductance can be either zero or a pre-programmed analogue value representing the weights associated to each input. Two parallel Flash-EEPROM banks implement: the weighted sum of inputs with positive weights, and the weighted sum of inputs with negative weights. The rest of the circuit, called the conductance comparator, measures the conductance based on the current through the memory cells. The precision to which the threshold of a floating gate can be programmed determines the bit equivalent precision of the weights.

The speed performance of LCTL is improved by the solution proposed in [29] where the nMOS banks are external to the latch (Fig. 5c), avoiding the large/long feedback chain. It is called Cross-couple Inverters with Asymmetrical Loads Threshold Logic (CIALTL). Note that, in spite of having identical names, the circuit topologies in [29] and [22] are different. In this gate, the input transistor arrays (MxiMyi, i = 1, , n) are connected directly to the latchs output nodes, and precharging occurs when 1 and 2 are at logic 0, putting nodes D, OUT and OUT at logic 1. For the evaluation phase, both 1 and 2 are at logic 1, but 2 must return to a low level before 1 in order to allow the latch to switch. CIALTL needs two control signals, which have to be obtained from a clock. The circuit arrangement for realizing logic elements that can be represented by threshold value equations patented by Prange et al. [28] is a simplified version of CIAL (Fig. 5d).

More recently, a number of TLGs based on advanced CMOS differential logic structures have been proposed. Examples are: Single Input Current-Sensing Differential Logic

(SCSDL) [32], [33]. Fig. 6 shows its schematic for a generic pull-down tree and the circuit structure for an n-input MAJORITY gate.

Figure 7. Differential current-switch threshold logic (DCSTL) from [27], and conductance sensing using floating gates for the inputs from [11]. Differential Current-Switch Threshold Logic (DCSTL)

[27] (Fig. 7a), which restricts the voltage swing of the internal nodes for lowering the power consumption. Experiments have shown that DCSTL exhibits better power-delay product than LCTL [1] and CIALTL [29].

All the solutions detailed above either compare the sum of weights with a threshold [28], [32], [33], [26], [36], [37], or compare two weighted sums [1], [22], [27], [29]. For the second case, additional transistors are needed to differentiate the case when the two weighted sums are equal. A better alternative is to implement the function f with one bank, while implementing f with the other. These have transitions in opposite directions, leading to increased speed and better noise margins [2]. A differential solution using this idea is the Split-Precharge Differential Noise Immune Threshold Logic (SPD-NTL) gate recently reported [3], [20], and presented in the next figure.

Current-Mode Threshold Logic (CMTL) [5] also uses two banks of parallel transistor for inputs and threshold followed by sensing. Low power is achieve by limiting the voltage swing on interconnects and the internal nodes of the CMTL gates. Variations are: Discharged CMTL (DCMTL), and Equalized CMTL (ECMTL).

[15] Johnson M.G. A symmetric CMOS NOR gate for high-speed applications. IEEE J. Solid-State Circuits, 23(10):12331236, Oct. 1988.

[16] Jung S., Thewes R., Scheiter T., Goser K.F., Weber W. A low-power and high-performance CMOS fingerprint sensing and encoding architecture. IEEE J. Solid-State Circuits, 34(7):978984, Jul. 1999.

[17] Kistler W.M., Gerstner W., van Hemmen J.L. Reduction of the Hodgkin-Huxley equations to a single-variable threshold model. Neural Computation, 9(5):10151045, 1997.

Figure 8. Split-Precharge Differential Noise Immune Threshold Logic (SPD-NTL) gate from [3]. [18] Kotani K., Shibata T., Imai M., Ohmi T. Clocked-neuron-MOS

logic circuits employing auto-threshold-adjustment. Proc. ISSCC95, San Francisco, 1995, pp. 320321, 388. 4. CONCLUSIONS

[19] Kotani K., Shibata T., Imai M., Ohmi T. Clocked-controlled neuron-MOS logic gates. IEEE Trans. Circuits Syst. II, 45(4): 518522, April 1998.

The present state-of-the-art of shows a large variety of differential TLGs. Some are quite advanced, and have allowed for drastically reducing the dissipated power. Fast and low-power TLGs are therefore implementable, the major differences between one solution and another being the power-delay tradeoffs. The other design parameter to consider is the fan-in. Only a few solutions allow for really large fan-ins, the majority being somehow limited. It is to be expected that the new developments presented would make differential TLGs even more attractive [13], [20], [2], [3].

[20] Lee J., Park J., Song B., Kim W. Split-level precharge differential logic: a new type of high-speed charge-recycling differential logic. IEEE J. Solid-State Circuits, 36(8):12761280, Aug. 2001.

[21] Lev L.A. Fast static cascode logic gate, U.S. Patent 5438283, Aug. 1, 1995.

[22] Lpez J.A.H., Tejero J.G., Ramos J.F., Bohrquez A.G., New types of digital comparators. Proc. ISCAS95, Seattle, vol. 1, 1995, pp. 2932.

[23] McCulloch W., Pitts W. A logical calculus of the ideas immanent in nervous activity. Bull. Math. Biophysiol., 5:115133, 1943. [24] Naffziger S.D., Colon-Bonet G., Fischer T., Reidlinger R., Sullivan T.J., Grutkowski T. The implementation of the Itanium 2 microprocessor. IEEE J. Solid-State Circuits, 37:14481460, Nov. 2002.

5. REFERENCES [1] Avellido M.J., Quintana J.M., Rueda A., Jimnez E. A low-power

CMOS threshold-gate. Electron. Lett., 31:21572159, Dec. 1995. [25] zdemir H., A. Kepkep, B. Pamir, Y. Leblebici, U. ilingirolu, A

capacitive threshold-logic gate. IEEE J. Solid-State Circuits, 31:11411150, Aug. 1996. [2] Beiu V. Low-Power Differential Conductance-Based Logic Gate

and Method of Operation Thereof. US Patent application US/09/667,312, allowed on February 17, in press, 2003.

[26] Pdure M., Dan C., Coofan S., Bodea M., Vassiliadis S. Capacitive threshold logic: a designer perspective. Proc. CAS99, Sinaia, 1999, vol. 1, pp. 8184. [3] Beiu V., Tatapudi S. Split-Precharge Differential Noise-Immune

Threshold Logic Gate (SPD-NTL). Proc. IWANN03, Menorca, in press, Jun. 2003.

[27] Pdure M., Coofan S., Dan C., Bodea M., Vassiliadis S. A new latch-based threshold logic family. Proc. CAS01, Sinaia, 2001, vol. 2, pp. 531534. [4] Beiu V., Quintana J.M., Avedillo M.J. VLSI implementation of

threshold logic: a comprehensive survey. IEEE Trans. Neural Networks, 14(5), in press, Sep. 2003.

[28] Prange S., Thewes R., Wohlrab E., Weber W. Circuit arrangement for realizing logic elements that can be represented by threshold value equations. U.S. Patent 5991789, Nov. 23, 1999. [5] Bobba S., Hajj I.N., Current-mode threshold logic gates. Proc.

ICCD2000, Austin, 2000, pp. 235240. [29] Ramos J.F., Lpez J.A.H., Martn M.J., Tejero J.C., Bohrquez A.G. A threshold logic gate based on clocked coupled inverters. Intl. J. Electronics, 84:371382, Apr. 1998.

[6] Burns J.R., Trenton N.J., Powlus R.A. Threshold circuit utilizing field effect transistors. U.S. Patent 3260863, Jul. 12, 1966.

[7] Celinski P., Al-Sarawi S., Abbott D. Delay analysis of neuron-MOS and capacitive threshold-logic. Proc. ICECS2000, Beirut, 2000, vol. 2, pp. 932935.

[30] Schuster S.E., Cook P.W. Low-power synchronous-to-asyn-chronous-to-synchronous interlocked pipelined CMOS circuits operating at 3.34.5 GHz. IEEE J. Solid-State Circuits, 38(4): 622630, Apr. 1996 [8] Celinski P., Lpez J.F., Al-Sarawi S., Abbott D. Low power, high

speed, charge recycling CMOS threshold logic gate. Electron. Lett., 37(17):10671069, Aug. 2001.

[31] Shibata T., Ohmi T. An intelligent MOS transistor featuring gate-level weighted sum and threshold operations. in IEDM Technical Digest, 1991, pp. 919922. [9] Celinski P., Lpez J.F., Al-Sarawi S., Abbott D. Compact parallel

(m,n) counters based on self-timed threshold logic. Electron. Lett., 38(13):633635, Jun. 2002.

[32] Strandberg R., Yuan J. Single input current-sensing differential Logic (SCSDL). Proc. NORCHIP'99, Oslo, 1999, pp. 328333.

[10] Celinski P., Al-Sarawi S., Abbot D., Lopez J.F. Low depth carry lookahead adder addition using charge recycling threshold logic. Proc. ISCAS2002, Scottsdale, 2002, vol. 1, pp. 469472.

[33] Strandberg R., Yuan J. Single input current-sensing differential logic (SCSDL). Proc. ISCAS2000, Geneva, 2000, vol. 1, pp. 764767.

[11] Fabbrizio V., Raynal F., Mariaud X., Kramer A., Colli G. Low-power, low-voltage conductance mode CMOS analog neuron. Proc. MicroNeuro96, Lausanne, pp. 111115.

[34] Tsividis Y.P. Switched neural networks, U.S. Patent 4873661, Oct. 10, 1989.

[35] Tsividis Y.P., Anastassiou D. Switched-capacitor neural networks, Electron. Lett., 23:958959, 1987. [12] Garca J.L., Ramos J.F., Bohrquez A.G. A balanced capacitive

threshold logic gate. Proc. DCIS2000, Montpellier, 2000 (www.el.uma.es/Ppepefer/DCIS2000.pdf).

[36] Weber W., Prange S., Thewes R., Wohlrab E. A neuron MOS transistor-based multiplier cell. IEDM Technical Digest, 1995, pp. 21.5.121.5.4. [13] Gayles E.S. Data enabled logic circuits. US Patent 6078196, Jun.

20, 2000. [37] W. Weber, S.J. Prange, R. Thewes, E. Wohlrab, A. Luck, On the application of neuron MOS transistor principle for modern VLSI design. IEEE Trans. Electron Devices, 43:17001708, Oct. 1996.

[14] Huang H.Y., Wang T.N. CMOS capacitor coupling logic (C3L) logic circuits. Proc. APASIC 2000, Cheju, 2000, pp. 3336.

INTRODUCTIONCAPACITIVE SOLUTIONSThe Switched CapacitorThe Neuron MOS Transistor

CONDUCTANCE SOLUTIONSCONCLUSIONSREFERENCES