Transmitter - Indico...TUNING SYSTEMFOR XILINX MGT TRANSCEIVERS V. FINOTTI1 †, A. M. CASCADAN1 1...
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T UNING S YSTEM FOR X ILINX MGT T RANSCEIVERS V. F INOTTI 1† , A. M. C ASCADAN 1 1 Núcleo de Computacão Científica, São Paulo State University, São Paulo, Brazil † vfi[email protected] A BSTRACT High speed Serializer-Deserializer interfaces (SerDes) are a recurrent solution for communications in FPGAs, representing an alternative to paral- lel buses running at a lower rate. Although these interfaces save limited input/output resources, high rate communication demands special signal conditioning to overcome noise and interference. Modern FPGAs such as Xilinx Virtex 7 [1] offer SerDes modules called Multi-Giga Transceivers (MGTs). They incorporate the hardware infrastruc- ture required for high speed communication, allowing the user to calibrate the signal conditioning parameters for optimal results in different applica- tions using the Xilinx Vivado Design Suite [2]. The calibration for MGTs communicating between different FPGAs should be performed manually, which is a painful process given the numer- ous parameter combinations. In order to overcome this difficulty, we have developed a tuning system in Python, aiming to automate the tuning process of Xilinx MGT transceivers. GTH T RANSCEIVER The GTH [3] is a MGT transceiver for optical and backplane communi- cation. Performance up to 13.1 Gb/s Support to many industry standard protocols Transmission signal conditioning – Emphasis (TX Diff Swing, Pre-cursor, Post-Cursor) – Equalization (DFE) GTH TXDIFFSWING TXPRE TXPOST 1 0 0 1 1 0 0 1 Data Transmission RXTERM DFE GTH Receiver 1 0 0 1 Transmitter TXDIFFSWING TXPRE TXPOST 1 0 0 1 1 0 0 1 Data Transmission RXTERM DFE GTH Receiver 1 0 0 1 In this simplex transmission between two GTHs, the emphasis happens at transmitter side, while the equalization is done at receiver side. V IVADO & IBERT Xilinx Vivado Design Suite and the Integrated Bit Error Ratio Tester (IB- ERT) IP core are used to evaluate the GTHs performance and calibrate them for a specific application. Only one JTAG chain can be accessed at a time. Tuning must be done manually. [4] Transmitter Receiver TXDIFFSWING TXPRE TXPOST RXTERM DFE LINK STABILITY OPEN AREA Data Transmission Vivado Software Vivado Software User Two Vivado instances must be opened, one for transmitter and one for receiver. The user needs to manually set the parameters for both GTHs, and then test the link performance. T UNING S YSTEM Python scripts interface with Vivado subprocesses. They search for an optimal configuration, changing the tuning parameters and measuring the performance for each case. XilinxTCL.py pyIBERT.py Python Script Transmitter Receiver XilinxTCL.py pyIBERT.py TXDIFFSWING TXPRE TXPOST RXTERM DFE LINK STABILITY OPEN AREA Data Transmission R ESULTS Improvements were observed at the links performance. The figure shows a comparison of the eye scans of one channel before (a) and after tuning (b) Notice the wider opening in the second case. (a) Before tuning (b) After tuning R EFERENCES [1] Xilinx Inc., Virtex-7 FPGA Family https: //www.xilinx.com/products/silicon-devices/fpga/virtex-7.html, Accessed 09 Jan 2017. [2] Xilinx Inc., Vivado Design Suite, https://www.xilinx.com/products/design-tools/vivado.html, Accessed 09 Jan 2017. [3] Xilinx Inc., 7 Series FPGAs GTX/GTH Transceivers - User Guide, https://www.xilinx.com/support/documentation/user_guides/ ug476_7Series_Transceivers.pdf, Accessed 09 Jan 2017. [4] Xilinx Forums, Can I make an IBERT design to test the connection between two boards?, https://forums.xilinx.com/t5/Networking-and-Connectivity/ Can-I-make-an-IBERT-design-to-test-the-connection-between-two/ td-p/383349, Accessed 09 Jan 2017. A CKNOWLEDGEMENTS This material is based upon work supported by the São Paulo Research Foundation (FAPESP) under Grant No. 2013/01907-0 and by funds provided by the cooperation agreement with PADTEC S/A under FUNDUNESP Grant No. 2215/2013.
Transcript of Transmitter - Indico...TUNING SYSTEMFOR XILINX MGT TRANSCEIVERS V. FINOTTI1 †, A. M. CASCADAN1 1...
TUNING SYSTEM FOR XILINX MGTTRANSCEIVERS
V. FINOTTI1 †, A. M. CASCADAN1
1Núcleo de Computacão Científica, São Paulo State University, São Paulo, Brazil† [email protected]
ABSTRACT
High speed Serializer-Deserializer interfaces (SerDes) are a recurrentsolution for communications in FPGAs, representing an alternative to paral-lel buses running at a lower rate. Although these interfaces save limitedinput/output resources, high rate communication demands special signalconditioning to overcome noise and interference.
Modern FPGAs such as Xilinx Virtex 7 [1] offer SerDes modules calledMulti-Giga Transceivers (MGTs). They incorporate the hardware infrastruc-ture required for high speed communication, allowing the user to calibratethe signal conditioning parameters for optimal results in different applica-tions using the Xilinx Vivado Design Suite [2].
The calibration for MGTs communicating between different FPGAsshould be performed manually, which is a painful process given the numer-ous parameter combinations. In order to overcome this difficulty, we havedeveloped a tuning system in Python, aiming to automate the tuning processof Xilinx MGT transceivers.
GTH TRANSCEIVER
The GTH [3] is a MGT transceiver for optical and backplane communi-cation.
Performance up to 13.1 Gb/sSupport to many industry standard protocolsTransmission signal conditioning
– Emphasis (TX Diff Swing, Pre-cursor, Post-Cursor)
– Equalization (DFE)
GTH
TXDIFFSWING
TXPRE
TXPOST
1
0
0
1
1 0 0 1
Data Transmission
RXTERM
DFE
GTH
Receiver
1
0
0
1
Transmitter
TXDIFFSWING
TXPRE
TXPOST
1
0
0
1
1 0 0 1
Data Transmission
RXTERM
DFE
GTH
Receiver
1
0
0
1
In this simplex transmission between two GTHs, the emphasis happensat transmitter side, while the equalization is done at receiver side.
VIVADO & IBERT
Xilinx Vivado Design Suite and the Integrated Bit Error Ratio Tester (IB-ERT) IP core are used to evaluate the GTHs performance and calibratethem for a specific application. Only one JTAG chain can be accessed ata time. Tuning must be done manually. [4]
Transmitter
Receiver
TXDIFFSWING
TXPRE
TXPOST
RXTERM
DFE
LINK STABILITY
OPEN AREA
Data
Tra
nsm
issio
n
Vivado Software
Vivado Software
User
Two Vivado instances must be opened, one for transmitter and one forreceiver. The user needs to manually set the parameters for both GTHs,and then test the link performance.
TUNING SYSTEM
Python scripts interface with Vivado subprocesses. They search for anoptimal configuration, changing the tuning parameters and measuring theperformance for each case.
XilinxTCL.py
pyIBERT.py
Python
Script
Transmitter
Receiver
XilinxTCL.py
pyIBERT.py
TXDIFFSWING
TXPRE
TXPOST
RXTERM
DFE
LINK STABILITY
OPEN AREA
Data
Tra
nsm
issio
n
RESULTS
Improvements were observed at the links performance. The figureshows a comparison of the eye scans of one channel before (a) and aftertuning (b) Notice the wider opening in the second case.
(a) Before tuning
(b) After tuning
REFERENCES
[1] Xilinx Inc., Virtex-7 FPGA Family https://www.xilinx.com/products/silicon-devices/fpga/virtex-7.html,Accessed 09 Jan 2017.
[2] Xilinx Inc., Vivado Design Suite,https://www.xilinx.com/products/design-tools/vivado.html,Accessed 09 Jan 2017.
[3] Xilinx Inc., 7 Series FPGAs GTX/GTH Transceivers - User Guide,https://www.xilinx.com/support/documentation/user_guides/ug476_7Series_Transceivers.pdf, Accessed 09 Jan 2017.
[4] Xilinx Forums, Can I make an IBERT design to test the connection between twoboards?,https://forums.xilinx.com/t5/Networking-and-Connectivity/Can-I-make-an-IBERT-design-to-test-the-connection-between-two/td-p/383349, Accessed 09 Jan 2017.
ACKNOWLEDGEMENTS
This material is based upon work supported by the São Paulo Research Foundation (FAPESP)under Grant No. 2013/01907-0 and by funds provided by the cooperation agreement withPADTEC S/A under FUNDUNESP Grant No. 2215/2013.
