Transformer Coupled Power

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSII: EXPRESS BRIEFS, VOL. 55, NO. 6, JUNE 2008 507 Transformer-Coupled Power Amplier Stability and Power Back-Off Analysis Debopriyo Chowdhury  , Student Member, IEEE , Patr ick Re ynaer t  , Member, IEEE , and Ali M. Niknejad  , Member, IEEE  Abstract—We pr es e nt a ma the ma ti cal an al ys is of th e common-mode instabilit y and powe r back-off feature of a transformer-coupled Class-AB differential power amplier (PA). The efcient impedance matching of the transformer combiner and efciency improvement at power back-off, a major benet of this structure, are illustrated. In addition, an analytical model is derived to pre dict the common-mod e oscil lation s in P A. The analyt ical re sul ts, bas ed on a simple hand-c alc ulatio n model for the transistor, show good agreement with simulation results usi ng comple te 90- nm mod els . Two met hods to sup pr ess the common-mode oscillations are investigated and analyzed in detail.  Index T erms— CMOS, power amplier s (P As) , power com- bining, stability. I. INTRODUCTION T HE rapid growth of the wireless industry over the last decade has led to a successful development of low cost high frequency CMOS circuits. However, still today the power amplier (PA) is often implemented in a separate technology, hindering full integration. In the last few years, considerable research effort has been invested in the development of fully-in- tegrated CMOS PAs [1]–[3]. Stability has always been a major concern for designers of hig h fre que ncy amp liers . Although ins tab ilit ies can be enc oun - tered in all RF and microwave circuits, PAs have the potential to exhibit one or more types of instabilities simultaneously. In addition to the linear feedback mechanism that creates an oscil- lation, the strong nonlinearity of PAs may also push them into an unstable region. The instability has been analyzed in details for a switching-mode amplier using chaos theory and bifurca- tion tools [4]. In this paper, we focus on ampliers employed in modern communication systems that employ amplitude modu- lation and multi-carrier signaling. For such applications, linear ampliers such as Class-AB are mostly used and their stability analysis, taking into account both on-chip and off-chip compo- nents, needs careful consideration. Of particular importance are Manu scrip t recei ved July 1, 2007. This work was supp orted by BWRC spo nso rs, the Nat ion al Sci ence Found ati on Inf ras tru ctu re und er Grant 0403427, ST Microelectronics, the DARPA TEAM program under Contract DAAB07-02-1-L428, and by C2S2 (one of ve research centers funded under the Focus Center Research Program, a Semiconductor Research Corporation Program). This paper was recommended by Associate Editor E. Alarcon. D. Chowdhury and A. M. Niknejad are with the Department of Electrical Engineering and Computer Science, University of California at Berkeley, CA 94720 USA. (e-mail: [email protected] ). P. Reyn aert was withthe Depar tmen t of Elect ricalEngineeri ng and Comp uter Science, University of California at Berkeley, CA 94720 USA. He is now with the Department of Electrical Engineering (ESAT-MIC AS), Katholieke Univer- siteit Leuven, Leuven B-3000, Belgium. Digital Object Identier 10.1109/TCSII.2007.914 899 Fig. 1. P A topology u sing transformers fo r power comb ining. common-mode oscillations in differential PA, which are often not cap tured by tra dit ional mic rowave approa che s (lik e the crite rion or t he test) . W e pres ent a ma thema tical a nalys is of the common-mode instability of a transformer-coupled PA as well as means to suppress the oscillation. The other important challenge for CMOS technology is to obtain sufcient output power from a PA, particularly because of the low breakdown voltage and high knee voltage of deeply- scaled CMOS transistors. Power combining is an attractive so- lution [2], [3], [5]. In particular, we have presented in [1] and [3] an on-chip transformer-based voltage combiner, that com- bines the power of four push-pull ampliers. This type of trans- former combiner has the property that individual stages can be tur ned of f in power bac k-o ff mode to enh ance ef ci ency at lower output power [3]. The power back-off feature is fairly general and can be applied successfully in many architectures. In this work, we present an in-depth analysis of power combining and power back-off properties. II. TRANSFORMER-BASED POWER COMBINING AND POWER BACK-OFF A simpli edsch ema tic of thearc hit ect ure use d in [1] is sho wn in Fig. 1. In contrast to the distributed active transformer (DAT) ap pr oach of [2], the topology in Fi g. 1 al so al lo wspowe r cont rol since each stage works independently and can be turned off. In what follows, the power combining and power back-off proper- ties of this architecture are analyzed in greater detail.  A. P ower Combining and Impedance T ransformation When calculati ng the trans formed load imped ance as see n by P A , it is impo rta nt to reali ze that the secondar y wi nd ing of ea ch tr an sf or me r ca rr ies the same current . 1549-7747/$25.00 © 2008 IEEE

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 55, NO. 6, JUNE 2008 507

Transformer-Coupled Power Amplifier Stability andPower Back-Off Analysis

Debopriyo Chowdhury  , Student Member, IEEE , Patrick Reynaert  , Member, IEEE , andAli M. Niknejad , Member, IEEE 

 Abstract—We present a mathematical analysis of thecommon-mode instability and power back-off feature of atransformer-coupled Class-AB differential power amplifier (PA).The efficient impedance matching of the transformer combinerand efficiency improvement at power back-off, a major benefitof this structure, are illustrated. In addition, an analytical modelis derived to predict the common-mode oscillations in PA. Theanalytical results, based on a simple hand-calculation modelfor the transistor, show good agreement with simulation resultsusing complete 90-nm models. Two methods to suppress thecommon-mode oscillations are investigated and analyzed in detail.

  Index Terms—CMOS, power amplifiers (PAs), power com-bining, stability.

I. INTRODUCTION

THE rapid growth of the wireless industry over the last

decade has led to a successful development of low cost

high frequency CMOS circuits. However, still today the power

amplifier (PA) is often implemented in a separate technology,

hindering full integration. In the last few years, considerable

research effort has been invested in the development of fully-in-

tegrated CMOS PAs [1]–[3].

Stability has always been a major concern for designers of high frequency amplifiers. Although instabilities can be encoun-

tered in all RF and microwave circuits, PAs have the potentialto exhibit one or more types of instabilities simultaneously. In

addition to the linear feedback mechanism that creates an oscil-

lation, the strong nonlinearity of PAs may also push them into

an unstable region. The instability has been analyzed in details

for a switching-mode amplifier using chaos theory and bifurca-tion tools [4]. In this paper, we focus on amplifiers employed in

modern communication systems that employ amplitude modu-lation and multi-carrier signaling. For such applications, linear

amplifiers such as Class-AB are mostly used and their stability

analysis, taking into account both on-chip and off-chip compo-

nents, needs careful consideration. Of particular importance are

Manuscript received July 1, 2007. This work was supported by BWRCsponsors, the National Science Foundation Infrastructure under Grant0403427, ST Microelectronics, the DARPA TEAM program under ContractDAAB07-02-1-L428, and by C2S2 (one of five research centers funded underthe Focus Center Research Program, a Semiconductor Research CorporationProgram). This paper was recommended by Associate Editor E. Alarcon.

D. Chowdhury and A. M. Niknejad are with the Department of ElectricalEngineering and Computer Science, University of California at Berkeley, CA94720 USA. (e-mail: [email protected]).

P. Reynaert was withthe Department of ElectricalEngineering and ComputerScience, University of California at Berkeley, CA 94720 USA. He is now withthe Department of Electrical Engineering (ESAT-MICAS), Katholieke Univer-siteit Leuven, Leuven B-3000, Belgium.

Digital Object Identifier 10.1109/TCSII.2007.914899

Fig. 1. PA topology using transformers for power combining.

common-mode oscillations in differential PA, which are often

not captured by traditional microwave approaches (like the –

criterion or the test). We present a mathematical analysis of 

the common-mode instability of a transformer-coupled PA as

well as means to suppress the oscillation.

The other important challenge for CMOS technology is to

obtain sufficient output power from a PA, particularly because

of the low breakdown voltage and high knee voltage of deeply-

scaled CMOS transistors. Power combining is an attractive so-lution [2], [3], [5]. In particular, we have presented in [1] and

[3] an on-chip transformer-based voltage combiner, that com-

bines the power of four push-pull amplifiers. This type of trans-

former combiner has the property that individual stages can be

turned off in power back-off mode to enhance efficiency at lower

output power [3]. The power back-off feature is fairly general

and can be applied successfully in many architectures. In this

work, we present an in-depth analysis of power combining and

power back-off properties.

II. TRANSFORMER-BASED POWER COMBINING AND

POWER BACK-OFF

A simplified schematic of the architecture used in [1] is shownin Fig. 1. In contrast to the distributed active transformer (DAT)approach of [2], the topology in Fig. 1 also allows power controlsince each stage works independently and can be turned off. Inwhat follows, the power combining and power back-off proper-ties of this architecture are analyzed in greater detail.

 A. Power Combining and Impedance Transformation

When calculating the transformed load impedanceas seen by PA , it is important to realize that the secondary

winding of each transformer carries the same current .

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508 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 55, NO. 6, JUNE 2008

As such, all PAs are coupled to each other. Using superposition,the transformed load impedance can be obtained as

(1)

with being the number of transformers, the transformerturn ratio, the output impedance and the complexoutput voltage of each PA. It can clearly be seen that thetransformed load impedance depends on both the outputimpedance and output voltage (both magnitude and phase) of each PA, which can be considered as a form of  load-pull.

When all PAs have the same output impedance, generate thesame output voltage, and all transformers use the same windingratio , (1) simplifies to a resistive value of 

(2)

The impedance seen by each amplifier is now determined bytwo factors only: the turn ratio of each transformer and thenumber of parallel stages . Note that it is independent of output impedance of the other PAs. Under the same conditions,the total output power, delivered to the load, equals

(3)

and the impedance transformation ratio is defined as

(4)

From (3), it can be seen that the output power can be increasedeither by increasing or . On the other hand, (4) shows thatthe impedance transformation ratio increases only linearly with

but quadratically with . It is well known that practicallya higher turn ratio, i.e., a high , also results in a high inser-tion loss [2]. Therefore, it is far more efficient to increase thenumber of stages , rather than increasing . Such an approachachieves a high output power with a rather moderate impedancetransformation ratio. This is an important aspect in low-voltagePA design.

 B. Power Control and Power Back-Off 

When one or more amplifiers in Fig. 1 are turned off , the

output power will decrease. Let us assume that the topology con-sists of four identical stagescoupled using four 1:1 transformers.When all four stages are active, the transformed impedance seenby each stage is and the gain of each stage is

. If is the input voltage, the output voltage of eachstage and the total output voltage across the load aregiven by

(5)

(6)

This is the case when peak output power is being generated andall the amplifiers are designed to operate at maximum efficiencyat this power level.

Now suppose that the input voltage reduces from toand two of the parallel stages are turned off. The impedance

Fig. 2. Efficiency versus output power for Class-B amplifier.

transformation ratio changes from 1:4 to 1:2 and each stage seesan effective resistance . The output voltage of eachstage and the total output voltage are now given by

(7)

(8)

Thus, we see that in spite of turning off 2 stages (6-dB powerback-off), because of dynamic load variation, the output swingof each active stage is still the same and hence it operatesat peak efficiency even at a lower power, an important feature insystems having high peak-to-average power ratio (PAPR). Thesame is true even if one or three stages are turned off to get 2.5-or 12-dB power back-off, respectively.

Let us now analyze the effect of power back-off on the dif-

ferent classes of amplifiers. The efficiency of a single Class-Bamplifier is given by

(9)

where is the supply voltage. From the previous analysis,we have seen that when we turn off stages, due to dynamic loadmodulation, the output swing of each of the remaining activedevices returns tothemaximumvalue at2.5-,6-,and12-dBpower back-off. Thus, even at reduced output power, each activeClass-B amplifier, and thus the whole structure operates at peak efficiency. This is illustrated by Fig. 2.

For Class-A amplifiers, the efficiency is given by

(10)

where is the bias current of each stage. At a specified back-off, when a stage is turned off, returns to the maximumvalue, but since increases, the efficiency of a Class-A am-plifier does not return to peak value, unlike Class-B amplifiers.Thus, this scheme of average efficiency enhancement works bestfor Class-B amplifiers. However, if one dynamically adjusts thebias current of the remaining active PAs, the efficiency of Class-A can further be increased and peak efficiency can againbe achieved at power back-off.

In the ideal analysis shown above, we have neglected theloading effects of the “off” amplifier. It can be shown that if 

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510 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 55, NO. 6, JUNE 2008

where represents the network currents and voltages shown inFig. 4 and is the input matrix and are given by

The matrix is as shown in (12) at the bottom of the previouspage, where ( is due to finite of on-chiptransformer winding) and .

For the system to oscillate, there must be finite current flowin the circuit, meaning that matrix must be nonzero, even inthe absence of any applied signal [6], [7]. This can be true onlyif is a singular matrix

(13)

The complete expression for is shown in Appendix. Ingeneral, the determinant has a real part as well as an imaginarypart and thus we have two equations. Setting the real part equalto zero gives us the oscillation frequency, while setting the imag-inary part equal to zero gives us the start-up condition. However,if we make a high approximation and neglect the losses in thesystem, (13) can be simplified as

(14)

A solution of (14) gives the potential oscillating frequenciesfor the designed PA. From (14), we see that there are three posi-tive solutions of , meaning that the amplifier can exhibit multi-mode oscillations. In a general case, the three frequency compo-nents can exist simultaneously and thus the voltage at any node,ignoring nonlinearities, can be written as

(15)For analysis of oscillating frequency, we set the input matrix

[in (11)] to zero. However, if now a voltage is applied at theoscillating frequency, the matrix equation can be re-solved toobtain the port input impedance . For oscillationto occur, the real part of this port impedance must be negative.Having already determined the possible oscillation frequencies,it becomes very easy for us to calculate the input impedance of the amplifier and determine if start-up conditions are satisfiedor not.

As an example, if , nH, ,, then the three solutions are GHz,GHz and GHz. Time-domain simula-

tion results for this combination shows that only the mode at11.39 GHz exists. The frequency being very high, the losses

of the system are high enough to suppress this mode. The toneat 1.02 GHz cannot sustain, because the real part of the input

Fig. 5. Simulated and calculated oscillation frequency as a function of  L  andL  .

impedance at that frequency is positive. On the other hand, theresistance being negative at 11.39 GHz, we observe the oscil-

lation tone in simulation. Multimode oscillations are possiblein general although they require a system nonlinearity that ishigher than cubic [8].

The analysis in this paper accurately predicts the existenceof common-mode instability in a linear PA. It is interesting toobserve that because of the presence of ground bond-wire, thebypass capacitor is not connected to a perfect ground and henceit can indeed cause instability.

C. Verification With Simulation Results

The concept developed in the previous section is verifiedusing the designed PA in 90-nm 1P7M CMOS process. Atransient analysis was performed and a Fourier transform of the

output voltage was used to obtain oscillation frequency. Fig. 5shows a comparison of the simulated and analytically calcu-lated values of the frequency of oscillation as a function of theprimary inductance ( , and are held fixed at 1 nH,1 nH, and 20 pF) and also as a function of ( , , and

are held fixed at 100 pH, 1 nH, and 20 pF). The predictedvalue of oscillation from matrix analysis is a little higher thanthe simulated value due to the extra capacitance present in thecomplete 90-nm transistor model. However, in spite of this,we can see that for various combinations of component values,the analytical method proposed in this paper can predict theinstability of the amplifier with a good degree of accuracy.

 D. Stabilization of the Amplifier 1) Adding a Gate Resistance: A PA needs to be stable for

passive load and source terminations. A common way to achievethis in microwave amplifiers is to insert a gate resistance (la-beled in Fig. 4), so that the losses in the system compen-sate for any negative port resistance. However, adding gate re-sistance impacts power gain of the amplifier and we would liketo use the smallest possible value, or design an appropriate by-pass network, to realize the best performance, especially at highfrequency.

Fig. 6 shows the variation in the real part of input impedanceas a function of frequency, which can be obtained from the so-lution of (11) . At the oscillation frequency, this

resistance will be negative and as a first guess we can use thisvalue as the gate resistance. However, it is important to note that

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CHOWDHURY et al.: TRANSFORMER-COUPLED PA STABILITY AND POWER BACK-OFF ANALYSIS 511

Fig. 6. Real part of the input impedance versus frequency.

Fig. 7. Comparison of gate resistance and series bypass resistance required tokill oscillation.

as soon as we add an to the system, the oscillation frequencychanges and should be re-evaulated using (14). This is whereit becomes necessary to use the complete equation described inAppendix . Once the new oscillation frequency is calculated, wecan recalculate the negative resistance at that frequency and up-date the value of . In practice, the iteration converges withintwo or three attempts. Fig. 7 shows a comparison of analyticallycalculated value of gate resistance and simulated value requiredto suppress all oscillations, for different values of theground lineinductance . Similar tests were also performed by varyingdifferent component values of the PA circuit. It is seen that theproposed method can accurately determine the required loss and

also gives insight to its variation with different component pa-rameters, so that we may account for process variations.

2) De-Q Bypass Capacitor: Another stabilizing option is toinsert a resistance in series with the bypass capacitor, asshown in Fig. 3. The matrix equation formulated in this work already includes the effect of and hence we may calculatethe oscillation frequency and the negative resistance at that fre-quency, exactly as before, but this time using a finite value for

. As increases, the input impedance becomes more pos-itive. Fig. 7 compares the simulated and analytically obtainedvalue of required to suppress oscillation. From the graph,we see that for larger values of , the value of required islarge, making this method alone unsuitable. However, we may

easily extend this idea to design a bypass network with multiple

 RC  networks in parallel, in such a way that it is low Q over awide frequency range (for stabilization), as well as moderatelylow impedance. The matrix method described in this paper canbe directly extended to include such a network.

IV. CONCLUSION

Power combining and novel transformer architectures are be-coming more important as a means to implement fully inte-grated CMOS PAs. This paper has described the basic operationof transformer based power combining and impedance transfor-mation. Furthermore, it is shown that by using the correct classof operation in the core PA, efficiency boost at power back-off is obtainable. An analytical analysis of common-mode oscilla-tions was described and the results are compared with transientsimulations. A good comparison between the two is achievedwhich clearly demonstrates the usefulness of this approach. Twotechniques to suppress the common-mode oscillations were in-vestigated using the proposed analysis technique.

APPENDIXDETERMINANT OF A

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