Comparative Study on Circuit Performance Depending on Double-Gate (DG) and Triple-Gate (TG) FinFET Structure

Kwan Young Kim, So Ra Park, Seung Hwan Seo, Gu-Cheol Kang, Kang Seob Roh, Sunyeong Lee, Kwan-Jae Song, Chang

Min Choi, Kichan Jeon, Jun-Hyun Park, Jieun Lee, Tae Yoon Kim, Dong Myong Kim, and Dae Hwan Kim School of Electrical Engineering, Kookmin University, Seoul 136-702, Korea

Abstract

The comparative study on trade-off between drive current and total gate capacitance in DG and TG FinFET is performed using 3-D device simulation. Our result shows that there is the room for further optimizing the thickness of top oxide of Si-fin (Tmask) with a fixed thickness of the sidewall oxide of Si-fin (Tox) in perspective of the intrinsic logic delay, and the optimal Tmask is about 10×Tox (≈fin width Wfin in our case) with a fixed Hfin. The Si-fin height Hfin-dependence of a FinFET gate delay is very critical and becomes more prominent with the increase of both Hfin and Tmask because the fringing capacitance takes a considerable portion of CG. In addition, FinFET circuit operation goes into the drive current-dominant region rather than the parasitic capacitance-dominant region as Hfin increases.

I. Introduction

With the continuous scaling of MOSFET into nanometer regime, nonplanar three-dimensional (3-D) transistors have shown ways to overcome short-channel effects (SCEs). Among them, double-gate (DG) and triple-gate (TG) FinFETs provides not only superior short-channel control, ideal subthreshold slope, and higher drive current but also the compatibility with conventional CMOS process [1]. Although the research on 3-D transistors has been fast in progress, most design guidelines of various parameters have been reported in perspective of DC characteristics such as SCEs or current drivability [2, 3]. In digital VLSI circuits, it is worthwhile to notice both the parasitic capacitance and capacitive coupling in order to estimate the influence on the circuit performance [4].

On the other hand, FinFET is fabricated by using the hard mask oxide or SiN technology on top of Si-fin in order to define the nano-scale feature size beyond state-of-the-art lithography. Moreover, the drive current of TG FinFET is higher than that of DG FinFET with the same fin size [5], because a thin top oxide of Si-fin is used, as is the case in a sidewall channel. Nevertheless, the intrinsic gate delay in TG FinFET is not necessarily smaller than that in DG FinFET because a total gate capacitance (fan-out capacitance in a chain of the logic gate) in the former is larger than that in the latter [6]. Therefore, there is the room for further optimizing the thickness of top oxide of Si-fin (Tmask) with a fixed thickness of the sidewall oxide of Si-fin (Tox) in perspective of the intrinsic logic delay.

In this work, the comparative study on trade-off between drive current and total gate capacitance in DG and TG FinFET is performed using 3-D device simulation. Modulated parameters are the Si-fin height (Hfin) and Tmask.

II. Simulation Results and Discussions

Fig.1 shows the bird’s eye view structure of FinFET. The 3-D device simulation was performed by ISE TCAD tool (SENTAURUS DEVICE 3-D simulator) [7]. Used device parameters are as follows: the gate length (LG)=30 nm, fin width (Wfin)=10 nm, S/D overlap length (Lov)=5 nm and Tox=1 nm, respectively. Both Tmask (=1~100 nm) and Hfin (=20~60 nm) are modulated as parameters affecting both the drive current and the gate capacitance. Therefore, while the condition of Tmask =1 nm corresponds to TG FinFET, the others do to DG FinFETs. In addition, all of LG, Wfin, and Hfin are in the range of known FinFET criteria for ideal SCEs.

Fig. 2 shows the current-voltage (IDS-VGS) and the capacitance-voltage (C-V) characteristics of FinFETs with Tmask =1 and 50 nm, respectively. Total gate capacitance CG is extracted under VD=0 V and the drain on current ION is extracted at

VG=VDD=1.0 V. The quantum effects in Si-fin are incorporated in 3-D device simulation. It is straightforward that both ION and CG of TG FinFET is larger than those of DG FinFET. Critical DC parameters are summarized in Table I.

Fig. 3 shows the electron density in Si-fin. The top corner of Si-fin body in TG FinFET shows higher inversion charge density than that in DG FinFET due to a strong vertical electric field through a thin Tmask. However, it is noticeable that the CG in DG FinFET with thick Tmask is smaller than that in TG FinFET as shown in Fig. 2(b).

Simulated CG includes most of fringing field effects such as inner and outer fringing field over the insulator, except contact-to-contact [7]. Fig. 4 shows the components of fringing field-induced parasitic capacitance, which are an inner fringing capacitance by gate-to-drain overlap (Cov), gate-to-top of drain overlap (CTov), outer fringing capacitance by gate-to-top of fin (CTfr), and gate-to-sidewall of fin (CSfr), respectively. Therefore, the CG is given like following equations:

G G S G DC C C= + , (1)

2GD ox Tfr Sfr ov TovC C C C C C= + + + + . (2)

As Tmask increases, both CTfr and CTov decrease due to reduced fringing field [6]. In addition, as Hfin increases, both CSfr and Cov increase followed by the increase of CGD as shown in Fig. 5. The Hfin and Tmask dependence of critical AC parameters are summarized in Fig. 6. Our result shows that the Hfin-dependence of a FinFET gate delay is very critical and becomes more prominent with the increase of both Hfin and Tmask because the fringing capacitance takes a considerable portion of CG.

Finally, the FinFET gate delay decreases as Hfin increases, as shown in Fig. 7. It shows that the optimal Tmask is about 10×Tox ≈ Wfin with a fixed Hfin, and the FinFET circuit operation goes into the drive current-dominant region rather than the parasitic capacitance-dominant region as Hfin increases.

III. Conclusions

The comparative study on trade-off between drive current and total gate capacitance in DG and TG FinFET is performed using 3-D device simulation. Our result shows that the optimal Tmask is about 10×Tox (≈Wfin in our case) with a fixed Hfin, and the FinFET circuit operation goes into the drive current-dominant region rather than the parasitic capacitance-dominant region as Hfin increases. It means that the initial Hfin should be very carefully determined in perspective of not only a process technology but also both the layout-dependence of circuit performance and the design for manufacturability.

Acknowledgements

This work was supported by research program 2007 of Kookmin University in Korea, and the CAD software was supported by IC Design Education Center (IDEC).

References [1] S.H. Tang, et al., Proc. Int. Solid-State Circuits Conf., pp.118-119,

2001. [2] Gen Pei, et al., Electron Devices, IEEE Transactions on, vol. 49, pp.

1411-1418, 2002. [3] Ji-Woon Yang, et al., Electron Devices, IEEE Transactions on, vol. 52,

no. 6, June 2005, pp. 1159-1164, 2005. [4] Y. Shinho, et al., IEDM. Tech. Dig., pp. 976-979, 2006. [5] B. S. Doyle, et al., Electron Device Letters, IEEE, vol. 24, pp. 263-265,

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TP2-49

2003

[6] Wen Wu, et al., Electron Devices, IEEE Transactions on, vol. 54, pp. 242-250, 2007.

[7] Synopsys Sentaurus Device User Guide, 1995-2007, Synopsys, Mountain View, CA.

X

YZ

Fig. 1. The bird’s eye view of multi-gate MOSFET structure is simulated using 3-D device simulator with optimized 3-D mesh structure. Triple-gate (TG) FinFET with Tmask=1nm, Double-gate (DG) FinFET with Tmask>1nm, and Hfin=20~60nm are variable. LG=30 nm, Wfin=10nm, Lsp=10nm and Tox=10Å.

-0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.00.0

1.0x10-5

2.0x10-5

3.0x10-5

4.0x10-5

5.0x10-5

6.0x10-5

7.0x10-5

-1.5 -1.0 -0.5 0.0 0.5 1.0 1.50

25

50

75

100

125

150

Solid symbol: CG

Open symbol: CGD

Dra

in C

urre

nt, I

DS [

A]

Gate Voltage, VGS [V]

Tmask=1nm Tmask=50nm

Solid symbol: VD=1.0VOpen symbol: VD=0.05V

Cap

acita

nce,

C [

aF]

Gate Voltage, VGS [V] (a) (b) Fig. 2. The IDS-VGS characteristics in (a) and C-V characteristics in (b) of FinFETs using different Tmask with Hfin=40nm. Table. I. The DC parameter comparison of simulated TG and DG FinFET structure in Fig. 2. VT is measured at IDS=0.1*2Hfin*Wfin/LG[㎂].

Device type VT

[V] SSW

[mV/dec] DIBL

[mV/V] TG (Tmask=1nm) -0.1 65.5 16.8

DG (Tmask=50nm) -0.1 65.8 16.8

0 5 10 15 20 25 30 35 401015

1016

1017

1018

1019

1020

1021

Ele

ctro

n D

ensi

ty [

cm-3]

Distance from Hard Mask Oxide, Z [nm]

TG (Tmask=1nm) DG (Tmask=50nm)

Symbol: A-A'Line: B-B'

Fig. 3. The electron density of silicon fin body in FinFETs using different Tmask with Hfin=40nm.

Fig. 4. Parasitic capacitance in FinFET. CTfr: gate-to-top of fin fringing capacitance, CSfr: gate-to-sidewall of fin fringing capacitance, Cov: overlap capacitance, and CTov: overlap capacitance through Tmask.

-1.5 -1.0 -0.5 0.0 0.5 1.0 1.50

30

60

90

120

150

180

210

-1.0 -0.5 0.0 0.5 1.0 1.5

Solid symbol: CG

Open symbol: CGD

Hfin=20nm

Cap

acita

nce,

C [

aF]

Gate Voltage, VGS [V]

Tmask=1nm Tmask=10nm Tmask=50nm Tmask=100nm

Hfin=60nm

Gate Voltage, VGS [V] Fig. 5. C-V curve from FinFETs with various Tmask and Hfin.

15 20 25 30 35 40 45 50 55 60 6570

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90

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Tot

al C

apac

itanc

e, C

G [

aF]

Height of Fin, Hfin [nm]

Tmask=1nm Tmask=10nm Tmask=50nm Tmask=100nm

Fig. 6. The Hfin and Tmask dependence of critical AC parameters

1 10 1001.0

1.2

1.4

1.6

1.8

2.0

2.2

2.4

2.6

2.8

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5.0x10-5

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Gat

e D

elay

(C

G∗V

DD/I

DS,

sat)

, τ [p

sec]

Hard Mask Oxide, Tmask [nm]

Dri

ve C

urre

nt, I

ON [

A]

Hard Mask Oxide, Tmask [nm]

Hfin=20nm Hfin=40nm Hfin=60nm

A B

B’ A’

Fig. 7. The FinFET gate delay (τ) and drive current (ION) as Hfin and Tmask.

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